2 * linux/include/asm-arm/arch-ebsa285/hardware.h
4 * Copyright (C) 1998-1999 Russell King.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This file contains the hardware definitions of the EBSA-285.
12 #ifndef __ASM_ARCH_HARDWARE_H
13 #define __ASM_ARCH_HARDWARE_H
15 #include <linux/config.h>
16 #include <asm/arch/memory.h>
18 #ifdef CONFIG_ARCH_FOOTBRIDGE
19 /* Virtual Physical Size
20 * 0xff800000 0x40000000 1MB X-Bus
21 * 0xff000000 0x7c000000 1MB PCI I/O space
22 * 0xfe000000 0x42000000 1MB CSR
23 * 0xfd000000 0x78000000 1MB Outbound write flush (not supported)
24 * 0xfc000000 0x79000000 1MB PCI IACK/special space
25 * 0xfb000000 0x7a000000 16MB PCI Config type 1
26 * 0xfa000000 0x7b000000 16MB PCI Config type 0
27 * 0xf9000000 0x50000000 1MB Cache flush
28 * 0xf0000000 0x80000000 16MB ISA memory
30 #define XBUS_SIZE 0x00100000
31 #define XBUS_BASE 0xff800000
33 #define PCIO_SIZE 0x00100000
34 #define PCIO_BASE 0xff000000
36 #define ARMCSR_SIZE 0x00100000
37 #define ARMCSR_BASE 0xfe000000
39 #define WFLUSH_SIZE 0x00100000
40 #define WFLUSH_BASE 0xfd000000
42 #define PCIIACK_SIZE 0x00100000
43 #define PCIIACK_BASE 0xfc000000
45 #define PCICFG1_SIZE 0x01000000
46 #define PCICFG1_BASE 0xfb000000
48 #define PCICFG0_SIZE 0x01000000
49 #define PCICFG0_BASE 0xfa000000
51 #define PCIMEM_SIZE 0x01000000
52 #define PCIMEM_BASE 0xf0000000
54 #elif defined(CONFIG_ARCH_CO285)
56 * This is the COEBSA285 cut-down mapping
58 #define PCIMEM_SIZE 0x80000000
59 #define PCIMEM_BASE 0x80000000
61 #define WFLUSH_SIZE 0x01000000
62 #define WFLUSH_BASE 0x7d000000
64 #define ARMCSR_SIZE 0x00100000
65 #define ARMCSR_BASE 0x7cf00000
67 #define XBUS_SIZE 0x00020000
68 #define XBUS_BASE 0x7cee0000
70 #define PCIO_SIZE 0x00010000
71 #define PCIO_BASE 0x7ced0000
75 #error "Undefined footbridge architecture"
79 #define XBUS_LEDS ((volatile unsigned char *)(XBUS_BASE + 0x12000))
80 #define XBUS_LED_AMBER (1 << 0)
81 #define XBUS_LED_GREEN (1 << 1)
82 #define XBUS_LED_RED (1 << 2)
83 #define XBUS_LED_TOGGLE (1 << 8)
85 #define XBUS_SWITCH ((volatile unsigned char *)(XBUS_BASE + 0x12000))
86 #define XBUS_SWITCH_SWITCH ((*XBUS_SWITCH) & 15)
87 #define XBUS_SWITCH_J17_13 ((*XBUS_SWITCH) & (1 << 4))
88 #define XBUS_SWITCH_J17_11 ((*XBUS_SWITCH) & (1 << 5))
89 #define XBUS_SWITCH_J17_9 ((*XBUS_SWITCH) & (1 << 6))
91 #define UNCACHEABLE_ADDR (ARMCSR_BASE + 0x108)
96 #define PIC_MASK_LO 0x21
98 #define PIC_MASK_HI 0xA1
101 #define GPIO_CCLK 0x800
102 #define GPIO_DSCLK 0x400
103 #define GPIO_E2CLK 0x200
104 #define GPIO_IOLOAD 0x100
105 #define GPIO_RED_LED 0x080
106 #define GPIO_WDTIMER 0x040
107 #define GPIO_DATA 0x020
108 #define GPIO_IOCLK 0x010
109 #define GPIO_DONE 0x008
110 #define GPIO_FAN 0x004
111 #define GPIO_GREEN_LED 0x002
112 #define GPIO_RESET 0x001
115 #define CPLD_DS_ENABLE 8
116 #define CPLD_7111_DISABLE 4
117 #define CPLD_UNMUTE 2
118 #define CPLD_FLASH_WR_ENABLE 1
121 extern void gpio_modify_op(int mask, int set);
122 extern void gpio_modify_io(int mask, int in);
123 extern int gpio_read(void);
124 extern void cpld_modify(int mask, int set);
127 #define pcibios_assign_all_busses() 1
129 #define PCIBIOS_MIN_IO 0x1000
130 #define PCIBIOS_MIN_MEM 0x81000000