2 * Frame buffer driver for Trident Blade and Image series
4 * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro>
7 * CREDITS:(in order of appearance)
8 * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video
9 * Special thanks ;) to Mattia Crivellini <tia@mclink.it>
10 * much inspired by the XFree86 4.x Trident driver sources
11 * by Alan Hourihane the FreeVGA project
12 * Francesco Salvestrini <salvestrini@users.sf.net> XP support,
15 * timing value tweaking so it looks good on every monitor in every mode
19 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/pci.h>
24 #include <linux/delay.h>
25 #include <video/vga.h>
26 #include <video/trident.h>
28 #define VERSION "0.7.9-NEWAPI"
30 struct tridentfb_par {
31 void __iomem *io_virt; /* iospace virtual memory address */
35 void (*init_accel) (struct tridentfb_par *, int, int);
36 void (*wait_engine) (struct tridentfb_par *);
38 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
40 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
43 static unsigned char eng_oper; /* engine operation... */
44 static struct fb_ops tridentfb_ops;
46 static struct fb_fix_screeninfo tridentfb_fix = {
48 .type = FB_TYPE_PACKED_PIXELS,
50 .visual = FB_VISUAL_PSEUDOCOLOR,
51 .accel = FB_ACCEL_NONE,
54 /* defaults which are normally overriden by user values */
57 static char *mode_option __devinitdata = "640x480";
58 static int bpp __devinitdata = 8;
60 static int noaccel __devinitdata;
65 static int fp __devinitdata;
66 static int crt __devinitdata;
68 static int memsize __devinitdata;
69 static int memdiff __devinitdata;
72 module_param(mode_option, charp, 0);
73 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
74 module_param_named(mode, mode_option, charp, 0);
75 MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
76 module_param(bpp, int, 0);
77 module_param(center, int, 0);
78 module_param(stretch, int, 0);
79 module_param(noaccel, int, 0);
80 module_param(memsize, int, 0);
81 module_param(memdiff, int, 0);
82 module_param(nativex, int, 0);
83 module_param(fp, int, 0);
84 MODULE_PARM_DESC(fp, "Define if flatpanel is connected");
85 module_param(crt, int, 0);
86 MODULE_PARM_DESC(crt, "Define if CRT is connected");
88 static int is_oldclock(int id)
90 return (id == TGUI9660);
93 static int is_blade(int id)
95 return (id == BLADE3D) ||
96 (id == CYBERBLADEE4) ||
97 (id == CYBERBLADEi7) ||
98 (id == CYBERBLADEi7D) ||
99 (id == CYBERBLADEi1) ||
100 (id == CYBERBLADEi1D) ||
101 (id == CYBERBLADEAi1) ||
102 (id == CYBERBLADEAi1D);
105 static int is_xp(int id)
107 return (id == CYBERBLADEXPAi1) ||
108 (id == CYBERBLADEXPm8) ||
109 (id == CYBERBLADEXPm16);
112 static int is3Dchip(int id)
114 return ((id == BLADE3D) || (id == CYBERBLADEE4) ||
115 (id == CYBERBLADEi7) || (id == CYBERBLADEi7D) ||
116 (id == CYBER9397) || (id == CYBER9397DVD) ||
117 (id == CYBER9520) || (id == CYBER9525DVD) ||
118 (id == IMAGE975) || (id == IMAGE985) ||
119 (id == CYBERBLADEi1) || (id == CYBERBLADEi1D) ||
120 (id == CYBERBLADEAi1) || (id == CYBERBLADEAi1D) ||
121 (id == CYBERBLADEXPm8) || (id == CYBERBLADEXPm16) ||
122 (id == CYBERBLADEXPAi1));
125 static int iscyber(int id)
141 case CYBERBLADEXPAi1:
149 case CYBERBLADEi7: /* VIA MPV4 integrated version */
152 /* case CYBERBLDAEXPm8: Strange */
153 /* case CYBERBLDAEXPm16: Strange */
158 static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)
160 fb_writeb(val, p->io_virt + reg);
163 static inline u8 t_inb(struct tridentfb_par *p, u16 reg)
165 return fb_readb(p->io_virt + reg);
168 static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v)
170 fb_writel(v, par->io_virt + r);
173 static inline u32 readmmr(struct tridentfb_par *par, u16 r)
175 return fb_readl(par->io_virt + r);
179 * Blade specific acceleration.
182 #define point(x, y) ((y) << 16 | (x))
194 static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp)
196 int v1 = (pitch >> 3) << 20;
213 v2 = v1 | (tmp << 29);
214 writemmr(par, 0x21C0, v2);
215 writemmr(par, 0x21C4, v2);
216 writemmr(par, 0x21B8, v2);
217 writemmr(par, 0x21BC, v2);
218 writemmr(par, 0x21D0, v1);
219 writemmr(par, 0x21D4, v1);
220 writemmr(par, 0x21C8, v1);
221 writemmr(par, 0x21CC, v1);
222 writemmr(par, 0x216C, 0);
225 static void blade_wait_engine(struct tridentfb_par *par)
227 while (readmmr(par, STA) & 0xFA800000) ;
230 static void blade_fill_rect(struct tridentfb_par *par,
231 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
233 writemmr(par, CLR, c);
234 writemmr(par, ROP, rop ? 0x66 : ROP_S);
235 writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
237 writemmr(par, DR1, point(x, y));
238 writemmr(par, DR2, point(x + w - 1, y + h - 1));
241 static void blade_copy_rect(struct tridentfb_par *par,
242 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
247 s2 = point(x1 + w - 1, y1 + h - 1);
249 d2 = point(x2 + w - 1, y2 + h - 1);
251 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
254 writemmr(par, ROP, ROP_S);
255 writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
257 writemmr(par, SR1, direction ? s2 : s1);
258 writemmr(par, SR2, direction ? s1 : s2);
259 writemmr(par, DR1, direction ? d2 : d1);
260 writemmr(par, DR2, direction ? d1 : d2);
264 * BladeXP specific acceleration functions
268 #define masked_point(x, y) ((y & 0xffff)<<16|(x & 0xffff))
270 static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp)
290 switch (pitch << (bpp >> 3)) {
306 t_outb(par, x, 0x2125);
326 writemmr(par, 0x2154, v1);
327 writemmr(par, 0x2150, v1);
328 t_outb(par, 3, 0x2126);
331 static void xp_wait_engine(struct tridentfb_par *par)
339 busy = t_inb(par, STA) & 0x80;
343 if (count == 10000000) {
349 t_outb(par, 0x00, 0x2120);
356 static void xp_fill_rect(struct tridentfb_par *par,
357 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
359 writemmr(par, 0x2127, ROP_P);
360 writemmr(par, 0x2158, c);
361 writemmr(par, 0x2128, 0x4000);
362 writemmr(par, 0x2140, masked_point(h, w));
363 writemmr(par, 0x2138, masked_point(y, x));
364 t_outb(par, 0x01, 0x2124);
365 t_outb(par, eng_oper, 0x2125);
368 static void xp_copy_rect(struct tridentfb_par *par,
369 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
372 u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
376 if ((x1 < x2) && (y1 == y2)) {
394 writemmr(par, 0x2128, direction);
395 t_outb(par, ROP_S, 0x2127);
396 writemmr(par, 0x213C, masked_point(y1_tmp, x1_tmp));
397 writemmr(par, 0x2138, masked_point(y2_tmp, x2_tmp));
398 writemmr(par, 0x2140, masked_point(h, w));
399 t_outb(par, 0x01, 0x2124);
403 * Image specific acceleration functions
405 static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp)
423 writemmr(par, 0x2120, 0xF0000000);
424 writemmr(par, 0x2120, 0x40000000 | tmp);
425 writemmr(par, 0x2120, 0x80000000);
426 writemmr(par, 0x2144, 0x00000000);
427 writemmr(par, 0x2148, 0x00000000);
428 writemmr(par, 0x2150, 0x00000000);
429 writemmr(par, 0x2154, 0x00000000);
430 writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch);
431 writemmr(par, 0x216C, 0x00000000);
432 writemmr(par, 0x2170, 0x00000000);
433 writemmr(par, 0x217C, 0x00000000);
434 writemmr(par, 0x2120, 0x10000000);
435 writemmr(par, 0x2130, (2047 << 16) | 2047);
438 static void image_wait_engine(struct tridentfb_par *par)
440 while (readmmr(par, 0x2164) & 0xF0000000) ;
443 static void image_fill_rect(struct tridentfb_par *par,
444 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
446 writemmr(par, 0x2120, 0x80000000);
447 writemmr(par, 0x2120, 0x90000000 | ROP_S);
449 writemmr(par, 0x2144, c);
451 writemmr(par, DR1, point(x, y));
452 writemmr(par, DR2, point(x + w - 1, y + h - 1));
454 writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
457 static void image_copy_rect(struct tridentfb_par *par,
458 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
463 s2 = point(x1 + w - 1, y1 + h - 1);
465 d2 = point(x2 + w - 1, y2 + h - 1);
467 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
470 writemmr(par, 0x2120, 0x80000000);
471 writemmr(par, 0x2120, 0x90000000 | ROP_S);
473 writemmr(par, SR1, direction ? s2 : s1);
474 writemmr(par, SR2, direction ? s1 : s2);
475 writemmr(par, DR1, direction ? d2 : d1);
476 writemmr(par, DR2, direction ? d1 : d2);
477 writemmr(par, 0x2124,
478 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction);
482 * Accel functions called by the upper layers
484 #ifdef CONFIG_FB_TRIDENT_ACCEL
485 static void tridentfb_fillrect(struct fb_info *info,
486 const struct fb_fillrect *fr)
488 struct tridentfb_par *par = info->par;
489 int bpp = info->var.bits_per_pixel;
500 col = ((u32 *)(info->pseudo_palette))[fr->color];
503 col = ((u32 *)(info->pseudo_palette))[fr->color];
507 par->fill_rect(par, fr->dx, fr->dy, fr->width,
508 fr->height, col, fr->rop);
509 par->wait_engine(par);
511 static void tridentfb_copyarea(struct fb_info *info,
512 const struct fb_copyarea *ca)
514 struct tridentfb_par *par = info->par;
516 par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy,
517 ca->width, ca->height);
518 par->wait_engine(par);
520 #else /* !CONFIG_FB_TRIDENT_ACCEL */
521 #define tridentfb_fillrect cfb_fillrect
522 #define tridentfb_copyarea cfb_copyarea
523 #endif /* CONFIG_FB_TRIDENT_ACCEL */
527 * Hardware access functions
530 static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
532 return vga_mm_rcrt(par->io_virt, reg);
535 static inline void write3X4(struct tridentfb_par *par, int reg,
538 vga_mm_wcrt(par->io_virt, reg, val);
541 static inline unsigned char read3CE(struct tridentfb_par *par,
544 return vga_mm_rgfx(par->io_virt, reg);
547 static inline void writeAttr(struct tridentfb_par *par, int reg,
550 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
551 vga_mm_wattr(par->io_virt, reg, val);
554 static inline void write3CE(struct tridentfb_par *par, int reg,
557 vga_mm_wgfx(par->io_virt, reg, val);
560 static void enable_mmio(void)
565 /* Unprotect registers */
566 vga_io_wseq(NewMode1, 0x80);
570 outb(inb(0x3D5) | 0x01, 0x3D5);
573 static void disable_mmio(struct tridentfb_par *par)
576 vga_mm_rseq(par->io_virt, 0x0B);
578 /* Unprotect registers */
579 vga_mm_wseq(par->io_virt, NewMode1, 0x80);
582 t_outb(par, PCIReg, 0x3D4);
583 t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);
586 static void crtc_unlock(struct tridentfb_par *par)
588 write3X4(par, VGA_CRTC_V_SYNC_END,
589 read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F);
592 /* Return flat panel's maximum x resolution */
593 static int __devinit get_nativex(struct tridentfb_par *par)
600 tmp = (read3CE(par, VertStretch) >> 4) & 3;
621 output("%dx%d flat panel found\n", x, y);
626 static void set_lwidth(struct tridentfb_par *par, int width)
628 write3X4(par, VGA_CRTC_OFFSET, width & 0xFF);
629 write3X4(par, AddColReg,
630 (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
633 /* For resolutions smaller than FP resolution stretch */
634 static void screen_stretch(struct tridentfb_par *par)
636 if (par->chip_id != CYBERBLADEXPAi1)
637 write3CE(par, BiosReg, 0);
639 write3CE(par, BiosReg, 8);
640 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1);
641 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1);
644 /* For resolutions smaller than FP resolution center */
645 static void screen_center(struct tridentfb_par *par)
647 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80);
648 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80);
651 /* Address of first shown pixel in display memory */
652 static void set_screen_start(struct tridentfb_par *par, int base)
655 write3X4(par, VGA_CRTC_START_LO, base & 0xFF);
656 write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8);
657 tmp = read3X4(par, CRTCModuleTest) & 0xDF;
658 write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
659 tmp = read3X4(par, CRTHiOrd) & 0xF8;
660 write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17));
663 /* Set dotclock frequency */
664 static void set_vclk(struct tridentfb_par *par, unsigned long freq)
667 unsigned long fi, d, di;
668 unsigned char best_m = 0, best_n = 0, best_k = 0;
669 unsigned char hi, lo;
672 for (k = 1; k >= 0; k--)
673 for (m = 0; m < 32; m++)
674 for (n = 0; n < 122; n++) {
675 fi = ((14318l * (n + 8)) / (m + 2)) >> k;
676 if ((di = abs(fi - freq)) < d) {
686 if (is_oldclock(par->chip_id)) {
687 lo = best_n | (best_m << 7);
688 hi = (best_m >> 1) | (best_k << 4);
691 hi = best_m | (best_k << 6);
694 if (is3Dchip(par->chip_id)) {
695 vga_mm_wseq(par->io_virt, ClockHigh, hi);
696 vga_mm_wseq(par->io_virt, ClockLow, lo);
698 t_outb(par, lo, 0x43C8);
699 t_outb(par, hi, 0x43C9);
701 debug("VCLK = %X %X\n", hi, lo);
704 /* Set number of lines for flat panels*/
705 static void set_number_of_lines(struct tridentfb_par *par, int lines)
707 int tmp = read3CE(par, CyberEnhance) & 0x8F;
710 else if (lines > 768)
712 else if (lines > 600)
714 else if (lines > 480)
716 write3CE(par, CyberEnhance, tmp);
720 * If we see that FP is active we assume we have one.
721 * Otherwise we have a CRT display. User can override.
723 static int __devinit is_flatpanel(struct tridentfb_par *par)
727 if (crt || !iscyber(par->chip_id))
729 return (read3CE(par, FPConfig) & 0x10) ? 1 : 0;
732 /* Try detecting the video memory size */
733 static unsigned int __devinit get_memsize(struct tridentfb_par *par)
735 unsigned char tmp, tmp2;
738 /* If memory size provided by user */
742 switch (par->chip_id) {
747 tmp = read3X4(par, SPR) & 0x0F;
763 k = 10 * Mb; /* XP */
769 k = 12 * Mb; /* XP */
772 k = 14 * Mb; /* XP */
775 k = 16 * Mb; /* XP */
779 tmp2 = vga_mm_rseq(par->io_virt, 0xC1);
809 output("framebuffer size = %d Kb\n", k / Kb);
813 /* See if we can handle the video mode described in var */
814 static int tridentfb_check_var(struct fb_var_screeninfo *var,
815 struct fb_info *info)
817 struct tridentfb_par *par = info->par;
818 int bpp = var->bits_per_pixel;
821 /* check color depth */
823 bpp = var->bits_per_pixel = 32;
824 /* check whether resolution fits on panel and in memory */
825 if (par->flatpanel && nativex && var->xres > nativex)
827 if (var->xres * var->yres_virtual * bpp / 8 > info->fix.smem_len)
833 var->green.offset = 0;
834 var->blue.offset = 0;
836 var->green.length = 6;
837 var->blue.length = 6;
840 var->red.offset = 11;
841 var->green.offset = 5;
842 var->blue.offset = 0;
844 var->green.length = 6;
845 var->blue.length = 5;
848 var->red.offset = 16;
849 var->green.offset = 8;
850 var->blue.offset = 0;
852 var->green.length = 8;
853 var->blue.length = 8;
864 /* Pan the display */
865 static int tridentfb_pan_display(struct fb_var_screeninfo *var,
866 struct fb_info *info)
868 struct tridentfb_par *par = info->par;
872 offset = (var->xoffset + (var->yoffset * var->xres))
873 * var->bits_per_pixel / 32;
874 info->var.xoffset = var->xoffset;
875 info->var.yoffset = var->yoffset;
876 set_screen_start(par, offset);
881 static void shadowmode_on(struct tridentfb_par *par)
883 write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81);
886 static void shadowmode_off(struct tridentfb_par *par)
888 write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E);
891 /* Set the hardware to the requested video mode */
892 static int tridentfb_set_par(struct fb_info *info)
894 struct tridentfb_par *par = (struct tridentfb_par *)(info->par);
895 u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend;
896 u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend;
897 struct fb_var_screeninfo *var = &info->var;
898 int bpp = var->bits_per_pixel;
903 hdispend = var->xres / 8 - 1;
904 hsyncstart = (var->xres + var->right_margin) / 8 - 1;
905 hsyncend = (var->xres + var->right_margin + var->hsync_len) / 8 - 1;
906 htotal = (var->xres + var->left_margin + var->right_margin +
907 var->hsync_len) / 8 - 5;
908 hblankstart = hdispend + 2;
909 hblankend = htotal + 3;
911 vdispend = var->yres - 1;
912 vsyncstart = var->yres + var->lower_margin;
913 vsyncend = vsyncstart + var->vsync_len;
914 vtotal = var->upper_margin + vsyncend - 2;
915 vblankstart = vdispend + 2;
919 write3CE(par, CyberControl, 8);
921 if (par->flatpanel && var->xres < nativex) {
923 * on flat panels with native size larger
924 * than requested resolution decide whether
925 * we stretch or center
927 t_outb(par, 0xEB, VGA_MIS_W);
937 t_outb(par, 0x2B, VGA_MIS_W);
938 write3CE(par, CyberControl, 8);
941 /* vertical timing values */
942 write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF);
943 write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF);
944 write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF);
945 write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F));
946 write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF);
947 write3X4(par, VGA_CRTC_V_BLANK_END, vblankend & 0xFF);
949 /* horizontal timing values */
950 write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF);
951 write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF);
952 write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF);
953 write3X4(par, VGA_CRTC_H_SYNC_END,
954 (hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
955 write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF);
956 write3X4(par, VGA_CRTC_H_BLANK_END, hblankend & 0x1F);
958 /* higher bits of vertical timing values */
960 if (vtotal & 0x100) tmp |= 0x01;
961 if (vdispend & 0x100) tmp |= 0x02;
962 if (vsyncstart & 0x100) tmp |= 0x04;
963 if (vblankstart & 0x100) tmp |= 0x08;
965 if (vtotal & 0x200) tmp |= 0x20;
966 if (vdispend & 0x200) tmp |= 0x40;
967 if (vsyncstart & 0x200) tmp |= 0x80;
968 write3X4(par, VGA_CRTC_OVERFLOW, tmp);
970 tmp = read3X4(par, CRTHiOrd) & 0x07;
971 tmp |= 0x08; /* line compare bit 10 */
972 if (vtotal & 0x400) tmp |= 0x80;
973 if (vblankstart & 0x400) tmp |= 0x40;
974 if (vsyncstart & 0x400) tmp |= 0x20;
975 if (vdispend & 0x400) tmp |= 0x10;
976 write3X4(par, CRTHiOrd, tmp);
978 tmp = (htotal >> 8) & 0x01;
979 tmp |= (hdispend >> 7) & 0x02;
980 tmp |= (hsyncstart >> 5) & 0x08;
981 tmp |= (hblankstart >> 4) & 0x10;
982 write3X4(par, HorizOverflow, tmp);
985 if (vblankstart & 0x200) tmp |= 0x20;
986 //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */
987 write3X4(par, VGA_CRTC_MAX_SCAN, tmp);
989 write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF);
990 write3X4(par, VGA_CRTC_PRESET_ROW, 0);
991 write3X4(par, VGA_CRTC_MODE, 0xC3);
993 write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */
995 tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80;
996 /* enable access extended memory */
997 write3X4(par, CRTCModuleTest, tmp);
999 /* enable GE for text acceleration */
1000 write3X4(par, GraphEngReg, 0x80);
1002 #ifdef CONFIG_FB_TRIDENT_ACCEL
1003 par->init_accel(par, info->var.xres, bpp);
1021 write3X4(par, PixelBusReg, tmp);
1024 if (iscyber(par->chip_id))
1026 write3X4(par, DRAMControl, tmp); /* both IO, linear enable */
1028 write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40);
1029 write3X4(par, Performance, 0x92);
1030 /* MMIO & PCI read and write burst enable */
1031 write3X4(par, PCIReg, 0x07);
1033 /* convert from picoseconds to kHz */
1034 vclk = PICOS2KHZ(info->var.pixclock);
1037 set_vclk(par, vclk);
1039 vga_mm_wseq(par->io_virt, 0, 3);
1040 vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */
1041 /* enable 4 maps because needed in chain4 mode */
1042 vga_mm_wseq(par->io_virt, 2, 0x0F);
1043 vga_mm_wseq(par->io_virt, 3, 0);
1044 vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */
1046 /* divide clock by 2 if 32bpp chain4 mode display and CPU path */
1047 write3CE(par, MiscExtFunc, (bpp == 32) ? 0x1A : 0x12);
1048 write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */
1049 write3CE(par, 0x6, 0x05); /* graphics mode */
1050 write3CE(par, 0x7, 0x0F); /* planes? */
1052 if (par->chip_id == CYBERBLADEXPAi1) {
1053 /* This fixes snow-effect in 32 bpp */
1054 write3X4(par, VGA_CRTC_H_SYNC_START, 0x84);
1057 /* graphics mode and support 256 color modes */
1058 writeAttr(par, 0x10, 0x41);
1059 writeAttr(par, 0x12, 0x0F); /* planes */
1060 writeAttr(par, 0x13, 0); /* horizontal pel panning */
1063 for (tmp = 0; tmp < 0x10; tmp++)
1064 writeAttr(par, tmp, tmp);
1065 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
1066 t_outb(par, 0x20, VGA_ATT_W); /* enable attr */
1084 t_inb(par, VGA_PEL_IW);
1085 t_inb(par, VGA_PEL_MSK);
1086 t_inb(par, VGA_PEL_MSK);
1087 t_inb(par, VGA_PEL_MSK);
1088 t_inb(par, VGA_PEL_MSK);
1089 t_outb(par, tmp, VGA_PEL_MSK);
1090 t_inb(par, VGA_PEL_IW);
1093 set_number_of_lines(par, info->var.yres);
1094 set_lwidth(par, info->var.xres * bpp / (4 * 16));
1095 info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1096 info->fix.line_length = info->var.xres * (bpp >> 3);
1097 info->cmap.len = (bpp == 8) ? 256 : 16;
1102 /* Set one color register */
1103 static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1104 unsigned blue, unsigned transp,
1105 struct fb_info *info)
1107 int bpp = info->var.bits_per_pixel;
1108 struct tridentfb_par *par = info->par;
1110 if (regno >= info->cmap.len)
1114 t_outb(par, 0xFF, VGA_PEL_MSK);
1115 t_outb(par, regno, VGA_PEL_IW);
1117 t_outb(par, red >> 10, VGA_PEL_D);
1118 t_outb(par, green >> 10, VGA_PEL_D);
1119 t_outb(par, blue >> 10, VGA_PEL_D);
1121 } else if (regno < 16) {
1122 if (bpp == 16) { /* RGB 565 */
1125 col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
1126 ((blue & 0xF800) >> 11);
1128 ((u32 *)(info->pseudo_palette))[regno] = col;
1129 } else if (bpp == 32) /* ARGB 8888 */
1130 ((u32*)info->pseudo_palette)[regno] =
1131 ((transp & 0xFF00) << 16) |
1132 ((red & 0xFF00) << 8) |
1133 ((green & 0xFF00)) |
1134 ((blue & 0xFF00) >> 8);
1137 /* debug("exit\n"); */
1141 /* Try blanking the screen.For flat panels it does nothing */
1142 static int tridentfb_blank(int blank_mode, struct fb_info *info)
1144 unsigned char PMCont, DPMSCont;
1145 struct tridentfb_par *par = info->par;
1150 t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */
1151 PMCont = t_inb(par, 0x83C6) & 0xFC;
1152 DPMSCont = read3CE(par, PowerStatus) & 0xFC;
1153 switch (blank_mode) {
1154 case FB_BLANK_UNBLANK:
1155 /* Screen: On, HSync: On, VSync: On */
1156 case FB_BLANK_NORMAL:
1157 /* Screen: Off, HSync: On, VSync: On */
1161 case FB_BLANK_HSYNC_SUSPEND:
1162 /* Screen: Off, HSync: Off, VSync: On */
1166 case FB_BLANK_VSYNC_SUSPEND:
1167 /* Screen: Off, HSync: On, VSync: Off */
1171 case FB_BLANK_POWERDOWN:
1172 /* Screen: Off, HSync: Off, VSync: Off */
1178 write3CE(par, PowerStatus, DPMSCont);
1179 t_outb(par, 4, 0x83C8);
1180 t_outb(par, PMCont, 0x83C6);
1184 /* let fbcon do a softblank for us */
1185 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1188 static struct fb_ops tridentfb_ops = {
1189 .owner = THIS_MODULE,
1190 .fb_setcolreg = tridentfb_setcolreg,
1191 .fb_pan_display = tridentfb_pan_display,
1192 .fb_blank = tridentfb_blank,
1193 .fb_check_var = tridentfb_check_var,
1194 .fb_set_par = tridentfb_set_par,
1195 .fb_fillrect = tridentfb_fillrect,
1196 .fb_copyarea = tridentfb_copyarea,
1197 .fb_imageblit = cfb_imageblit,
1200 static int __devinit trident_pci_probe(struct pci_dev *dev,
1201 const struct pci_device_id *id)
1204 unsigned char revision;
1205 struct fb_info *info;
1206 struct tridentfb_par *default_par;
1211 err = pci_enable_device(dev);
1215 info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev);
1218 default_par = info->par;
1220 chip_id = id->device;
1222 if (chip_id == CYBERBLADEi1)
1223 output("*** Please do use cyblafb, Cyberblade/i1 support "
1224 "will soon be removed from tridentfb!\n");
1227 /* If PCI id is 0x9660 then further detect chip type */
1229 if (chip_id == TGUI9660) {
1230 revision = vga_io_rseq(RevisionID);
1235 chip_id = CYBER9397;
1238 chip_id = CYBER9397DVD;
1247 chip_id = CYBER9385;
1250 chip_id = CYBER9382;
1253 chip_id = CYBER9388;
1260 chip3D = is3Dchip(chip_id);
1262 if (is_xp(chip_id)) {
1263 default_par->init_accel = xp_init_accel;
1264 default_par->wait_engine = xp_wait_engine;
1265 default_par->fill_rect = xp_fill_rect;
1266 default_par->copy_rect = xp_copy_rect;
1267 } else if (is_blade(chip_id)) {
1268 default_par->init_accel = blade_init_accel;
1269 default_par->wait_engine = blade_wait_engine;
1270 default_par->fill_rect = blade_fill_rect;
1271 default_par->copy_rect = blade_copy_rect;
1273 default_par->init_accel = image_init_accel;
1274 default_par->wait_engine = image_wait_engine;
1275 default_par->fill_rect = image_fill_rect;
1276 default_par->copy_rect = image_copy_rect;
1279 default_par->chip_id = chip_id;
1281 /* acceleration is on by default for 3D chips */
1282 defaultaccel = chip3D && !noaccel;
1284 /* setup MMIO region */
1285 tridentfb_fix.mmio_start = pci_resource_start(dev, 1);
1286 tridentfb_fix.mmio_len = chip3D ? 0x20000 : 0x10000;
1288 if (!request_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len, "tridentfb")) {
1289 debug("request_region failed!\n");
1290 framebuffer_release(info);
1294 default_par->io_virt = ioremap_nocache(tridentfb_fix.mmio_start,
1295 tridentfb_fix.mmio_len);
1297 if (!default_par->io_virt) {
1298 debug("ioremap failed\n");
1303 /* setup framebuffer memory */
1304 tridentfb_fix.smem_start = pci_resource_start(dev, 0);
1305 tridentfb_fix.smem_len = get_memsize(default_par);
1307 if (!request_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len, "tridentfb")) {
1308 debug("request_mem_region failed!\n");
1309 disable_mmio(info->par);
1316 info->screen_base = ioremap_nocache(tridentfb_fix.smem_start,
1317 tridentfb_fix.smem_len);
1319 if (!info->screen_base) {
1320 debug("ioremap failed\n");
1325 output("%s board found\n", pci_name(dev));
1326 default_par->flatpanel = is_flatpanel(default_par);
1328 if (default_par->flatpanel)
1329 nativex = get_nativex(default_par);
1331 info->fix = tridentfb_fix;
1332 info->fbops = &tridentfb_ops;
1335 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1336 #ifdef CONFIG_FB_TRIDENT_ACCEL
1337 info->flags |= FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT;
1339 if (!fb_find_mode(&info->var, info,
1340 mode_option, NULL, 0, NULL, bpp)) {
1344 err = fb_alloc_cmap(&info->cmap, 256, 0);
1348 if (defaultaccel && default_par->init_accel)
1349 info->var.accel_flags |= FB_ACCELF_TEXT;
1351 info->var.accel_flags &= ~FB_ACCELF_TEXT;
1352 info->var.activate |= FB_ACTIVATE_NOW;
1353 info->device = &dev->dev;
1354 if (register_framebuffer(info) < 0) {
1355 printk(KERN_ERR "tridentfb: could not register Trident framebuffer\n");
1356 fb_dealloc_cmap(&info->cmap);
1360 output("fb%d: %s frame buffer device %dx%d-%dbpp\n",
1361 info->node, info->fix.id, info->var.xres,
1362 info->var.yres, info->var.bits_per_pixel);
1364 pci_set_drvdata(dev, info);
1368 if (info->screen_base)
1369 iounmap(info->screen_base);
1370 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1371 disable_mmio(info->par);
1373 if (default_par->io_virt)
1374 iounmap(default_par->io_virt);
1375 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1376 framebuffer_release(info);
1380 static void __devexit trident_pci_remove(struct pci_dev *dev)
1382 struct fb_info *info = pci_get_drvdata(dev);
1383 struct tridentfb_par *par = info->par;
1385 unregister_framebuffer(info);
1386 iounmap(par->io_virt);
1387 iounmap(info->screen_base);
1388 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1389 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1390 pci_set_drvdata(dev, NULL);
1391 framebuffer_release(info);
1394 /* List of boards that we are trying to support */
1395 static struct pci_device_id trident_devices[] = {
1396 {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1397 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1398 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1399 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1400 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1401 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1402 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1403 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1404 {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1405 {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1406 {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1407 {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1408 {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1409 {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1410 {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1411 {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1412 {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1413 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1414 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1415 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1419 MODULE_DEVICE_TABLE(pci, trident_devices);
1421 static struct pci_driver tridentfb_pci_driver = {
1422 .name = "tridentfb",
1423 .id_table = trident_devices,
1424 .probe = trident_pci_probe,
1425 .remove = __devexit_p(trident_pci_remove)
1429 * Parse user specified options (`video=trident:')
1431 * video=trident:800x600,bpp=16,noaccel
1434 static int __init tridentfb_setup(char *options)
1437 if (!options || !*options)
1439 while ((opt = strsep(&options, ",")) != NULL) {
1442 if (!strncmp(opt, "noaccel", 7))
1444 else if (!strncmp(opt, "fp", 2))
1446 else if (!strncmp(opt, "crt", 3))
1448 else if (!strncmp(opt, "bpp=", 4))
1449 bpp = simple_strtoul(opt + 4, NULL, 0);
1450 else if (!strncmp(opt, "center", 6))
1452 else if (!strncmp(opt, "stretch", 7))
1454 else if (!strncmp(opt, "memsize=", 8))
1455 memsize = simple_strtoul(opt + 8, NULL, 0);
1456 else if (!strncmp(opt, "memdiff=", 8))
1457 memdiff = simple_strtoul(opt + 8, NULL, 0);
1458 else if (!strncmp(opt, "nativex=", 8))
1459 nativex = simple_strtoul(opt + 8, NULL, 0);
1467 static int __init tridentfb_init(void)
1470 char *option = NULL;
1472 if (fb_get_options("tridentfb", &option))
1474 tridentfb_setup(option);
1476 output("Trident framebuffer %s initializing\n", VERSION);
1477 return pci_register_driver(&tridentfb_pci_driver);
1480 static void __exit tridentfb_exit(void)
1482 pci_unregister_driver(&tridentfb_pci_driver);
1485 module_init(tridentfb_init);
1486 module_exit(tridentfb_exit);
1488 MODULE_AUTHOR("Jani Monoses <jani@iv.ro>");
1489 MODULE_DESCRIPTION("Framebuffer driver for Trident cards");
1490 MODULE_LICENSE("GPL");