2 * Frame buffer driver for Trident TGUI, Blade and Image series
4 * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro>
7 * CREDITS:(in order of appearance)
8 * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video
9 * Special thanks ;) to Mattia Crivellini <tia@mclink.it>
10 * much inspired by the XFree86 4.x Trident driver sources
11 * by Alan Hourihane the FreeVGA project
12 * Francesco Salvestrini <salvestrini@users.sf.net> XP support,
15 * timing value tweaking so it looks good on every monitor in every mode
18 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/pci.h>
23 #include <linux/delay.h>
24 #include <video/vga.h>
25 #include <video/trident.h>
27 struct tridentfb_par {
28 void __iomem *io_virt; /* iospace virtual memory address */
32 void (*init_accel) (struct tridentfb_par *, int, int);
33 void (*wait_engine) (struct tridentfb_par *);
35 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
37 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
38 unsigned char eng_oper; /* engine operation... */
41 static struct fb_ops tridentfb_ops;
43 static struct fb_fix_screeninfo tridentfb_fix = {
45 .type = FB_TYPE_PACKED_PIXELS,
47 .visual = FB_VISUAL_PSEUDOCOLOR,
48 .accel = FB_ACCEL_NONE,
51 /* defaults which are normally overriden by user values */
54 static char *mode_option __devinitdata = "640x480-8@60";
55 static int bpp __devinitdata = 8;
57 static int noaccel __devinitdata;
62 static int fp __devinitdata;
63 static int crt __devinitdata;
65 static int memsize __devinitdata;
66 static int memdiff __devinitdata;
69 module_param(mode_option, charp, 0);
70 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
71 module_param_named(mode, mode_option, charp, 0);
72 MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
73 module_param(bpp, int, 0);
74 module_param(center, int, 0);
75 module_param(stretch, int, 0);
76 module_param(noaccel, int, 0);
77 module_param(memsize, int, 0);
78 module_param(memdiff, int, 0);
79 module_param(nativex, int, 0);
80 module_param(fp, int, 0);
81 MODULE_PARM_DESC(fp, "Define if flatpanel is connected");
82 module_param(crt, int, 0);
83 MODULE_PARM_DESC(crt, "Define if CRT is connected");
85 static inline int is_oldclock(int id)
87 return (id == TGUI9440) ||
92 static inline int is_oldprotect(int id)
94 return is_oldclock(id) ||
95 (id == PROVIDIA9685) ||
100 static inline int is_blade(int id)
102 return (id == BLADE3D) ||
103 (id == CYBERBLADEE4) ||
104 (id == CYBERBLADEi7) ||
105 (id == CYBERBLADEi7D) ||
106 (id == CYBERBLADEi1) ||
107 (id == CYBERBLADEi1D) ||
108 (id == CYBERBLADEAi1) ||
109 (id == CYBERBLADEAi1D);
112 static inline int is_xp(int id)
114 return (id == CYBERBLADEXPAi1) ||
115 (id == CYBERBLADEXPm8) ||
116 (id == CYBERBLADEXPm16);
119 static inline int is3Dchip(int id)
121 return is_blade(id) || is_xp(id) ||
122 (id == CYBER9397) || (id == CYBER9397DVD) ||
123 (id == CYBER9520) || (id == CYBER9525DVD) ||
124 (id == IMAGE975) || (id == IMAGE985);
127 static inline int iscyber(int id)
143 case CYBERBLADEXPAi1:
147 case CYBERBLADEi7: /* VIA MPV4 integrated version */
149 /* case CYBERBLDAEXPm8: Strange */
150 /* case CYBERBLDAEXPm16: Strange */
155 static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)
157 fb_writeb(val, p->io_virt + reg);
160 static inline u8 t_inb(struct tridentfb_par *p, u16 reg)
162 return fb_readb(p->io_virt + reg);
165 static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v)
167 fb_writel(v, par->io_virt + r);
170 static inline u32 readmmr(struct tridentfb_par *par, u16 r)
172 return fb_readl(par->io_virt + r);
176 * Blade specific acceleration.
179 #define point(x, y) ((y) << 16 | (x))
181 static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp)
183 int v1 = (pitch >> 3) << 20;
184 int tmp = bpp == 24 ? 2 : (bpp >> 4);
185 int v2 = v1 | (tmp << 29);
187 writemmr(par, 0x21C0, v2);
188 writemmr(par, 0x21C4, v2);
189 writemmr(par, 0x21B8, v2);
190 writemmr(par, 0x21BC, v2);
191 writemmr(par, 0x21D0, v1);
192 writemmr(par, 0x21D4, v1);
193 writemmr(par, 0x21C8, v1);
194 writemmr(par, 0x21CC, v1);
195 writemmr(par, 0x216C, 0);
198 static void blade_wait_engine(struct tridentfb_par *par)
200 while (readmmr(par, STATUS) & 0xFA800000)
204 static void blade_fill_rect(struct tridentfb_par *par,
205 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
207 writemmr(par, COLOR, c);
208 writemmr(par, ROP, rop ? ROP_X : ROP_S);
209 writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
211 writemmr(par, DST1, point(x, y));
212 writemmr(par, DST2, point(x + w - 1, y + h - 1));
215 static void blade_copy_rect(struct tridentfb_par *par,
216 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
219 u32 s1 = point(x1, y1);
220 u32 s2 = point(x1 + w - 1, y1 + h - 1);
221 u32 d1 = point(x2, y2);
222 u32 d2 = point(x2 + w - 1, y2 + h - 1);
224 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
227 writemmr(par, ROP, ROP_S);
228 writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
230 writemmr(par, SRC1, direction ? s2 : s1);
231 writemmr(par, SRC2, direction ? s1 : s2);
232 writemmr(par, DST1, direction ? d2 : d1);
233 writemmr(par, DST2, direction ? d1 : d2);
237 * BladeXP specific acceleration functions
240 static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp)
242 unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
243 int v1 = pitch << (bpp == 24 ? 20 : (18 + x));
245 switch (pitch << (bpp >> 3)) {
261 t_outb(par, x, 0x2125);
263 par->eng_oper = x | 0x40;
265 writemmr(par, 0x2154, v1);
266 writemmr(par, 0x2150, v1);
267 t_outb(par, 3, 0x2126);
270 static void xp_wait_engine(struct tridentfb_par *par)
275 while (t_inb(par, STATUS) & 0x80) {
277 if (count == 10000000) {
283 t_outb(par, 0x00, STATUS);
291 static void xp_fill_rect(struct tridentfb_par *par,
292 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
294 writemmr(par, 0x2127, ROP_P);
295 writemmr(par, 0x2158, c);
296 writemmr(par, DRAWFL, 0x4000);
297 writemmr(par, OLDDIM, point(h, w));
298 writemmr(par, OLDDST, point(y, x));
299 t_outb(par, 0x01, OLDCMD);
300 t_outb(par, par->eng_oper, 0x2125);
303 static void xp_copy_rect(struct tridentfb_par *par,
304 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
306 u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
307 int direction = 0x0004;
309 if ((x1 < x2) && (y1 == y2)) {
327 writemmr(par, DRAWFL, direction);
328 t_outb(par, ROP_S, 0x2127);
329 writemmr(par, OLDSRC, point(y1_tmp, x1_tmp));
330 writemmr(par, OLDDST, point(y2_tmp, x2_tmp));
331 writemmr(par, OLDDIM, point(h, w));
332 t_outb(par, 0x01, OLDCMD);
336 * Image specific acceleration functions
338 static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp)
340 int tmp = bpp == 24 ? 2: (bpp >> 4);
342 writemmr(par, 0x2120, 0xF0000000);
343 writemmr(par, 0x2120, 0x40000000 | tmp);
344 writemmr(par, 0x2120, 0x80000000);
345 writemmr(par, 0x2144, 0x00000000);
346 writemmr(par, 0x2148, 0x00000000);
347 writemmr(par, 0x2150, 0x00000000);
348 writemmr(par, 0x2154, 0x00000000);
349 writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch);
350 writemmr(par, 0x216C, 0x00000000);
351 writemmr(par, 0x2170, 0x00000000);
352 writemmr(par, 0x217C, 0x00000000);
353 writemmr(par, 0x2120, 0x10000000);
354 writemmr(par, 0x2130, (2047 << 16) | 2047);
357 static void image_wait_engine(struct tridentfb_par *par)
359 while (readmmr(par, 0x2164) & 0xF0000000)
363 static void image_fill_rect(struct tridentfb_par *par,
364 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
366 writemmr(par, 0x2120, 0x80000000);
367 writemmr(par, 0x2120, 0x90000000 | ROP_S);
369 writemmr(par, 0x2144, c);
371 writemmr(par, DST1, point(x, y));
372 writemmr(par, DST2, point(x + w - 1, y + h - 1));
374 writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
377 static void image_copy_rect(struct tridentfb_par *par,
378 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
381 u32 s1 = point(x1, y1);
382 u32 s2 = point(x1 + w - 1, y1 + h - 1);
383 u32 d1 = point(x2, y2);
384 u32 d2 = point(x2 + w - 1, y2 + h - 1);
386 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
389 writemmr(par, 0x2120, 0x80000000);
390 writemmr(par, 0x2120, 0x90000000 | ROP_S);
392 writemmr(par, SRC1, direction ? s2 : s1);
393 writemmr(par, SRC2, direction ? s1 : s2);
394 writemmr(par, DST1, direction ? d2 : d1);
395 writemmr(par, DST2, direction ? d1 : d2);
396 writemmr(par, 0x2124,
397 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction);
401 * TGUI 9440/96XX acceleration
404 static void tgui_init_accel(struct tridentfb_par *par, int pitch, int bpp)
406 unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
408 /* disable clipping */
409 writemmr(par, 0x2148, 0);
410 writemmr(par, 0x214C, point(4095, 2047));
412 switch ((pitch * bpp) / 8) {
428 fb_writew(x, par->io_virt + 0x2122);
431 static void tgui_fill_rect(struct tridentfb_par *par,
432 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
434 t_outb(par, ROP_P, 0x2127);
435 writemmr(par, OLDCLR, c);
436 writemmr(par, DRAWFL, 0x4020);
437 writemmr(par, OLDDIM, point(w - 1, h - 1));
438 writemmr(par, OLDDST, point(x, y));
439 t_outb(par, 1, OLDCMD);
442 static void tgui_copy_rect(struct tridentfb_par *par,
443 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
446 u16 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
448 if ((x1 < x2) && (y1 == y2)) {
466 writemmr(par, DRAWFL, 0x4 | flags);
467 t_outb(par, ROP_S, 0x2127);
468 writemmr(par, OLDSRC, point(x1_tmp, y1_tmp));
469 writemmr(par, OLDDST, point(x2_tmp, y2_tmp));
470 writemmr(par, OLDDIM, point(w - 1, h - 1));
471 t_outb(par, 1, OLDCMD);
475 * Accel functions called by the upper layers
477 #ifdef CONFIG_FB_TRIDENT_ACCEL
478 static void tridentfb_fillrect(struct fb_info *info,
479 const struct fb_fillrect *fr)
481 struct tridentfb_par *par = info->par;
484 if (info->flags & FBINFO_HWACCEL_DISABLED) {
485 cfb_fillrect(info, fr);
488 if (info->var.bits_per_pixel == 8) {
493 col = ((u32 *)(info->pseudo_palette))[fr->color];
495 par->wait_engine(par);
496 par->fill_rect(par, fr->dx, fr->dy, fr->width,
497 fr->height, col, fr->rop);
500 static void tridentfb_copyarea(struct fb_info *info,
501 const struct fb_copyarea *ca)
503 struct tridentfb_par *par = info->par;
505 if (info->flags & FBINFO_HWACCEL_DISABLED) {
506 cfb_copyarea(info, ca);
509 par->wait_engine(par);
510 par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy,
511 ca->width, ca->height);
514 static int tridentfb_sync(struct fb_info *info)
516 struct tridentfb_par *par = info->par;
518 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
519 par->wait_engine(par);
523 #define tridentfb_fillrect cfb_fillrect
524 #define tridentfb_copyarea cfb_copyarea
525 #endif /* CONFIG_FB_TRIDENT_ACCEL */
528 * Hardware access functions
531 static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
533 return vga_mm_rcrt(par->io_virt, reg);
536 static inline void write3X4(struct tridentfb_par *par, int reg,
539 vga_mm_wcrt(par->io_virt, reg, val);
542 static inline unsigned char read3CE(struct tridentfb_par *par,
545 return vga_mm_rgfx(par->io_virt, reg);
548 static inline void writeAttr(struct tridentfb_par *par, int reg,
551 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
552 vga_mm_wattr(par->io_virt, reg, val);
555 static inline void write3CE(struct tridentfb_par *par, int reg,
558 vga_mm_wgfx(par->io_virt, reg, val);
561 static void enable_mmio(void)
566 /* Unprotect registers */
567 vga_io_wseq(NewMode1, 0x80);
571 outb(inb(0x3D5) | 0x01, 0x3D5);
574 static void disable_mmio(struct tridentfb_par *par)
577 vga_mm_rseq(par->io_virt, 0x0B);
579 /* Unprotect registers */
580 vga_mm_wseq(par->io_virt, NewMode1, 0x80);
583 t_outb(par, PCIReg, 0x3D4);
584 t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);
587 static inline void crtc_unlock(struct tridentfb_par *par)
589 write3X4(par, VGA_CRTC_V_SYNC_END,
590 read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F);
593 /* Return flat panel's maximum x resolution */
594 static int __devinit get_nativex(struct tridentfb_par *par)
601 tmp = (read3CE(par, VertStretch) >> 4) & 3;
622 output("%dx%d flat panel found\n", x, y);
627 static inline void set_lwidth(struct tridentfb_par *par, int width)
629 write3X4(par, VGA_CRTC_OFFSET, width & 0xFF);
630 write3X4(par, AddColReg,
631 (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
634 /* For resolutions smaller than FP resolution stretch */
635 static void screen_stretch(struct tridentfb_par *par)
637 if (par->chip_id != CYBERBLADEXPAi1)
638 write3CE(par, BiosReg, 0);
640 write3CE(par, BiosReg, 8);
641 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1);
642 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1);
645 /* For resolutions smaller than FP resolution center */
646 static inline void screen_center(struct tridentfb_par *par)
648 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80);
649 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80);
652 /* Address of first shown pixel in display memory */
653 static void set_screen_start(struct tridentfb_par *par, int base)
656 write3X4(par, VGA_CRTC_START_LO, base & 0xFF);
657 write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8);
658 tmp = read3X4(par, CRTCModuleTest) & 0xDF;
659 write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
660 tmp = read3X4(par, CRTHiOrd) & 0xF8;
661 write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17));
664 /* Set dotclock frequency */
665 static void set_vclk(struct tridentfb_par *par, unsigned long freq)
668 unsigned long fi, d, di;
669 unsigned char best_m = 0, best_n = 0, best_k = 0;
670 unsigned char hi, lo;
673 for (k = 1; k >= 0; k--)
674 for (m = 0; m < 32; m++) {
676 for (n = (n < 0 ? 0 : n); n < 122; n++) {
677 fi = ((14318l * (n + 8)) / (m + 2)) >> k;
690 if (is_oldclock(par->chip_id)) {
691 lo = best_n | (best_m << 7);
692 hi = (best_m >> 1) | (best_k << 4);
695 hi = best_m | (best_k << 6);
698 if (is3Dchip(par->chip_id)) {
699 vga_mm_wseq(par->io_virt, ClockHigh, hi);
700 vga_mm_wseq(par->io_virt, ClockLow, lo);
702 t_outb(par, lo, 0x43C8);
703 t_outb(par, hi, 0x43C9);
705 debug("VCLK = %X %X\n", hi, lo);
708 /* Set number of lines for flat panels*/
709 static void set_number_of_lines(struct tridentfb_par *par, int lines)
711 int tmp = read3CE(par, CyberEnhance) & 0x8F;
714 else if (lines > 768)
716 else if (lines > 600)
718 else if (lines > 480)
720 write3CE(par, CyberEnhance, tmp);
724 * If we see that FP is active we assume we have one.
725 * Otherwise we have a CRT display. User can override.
727 static int __devinit is_flatpanel(struct tridentfb_par *par)
731 if (crt || !iscyber(par->chip_id))
733 return (read3CE(par, FPConfig) & 0x10) ? 1 : 0;
736 /* Try detecting the video memory size */
737 static unsigned int __devinit get_memsize(struct tridentfb_par *par)
739 unsigned char tmp, tmp2;
742 /* If memory size provided by user */
746 switch (par->chip_id) {
751 tmp = read3X4(par, SPR) & 0x0F;
767 k = 10 * Mb; /* XP */
773 k = 12 * Mb; /* XP */
776 k = 14 * Mb; /* XP */
779 k = 16 * Mb; /* XP */
783 tmp2 = vga_mm_rseq(par->io_virt, 0xC1);
813 output("framebuffer size = %d Kb\n", k / Kb);
817 /* See if we can handle the video mode described in var */
818 static int tridentfb_check_var(struct fb_var_screeninfo *var,
819 struct fb_info *info)
821 struct tridentfb_par *par = info->par;
822 int bpp = var->bits_per_pixel;
824 int ramdac = 230000; /* 230MHz for most 3D chips */
827 /* check color depth */
829 bpp = var->bits_per_pixel = 32;
830 if (bpp != 8 && bpp != 16 && bpp != 32)
832 if (par->chip_id == TGUI9440 && bpp == 32)
834 /* check whether resolution fits on panel and in memory */
835 if (par->flatpanel && nativex && var->xres > nativex)
837 /* various resolution checks */
838 var->xres = (var->xres + 7) & ~0x7;
839 if (var->xres > var->xres_virtual)
840 var->xres_virtual = var->xres;
841 if (var->yres > var->yres_virtual)
842 var->yres_virtual = var->yres;
843 if (var->xres_virtual > 4095 || var->yres > 2048)
845 /* prevent from position overflow for acceleration */
846 if (var->yres_virtual > 0xffff)
848 line_length = var->xres_virtual * bpp / 8;
850 if (!is3Dchip(par->chip_id) &&
851 !(info->flags & FBINFO_HWACCEL_DISABLED)) {
852 /* acceleration requires line length to be power of 2 */
853 if (line_length <= 512)
854 var->xres_virtual = 512 * 8 / bpp;
855 else if (line_length <= 1024)
856 var->xres_virtual = 1024 * 8 / bpp;
857 else if (line_length <= 2048)
858 var->xres_virtual = 2048 * 8 / bpp;
859 else if (line_length <= 4096)
860 var->xres_virtual = 4096 * 8 / bpp;
861 else if (line_length <= 8192)
862 var->xres_virtual = 8192 * 8 / bpp;
866 line_length = var->xres_virtual * bpp / 8;
869 if (var->yres > var->yres_virtual)
870 var->yres_virtual = var->yres;
871 if (line_length * var->yres_virtual > info->fix.smem_len)
877 var->green.offset = 0;
878 var->blue.offset = 0;
880 var->green.length = 6;
881 var->blue.length = 6;
884 var->red.offset = 11;
885 var->green.offset = 5;
886 var->blue.offset = 0;
888 var->green.length = 6;
889 var->blue.length = 5;
892 var->red.offset = 16;
893 var->green.offset = 8;
894 var->blue.offset = 0;
896 var->green.length = 8;
897 var->blue.length = 8;
903 if (is_xp(par->chip_id))
906 switch (par->chip_id) {
908 ramdac = (bpp >= 16) ? 45000 : 90000;
922 /* The clock is doubled for 32 bpp */
926 if (PICOS2KHZ(var->pixclock) > ramdac)
935 /* Pan the display */
936 static int tridentfb_pan_display(struct fb_var_screeninfo *var,
937 struct fb_info *info)
939 struct tridentfb_par *par = info->par;
943 offset = (var->xoffset + (var->yoffset * var->xres_virtual))
944 * var->bits_per_pixel / 32;
945 info->var.xoffset = var->xoffset;
946 info->var.yoffset = var->yoffset;
947 set_screen_start(par, offset);
952 static inline void shadowmode_on(struct tridentfb_par *par)
954 write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81);
957 static inline void shadowmode_off(struct tridentfb_par *par)
959 write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E);
962 /* Set the hardware to the requested video mode */
963 static int tridentfb_set_par(struct fb_info *info)
965 struct tridentfb_par *par = info->par;
966 u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend;
967 u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend;
968 struct fb_var_screeninfo *var = &info->var;
969 int bpp = var->bits_per_pixel;
974 hdispend = var->xres / 8 - 1;
975 hsyncstart = (var->xres + var->right_margin) / 8;
976 hsyncend = (var->xres + var->right_margin + var->hsync_len) / 8;
977 htotal = (var->xres + var->left_margin + var->right_margin +
978 var->hsync_len) / 8 - 5;
979 hblankstart = hdispend + 1;
980 hblankend = htotal + 3;
982 vdispend = var->yres - 1;
983 vsyncstart = var->yres + var->lower_margin;
984 vsyncend = vsyncstart + var->vsync_len;
985 vtotal = var->upper_margin + vsyncend - 2;
986 vblankstart = vdispend + 1;
989 if (info->var.vmode & FB_VMODE_INTERLACED) {
999 write3CE(par, CyberControl, 8);
1001 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
1003 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
1006 if (par->flatpanel && var->xres < nativex) {
1008 * on flat panels with native size larger
1009 * than requested resolution decide whether
1010 * we stretch or center
1012 t_outb(par, tmp | 0xC0, VGA_MIS_W);
1019 screen_stretch(par);
1022 t_outb(par, tmp, VGA_MIS_W);
1023 write3CE(par, CyberControl, 8);
1026 /* vertical timing values */
1027 write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF);
1028 write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF);
1029 write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF);
1030 write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F));
1031 write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF);
1032 write3X4(par, VGA_CRTC_V_BLANK_END, vblankend & 0xFF);
1034 /* horizontal timing values */
1035 write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF);
1036 write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF);
1037 write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF);
1038 write3X4(par, VGA_CRTC_H_SYNC_END,
1039 (hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
1040 write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF);
1041 write3X4(par, VGA_CRTC_H_BLANK_END, hblankend & 0x1F);
1043 /* higher bits of vertical timing values */
1045 if (vtotal & 0x100) tmp |= 0x01;
1046 if (vdispend & 0x100) tmp |= 0x02;
1047 if (vsyncstart & 0x100) tmp |= 0x04;
1048 if (vblankstart & 0x100) tmp |= 0x08;
1050 if (vtotal & 0x200) tmp |= 0x20;
1051 if (vdispend & 0x200) tmp |= 0x40;
1052 if (vsyncstart & 0x200) tmp |= 0x80;
1053 write3X4(par, VGA_CRTC_OVERFLOW, tmp);
1055 tmp = read3X4(par, CRTHiOrd) & 0x07;
1056 tmp |= 0x08; /* line compare bit 10 */
1057 if (vtotal & 0x400) tmp |= 0x80;
1058 if (vblankstart & 0x400) tmp |= 0x40;
1059 if (vsyncstart & 0x400) tmp |= 0x20;
1060 if (vdispend & 0x400) tmp |= 0x10;
1061 write3X4(par, CRTHiOrd, tmp);
1063 tmp = (htotal >> 8) & 0x01;
1064 tmp |= (hdispend >> 7) & 0x02;
1065 tmp |= (hsyncstart >> 5) & 0x08;
1066 tmp |= (hblankstart >> 4) & 0x10;
1067 write3X4(par, HorizOverflow, tmp);
1070 if (vblankstart & 0x200) tmp |= 0x20;
1071 //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */
1072 write3X4(par, VGA_CRTC_MAX_SCAN, tmp);
1074 write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF);
1075 write3X4(par, VGA_CRTC_PRESET_ROW, 0);
1076 write3X4(par, VGA_CRTC_MODE, 0xC3);
1078 write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */
1080 tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80;
1081 /* enable access extended memory */
1082 write3X4(par, CRTCModuleTest, tmp);
1083 tmp = read3CE(par, MiscIntContReg) & ~0x4;
1084 if (info->var.vmode & FB_VMODE_INTERLACED)
1086 write3CE(par, MiscIntContReg, tmp);
1088 /* enable GE for text acceleration */
1089 write3X4(par, GraphEngReg, 0x80);
1106 write3X4(par, PixelBusReg, tmp);
1108 tmp = read3X4(par, DRAMControl);
1109 if (!is_oldprotect(par->chip_id))
1111 if (iscyber(par->chip_id))
1113 write3X4(par, DRAMControl, tmp); /* both IO, linear enable */
1115 write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40);
1116 if (!is_xp(par->chip_id))
1117 write3X4(par, Performance, read3X4(par, Performance) | 0x10);
1118 /* MMIO & PCI read and write burst enable */
1119 if (par->chip_id != TGUI9440)
1120 write3X4(par, PCIReg, read3X4(par, PCIReg) | 0x06);
1122 vga_mm_wseq(par->io_virt, 0, 3);
1123 vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */
1124 /* enable 4 maps because needed in chain4 mode */
1125 vga_mm_wseq(par->io_virt, 2, 0x0F);
1126 vga_mm_wseq(par->io_virt, 3, 0);
1127 vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */
1129 /* convert from picoseconds to kHz */
1130 vclk = PICOS2KHZ(info->var.pixclock);
1132 /* divide clock by 2 if 32bpp chain4 mode display and CPU path */
1133 tmp = read3CE(par, MiscExtFunc) & 0xF0;
1134 if (bpp == 32 || (par->chip_id == TGUI9440 && bpp == 16)) {
1138 set_vclk(par, vclk);
1139 write3CE(par, MiscExtFunc, tmp | 0x12);
1140 write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */
1141 write3CE(par, 0x6, 0x05); /* graphics mode */
1142 write3CE(par, 0x7, 0x0F); /* planes? */
1144 /* graphics mode and support 256 color modes */
1145 writeAttr(par, 0x10, 0x41);
1146 writeAttr(par, 0x12, 0x0F); /* planes */
1147 writeAttr(par, 0x13, 0); /* horizontal pel panning */
1150 for (tmp = 0; tmp < 0x10; tmp++)
1151 writeAttr(par, tmp, tmp);
1152 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
1153 t_outb(par, 0x20, VGA_ATT_W); /* enable attr */
1168 t_inb(par, VGA_PEL_IW);
1169 t_inb(par, VGA_PEL_MSK);
1170 t_inb(par, VGA_PEL_MSK);
1171 t_inb(par, VGA_PEL_MSK);
1172 t_inb(par, VGA_PEL_MSK);
1173 t_outb(par, tmp, VGA_PEL_MSK);
1174 t_inb(par, VGA_PEL_IW);
1177 set_number_of_lines(par, info->var.yres);
1178 info->fix.line_length = info->var.xres_virtual * bpp / 8;
1179 set_lwidth(par, info->fix.line_length / 8);
1181 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1182 par->init_accel(par, info->var.xres_virtual, bpp);
1184 info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1185 info->cmap.len = (bpp == 8) ? 256 : 16;
1190 /* Set one color register */
1191 static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1192 unsigned blue, unsigned transp,
1193 struct fb_info *info)
1195 int bpp = info->var.bits_per_pixel;
1196 struct tridentfb_par *par = info->par;
1198 if (regno >= info->cmap.len)
1202 t_outb(par, 0xFF, VGA_PEL_MSK);
1203 t_outb(par, regno, VGA_PEL_IW);
1205 t_outb(par, red >> 10, VGA_PEL_D);
1206 t_outb(par, green >> 10, VGA_PEL_D);
1207 t_outb(par, blue >> 10, VGA_PEL_D);
1209 } else if (regno < 16) {
1210 if (bpp == 16) { /* RGB 565 */
1213 col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
1214 ((blue & 0xF800) >> 11);
1216 ((u32 *)(info->pseudo_palette))[regno] = col;
1217 } else if (bpp == 32) /* ARGB 8888 */
1218 ((u32 *)info->pseudo_palette)[regno] =
1219 ((transp & 0xFF00) << 16) |
1220 ((red & 0xFF00) << 8) |
1221 ((green & 0xFF00)) |
1222 ((blue & 0xFF00) >> 8);
1225 /* debug("exit\n"); */
1229 /* Try blanking the screen. For flat panels it does nothing */
1230 static int tridentfb_blank(int blank_mode, struct fb_info *info)
1232 unsigned char PMCont, DPMSCont;
1233 struct tridentfb_par *par = info->par;
1238 t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */
1239 PMCont = t_inb(par, 0x83C6) & 0xFC;
1240 DPMSCont = read3CE(par, PowerStatus) & 0xFC;
1241 switch (blank_mode) {
1242 case FB_BLANK_UNBLANK:
1243 /* Screen: On, HSync: On, VSync: On */
1244 case FB_BLANK_NORMAL:
1245 /* Screen: Off, HSync: On, VSync: On */
1249 case FB_BLANK_HSYNC_SUSPEND:
1250 /* Screen: Off, HSync: Off, VSync: On */
1254 case FB_BLANK_VSYNC_SUSPEND:
1255 /* Screen: Off, HSync: On, VSync: Off */
1259 case FB_BLANK_POWERDOWN:
1260 /* Screen: Off, HSync: Off, VSync: Off */
1266 write3CE(par, PowerStatus, DPMSCont);
1267 t_outb(par, 4, 0x83C8);
1268 t_outb(par, PMCont, 0x83C6);
1272 /* let fbcon do a softblank for us */
1273 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1276 static struct fb_ops tridentfb_ops = {
1277 .owner = THIS_MODULE,
1278 .fb_setcolreg = tridentfb_setcolreg,
1279 .fb_pan_display = tridentfb_pan_display,
1280 .fb_blank = tridentfb_blank,
1281 .fb_check_var = tridentfb_check_var,
1282 .fb_set_par = tridentfb_set_par,
1283 .fb_fillrect = tridentfb_fillrect,
1284 .fb_copyarea = tridentfb_copyarea,
1285 .fb_imageblit = cfb_imageblit,
1286 #ifdef CONFIG_FB_TRIDENT_ACCEL
1287 .fb_sync = tridentfb_sync,
1291 static int __devinit trident_pci_probe(struct pci_dev *dev,
1292 const struct pci_device_id *id)
1295 unsigned char revision;
1296 struct fb_info *info;
1297 struct tridentfb_par *default_par;
1301 err = pci_enable_device(dev);
1305 info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev);
1308 default_par = info->par;
1310 chip_id = id->device;
1312 if (chip_id == CYBERBLADEi1)
1313 output("*** Please do use cyblafb, Cyberblade/i1 support "
1314 "will soon be removed from tridentfb!\n");
1316 #ifndef CONFIG_FB_TRIDENT_ACCEL
1320 /* If PCI id is 0x9660 then further detect chip type */
1322 if (chip_id == TGUI9660) {
1323 revision = vga_io_rseq(RevisionID);
1327 chip_id = PROVIDIA9685;
1331 chip_id = CYBER9397;
1334 chip_id = CYBER9397DVD;
1343 chip_id = CYBER9385;
1346 chip_id = CYBER9382;
1349 chip_id = CYBER9388;
1356 chip3D = is3Dchip(chip_id);
1358 if (is_xp(chip_id)) {
1359 default_par->init_accel = xp_init_accel;
1360 default_par->wait_engine = xp_wait_engine;
1361 default_par->fill_rect = xp_fill_rect;
1362 default_par->copy_rect = xp_copy_rect;
1363 tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADEXP;
1364 } else if (is_blade(chip_id)) {
1365 default_par->init_accel = blade_init_accel;
1366 default_par->wait_engine = blade_wait_engine;
1367 default_par->fill_rect = blade_fill_rect;
1368 default_par->copy_rect = blade_copy_rect;
1369 tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADE3D;
1370 } else if (chip3D) { /* 3DImage family left */
1371 default_par->init_accel = image_init_accel;
1372 default_par->wait_engine = image_wait_engine;
1373 default_par->fill_rect = image_fill_rect;
1374 default_par->copy_rect = image_copy_rect;
1375 tridentfb_fix.accel = FB_ACCEL_TRIDENT_3DIMAGE;
1376 } else { /* TGUI 9440/96XX family */
1377 default_par->init_accel = tgui_init_accel;
1378 default_par->wait_engine = xp_wait_engine;
1379 default_par->fill_rect = tgui_fill_rect;
1380 default_par->copy_rect = tgui_copy_rect;
1381 tridentfb_fix.accel = FB_ACCEL_TRIDENT_TGUI;
1384 default_par->chip_id = chip_id;
1386 /* setup MMIO region */
1387 tridentfb_fix.mmio_start = pci_resource_start(dev, 1);
1388 tridentfb_fix.mmio_len = pci_resource_len(dev, 1);
1390 if (!request_mem_region(tridentfb_fix.mmio_start,
1391 tridentfb_fix.mmio_len, "tridentfb")) {
1392 debug("request_region failed!\n");
1393 framebuffer_release(info);
1397 default_par->io_virt = ioremap_nocache(tridentfb_fix.mmio_start,
1398 tridentfb_fix.mmio_len);
1400 if (!default_par->io_virt) {
1401 debug("ioremap failed\n");
1408 /* setup framebuffer memory */
1409 tridentfb_fix.smem_start = pci_resource_start(dev, 0);
1410 tridentfb_fix.smem_len = get_memsize(default_par);
1412 if (!request_mem_region(tridentfb_fix.smem_start,
1413 tridentfb_fix.smem_len, "tridentfb")) {
1414 debug("request_mem_region failed!\n");
1415 disable_mmio(info->par);
1420 info->screen_base = ioremap_nocache(tridentfb_fix.smem_start,
1421 tridentfb_fix.smem_len);
1423 if (!info->screen_base) {
1424 debug("ioremap failed\n");
1429 default_par->flatpanel = is_flatpanel(default_par);
1431 if (default_par->flatpanel)
1432 nativex = get_nativex(default_par);
1434 info->fix = tridentfb_fix;
1435 info->fbops = &tridentfb_ops;
1436 info->pseudo_palette = default_par->pseudo_pal;
1438 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1439 if (!noaccel && default_par->init_accel) {
1440 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1441 info->flags |= FBINFO_HWACCEL_COPYAREA;
1442 info->flags |= FBINFO_HWACCEL_FILLRECT;
1444 info->flags |= FBINFO_HWACCEL_DISABLED;
1446 if (!fb_find_mode(&info->var, info,
1447 mode_option, NULL, 0, NULL, bpp)) {
1451 err = fb_alloc_cmap(&info->cmap, 256, 0);
1455 info->var.activate |= FB_ACTIVATE_NOW;
1456 info->device = &dev->dev;
1457 if (register_framebuffer(info) < 0) {
1458 printk(KERN_ERR "tridentfb: could not register framebuffer\n");
1459 fb_dealloc_cmap(&info->cmap);
1463 output("fb%d: %s frame buffer device %dx%d-%dbpp\n",
1464 info->node, info->fix.id, info->var.xres,
1465 info->var.yres, info->var.bits_per_pixel);
1467 pci_set_drvdata(dev, info);
1471 if (info->screen_base)
1472 iounmap(info->screen_base);
1473 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1474 disable_mmio(info->par);
1476 if (default_par->io_virt)
1477 iounmap(default_par->io_virt);
1478 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1479 framebuffer_release(info);
1483 static void __devexit trident_pci_remove(struct pci_dev *dev)
1485 struct fb_info *info = pci_get_drvdata(dev);
1486 struct tridentfb_par *par = info->par;
1488 unregister_framebuffer(info);
1489 iounmap(par->io_virt);
1490 iounmap(info->screen_base);
1491 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1492 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1493 pci_set_drvdata(dev, NULL);
1494 framebuffer_release(info);
1497 /* List of boards that we are trying to support */
1498 static struct pci_device_id trident_devices[] = {
1499 {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1500 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1501 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1502 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1503 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1504 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1505 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1506 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1507 {PCI_VENDOR_ID_TRIDENT, TGUI9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1508 {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1509 {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1510 {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1511 {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1512 {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1513 {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1514 {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1515 {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1516 {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1517 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1518 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1519 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1523 MODULE_DEVICE_TABLE(pci, trident_devices);
1525 static struct pci_driver tridentfb_pci_driver = {
1526 .name = "tridentfb",
1527 .id_table = trident_devices,
1528 .probe = trident_pci_probe,
1529 .remove = __devexit_p(trident_pci_remove)
1533 * Parse user specified options (`video=trident:')
1535 * video=trident:800x600,bpp=16,noaccel
1538 static int __init tridentfb_setup(char *options)
1541 if (!options || !*options)
1543 while ((opt = strsep(&options, ",")) != NULL) {
1546 if (!strncmp(opt, "noaccel", 7))
1548 else if (!strncmp(opt, "fp", 2))
1550 else if (!strncmp(opt, "crt", 3))
1552 else if (!strncmp(opt, "bpp=", 4))
1553 bpp = simple_strtoul(opt + 4, NULL, 0);
1554 else if (!strncmp(opt, "center", 6))
1556 else if (!strncmp(opt, "stretch", 7))
1558 else if (!strncmp(opt, "memsize=", 8))
1559 memsize = simple_strtoul(opt + 8, NULL, 0);
1560 else if (!strncmp(opt, "memdiff=", 8))
1561 memdiff = simple_strtoul(opt + 8, NULL, 0);
1562 else if (!strncmp(opt, "nativex=", 8))
1563 nativex = simple_strtoul(opt + 8, NULL, 0);
1571 static int __init tridentfb_init(void)
1574 char *option = NULL;
1576 if (fb_get_options("tridentfb", &option))
1578 tridentfb_setup(option);
1580 return pci_register_driver(&tridentfb_pci_driver);
1583 static void __exit tridentfb_exit(void)
1585 pci_unregister_driver(&tridentfb_pci_driver);
1588 module_init(tridentfb_init);
1589 module_exit(tridentfb_exit);
1591 MODULE_AUTHOR("Jani Monoses <jani@iv.ro>");
1592 MODULE_DESCRIPTION("Framebuffer driver for Trident cards");
1593 MODULE_LICENSE("GPL");