2 * Frame buffer driver for Trident TGUI, Blade and Image series
4 * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro>
7 * CREDITS:(in order of appearance)
8 * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video
9 * Special thanks ;) to Mattia Crivellini <tia@mclink.it>
10 * much inspired by the XFree86 4.x Trident driver sources
11 * by Alan Hourihane the FreeVGA project
12 * Francesco Salvestrini <salvestrini@users.sf.net> XP support,
15 * timing value tweaking so it looks good on every monitor in every mode
18 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/pci.h>
23 #include <linux/delay.h>
24 #include <video/vga.h>
25 #include <video/trident.h>
27 struct tridentfb_par {
28 void __iomem *io_virt; /* iospace virtual memory address */
32 void (*init_accel) (struct tridentfb_par *, int, int);
33 void (*wait_engine) (struct tridentfb_par *);
35 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
37 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
38 unsigned char eng_oper; /* engine operation... */
41 static struct fb_ops tridentfb_ops;
43 static struct fb_fix_screeninfo tridentfb_fix = {
45 .type = FB_TYPE_PACKED_PIXELS,
47 .visual = FB_VISUAL_PSEUDOCOLOR,
48 .accel = FB_ACCEL_NONE,
51 /* defaults which are normally overriden by user values */
54 static char *mode_option __devinitdata = "640x480-8@60";
55 static int bpp __devinitdata = 8;
57 static int noaccel __devinitdata;
62 static int fp __devinitdata;
63 static int crt __devinitdata;
65 static int memsize __devinitdata;
66 static int memdiff __devinitdata;
69 module_param(mode_option, charp, 0);
70 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
71 module_param_named(mode, mode_option, charp, 0);
72 MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
73 module_param(bpp, int, 0);
74 module_param(center, int, 0);
75 module_param(stretch, int, 0);
76 module_param(noaccel, int, 0);
77 module_param(memsize, int, 0);
78 module_param(memdiff, int, 0);
79 module_param(nativex, int, 0);
80 module_param(fp, int, 0);
81 MODULE_PARM_DESC(fp, "Define if flatpanel is connected");
82 module_param(crt, int, 0);
83 MODULE_PARM_DESC(crt, "Define if CRT is connected");
85 static inline int is_oldclock(int id)
87 return (id == TGUI9440) ||
92 static inline int is_oldprotect(int id)
94 return is_oldclock(id) ||
95 (id == PROVIDIA9685) ||
100 static inline int is_blade(int id)
102 return (id == BLADE3D) ||
103 (id == CYBERBLADEE4) ||
104 (id == CYBERBLADEi7) ||
105 (id == CYBERBLADEi7D) ||
106 (id == CYBERBLADEi1) ||
107 (id == CYBERBLADEi1D) ||
108 (id == CYBERBLADEAi1) ||
109 (id == CYBERBLADEAi1D);
112 static inline int is_xp(int id)
114 return (id == CYBERBLADEXPAi1) ||
115 (id == CYBERBLADEXPm8) ||
116 (id == CYBERBLADEXPm16);
119 static inline int is3Dchip(int id)
121 return is_blade(id) || is_xp(id) ||
122 (id == CYBER9397) || (id == CYBER9397DVD) ||
123 (id == CYBER9520) || (id == CYBER9525DVD) ||
124 (id == IMAGE975) || (id == IMAGE985);
127 static inline int iscyber(int id)
143 case CYBERBLADEXPAi1:
147 case CYBERBLADEi7: /* VIA MPV4 integrated version */
149 /* case CYBERBLDAEXPm8: Strange */
150 /* case CYBERBLDAEXPm16: Strange */
155 static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)
157 fb_writeb(val, p->io_virt + reg);
160 static inline u8 t_inb(struct tridentfb_par *p, u16 reg)
162 return fb_readb(p->io_virt + reg);
165 static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v)
167 fb_writel(v, par->io_virt + r);
170 static inline u32 readmmr(struct tridentfb_par *par, u16 r)
172 return fb_readl(par->io_virt + r);
176 * Blade specific acceleration.
179 #define point(x, y) ((y) << 16 | (x))
181 static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp)
183 int v1 = (pitch >> 3) << 20;
184 int tmp = bpp == 24 ? 2 : (bpp >> 4);
185 int v2 = v1 | (tmp << 29);
187 writemmr(par, 0x21C0, v2);
188 writemmr(par, 0x21C4, v2);
189 writemmr(par, 0x21B8, v2);
190 writemmr(par, 0x21BC, v2);
191 writemmr(par, 0x21D0, v1);
192 writemmr(par, 0x21D4, v1);
193 writemmr(par, 0x21C8, v1);
194 writemmr(par, 0x21CC, v1);
195 writemmr(par, 0x216C, 0);
198 static void blade_wait_engine(struct tridentfb_par *par)
200 while (readmmr(par, STATUS) & 0xFA800000)
204 static void blade_fill_rect(struct tridentfb_par *par,
205 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
207 writemmr(par, COLOR, c);
208 writemmr(par, ROP, rop ? ROP_X : ROP_S);
209 writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
211 writemmr(par, DST1, point(x, y));
212 writemmr(par, DST2, point(x + w - 1, y + h - 1));
215 static void blade_copy_rect(struct tridentfb_par *par,
216 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
219 u32 s1 = point(x1, y1);
220 u32 s2 = point(x1 + w - 1, y1 + h - 1);
221 u32 d1 = point(x2, y2);
222 u32 d2 = point(x2 + w - 1, y2 + h - 1);
224 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
227 writemmr(par, ROP, ROP_S);
228 writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
230 writemmr(par, SRC1, direction ? s2 : s1);
231 writemmr(par, SRC2, direction ? s1 : s2);
232 writemmr(par, DST1, direction ? d2 : d1);
233 writemmr(par, DST2, direction ? d1 : d2);
237 * BladeXP specific acceleration functions
240 static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp)
242 unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
243 int v1 = pitch << (bpp == 24 ? 20 : (18 + x));
245 switch (pitch << (bpp >> 3)) {
261 t_outb(par, x, 0x2125);
263 par->eng_oper = x | 0x40;
265 writemmr(par, 0x2154, v1);
266 writemmr(par, 0x2150, v1);
267 t_outb(par, 3, 0x2126);
270 static void xp_wait_engine(struct tridentfb_par *par)
275 while (t_inb(par, STATUS) & 0x80) {
277 if (count == 10000000) {
283 t_outb(par, 0x00, STATUS);
291 static void xp_fill_rect(struct tridentfb_par *par,
292 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
294 writemmr(par, 0x2127, ROP_P);
295 writemmr(par, 0x2158, c);
296 writemmr(par, DRAWFL, 0x4000);
297 writemmr(par, OLDDIM, point(h, w));
298 writemmr(par, OLDDST, point(y, x));
299 t_outb(par, 0x01, OLDCMD);
300 t_outb(par, par->eng_oper, 0x2125);
303 static void xp_copy_rect(struct tridentfb_par *par,
304 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
306 u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
307 int direction = 0x0004;
309 if ((x1 < x2) && (y1 == y2)) {
327 writemmr(par, DRAWFL, direction);
328 t_outb(par, ROP_S, 0x2127);
329 writemmr(par, OLDSRC, point(y1_tmp, x1_tmp));
330 writemmr(par, OLDDST, point(y2_tmp, x2_tmp));
331 writemmr(par, OLDDIM, point(h, w));
332 t_outb(par, 0x01, OLDCMD);
336 * Image specific acceleration functions
338 static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp)
340 int tmp = bpp == 24 ? 2: (bpp >> 4);
342 writemmr(par, 0x2120, 0xF0000000);
343 writemmr(par, 0x2120, 0x40000000 | tmp);
344 writemmr(par, 0x2120, 0x80000000);
345 writemmr(par, 0x2144, 0x00000000);
346 writemmr(par, 0x2148, 0x00000000);
347 writemmr(par, 0x2150, 0x00000000);
348 writemmr(par, 0x2154, 0x00000000);
349 writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch);
350 writemmr(par, 0x216C, 0x00000000);
351 writemmr(par, 0x2170, 0x00000000);
352 writemmr(par, 0x217C, 0x00000000);
353 writemmr(par, 0x2120, 0x10000000);
354 writemmr(par, 0x2130, (2047 << 16) | 2047);
357 static void image_wait_engine(struct tridentfb_par *par)
359 while (readmmr(par, 0x2164) & 0xF0000000)
363 static void image_fill_rect(struct tridentfb_par *par,
364 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
366 writemmr(par, 0x2120, 0x80000000);
367 writemmr(par, 0x2120, 0x90000000 | ROP_S);
369 writemmr(par, 0x2144, c);
371 writemmr(par, DST1, point(x, y));
372 writemmr(par, DST2, point(x + w - 1, y + h - 1));
374 writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
377 static void image_copy_rect(struct tridentfb_par *par,
378 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
381 u32 s1 = point(x1, y1);
382 u32 s2 = point(x1 + w - 1, y1 + h - 1);
383 u32 d1 = point(x2, y2);
384 u32 d2 = point(x2 + w - 1, y2 + h - 1);
386 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
389 writemmr(par, 0x2120, 0x80000000);
390 writemmr(par, 0x2120, 0x90000000 | ROP_S);
392 writemmr(par, SRC1, direction ? s2 : s1);
393 writemmr(par, SRC2, direction ? s1 : s2);
394 writemmr(par, DST1, direction ? d2 : d1);
395 writemmr(par, DST2, direction ? d1 : d2);
396 writemmr(par, 0x2124,
397 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction);
401 * TGUI 9440/96XX acceleration
404 static void tgui_init_accel(struct tridentfb_par *par, int pitch, int bpp)
406 unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
408 /* disable clipping */
409 writemmr(par, 0x2148, 0);
410 writemmr(par, 0x214C, point(4095, 2047));
412 switch ((pitch * bpp) / 8) {
428 fb_writew(x, par->io_virt + 0x2122);
431 static void tgui_fill_rect(struct tridentfb_par *par,
432 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
434 t_outb(par, ROP_P, 0x2127);
435 writemmr(par, OLDCLR, c);
436 writemmr(par, DRAWFL, 0x4020);
437 writemmr(par, OLDDIM, point(w - 1, h - 1));
438 writemmr(par, OLDDST, point(x, y));
439 t_outb(par, 1, OLDCMD);
442 static void tgui_copy_rect(struct tridentfb_par *par,
443 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
446 u16 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
448 if ((x1 < x2) && (y1 == y2)) {
466 writemmr(par, DRAWFL, 0x4 | flags);
467 t_outb(par, ROP_S, 0x2127);
468 writemmr(par, OLDSRC, point(x1_tmp, y1_tmp));
469 writemmr(par, OLDDST, point(x2_tmp, y2_tmp));
470 writemmr(par, OLDDIM, point(w - 1, h - 1));
471 t_outb(par, 1, OLDCMD);
475 * Accel functions called by the upper layers
477 #ifdef CONFIG_FB_TRIDENT_ACCEL
478 static void tridentfb_fillrect(struct fb_info *info,
479 const struct fb_fillrect *fr)
481 struct tridentfb_par *par = info->par;
484 if (info->flags & FBINFO_HWACCEL_DISABLED) {
485 cfb_fillrect(info, fr);
488 if (info->var.bits_per_pixel == 8) {
493 col = ((u32 *)(info->pseudo_palette))[fr->color];
495 par->wait_engine(par);
496 par->fill_rect(par, fr->dx, fr->dy, fr->width,
497 fr->height, col, fr->rop);
500 static void tridentfb_copyarea(struct fb_info *info,
501 const struct fb_copyarea *ca)
503 struct tridentfb_par *par = info->par;
505 if (info->flags & FBINFO_HWACCEL_DISABLED) {
506 cfb_copyarea(info, ca);
509 par->wait_engine(par);
510 par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy,
511 ca->width, ca->height);
514 static int tridentfb_sync(struct fb_info *info)
516 struct tridentfb_par *par = info->par;
518 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
519 par->wait_engine(par);
523 #define tridentfb_fillrect cfb_fillrect
524 #define tridentfb_copyarea cfb_copyarea
525 #endif /* CONFIG_FB_TRIDENT_ACCEL */
528 * Hardware access functions
531 static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
533 return vga_mm_rcrt(par->io_virt, reg);
536 static inline void write3X4(struct tridentfb_par *par, int reg,
539 vga_mm_wcrt(par->io_virt, reg, val);
542 static inline unsigned char read3CE(struct tridentfb_par *par,
545 return vga_mm_rgfx(par->io_virt, reg);
548 static inline void writeAttr(struct tridentfb_par *par, int reg,
551 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
552 vga_mm_wattr(par->io_virt, reg, val);
555 static inline void write3CE(struct tridentfb_par *par, int reg,
558 vga_mm_wgfx(par->io_virt, reg, val);
561 static void enable_mmio(struct tridentfb_par *par)
566 /* Unprotect registers */
567 vga_io_wseq(NewMode1, 0x80);
568 if (!is_oldprotect(par->chip_id))
569 vga_io_wseq(Protection, 0x92);
573 outb(inb(0x3D5) | 0x01, 0x3D5);
576 static void disable_mmio(struct tridentfb_par *par)
579 vga_mm_rseq(par->io_virt, 0x0B);
581 /* Unprotect registers */
582 vga_mm_wseq(par->io_virt, NewMode1, 0x80);
583 if (!is_oldprotect(par->chip_id))
584 vga_mm_wseq(par->io_virt, Protection, 0x92);
587 t_outb(par, PCIReg, 0x3D4);
588 t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);
591 static inline void crtc_unlock(struct tridentfb_par *par)
593 write3X4(par, VGA_CRTC_V_SYNC_END,
594 read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F);
597 /* Return flat panel's maximum x resolution */
598 static int __devinit get_nativex(struct tridentfb_par *par)
605 tmp = (read3CE(par, VertStretch) >> 4) & 3;
626 output("%dx%d flat panel found\n", x, y);
631 static inline void set_lwidth(struct tridentfb_par *par, int width)
633 write3X4(par, VGA_CRTC_OFFSET, width & 0xFF);
634 write3X4(par, AddColReg,
635 (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
638 /* For resolutions smaller than FP resolution stretch */
639 static void screen_stretch(struct tridentfb_par *par)
641 if (par->chip_id != CYBERBLADEXPAi1)
642 write3CE(par, BiosReg, 0);
644 write3CE(par, BiosReg, 8);
645 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1);
646 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1);
649 /* For resolutions smaller than FP resolution center */
650 static inline void screen_center(struct tridentfb_par *par)
652 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80);
653 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80);
656 /* Address of first shown pixel in display memory */
657 static void set_screen_start(struct tridentfb_par *par, int base)
660 write3X4(par, VGA_CRTC_START_LO, base & 0xFF);
661 write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8);
662 tmp = read3X4(par, CRTCModuleTest) & 0xDF;
663 write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
664 tmp = read3X4(par, CRTHiOrd) & 0xF8;
665 write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17));
668 /* Set dotclock frequency */
669 static void set_vclk(struct tridentfb_par *par, unsigned long freq)
672 unsigned long fi, d, di;
673 unsigned char best_m = 0, best_n = 0, best_k = 0;
674 unsigned char hi, lo;
677 for (k = 1; k >= 0; k--)
678 for (m = 0; m < 32; m++) {
680 for (n = (n < 0 ? 0 : n); n < 122; n++) {
681 fi = ((14318l * (n + 8)) / (m + 2)) >> k;
694 if (is_oldclock(par->chip_id)) {
695 lo = best_n | (best_m << 7);
696 hi = (best_m >> 1) | (best_k << 4);
699 hi = best_m | (best_k << 6);
702 if (is3Dchip(par->chip_id)) {
703 vga_mm_wseq(par->io_virt, ClockHigh, hi);
704 vga_mm_wseq(par->io_virt, ClockLow, lo);
706 t_outb(par, lo, 0x43C8);
707 t_outb(par, hi, 0x43C9);
709 debug("VCLK = %X %X\n", hi, lo);
712 /* Set number of lines for flat panels*/
713 static void set_number_of_lines(struct tridentfb_par *par, int lines)
715 int tmp = read3CE(par, CyberEnhance) & 0x8F;
718 else if (lines > 768)
720 else if (lines > 600)
722 else if (lines > 480)
724 write3CE(par, CyberEnhance, tmp);
728 * If we see that FP is active we assume we have one.
729 * Otherwise we have a CRT display. User can override.
731 static int __devinit is_flatpanel(struct tridentfb_par *par)
735 if (crt || !iscyber(par->chip_id))
737 return (read3CE(par, FPConfig) & 0x10) ? 1 : 0;
740 /* Try detecting the video memory size */
741 static unsigned int __devinit get_memsize(struct tridentfb_par *par)
743 unsigned char tmp, tmp2;
746 /* If memory size provided by user */
750 switch (par->chip_id) {
755 tmp = read3X4(par, SPR) & 0x0F;
771 k = 10 * Mb; /* XP */
777 k = 12 * Mb; /* XP */
780 k = 14 * Mb; /* XP */
783 k = 16 * Mb; /* XP */
787 tmp2 = vga_mm_rseq(par->io_virt, 0xC1);
817 output("framebuffer size = %d Kb\n", k / Kb);
821 /* See if we can handle the video mode described in var */
822 static int tridentfb_check_var(struct fb_var_screeninfo *var,
823 struct fb_info *info)
825 struct tridentfb_par *par = info->par;
826 int bpp = var->bits_per_pixel;
828 int ramdac = 230000; /* 230MHz for most 3D chips */
831 /* check color depth */
833 bpp = var->bits_per_pixel = 32;
834 if (bpp != 8 && bpp != 16 && bpp != 32)
836 if (par->chip_id == TGUI9440 && bpp == 32)
838 /* check whether resolution fits on panel and in memory */
839 if (par->flatpanel && nativex && var->xres > nativex)
841 /* various resolution checks */
842 var->xres = (var->xres + 7) & ~0x7;
843 if (var->xres > var->xres_virtual)
844 var->xres_virtual = var->xres;
845 if (var->yres > var->yres_virtual)
846 var->yres_virtual = var->yres;
847 if (var->xres_virtual > 4095 || var->yres > 2048)
849 /* prevent from position overflow for acceleration */
850 if (var->yres_virtual > 0xffff)
852 line_length = var->xres_virtual * bpp / 8;
854 if (!is3Dchip(par->chip_id) &&
855 !(info->flags & FBINFO_HWACCEL_DISABLED)) {
856 /* acceleration requires line length to be power of 2 */
857 if (line_length <= 512)
858 var->xres_virtual = 512 * 8 / bpp;
859 else if (line_length <= 1024)
860 var->xres_virtual = 1024 * 8 / bpp;
861 else if (line_length <= 2048)
862 var->xres_virtual = 2048 * 8 / bpp;
863 else if (line_length <= 4096)
864 var->xres_virtual = 4096 * 8 / bpp;
865 else if (line_length <= 8192)
866 var->xres_virtual = 8192 * 8 / bpp;
870 line_length = var->xres_virtual * bpp / 8;
873 /* datasheet specifies how to set panning only up to 4 MB */
874 if (line_length * (var->yres_virtual - var->yres) > (4 << 20))
875 var->yres_virtual = ((4 << 20) / line_length) + var->yres;
877 if (line_length * var->yres_virtual > info->fix.smem_len)
884 var->green = var->red;
885 var->blue = var->red;
888 var->red.offset = 11;
889 var->green.offset = 5;
890 var->blue.offset = 0;
892 var->green.length = 6;
893 var->blue.length = 5;
896 var->red.offset = 16;
897 var->green.offset = 8;
898 var->blue.offset = 0;
900 var->green.length = 8;
901 var->blue.length = 8;
907 if (is_xp(par->chip_id))
910 switch (par->chip_id) {
912 ramdac = (bpp >= 16) ? 45000 : 90000;
926 /* The clock is doubled for 32 bpp */
930 if (PICOS2KHZ(var->pixclock) > ramdac)
939 /* Pan the display */
940 static int tridentfb_pan_display(struct fb_var_screeninfo *var,
941 struct fb_info *info)
943 struct tridentfb_par *par = info->par;
947 offset = (var->xoffset + (var->yoffset * var->xres_virtual))
948 * var->bits_per_pixel / 32;
949 set_screen_start(par, offset);
954 static inline void shadowmode_on(struct tridentfb_par *par)
956 write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81);
959 static inline void shadowmode_off(struct tridentfb_par *par)
961 write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E);
964 /* Set the hardware to the requested video mode */
965 static int tridentfb_set_par(struct fb_info *info)
967 struct tridentfb_par *par = info->par;
968 u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend;
969 u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend;
970 struct fb_var_screeninfo *var = &info->var;
971 int bpp = var->bits_per_pixel;
976 hdispend = var->xres / 8 - 1;
977 hsyncstart = (var->xres + var->right_margin) / 8;
978 hsyncend = (var->xres + var->right_margin + var->hsync_len) / 8;
979 htotal = (var->xres + var->left_margin + var->right_margin +
980 var->hsync_len) / 8 - 5;
981 hblankstart = hdispend + 1;
982 hblankend = htotal + 3;
984 vdispend = var->yres - 1;
985 vsyncstart = var->yres + var->lower_margin;
986 vsyncend = vsyncstart + var->vsync_len;
987 vtotal = var->upper_margin + vsyncend - 2;
988 vblankstart = vdispend + 1;
991 if (info->var.vmode & FB_VMODE_INTERLACED) {
1002 write3CE(par, CyberControl, 8);
1004 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
1006 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
1009 if (par->flatpanel && var->xres < nativex) {
1011 * on flat panels with native size larger
1012 * than requested resolution decide whether
1013 * we stretch or center
1015 t_outb(par, tmp | 0xC0, VGA_MIS_W);
1022 screen_stretch(par);
1025 t_outb(par, tmp, VGA_MIS_W);
1026 write3CE(par, CyberControl, 8);
1029 /* vertical timing values */
1030 write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF);
1031 write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF);
1032 write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF);
1033 write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F));
1034 write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF);
1035 write3X4(par, VGA_CRTC_V_BLANK_END, vblankend & 0xFF);
1037 /* horizontal timing values */
1038 write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF);
1039 write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF);
1040 write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF);
1041 write3X4(par, VGA_CRTC_H_SYNC_END,
1042 (hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
1043 write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF);
1044 write3X4(par, VGA_CRTC_H_BLANK_END, hblankend & 0x1F);
1046 /* higher bits of vertical timing values */
1048 if (vtotal & 0x100) tmp |= 0x01;
1049 if (vdispend & 0x100) tmp |= 0x02;
1050 if (vsyncstart & 0x100) tmp |= 0x04;
1051 if (vblankstart & 0x100) tmp |= 0x08;
1053 if (vtotal & 0x200) tmp |= 0x20;
1054 if (vdispend & 0x200) tmp |= 0x40;
1055 if (vsyncstart & 0x200) tmp |= 0x80;
1056 write3X4(par, VGA_CRTC_OVERFLOW, tmp);
1058 tmp = read3X4(par, CRTHiOrd) & 0x07;
1059 tmp |= 0x08; /* line compare bit 10 */
1060 if (vtotal & 0x400) tmp |= 0x80;
1061 if (vblankstart & 0x400) tmp |= 0x40;
1062 if (vsyncstart & 0x400) tmp |= 0x20;
1063 if (vdispend & 0x400) tmp |= 0x10;
1064 write3X4(par, CRTHiOrd, tmp);
1066 tmp = (htotal >> 8) & 0x01;
1067 tmp |= (hdispend >> 7) & 0x02;
1068 tmp |= (hsyncstart >> 5) & 0x08;
1069 tmp |= (hblankstart >> 4) & 0x10;
1070 write3X4(par, HorizOverflow, tmp);
1073 if (vblankstart & 0x200) tmp |= 0x20;
1074 //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */
1075 write3X4(par, VGA_CRTC_MAX_SCAN, tmp);
1077 write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF);
1078 write3X4(par, VGA_CRTC_PRESET_ROW, 0);
1079 write3X4(par, VGA_CRTC_MODE, 0xC3);
1081 write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */
1083 tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80;
1084 /* enable access extended memory */
1085 write3X4(par, CRTCModuleTest, tmp);
1086 tmp = read3CE(par, MiscIntContReg) & ~0x4;
1087 if (info->var.vmode & FB_VMODE_INTERLACED)
1089 write3CE(par, MiscIntContReg, tmp);
1091 /* enable GE for text acceleration */
1092 write3X4(par, GraphEngReg, 0x80);
1109 write3X4(par, PixelBusReg, tmp);
1111 tmp = read3X4(par, DRAMControl);
1112 if (!is_oldprotect(par->chip_id))
1114 if (iscyber(par->chip_id))
1116 write3X4(par, DRAMControl, tmp); /* both IO, linear enable */
1118 write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40);
1119 if (!is_xp(par->chip_id))
1120 write3X4(par, Performance, read3X4(par, Performance) | 0x10);
1121 /* MMIO & PCI read and write burst enable */
1122 if (par->chip_id != TGUI9440 && par->chip_id != IMAGE975)
1123 write3X4(par, PCIReg, read3X4(par, PCIReg) | 0x06);
1125 vga_mm_wseq(par->io_virt, 0, 3);
1126 vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */
1127 /* enable 4 maps because needed in chain4 mode */
1128 vga_mm_wseq(par->io_virt, 2, 0x0F);
1129 vga_mm_wseq(par->io_virt, 3, 0);
1130 vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */
1132 /* convert from picoseconds to kHz */
1133 vclk = PICOS2KHZ(info->var.pixclock);
1135 /* divide clock by 2 if 32bpp chain4 mode display and CPU path */
1136 tmp = read3CE(par, MiscExtFunc) & 0xF0;
1137 if (bpp == 32 || (par->chip_id == TGUI9440 && bpp == 16)) {
1141 set_vclk(par, vclk);
1142 write3CE(par, MiscExtFunc, tmp | 0x12);
1143 write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */
1144 write3CE(par, 0x6, 0x05); /* graphics mode */
1145 write3CE(par, 0x7, 0x0F); /* planes? */
1147 /* graphics mode and support 256 color modes */
1148 writeAttr(par, 0x10, 0x41);
1149 writeAttr(par, 0x12, 0x0F); /* planes */
1150 writeAttr(par, 0x13, 0); /* horizontal pel panning */
1153 for (tmp = 0; tmp < 0x10; tmp++)
1154 writeAttr(par, tmp, tmp);
1155 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
1156 t_outb(par, 0x20, VGA_ATT_W); /* enable attr */
1171 t_inb(par, VGA_PEL_IW);
1172 t_inb(par, VGA_PEL_MSK);
1173 t_inb(par, VGA_PEL_MSK);
1174 t_inb(par, VGA_PEL_MSK);
1175 t_inb(par, VGA_PEL_MSK);
1176 t_outb(par, tmp, VGA_PEL_MSK);
1177 t_inb(par, VGA_PEL_IW);
1180 set_number_of_lines(par, info->var.yres);
1181 info->fix.line_length = info->var.xres_virtual * bpp / 8;
1182 set_lwidth(par, info->fix.line_length / 8);
1184 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1185 par->init_accel(par, info->var.xres_virtual, bpp);
1187 info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1188 info->cmap.len = (bpp == 8) ? 256 : 16;
1193 /* Set one color register */
1194 static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1195 unsigned blue, unsigned transp,
1196 struct fb_info *info)
1198 int bpp = info->var.bits_per_pixel;
1199 struct tridentfb_par *par = info->par;
1201 if (regno >= info->cmap.len)
1205 t_outb(par, 0xFF, VGA_PEL_MSK);
1206 t_outb(par, regno, VGA_PEL_IW);
1208 t_outb(par, red >> 10, VGA_PEL_D);
1209 t_outb(par, green >> 10, VGA_PEL_D);
1210 t_outb(par, blue >> 10, VGA_PEL_D);
1212 } else if (regno < 16) {
1213 if (bpp == 16) { /* RGB 565 */
1216 col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
1217 ((blue & 0xF800) >> 11);
1219 ((u32 *)(info->pseudo_palette))[regno] = col;
1220 } else if (bpp == 32) /* ARGB 8888 */
1221 ((u32 *)info->pseudo_palette)[regno] =
1222 ((transp & 0xFF00) << 16) |
1223 ((red & 0xFF00) << 8) |
1224 ((green & 0xFF00)) |
1225 ((blue & 0xFF00) >> 8);
1231 /* Try blanking the screen. For flat panels it does nothing */
1232 static int tridentfb_blank(int blank_mode, struct fb_info *info)
1234 unsigned char PMCont, DPMSCont;
1235 struct tridentfb_par *par = info->par;
1240 t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */
1241 PMCont = t_inb(par, 0x83C6) & 0xFC;
1242 DPMSCont = read3CE(par, PowerStatus) & 0xFC;
1243 switch (blank_mode) {
1244 case FB_BLANK_UNBLANK:
1245 /* Screen: On, HSync: On, VSync: On */
1246 case FB_BLANK_NORMAL:
1247 /* Screen: Off, HSync: On, VSync: On */
1251 case FB_BLANK_HSYNC_SUSPEND:
1252 /* Screen: Off, HSync: Off, VSync: On */
1256 case FB_BLANK_VSYNC_SUSPEND:
1257 /* Screen: Off, HSync: On, VSync: Off */
1261 case FB_BLANK_POWERDOWN:
1262 /* Screen: Off, HSync: Off, VSync: Off */
1268 write3CE(par, PowerStatus, DPMSCont);
1269 t_outb(par, 4, 0x83C8);
1270 t_outb(par, PMCont, 0x83C6);
1274 /* let fbcon do a softblank for us */
1275 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1278 static struct fb_ops tridentfb_ops = {
1279 .owner = THIS_MODULE,
1280 .fb_setcolreg = tridentfb_setcolreg,
1281 .fb_pan_display = tridentfb_pan_display,
1282 .fb_blank = tridentfb_blank,
1283 .fb_check_var = tridentfb_check_var,
1284 .fb_set_par = tridentfb_set_par,
1285 .fb_fillrect = tridentfb_fillrect,
1286 .fb_copyarea = tridentfb_copyarea,
1287 .fb_imageblit = cfb_imageblit,
1288 #ifdef CONFIG_FB_TRIDENT_ACCEL
1289 .fb_sync = tridentfb_sync,
1293 static int __devinit trident_pci_probe(struct pci_dev *dev,
1294 const struct pci_device_id *id)
1297 unsigned char revision;
1298 struct fb_info *info;
1299 struct tridentfb_par *default_par;
1303 err = pci_enable_device(dev);
1307 info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev);
1310 default_par = info->par;
1312 chip_id = id->device;
1314 if (chip_id == CYBERBLADEi1)
1315 output("*** Please do use cyblafb, Cyberblade/i1 support "
1316 "will soon be removed from tridentfb!\n");
1318 #ifndef CONFIG_FB_TRIDENT_ACCEL
1322 /* If PCI id is 0x9660 then further detect chip type */
1324 if (chip_id == TGUI9660) {
1325 revision = vga_io_rseq(RevisionID);
1329 chip_id = PROVIDIA9685;
1333 chip_id = CYBER9397;
1336 chip_id = CYBER9397DVD;
1345 chip_id = CYBER9385;
1348 chip_id = CYBER9382;
1351 chip_id = CYBER9388;
1358 chip3D = is3Dchip(chip_id);
1360 if (is_xp(chip_id)) {
1361 default_par->init_accel = xp_init_accel;
1362 default_par->wait_engine = xp_wait_engine;
1363 default_par->fill_rect = xp_fill_rect;
1364 default_par->copy_rect = xp_copy_rect;
1365 tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADEXP;
1366 } else if (is_blade(chip_id)) {
1367 default_par->init_accel = blade_init_accel;
1368 default_par->wait_engine = blade_wait_engine;
1369 default_par->fill_rect = blade_fill_rect;
1370 default_par->copy_rect = blade_copy_rect;
1371 tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADE3D;
1372 } else if (chip3D) { /* 3DImage family left */
1373 default_par->init_accel = image_init_accel;
1374 default_par->wait_engine = image_wait_engine;
1375 default_par->fill_rect = image_fill_rect;
1376 default_par->copy_rect = image_copy_rect;
1377 tridentfb_fix.accel = FB_ACCEL_TRIDENT_3DIMAGE;
1378 } else { /* TGUI 9440/96XX family */
1379 default_par->init_accel = tgui_init_accel;
1380 default_par->wait_engine = xp_wait_engine;
1381 default_par->fill_rect = tgui_fill_rect;
1382 default_par->copy_rect = tgui_copy_rect;
1383 tridentfb_fix.accel = FB_ACCEL_TRIDENT_TGUI;
1386 default_par->chip_id = chip_id;
1388 /* setup MMIO region */
1389 tridentfb_fix.mmio_start = pci_resource_start(dev, 1);
1390 tridentfb_fix.mmio_len = pci_resource_len(dev, 1);
1392 if (!request_mem_region(tridentfb_fix.mmio_start,
1393 tridentfb_fix.mmio_len, "tridentfb")) {
1394 debug("request_region failed!\n");
1395 framebuffer_release(info);
1399 default_par->io_virt = ioremap_nocache(tridentfb_fix.mmio_start,
1400 tridentfb_fix.mmio_len);
1402 if (!default_par->io_virt) {
1403 debug("ioremap failed\n");
1408 enable_mmio(default_par);
1410 /* setup framebuffer memory */
1411 tridentfb_fix.smem_start = pci_resource_start(dev, 0);
1412 tridentfb_fix.smem_len = get_memsize(default_par);
1414 if (!request_mem_region(tridentfb_fix.smem_start,
1415 tridentfb_fix.smem_len, "tridentfb")) {
1416 debug("request_mem_region failed!\n");
1417 disable_mmio(info->par);
1422 info->screen_base = ioremap_nocache(tridentfb_fix.smem_start,
1423 tridentfb_fix.smem_len);
1425 if (!info->screen_base) {
1426 debug("ioremap failed\n");
1431 default_par->flatpanel = is_flatpanel(default_par);
1433 if (default_par->flatpanel)
1434 nativex = get_nativex(default_par);
1436 info->fix = tridentfb_fix;
1437 info->fbops = &tridentfb_ops;
1438 info->pseudo_palette = default_par->pseudo_pal;
1440 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1441 if (!noaccel && default_par->init_accel) {
1442 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1443 info->flags |= FBINFO_HWACCEL_COPYAREA;
1444 info->flags |= FBINFO_HWACCEL_FILLRECT;
1446 info->flags |= FBINFO_HWACCEL_DISABLED;
1448 if (!fb_find_mode(&info->var, info,
1449 mode_option, NULL, 0, NULL, bpp)) {
1453 err = fb_alloc_cmap(&info->cmap, 256, 0);
1457 info->var.activate |= FB_ACTIVATE_NOW;
1458 info->device = &dev->dev;
1459 if (register_framebuffer(info) < 0) {
1460 printk(KERN_ERR "tridentfb: could not register framebuffer\n");
1461 fb_dealloc_cmap(&info->cmap);
1465 output("fb%d: %s frame buffer device %dx%d-%dbpp\n",
1466 info->node, info->fix.id, info->var.xres,
1467 info->var.yres, info->var.bits_per_pixel);
1469 pci_set_drvdata(dev, info);
1473 if (info->screen_base)
1474 iounmap(info->screen_base);
1475 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1476 disable_mmio(info->par);
1478 if (default_par->io_virt)
1479 iounmap(default_par->io_virt);
1480 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1481 framebuffer_release(info);
1485 static void __devexit trident_pci_remove(struct pci_dev *dev)
1487 struct fb_info *info = pci_get_drvdata(dev);
1488 struct tridentfb_par *par = info->par;
1490 unregister_framebuffer(info);
1491 iounmap(par->io_virt);
1492 iounmap(info->screen_base);
1493 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1494 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1495 pci_set_drvdata(dev, NULL);
1496 framebuffer_release(info);
1499 /* List of boards that we are trying to support */
1500 static struct pci_device_id trident_devices[] = {
1501 {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1502 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1503 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1504 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1505 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1506 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1507 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1508 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1509 {PCI_VENDOR_ID_TRIDENT, TGUI9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1510 {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1511 {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1512 {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1513 {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1514 {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1515 {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1516 {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1517 {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1518 {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1519 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1520 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1521 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1525 MODULE_DEVICE_TABLE(pci, trident_devices);
1527 static struct pci_driver tridentfb_pci_driver = {
1528 .name = "tridentfb",
1529 .id_table = trident_devices,
1530 .probe = trident_pci_probe,
1531 .remove = __devexit_p(trident_pci_remove)
1535 * Parse user specified options (`video=trident:')
1537 * video=trident:800x600,bpp=16,noaccel
1540 static int __init tridentfb_setup(char *options)
1543 if (!options || !*options)
1545 while ((opt = strsep(&options, ",")) != NULL) {
1548 if (!strncmp(opt, "noaccel", 7))
1550 else if (!strncmp(opt, "fp", 2))
1552 else if (!strncmp(opt, "crt", 3))
1554 else if (!strncmp(opt, "bpp=", 4))
1555 bpp = simple_strtoul(opt + 4, NULL, 0);
1556 else if (!strncmp(opt, "center", 6))
1558 else if (!strncmp(opt, "stretch", 7))
1560 else if (!strncmp(opt, "memsize=", 8))
1561 memsize = simple_strtoul(opt + 8, NULL, 0);
1562 else if (!strncmp(opt, "memdiff=", 8))
1563 memdiff = simple_strtoul(opt + 8, NULL, 0);
1564 else if (!strncmp(opt, "nativex=", 8))
1565 nativex = simple_strtoul(opt + 8, NULL, 0);
1573 static int __init tridentfb_init(void)
1576 char *option = NULL;
1578 if (fb_get_options("tridentfb", &option))
1580 tridentfb_setup(option);
1582 return pci_register_driver(&tridentfb_pci_driver);
1585 static void __exit tridentfb_exit(void)
1587 pci_unregister_driver(&tridentfb_pci_driver);
1590 module_init(tridentfb_init);
1591 module_exit(tridentfb_exit);
1593 MODULE_AUTHOR("Jani Monoses <jani@iv.ro>");
1594 MODULE_DESCRIPTION("Framebuffer driver for Trident cards");
1595 MODULE_LICENSE("GPL");