2 * linux/drivers/video/tgafb.c -- DEC 21030 TGA frame buffer device
4 * Copyright (C) 1995 Jay Estabrook
5 * Copyright (C) 1997 Geert Uytterhoeven
6 * Copyright (C) 1999,2000 Martin Lucina, Tom Zerucha
7 * Copyright (C) 2002 Richard Henderson
9 * This file is subject to the terms and conditions of the GNU General Public
10 * License. See the file COPYING in the main directory of this archive for
14 #include <linux/module.h>
15 #include <linux/kernel.h>
16 #include <linux/sched.h>
17 #include <linux/errno.h>
18 #include <linux/string.h>
20 #include <linux/slab.h>
21 #include <linux/delay.h>
22 #include <linux/init.h>
24 #include <linux/pci.h>
25 #include <linux/selection.h>
26 #include <linux/bitrev.h>
28 #include <video/tgafb.h>
34 static int tgafb_check_var(struct fb_var_screeninfo *, struct fb_info *);
35 static int tgafb_set_par(struct fb_info *);
36 static void tgafb_set_pll(struct tga_par *, int);
37 static int tgafb_setcolreg(unsigned, unsigned, unsigned, unsigned,
38 unsigned, struct fb_info *);
39 static int tgafb_blank(int, struct fb_info *);
40 static void tgafb_init_fix(struct fb_info *);
42 static void tgafb_imageblit(struct fb_info *, const struct fb_image *);
43 static void tgafb_fillrect(struct fb_info *, const struct fb_fillrect *);
44 static void tgafb_copyarea(struct fb_info *, const struct fb_copyarea *);
46 static int __devinit tgafb_pci_register(struct pci_dev *,
47 const struct pci_device_id *);
48 static void __devexit tgafb_pci_unregister(struct pci_dev *);
50 static const char *mode_option = "640x480@60";
54 * Frame buffer operations
57 static struct fb_ops tgafb_ops = {
59 .fb_check_var = tgafb_check_var,
60 .fb_set_par = tgafb_set_par,
61 .fb_setcolreg = tgafb_setcolreg,
62 .fb_blank = tgafb_blank,
63 .fb_fillrect = tgafb_fillrect,
64 .fb_copyarea = tgafb_copyarea,
65 .fb_imageblit = tgafb_imageblit,
70 * PCI registration operations
73 static struct pci_device_id const tgafb_pci_table[] = {
74 { PCI_VENDOR_ID_DEC, PCI_DEVICE_ID_DEC_TGA, PCI_ANY_ID, PCI_ANY_ID,
78 static struct pci_driver tgafb_driver = {
80 .id_table = tgafb_pci_table,
81 .probe = tgafb_pci_register,
82 .remove = __devexit_p(tgafb_pci_unregister),
87 * tgafb_check_var - Optional function. Validates a var passed in.
88 * @var: frame buffer variable screen structure
89 * @info: frame buffer structure that represents a single frame buffer
92 tgafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
94 struct tga_par *par = (struct tga_par *)info->par;
96 if (par->tga_type == TGA_TYPE_8PLANE) {
97 if (var->bits_per_pixel != 8)
100 if (var->bits_per_pixel != 32)
103 var->red.length = var->green.length = var->blue.length = 8;
104 if (var->bits_per_pixel == 32) {
105 var->red.offset = 16;
106 var->green.offset = 8;
107 var->blue.offset = 0;
110 if (var->xres_virtual != var->xres || var->yres_virtual != var->yres)
114 if (1000000000 / var->pixclock > TGA_PLL_MAX_FREQ)
116 if ((var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
119 /* Some of the acceleration routines assume the line width is
120 a multiple of 64 bytes. */
121 if (var->xres * (par->tga_type == TGA_TYPE_8PLANE ? 1 : 4) % 64)
128 * tgafb_set_par - Optional function. Alters the hardware state.
129 * @info: frame buffer structure that represents a single frame buffer
132 tgafb_set_par(struct fb_info *info)
134 static unsigned int const deep_presets[4] = {
140 static unsigned int const rasterop_presets[4] = {
146 static unsigned int const mode_presets[4] = {
152 static unsigned int const base_addr_presets[4] = {
159 struct tga_par *par = (struct tga_par *) info->par;
160 u32 htimings, vtimings, pll_freq;
164 /* Encode video timings. */
165 htimings = (((info->var.xres/4) & TGA_HORIZ_ACT_LSB)
166 | (((info->var.xres/4) & 0x600 << 19) & TGA_HORIZ_ACT_MSB));
167 vtimings = (info->var.yres & TGA_VERT_ACTIVE);
168 htimings |= ((info->var.right_margin/4) << 9) & TGA_HORIZ_FP;
169 vtimings |= (info->var.lower_margin << 11) & TGA_VERT_FP;
170 htimings |= ((info->var.hsync_len/4) << 14) & TGA_HORIZ_SYNC;
171 vtimings |= (info->var.vsync_len << 16) & TGA_VERT_SYNC;
172 htimings |= ((info->var.left_margin/4) << 21) & TGA_HORIZ_BP;
173 vtimings |= (info->var.upper_margin << 22) & TGA_VERT_BP;
175 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
176 htimings |= TGA_HORIZ_POLARITY;
177 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
178 vtimings |= TGA_VERT_POLARITY;
180 par->htimings = htimings;
181 par->vtimings = vtimings;
183 par->sync_on_green = !!(info->var.sync & FB_SYNC_ON_GREEN);
185 /* Store other useful values in par. */
186 par->xres = info->var.xres;
187 par->yres = info->var.yres;
188 par->pll_freq = pll_freq = 1000000000 / info->var.pixclock;
189 par->bits_per_pixel = info->var.bits_per_pixel;
191 tga_type = par->tga_type;
193 /* First, disable video. */
194 TGA_WRITE_REG(par, TGA_VALID_VIDEO | TGA_VALID_BLANK, TGA_VALID_REG);
196 /* Write the DEEP register. */
197 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
200 TGA_WRITE_REG(par, deep_presets[tga_type], TGA_DEEP_REG);
201 while (TGA_READ_REG(par, TGA_CMD_STAT_REG) & 1) /* wait for not busy */
205 /* Write some more registers. */
206 TGA_WRITE_REG(par, rasterop_presets[tga_type], TGA_RASTEROP_REG);
207 TGA_WRITE_REG(par, mode_presets[tga_type], TGA_MODE_REG);
208 TGA_WRITE_REG(par, base_addr_presets[tga_type], TGA_BASE_ADDR_REG);
210 /* Calculate & write the PLL. */
211 tgafb_set_pll(par, pll_freq);
213 /* Write some more registers. */
214 TGA_WRITE_REG(par, 0xffffffff, TGA_PLANEMASK_REG);
215 TGA_WRITE_REG(par, 0xffffffff, TGA_PIXELMASK_REG);
217 /* Init video timing regs. */
218 TGA_WRITE_REG(par, htimings, TGA_HORIZ_REG);
219 TGA_WRITE_REG(par, vtimings, TGA_VERT_REG);
221 /* Initalise RAMDAC. */
222 if (tga_type == TGA_TYPE_8PLANE) {
224 /* Init BT485 RAMDAC registers. */
225 BT485_WRITE(par, 0xa2 | (par->sync_on_green ? 0x8 : 0x0),
227 BT485_WRITE(par, 0x01, BT485_ADDR_PAL_WRITE);
228 BT485_WRITE(par, 0x14, BT485_CMD_3); /* cursor 64x64 */
229 BT485_WRITE(par, 0x40, BT485_CMD_1);
230 BT485_WRITE(par, 0x20, BT485_CMD_2); /* cursor off, for now */
231 BT485_WRITE(par, 0xff, BT485_PIXEL_MASK);
233 /* Fill palette registers. */
234 BT485_WRITE(par, 0x00, BT485_ADDR_PAL_WRITE);
235 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
237 #ifdef CONFIG_HW_CONSOLE
238 for (i = 0; i < 16; i++) {
239 int j = color_table[i];
241 TGA_WRITE_REG(par, default_red[j]|(BT485_DATA_PAL<<8),
243 TGA_WRITE_REG(par, default_grn[j]|(BT485_DATA_PAL<<8),
245 TGA_WRITE_REG(par, default_blu[j]|(BT485_DATA_PAL<<8),
248 for (i = 0; i < 240 * 3; i += 4) {
250 for (i = 0; i < 256 * 3; i += 4) {
252 TGA_WRITE_REG(par, 0x55 | (BT485_DATA_PAL << 8),
254 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
256 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
258 TGA_WRITE_REG(par, 0x00 | (BT485_DATA_PAL << 8),
262 } else { /* 24-plane or 24plusZ */
264 /* Init BT463 registers. */
265 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_0, 0x40);
266 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_1, 0x08);
267 BT463_WRITE(par, BT463_REG_ACC, BT463_CMD_REG_2,
268 (par->sync_on_green ? 0x80 : 0x40));
270 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_0, 0xff);
271 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_1, 0xff);
272 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_2, 0xff);
273 BT463_WRITE(par, BT463_REG_ACC, BT463_READ_MASK_3, 0x0f);
275 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_0, 0x00);
276 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_1, 0x00);
277 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_2, 0x00);
278 BT463_WRITE(par, BT463_REG_ACC, BT463_BLINK_MASK_3, 0x00);
280 /* Fill the palette. */
281 BT463_LOAD_ADDR(par, 0x0000);
282 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
284 #ifdef CONFIG_HW_CONSOLE
285 for (i = 0; i < 16; i++) {
286 int j = color_table[i];
288 TGA_WRITE_REG(par, default_red[j], TGA_RAMDAC_REG);
289 TGA_WRITE_REG(par, default_grn[j], TGA_RAMDAC_REG);
290 TGA_WRITE_REG(par, default_blu[j], TGA_RAMDAC_REG);
292 for (i = 0; i < 512 * 3; i += 4) {
294 for (i = 0; i < 528 * 3; i += 4) {
296 TGA_WRITE_REG(par, 0x55, TGA_RAMDAC_REG);
297 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
298 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
299 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
302 /* Fill window type table after start of vertical retrace. */
303 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
305 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
307 while (!(TGA_READ_REG(par, TGA_INTR_STAT_REG) & 0x01))
309 TGA_WRITE_REG(par, 0x01, TGA_INTR_STAT_REG);
311 BT463_LOAD_ADDR(par, BT463_WINDOW_TYPE_BASE);
312 TGA_WRITE_REG(par, BT463_REG_ACC << 2, TGA_RAMDAC_SETUP_REG);
314 for (i = 0; i < 16; i++) {
315 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
316 TGA_WRITE_REG(par, 0x01, TGA_RAMDAC_REG);
317 TGA_WRITE_REG(par, 0x00, TGA_RAMDAC_REG);
322 /* Finally, enable video scan (and pray for the monitor... :-) */
323 TGA_WRITE_REG(par, TGA_VALID_VIDEO, TGA_VALID_REG);
328 #define DIFFCHECK(X) \
331 int delta = f - (TGA_PLL_BASE_FREQ * (X)) / (r << shift); \
334 if (delta < min_diff) \
335 min_diff = delta, vm = m, va = a, vr = r; \
340 tgafb_set_pll(struct tga_par *par, int f)
342 int n, shift, base, min_diff, target;
343 int r,a,m,vm = 34, va = 1, vr = 30;
345 for (r = 0 ; r < 12 ; r++)
346 TGA_WRITE_REG(par, !r, TGA_CLOCK_REG);
348 if (f > TGA_PLL_MAX_FREQ)
349 f = TGA_PLL_MAX_FREQ;
351 if (f >= TGA_PLL_MAX_FREQ / 2)
353 else if (f >= TGA_PLL_MAX_FREQ / 4)
358 TGA_WRITE_REG(par, shift & 1, TGA_CLOCK_REG);
359 TGA_WRITE_REG(par, shift >> 1, TGA_CLOCK_REG);
361 for (r = 0 ; r < 10 ; r++)
362 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
365 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
366 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
368 else if (f <= 200000) {
369 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
370 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
373 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
374 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
377 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
378 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
379 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
380 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
381 TGA_WRITE_REG(par, 0, TGA_CLOCK_REG);
382 TGA_WRITE_REG(par, 1, TGA_CLOCK_REG);
384 target = (f << shift) / TGA_PLL_BASE_FREQ;
385 min_diff = TGA_PLL_MAX_FREQ;
392 for (n = base < 7 ? 7 : base; n < base + target && n < 449; n++) {
393 m = ((n + 3) / 7) - 1;
395 DIFFCHECK((m + 1) * 7);
397 DIFFCHECK((m + 1) * 7);
408 for (r = 0; r < 8; r++)
409 TGA_WRITE_REG(par, (vm >> r) & 1, TGA_CLOCK_REG);
410 for (r = 0; r < 8 ; r++)
411 TGA_WRITE_REG(par, (va >> r) & 1, TGA_CLOCK_REG);
412 for (r = 0; r < 7 ; r++)
413 TGA_WRITE_REG(par, (vr >> r) & 1, TGA_CLOCK_REG);
414 TGA_WRITE_REG(par, ((vr >> 7) & 1)|2, TGA_CLOCK_REG);
419 * tgafb_setcolreg - Optional function. Sets a color register.
420 * @regno: boolean, 0 copy local, 1 get_user() function
421 * @red: frame buffer colormap structure
422 * @green: The green value which can be up to 16 bits wide
423 * @blue: The blue value which can be up to 16 bits wide.
424 * @transp: If supported the alpha value which can be up to 16 bits wide.
425 * @info: frame buffer info structure
428 tgafb_setcolreg(unsigned regno, unsigned red, unsigned green, unsigned blue,
429 unsigned transp, struct fb_info *info)
431 struct tga_par *par = (struct tga_par *) info->par;
439 if (par->tga_type == TGA_TYPE_8PLANE) {
440 BT485_WRITE(par, regno, BT485_ADDR_PAL_WRITE);
441 TGA_WRITE_REG(par, BT485_DATA_PAL, TGA_RAMDAC_SETUP_REG);
442 TGA_WRITE_REG(par, red|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
443 TGA_WRITE_REG(par, green|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
444 TGA_WRITE_REG(par, blue|(BT485_DATA_PAL<<8),TGA_RAMDAC_REG);
447 u32 value = (regno << 16) | (regno << 8) | regno;
448 ((u32 *)info->pseudo_palette)[regno] = value;
450 BT463_LOAD_ADDR(par, regno);
451 TGA_WRITE_REG(par, BT463_PALETTE << 2, TGA_RAMDAC_SETUP_REG);
452 TGA_WRITE_REG(par, red, TGA_RAMDAC_REG);
453 TGA_WRITE_REG(par, green, TGA_RAMDAC_REG);
454 TGA_WRITE_REG(par, blue, TGA_RAMDAC_REG);
462 * tgafb_blank - Optional function. Blanks the display.
463 * @blank_mode: the blank mode we want.
464 * @info: frame buffer structure that represents a single frame buffer
467 tgafb_blank(int blank, struct fb_info *info)
469 struct tga_par *par = (struct tga_par *) info->par;
470 u32 vhcr, vvcr, vvvr;
473 local_irq_save(flags);
475 vhcr = TGA_READ_REG(par, TGA_HORIZ_REG);
476 vvcr = TGA_READ_REG(par, TGA_VERT_REG);
477 vvvr = TGA_READ_REG(par, TGA_VALID_REG);
478 vvvr &= ~(TGA_VALID_VIDEO | TGA_VALID_BLANK);
481 case FB_BLANK_UNBLANK: /* Unblanking */
482 if (par->vesa_blanked) {
483 TGA_WRITE_REG(par, vhcr & 0xbfffffff, TGA_HORIZ_REG);
484 TGA_WRITE_REG(par, vvcr & 0xbfffffff, TGA_VERT_REG);
485 par->vesa_blanked = 0;
487 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO, TGA_VALID_REG);
490 case FB_BLANK_NORMAL: /* Normal blanking */
491 TGA_WRITE_REG(par, vvvr | TGA_VALID_VIDEO | TGA_VALID_BLANK,
495 case FB_BLANK_VSYNC_SUSPEND: /* VESA blank (vsync off) */
496 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
497 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
498 par->vesa_blanked = 1;
501 case FB_BLANK_HSYNC_SUSPEND: /* VESA blank (hsync off) */
502 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
503 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
504 par->vesa_blanked = 1;
507 case FB_BLANK_POWERDOWN: /* Poweroff */
508 TGA_WRITE_REG(par, vhcr | 0x40000000, TGA_HORIZ_REG);
509 TGA_WRITE_REG(par, vvcr | 0x40000000, TGA_VERT_REG);
510 TGA_WRITE_REG(par, vvvr | TGA_VALID_BLANK, TGA_VALID_REG);
511 par->vesa_blanked = 1;
515 local_irq_restore(flags);
525 * tgafb_imageblit - REQUIRED function. Can use generic routines if
526 * non acclerated hardware and packed pixel based.
527 * Copies a image from system memory to the screen.
529 * @info: frame buffer structure that represents a single frame buffer
530 * @image: structure defining the image.
533 tgafb_imageblit(struct fb_info *info, const struct fb_image *image)
535 struct tga_par *par = (struct tga_par *) info->par;
536 u32 fgcolor, bgcolor, dx, dy, width, height, vxres, vyres, pixelmask;
537 unsigned long rincr, line_length, shift, pos, is8bpp;
539 const unsigned char *data;
540 void __iomem *regs_base;
541 void __iomem *fb_base;
545 width = image->width;
546 height = image->height;
547 vxres = info->var.xres_virtual;
548 vyres = info->var.yres_virtual;
549 line_length = info->fix.line_length;
550 rincr = (width + 7) / 8;
552 /* Crop the image to the screen. */
553 if (dx > vxres || dy > vyres)
555 if (dx + width > vxres)
557 if (dy + height > vyres)
560 /* For copies that aren't pixel expansion, there's little we
561 can do better than the generic code. */
562 /* ??? There is a DMA write mode; I wonder if that could be
563 made to pull the data from the image buffer... */
564 if (image->depth > 1) {
565 cfb_imageblit(info, image);
569 regs_base = par->tga_regs_base;
570 fb_base = par->tga_fb_base;
571 is8bpp = info->var.bits_per_pixel == 8;
573 /* Expand the color values to fill 32-bits. */
574 /* ??? Would be nice to notice colour changes elsewhere, so
575 that we can do this only when necessary. */
576 fgcolor = image->fg_color;
577 bgcolor = image->bg_color;
579 fgcolor |= fgcolor << 8;
580 fgcolor |= fgcolor << 16;
581 bgcolor |= bgcolor << 8;
582 bgcolor |= bgcolor << 16;
585 fgcolor = ((u32 *)info->pseudo_palette)[fgcolor];
587 bgcolor = ((u32 *)info->pseudo_palette)[bgcolor];
589 __raw_writel(fgcolor, regs_base + TGA_FOREGROUND_REG);
590 __raw_writel(bgcolor, regs_base + TGA_BACKGROUND_REG);
592 /* Acquire proper alignment; set up the PIXELMASK register
593 so that we only write the proper character cell. */
594 pos = dy * line_length;
601 shift = (pos & 7) >> 2;
605 data = (const unsigned char *) image->data;
607 /* Enable opaque stipple mode. */
609 ? TGA_MODE_SBM_8BPP | TGA_MODE_OPAQUE_STIPPLE
610 : TGA_MODE_SBM_24BPP | TGA_MODE_OPAQUE_STIPPLE),
611 regs_base + TGA_MODE_REG);
613 if (width + shift <= 32) {
614 unsigned long bwidth;
616 /* Handle common case of imaging a single character, in
617 a font less than 32 pixels wide. */
619 pixelmask = (1 << width) - 1;
621 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
624 bwidth = (width + 7) / 8;
626 for (i = 0; i < height; ++i) {
629 /* The image data is bit big endian; we need
631 for (j = 0; j < bwidth; ++j)
632 mask |= bitrev8(data[j]) << (j * 8);
634 __raw_writel(mask << shift, fb_base + pos);
640 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
641 } else if (shift == 0) {
642 unsigned long pos0 = pos;
643 const unsigned char *data0 = data;
644 unsigned long bincr = (is8bpp ? 8 : 8*4);
645 unsigned long bwidth;
647 /* Handle another common case in which accel_putcs
648 generates a large bitmap, which happens to be aligned.
649 Allow the tail to be misaligned. This case is
650 interesting because we've not got to hold partial
651 bytes across the words being written. */
655 bwidth = (width / 8) & -4;
656 for (i = 0; i < height; ++i) {
657 for (j = 0; j < bwidth; j += 4) {
659 mask |= bitrev8(data[j+0]) << (0 * 8);
660 mask |= bitrev8(data[j+1]) << (1 * 8);
661 mask |= bitrev8(data[j+2]) << (2 * 8);
662 mask |= bitrev8(data[j+3]) << (3 * 8);
663 __raw_writel(mask, fb_base + pos + j*bincr);
670 pixelmask = (1ul << (width & 31)) - 1;
672 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
675 pos = pos0 + bwidth*bincr;
676 data = data0 + bwidth;
677 bwidth = ((width & 31) + 7) / 8;
679 for (i = 0; i < height; ++i) {
681 for (j = 0; j < bwidth; ++j)
682 mask |= bitrev8(data[j]) << (j * 8);
683 __raw_writel(mask, fb_base + pos);
688 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
691 unsigned long pos0 = pos;
692 const unsigned char *data0 = data;
693 unsigned long bincr = (is8bpp ? 8 : 8*4);
694 unsigned long bwidth;
696 /* Finally, handle the generic case of misaligned start.
697 Here we split the write into 16-bit spans. This allows
698 us to use only one pixel mask, instead of four as would
699 be required by writing 24-bit spans. */
701 pixelmask = 0xffff << shift;
702 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
705 bwidth = (width / 8) & -2;
706 for (i = 0; i < height; ++i) {
707 for (j = 0; j < bwidth; j += 2) {
709 mask |= bitrev8(data[j+0]) << (0 * 8);
710 mask |= bitrev8(data[j+1]) << (1 * 8);
712 __raw_writel(mask, fb_base + pos + j*bincr);
719 pixelmask = ((1ul << (width & 15)) - 1) << shift;
721 __raw_writel(pixelmask, regs_base + TGA_PIXELMASK_REG);
724 pos = pos0 + bwidth*bincr;
725 data = data0 + bwidth;
726 bwidth = (width & 15) > 8;
728 for (i = 0; i < height; ++i) {
729 u32 mask = bitrev8(data[0]);
731 mask |= bitrev8(data[1]) << 8;
733 __raw_writel(mask, fb_base + pos);
739 __raw_writel(0xffffffff, regs_base + TGA_PIXELMASK_REG);
742 /* Disable opaque stipple mode. */
744 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
745 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
746 regs_base + TGA_MODE_REG);
750 * tgafb_fillrect - REQUIRED function. Can use generic routines if
751 * non acclerated hardware and packed pixel based.
752 * Draws a rectangle on the screen.
754 * @info: frame buffer structure that represents a single frame buffer
755 * @rect: structure defining the rectagle and operation.
758 tgafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
760 struct tga_par *par = (struct tga_par *) info->par;
761 int is8bpp = info->var.bits_per_pixel == 8;
762 u32 dx, dy, width, height, vxres, vyres, color;
763 unsigned long pos, align, line_length, i, j;
764 void __iomem *regs_base;
765 void __iomem *fb_base;
770 height = rect->height;
771 vxres = info->var.xres_virtual;
772 vyres = info->var.yres_virtual;
773 line_length = info->fix.line_length;
774 regs_base = par->tga_regs_base;
775 fb_base = par->tga_fb_base;
777 /* Crop the rectangle to the screen. */
778 if (dx > vxres || dy > vyres || !width || !height)
780 if (dx + width > vxres)
782 if (dy + height > vyres)
785 pos = dy * line_length + dx * (is8bpp ? 1 : 4);
787 /* ??? We could implement ROP_XOR with opaque fill mode
788 and a RasterOp setting of GXxor, but as far as I can
789 tell, this mode is not actually used in the kernel.
790 Thus I am ignoring it for now. */
791 if (rect->rop != ROP_COPY) {
792 cfb_fillrect(info, rect);
796 /* Expand the color value to fill 8 pixels. */
800 color |= color << 16;
801 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
802 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
805 color = ((u32 *)info->pseudo_palette)[color];
806 __raw_writel(color, regs_base + TGA_BLOCK_COLOR0_REG);
807 __raw_writel(color, regs_base + TGA_BLOCK_COLOR1_REG);
808 __raw_writel(color, regs_base + TGA_BLOCK_COLOR2_REG);
809 __raw_writel(color, regs_base + TGA_BLOCK_COLOR3_REG);
810 __raw_writel(color, regs_base + TGA_BLOCK_COLOR4_REG);
811 __raw_writel(color, regs_base + TGA_BLOCK_COLOR5_REG);
812 __raw_writel(color, regs_base + TGA_BLOCK_COLOR6_REG);
813 __raw_writel(color, regs_base + TGA_BLOCK_COLOR7_REG);
816 /* The DATA register holds the fill mask for block fill mode.
817 Since we're not stippling, this is all ones. */
818 __raw_writel(0xffffffff, regs_base + TGA_DATA_REG);
820 /* Enable block fill mode. */
822 ? TGA_MODE_SBM_8BPP | TGA_MODE_BLOCK_FILL
823 : TGA_MODE_SBM_24BPP | TGA_MODE_BLOCK_FILL),
824 regs_base + TGA_MODE_REG);
827 /* We can fill 2k pixels per operation. Notice blocks that fit
828 the width of the screen so that we can take advantage of this
829 and fill more than one line per write. */
830 if (width == line_length)
831 width *= height, height = 1;
833 /* The write into the frame buffer must be aligned to 4 bytes,
834 but we are allowed to encode the offset within the word in
835 the data word written. */
836 align = (pos & 3) << 16;
842 data = (width - 1) | align;
844 for (i = 0; i < height; ++i) {
845 __raw_writel(data, fb_base + pos);
849 unsigned long Bpp = (is8bpp ? 1 : 4);
850 unsigned long nwidth = width & -2048;
853 fdata = (2048 - 1) | align;
854 ldata = ((width & 2047) - 1) | align;
856 for (i = 0; i < height; ++i) {
857 for (j = 0; j < nwidth; j += 2048)
858 __raw_writel(fdata, fb_base + pos + j*Bpp);
860 __raw_writel(ldata, fb_base + pos + j*Bpp);
866 /* Disable block fill mode. */
868 ? TGA_MODE_SBM_8BPP | TGA_MODE_SIMPLE
869 : TGA_MODE_SBM_24BPP | TGA_MODE_SIMPLE),
870 regs_base + TGA_MODE_REG);
874 * tgafb_copyarea - REQUIRED function. Can use generic routines if
875 * non acclerated hardware and packed pixel based.
876 * Copies on area of the screen to another area.
878 * @info: frame buffer structure that represents a single frame buffer
879 * @area: structure defining the source and destination.
882 /* Handle the special case of copying entire lines, e.g. during scrolling.
883 We can avoid a lot of needless computation in this case. In the 8bpp
884 case we need to use the COPY64 registers instead of mask writes into
885 the frame buffer to achieve maximum performance. */
888 copyarea_line_8bpp(struct fb_info *info, u32 dy, u32 sy,
889 u32 height, u32 width)
891 struct tga_par *par = (struct tga_par *) info->par;
892 void __iomem *tga_regs = par->tga_regs_base;
893 unsigned long dpos, spos, i, n64;
895 /* Set up the MODE and PIXELSHIFT registers. */
896 __raw_writel(TGA_MODE_SBM_8BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
897 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
900 n64 = (height * width) / 64;
903 spos = (sy + height) * width;
904 dpos = (dy + height) * width;
906 for (i = 0; i < n64; ++i) {
909 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
911 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
918 for (i = 0; i < n64; ++i) {
919 __raw_writel(spos, tga_regs+TGA_COPY64_SRC);
921 __raw_writel(dpos, tga_regs+TGA_COPY64_DST);
928 /* Reset the MODE register to normal. */
929 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
933 copyarea_line_32bpp(struct fb_info *info, u32 dy, u32 sy,
934 u32 height, u32 width)
936 struct tga_par *par = (struct tga_par *) info->par;
937 void __iomem *tga_regs = par->tga_regs_base;
938 void __iomem *tga_fb = par->tga_fb_base;
941 unsigned long i, n16;
943 /* Set up the MODE and PIXELSHIFT registers. */
944 __raw_writel(TGA_MODE_SBM_24BPP | TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
945 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
948 n16 = (height * width) / 16;
951 src = tga_fb + (sy + height) * width * 4;
952 dst = tga_fb + (dy + height) * width * 4;
954 for (i = 0; i < n16; ++i) {
957 __raw_writel(0xffff, src);
959 __raw_writel(0xffff, dst);
963 src = tga_fb + sy * width * 4;
964 dst = tga_fb + dy * width * 4;
966 for (i = 0; i < n16; ++i) {
967 __raw_writel(0xffff, src);
969 __raw_writel(0xffff, dst);
976 /* Reset the MODE register to normal. */
977 __raw_writel(TGA_MODE_SBM_24BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
980 /* The general case of forward copy in 8bpp mode. */
982 copyarea_foreward_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy,
983 u32 height, u32 width, u32 line_length)
985 struct tga_par *par = (struct tga_par *) info->par;
986 unsigned long i, copied, left;
987 unsigned long dpos, spos, dalign, salign, yincr;
988 u32 smask_first, dmask_first, dmask_last;
989 int pixel_shift, need_prime, need_second;
990 unsigned long n64, n32, xincr_first;
991 void __iomem *tga_regs;
992 void __iomem *tga_fb;
1001 /* Compute the offsets and alignments in the frame buffer.
1002 More than anything else, these control how we do copies. */
1003 dpos = dy * line_length + dx;
1004 spos = sy * line_length + sx;
1010 /* Compute the value for the PIXELSHIFT register. This controls
1011 both non-co-aligned source and destination and copy direction. */
1012 if (dalign >= salign)
1013 pixel_shift = dalign - salign;
1015 pixel_shift = 8 - (salign - dalign);
1017 /* Figure out if we need an additional priming step for the
1018 residue register. */
1019 need_prime = (salign > dalign);
1023 /* Begin by copying the leading unaligned destination. Copy enough
1024 to make the next destination address 32-byte aligned. */
1025 copied = 32 - (dalign + (dpos & 31));
1028 xincr_first = (copied + 7) & -8;
1029 smask_first = dmask_first = (1ul << copied) - 1;
1030 smask_first <<= salign;
1031 dmask_first <<= dalign + need_prime*8;
1032 if (need_prime && copied > 24)
1034 left = width - copied;
1036 /* Care for small copies. */
1037 if (copied > width) {
1039 t = (1ul << width) - 1;
1040 t <<= dalign + need_prime*8;
1045 /* Attempt to use 64-byte copies. This is only possible if the
1046 source and destination are co-aligned at 64 bytes. */
1047 n64 = need_second = 0;
1048 if ((dpos & 63) == (spos & 63)
1049 && (height == 1 || line_length % 64 == 0)) {
1050 /* We may need a 32-byte copy to ensure 64 byte alignment. */
1051 need_second = (dpos + xincr_first) & 63;
1052 if ((need_second & 32) != need_second)
1053 printk(KERN_ERR "tgafb: need_second wrong\n");
1054 if (left >= need_second + 64) {
1055 left -= need_second;
1062 /* Copy trailing full 32-byte sections. This will be the main
1063 loop if the 64 byte loop can't be used. */
1067 /* Copy the trailing unaligned destination. */
1068 dmask_last = (1ul << left) - 1;
1070 tga_regs = par->tga_regs_base;
1071 tga_fb = par->tga_fb_base;
1073 /* Set up the MODE and PIXELSHIFT registers. */
1074 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1075 __raw_writel(pixel_shift, tga_regs+TGA_PIXELSHIFT_REG);
1078 for (i = 0; i < height; ++i) {
1083 sfb = tga_fb + spos;
1084 dfb = tga_fb + dpos;
1086 __raw_writel(smask_first, sfb);
1088 __raw_writel(dmask_first, dfb);
1095 __raw_writel(0xffffffff, sfb);
1097 __raw_writel(0xffffffff, dfb);
1103 if (n64 && (((unsigned long)sfb | (unsigned long)dfb) & 63))
1105 "tgafb: misaligned copy64 (s:%p, d:%p)\n",
1108 for (j = 0; j < n64; ++j) {
1109 __raw_writel(sfb - tga_fb, tga_regs+TGA_COPY64_SRC);
1111 __raw_writel(dfb - tga_fb, tga_regs+TGA_COPY64_DST);
1117 for (j = 0; j < n32; ++j) {
1118 __raw_writel(0xffffffff, sfb);
1120 __raw_writel(0xffffffff, dfb);
1127 __raw_writel(0xffffffff, sfb);
1129 __raw_writel(dmask_last, dfb);
1137 /* Reset the MODE register to normal. */
1138 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1141 /* The (almost) general case of backward copy in 8bpp mode. */
1143 copyarea_backward_8bpp(struct fb_info *info, u32 dx, u32 dy, u32 sx, u32 sy,
1144 u32 height, u32 width, u32 line_length,
1145 const struct fb_copyarea *area)
1147 struct tga_par *par = (struct tga_par *) info->par;
1148 unsigned long i, left, yincr;
1149 unsigned long depos, sepos, dealign, sealign;
1150 u32 mask_first, mask_last;
1152 void __iomem *tga_regs;
1153 void __iomem *tga_fb;
1155 yincr = line_length;
1162 /* Compute the offsets and alignments in the frame buffer.
1163 More than anything else, these control how we do copies. */
1164 depos = dy * line_length + dx + width;
1165 sepos = sy * line_length + sx + width;
1166 dealign = depos & 7;
1167 sealign = sepos & 7;
1169 /* ??? The documentation appears to be incorrect (or very
1170 misleading) wrt how pixel shifting works in backward copy
1171 mode, i.e. when PIXELSHIFT is negative. I give up for now.
1172 Do handle the common case of co-aligned backward copies,
1173 but frob everything else back on generic code. */
1174 if (dealign != sealign) {
1175 cfb_copyarea(info, area);
1179 /* We begin the copy with the trailing pixels of the
1180 unaligned destination. */
1181 mask_first = (1ul << dealign) - 1;
1182 left = width - dealign;
1184 /* Care for small copies. */
1185 if (dealign > width) {
1186 mask_first ^= (1ul << (dealign - width)) - 1;
1190 /* Next copy full words at a time. */
1194 /* Finally copy the unaligned head of the span. */
1195 mask_last = -1 << (32 - left);
1197 tga_regs = par->tga_regs_base;
1198 tga_fb = par->tga_fb_base;
1200 /* Set up the MODE and PIXELSHIFT registers. */
1201 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_COPY, tga_regs+TGA_MODE_REG);
1202 __raw_writel(0, tga_regs+TGA_PIXELSHIFT_REG);
1205 for (i = 0; i < height; ++i) {
1210 sfb = tga_fb + sepos;
1211 dfb = tga_fb + depos;
1213 __raw_writel(mask_first, sfb);
1215 __raw_writel(mask_first, dfb);
1219 for (j = 0; j < n32; ++j) {
1222 __raw_writel(0xffffffff, sfb);
1224 __raw_writel(0xffffffff, dfb);
1231 __raw_writel(mask_last, sfb);
1233 __raw_writel(mask_last, dfb);
1241 /* Reset the MODE register to normal. */
1242 __raw_writel(TGA_MODE_SBM_8BPP|TGA_MODE_SIMPLE, tga_regs+TGA_MODE_REG);
1246 tgafb_copyarea(struct fb_info *info, const struct fb_copyarea *area)
1248 unsigned long dx, dy, width, height, sx, sy, vxres, vyres;
1249 unsigned long line_length, bpp;
1253 width = area->width;
1254 height = area->height;
1257 vxres = info->var.xres_virtual;
1258 vyres = info->var.yres_virtual;
1259 line_length = info->fix.line_length;
1261 /* The top left corners must be in the virtual screen. */
1262 if (dx > vxres || sx > vxres || dy > vyres || sy > vyres)
1265 /* Clip the destination. */
1266 if (dx + width > vxres)
1268 if (dy + height > vyres)
1269 height = vyres - dy;
1271 /* The source must be completely inside the virtual screen. */
1272 if (sx + width > vxres || sy + height > vyres)
1275 bpp = info->var.bits_per_pixel;
1277 /* Detect copies of the entire line. */
1278 if (width * (bpp >> 3) == line_length) {
1280 copyarea_line_8bpp(info, dy, sy, height, width);
1282 copyarea_line_32bpp(info, dy, sy, height, width);
1285 /* ??? The documentation is unclear to me exactly how the pixelshift
1286 register works in 32bpp mode. Since I don't have hardware to test,
1287 give up for now and fall back on the generic routines. */
1289 cfb_copyarea(info, area);
1291 /* Detect overlapping source and destination that requires
1293 else if (dy == sy && dx > sx && dx < sx + width)
1294 copyarea_backward_8bpp(info, dx, dy, sx, sy, height,
1295 width, line_length, area);
1297 copyarea_foreward_8bpp(info, dx, dy, sx, sy, height,
1298 width, line_length);
1307 tgafb_init_fix(struct fb_info *info)
1309 struct tga_par *par = (struct tga_par *)info->par;
1310 u8 tga_type = par->tga_type;
1311 const char *tga_type_name;
1314 case TGA_TYPE_8PLANE:
1315 tga_type_name = "Digital ZLXp-E1";
1317 case TGA_TYPE_24PLANE:
1318 tga_type_name = "Digital ZLXp-E2";
1320 case TGA_TYPE_24PLUSZ:
1321 tga_type_name = "Digital ZLXp-E3";
1324 tga_type_name = "Unknown";
1328 strlcpy(info->fix.id, tga_type_name, sizeof(info->fix.id));
1330 info->fix.type = FB_TYPE_PACKED_PIXELS;
1331 info->fix.type_aux = 0;
1332 info->fix.visual = (tga_type == TGA_TYPE_8PLANE
1333 ? FB_VISUAL_PSEUDOCOLOR
1334 : FB_VISUAL_DIRECTCOLOR);
1336 info->fix.line_length = par->xres * (par->bits_per_pixel >> 3);
1337 info->fix.smem_start = (size_t) par->tga_fb_base;
1338 info->fix.smem_len = info->fix.line_length * par->yres;
1339 info->fix.mmio_start = (size_t) par->tga_regs_base;
1340 info->fix.mmio_len = 512;
1342 info->fix.xpanstep = 0;
1343 info->fix.ypanstep = 0;
1344 info->fix.ywrapstep = 0;
1346 info->fix.accel = FB_ACCEL_DEC_TGA;
1349 static __devinit int
1350 tgafb_pci_register(struct pci_dev *pdev, const struct pci_device_id *ent)
1352 static unsigned int const fb_offset_presets[4] = {
1353 TGA_8PLANE_FB_OFFSET,
1354 TGA_24PLANE_FB_OFFSET,
1356 TGA_24PLUSZ_FB_OFFSET
1359 void __iomem *mem_base;
1360 unsigned long bar0_start, bar0_len;
1361 struct fb_info *info;
1362 struct tga_par *par;
1366 /* Enable device in PCI config. */
1367 if (pci_enable_device(pdev)) {
1368 printk(KERN_ERR "tgafb: Cannot enable PCI device\n");
1372 /* Allocate the fb and par structures. */
1373 info = framebuffer_alloc(sizeof(struct tga_par), &pdev->dev);
1375 printk(KERN_ERR "tgafb: Cannot allocate memory\n");
1380 pci_set_drvdata(pdev, info);
1382 /* Request the mem regions. */
1383 bar0_start = pci_resource_start(pdev, 0);
1384 bar0_len = pci_resource_len(pdev, 0);
1386 if (!request_mem_region (bar0_start, bar0_len, "tgafb")) {
1387 printk(KERN_ERR "tgafb: cannot reserve FB region\n");
1391 /* Map the framebuffer. */
1392 mem_base = ioremap(bar0_start, bar0_len);
1394 printk(KERN_ERR "tgafb: Cannot map MMIO\n");
1398 /* Grab info about the card. */
1399 tga_type = (readl(mem_base) >> 12) & 0x0f;
1401 par->tga_mem_base = mem_base;
1402 par->tga_fb_base = mem_base + fb_offset_presets[tga_type];
1403 par->tga_regs_base = mem_base + TGA_REGS_OFFSET;
1404 par->tga_type = tga_type;
1405 pci_read_config_byte(pdev, PCI_REVISION_ID, &par->tga_chip_rev);
1407 /* Setup framebuffer. */
1408 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_COPYAREA |
1409 FBINFO_HWACCEL_IMAGEBLIT | FBINFO_HWACCEL_FILLRECT;
1410 info->fbops = &tgafb_ops;
1411 info->screen_base = par->tga_fb_base;
1412 info->pseudo_palette = (void *)(par + 1);
1414 /* This should give a reasonable default video mode. */
1416 ret = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL,
1417 tga_type == TGA_TYPE_8PLANE ? 8 : 32);
1418 if (ret == 0 || ret == 4) {
1419 printk(KERN_ERR "tgafb: Could not find valid video mode\n");
1424 if (fb_alloc_cmap(&info->cmap, 256, 0)) {
1425 printk(KERN_ERR "tgafb: Could not allocate color map\n");
1430 tgafb_set_par(info);
1431 tgafb_init_fix(info);
1433 if (register_framebuffer(info) < 0) {
1434 printk(KERN_ERR "tgafb: Could not register framebuffer\n");
1439 printk(KERN_INFO "tgafb: DC21030 [TGA] detected, rev=0x%02x\n",
1441 printk(KERN_INFO "tgafb: at PCI bus %d, device %d, function %d\n",
1442 pdev->bus->number, PCI_SLOT(pdev->devfn),
1443 PCI_FUNC(pdev->devfn));
1444 printk(KERN_INFO "fb%d: %s frame buffer device at 0x%lx\n",
1445 info->node, info->fix.id, bar0_start);
1452 release_mem_region(bar0_start, bar0_len);
1454 framebuffer_release(info);
1458 static void __devexit
1459 tgafb_pci_unregister(struct pci_dev *pdev)
1461 struct fb_info *info = pci_get_drvdata(pdev);
1462 struct tga_par *par = info->par;
1466 unregister_framebuffer(info);
1467 fb_dealloc_cmap(&info->cmap);
1468 iounmap(par->tga_mem_base);
1469 release_mem_region(pci_resource_start(pdev, 0),
1470 pci_resource_len(pdev, 0));
1471 framebuffer_release(info);
1474 static void __devexit
1477 pci_unregister_driver(&tgafb_driver);
1481 static int __devinit
1482 tgafb_setup(char *arg)
1487 while ((this_opt = strsep(&arg, ","))) {
1490 if (!strncmp(this_opt, "mode:", 5))
1491 mode_option = this_opt+5;
1494 "tgafb: unknown parameter %s\n",
1501 #endif /* !MODULE */
1503 static int __devinit
1507 char *option = NULL;
1509 if (fb_get_options("tgafb", &option))
1511 tgafb_setup(option);
1513 return pci_register_driver(&tgafb_driver);
1520 module_init(tgafb_init);
1521 module_exit(tgafb_exit);
1523 MODULE_DESCRIPTION("framebuffer driver for TGA chipset");
1524 MODULE_LICENSE("GPL");