2 * linux/drivers/video/savagefb.h -- S3 Savage Framebuffer Driver
4 * Copyright (c) 2001 Denis Oliver Kropp <dok@convergence.de>
6 * This file is subject to the terms and conditions of the GNU General
7 * Public License. See the file COPYING in the main directory of this
8 * archive for more details.
12 #ifndef __SAVAGEFB_H__
13 #define __SAVAGEFB_H__
15 #include <linux/i2c.h>
16 #include <linux/i2c-id.h>
17 #include <linux/i2c-algo-bit.h>
21 # define DBG(x) printk (KERN_DEBUG "savagefb: %s\n", (x));
24 # define SavagePrintRegs(...)
28 #define PCI_CHIP_SAVAGE4 0x8a22
29 #define PCI_CHIP_SAVAGE3D 0x8a20
30 #define PCI_CHIP_SAVAGE3D_MV 0x8a21
31 #define PCI_CHIP_SAVAGE2000 0x9102
32 #define PCI_CHIP_SAVAGE_MX_MV 0x8c10
33 #define PCI_CHIP_SAVAGE_MX 0x8c11
34 #define PCI_CHIP_SAVAGE_IX_MV 0x8c12
35 #define PCI_CHIP_SAVAGE_IX 0x8c13
36 #define PCI_CHIP_PROSAVAGE_PM 0x8a25
37 #define PCI_CHIP_PROSAVAGE_KM 0x8a26
38 /* Twister is a code name; hope I get the real name soon. */
39 #define PCI_CHIP_S3TWISTER_P 0x8d01
40 #define PCI_CHIP_S3TWISTER_K 0x8d02
41 #define PCI_CHIP_PROSAVAGE_DDR 0x8d03
42 #define PCI_CHIP_PROSAVAGE_DDRK 0x8d04
43 #define PCI_CHIP_SUPSAV_MX128 0x8c22
44 #define PCI_CHIP_SUPSAV_MX64 0x8c24
45 #define PCI_CHIP_SUPSAV_MX64C 0x8c26
46 #define PCI_CHIP_SUPSAV_IX128SDR 0x8c2a
47 #define PCI_CHIP_SUPSAV_IX128DDR 0x8c2b
48 #define PCI_CHIP_SUPSAV_IX64SDR 0x8c2c
49 #define PCI_CHIP_SUPSAV_IX64DDR 0x8c2d
50 #define PCI_CHIP_SUPSAV_IXCSDR 0x8c2e
51 #define PCI_CHIP_SUPSAV_IXCDDR 0x8c2f
55 #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX))
57 #define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) || (chip==S3_PROSAVAGE))
59 #define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE))
61 #define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000))
63 #define S3_MOBILE_TWISTER_SERIES(chip) ((chip==S3_TWISTER) || (chip == S3_PROSAVAGEDDR))
65 /* Chip tags. These are used to group the adapters into
82 #define BIOS_BSIZE 1024
83 #define BIOS_BASE 0xc0000
85 #define SAVAGE_NEWMMIO_REGBASE_S3 0x1000000 /* 16MB */
86 #define SAVAGE_NEWMMIO_REGBASE_S4 0x0000000
87 #define SAVAGE_NEWMMIO_REGSIZE 0x0080000 /* 512kb */
88 #define SAVAGE_NEWMMIO_VGABASE 0x8000
90 #define BASE_FREQ 14318
91 #define HALF_BASE_FREQ 7159
93 #define FIFO_CONTROL_REG 0x8200
94 #define MIU_CONTROL_REG 0x8204
95 #define STREAMS_TIMEOUT_REG 0x8208
96 #define MISC_TIMEOUT_REG 0x820c
98 #define MONO_PAT_0 0xa4e8
99 #define MONO_PAT_1 0xa4ec
101 #define MAXFIFO 0x7f00
103 #define BCI_CMD_NOP 0x40000000
104 #define BCI_CMD_SETREG 0x96000000
105 #define BCI_CMD_RECT 0x48000000
106 #define BCI_CMD_RECT_XP 0x01000000
107 #define BCI_CMD_RECT_YP 0x02000000
108 #define BCI_CMD_SEND_COLOR 0x00008000
109 #define BCI_CMD_DEST_GBD 0x00000000
110 #define BCI_CMD_SRC_GBD 0x00000020
111 #define BCI_CMD_SRC_SOLID 0x00000000
112 #define BCI_CMD_SRC_MONO 0x00000060
113 #define BCI_CMD_CLIP_NEW 0x00006000
114 #define BCI_CMD_CLIP_LR 0x00004000
116 #define BCI_CLIP_LR(l, r) ((((r) << 16) | (l)) & 0x0FFF0FFF)
117 #define BCI_CLIP_TL(t, l) ((((t) << 16) | (l)) & 0x0FFF0FFF)
118 #define BCI_CLIP_BR(b, r) ((((b) << 16) | (r)) & 0x0FFF0FFF)
119 #define BCI_W_H(w, h) (((h) << 16) | ((w) & 0xFFF))
120 #define BCI_X_Y(x, y) (((y) << 16) | ((x) & 0xFFF))
122 #define BCI_GBD1 0xE0
123 #define BCI_GBD2 0xE1
125 #define BCI_BUFFER_OFFSET 0x10000
126 #define BCI_SIZE 0x4000
128 #define BCI_SEND(dw) writel(dw, par->bci_base + par->bci_ptr++)
130 #define BCI_CMD_GET_ROP(cmd) (((cmd) >> 16) & 0xFF)
131 #define BCI_CMD_SET_ROP(cmd, rop) ((cmd) |= ((rop & 0xFF) << 16))
132 #define BCI_CMD_SEND_COLOR 0x00008000
140 unsigned int HDisplay;
141 unsigned int HSyncStart;
142 unsigned int HSyncEnd;
144 unsigned int HAdjusted;
145 unsigned int VDisplay;
146 unsigned int VSyncStart;
147 unsigned int VSyncEnd;
155 /* --------------------------------------------------------------------- */
157 #define NR_PALETTE 256
162 struct savagefb_i2c_chan {
163 struct savagefb_par *par;
164 struct i2c_adapter adapter;
165 struct i2c_algo_bit_data algo;
166 volatile u8 __iomem *ioaddr;
170 struct savagefb_par {
171 struct pci_dev *pcidev;
173 struct savagefb_i2c_chan chan;
175 u32 pseudo_palette[16];
195 volatile u8 __iomem *vbase;
200 volatile u32 __iomem *bci_base;
201 unsigned int bci_ptr;
207 void (*SavageWaitIdle) (struct savagefb_par *par);
208 void (*SavageWaitFifo) (struct savagefb_par *par, int space);
210 int MCLK, REFCLK, LCDclk;
211 int HorizScaleFactor;
214 int SavagePanelWidth;
215 int SavagePanelHeight;
218 u16 red, green, blue, transp;
219 } palette[NR_PALETTE];
224 unsigned char MiscOutReg; /* Misc */
225 unsigned char CRTC[25]; /* Crtc Controller */
226 unsigned char Sequencer[5]; /* Video Sequencer */
227 unsigned char Graphics[9]; /* Video Graphics */
228 unsigned char Attribute[21]; /* Video Atribute */
230 unsigned int mode, refresh;
231 unsigned char SR08, SR0E, SR0F;
232 unsigned char SR10, SR11, SR12, SR13, SR15, SR18, SR29, SR30;
233 unsigned char SR54[8];
235 unsigned char CR31, CR32, CR33, CR34, CR36, CR3A, CR3B, CR3C;
236 unsigned char CR40, CR41, CR42, CR43, CR45;
237 unsigned char CR50, CR51, CR53, CR55, CR58, CR5B, CR5D, CR5E;
238 unsigned char CR60, CR63, CR65, CR66, CR67, CR68, CR69, CR6D, CR6F;
239 unsigned char CR86, CR88;
240 unsigned char CR90, CR91, CRB0;
241 unsigned int STREAMS[22]; /* yuck, streams regs */
242 unsigned int MMPR0, MMPR1, MMPR2, MMPR3;
245 #define BCI_BD_BW_DISABLE 0x10000000
246 #define BCI_BD_SET_BPP(bd, bpp) ((bd) |= (((bpp) & 0xFF) << 16))
247 #define BCI_BD_SET_STRIDE(bd, st) ((bd) |= ((st) & 0xFFFF))
252 #define vga_in8(addr) (inb (addr))
253 #define vga_in16(addr) (inw (addr))
254 #define vga_in32(addr) (inl (addr))
256 #define vga_out8(addr,val) (outb ((val), (addr)))
257 #define vga_out16(addr,val) (outw ((val), (addr)))
258 #define vga_out32(addr,val) (outl ((val), (addr)))
260 #define savage_in16(addr) readw(par->mmio.vbase + (addr))
261 #define savage_in32(addr) readl(par->mmio.vbase + (addr))
263 #define savage_out16(addr,val) writew((val), par->mmio.vbase + (addr))
264 #define savage_out32(addr,val) writel((val), par->mmio.vbase + (addr))
266 static inline u8 VGArCR (u8 index)
272 static inline u8 VGArGR (u8 index)
278 static inline u8 VGArSEQ (u8 index)
284 #define VGAwCR(index, val) \
286 vga_out8 (0x3d4, index); \
287 vga_out8 (0x3d5, val); \
290 #define VGAwGR(index, val) \
292 vga_out8 (0x3ce, index); \
293 vga_out8 (0x3cf, val); \
296 #define VGAwSEQ(index, val) \
298 vga_out8 (0x3c4, index); \
299 vga_out8 (0x3c5, val); \
302 #define VGAenablePalette() \
306 tmp = vga_in8 (0x3da); \
307 vga_out8 (0x3c0, 0x00); \
308 paletteEnabled = 1; \
311 #define VGAdisablePalette() \
315 tmp = vga_in8 (0x3da); \
316 vga_out8 (0x3c0, 0x20); \
317 paletteEnabled = 0; \
320 #define VGAwATTR(index, value) \
324 if (paletteEnabled) \
329 tmp = vga_in8 (0x3da); \
330 vga_out8 (0x3c0, index); \
331 vga_out8 (0x3c0, value); \
334 #define VGAwMISC(value) \
336 vga_out8 (0x3c2, value); \
339 #ifndef CONFIG_FB_SAVAGE_ACCEL
340 #define savagefb_set_clip(x)
343 #define VerticalRetraceWait() \
345 vga_out8 (0x3d4, 0x17); \
346 if (vga_in8 (0x3d5) & 0x80) { \
347 while ((vga_in8(0x3da) & 0x08) == 0x08) ; \
348 while ((vga_in8(0x3da) & 0x08) == 0x00) ; \
352 extern int savagefb_probe_i2c_connector(struct fb_info *info,
354 extern void savagefb_create_i2c_busses(struct fb_info *info);
355 extern void savagefb_delete_i2c_busses(struct fb_info *info);
356 extern int savagefb_sync(struct fb_info *info);
357 extern void savagefb_copyarea(struct fb_info *info,
358 const struct fb_copyarea *region);
359 extern void savagefb_fillrect(struct fb_info *info,
360 const struct fb_fillrect *rect);
361 extern void savagefb_imageblit(struct fb_info *info,
362 const struct fb_image *image);
365 #endif /* __SAVAGEFB_H__ */