2 * linux/drivers/video/nvidia/nvidia.c - nVidia fb driver
4 * Copyright 2004 Antonino Daplas <adaplas@pol.net>
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file COPYING in the main directory of this archive
12 #include <linux/config.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/errno.h>
16 #include <linux/string.h>
18 #include <linux/tty.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
22 #include <linux/init.h>
23 #include <linux/pci.h>
29 #include <asm/pci-bridge.h>
31 #ifdef CONFIG_PMAC_BACKLIGHT
32 #include <asm/backlight.h>
40 #ifndef CONFIG_PCI /* sanity check */
41 #error This driver requires PCI support.
44 #undef CONFIG_FB_NVIDIA_DEBUG
45 #ifdef CONFIG_FB_NVIDIA_DEBUG
46 #define NVTRACE printk
48 #define NVTRACE if (0) printk
51 #define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__)
52 #define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__)
54 #ifdef CONFIG_FB_NVIDIA_DEBUG
55 #define assert(expr) \
57 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
58 #expr,__FILE__,__FUNCTION__,__LINE__); \
65 #define PFX "nvidiafb: "
67 /* HW cursor parameters */
70 static struct pci_device_id nvidiafb_pci_tbl[] = {
71 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
72 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
73 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
74 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
75 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
76 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
77 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT_UNKNOWN,
78 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
79 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
80 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
81 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
82 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
83 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
84 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
85 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
86 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
87 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
88 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
89 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
90 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
91 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
92 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
93 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
94 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
95 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
96 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
97 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
98 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
99 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
100 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
101 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
102 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
103 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
104 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
105 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
106 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
107 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
108 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
109 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
110 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
111 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
112 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
113 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_SE,
114 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
115 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
116 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
117 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
118 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
119 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_460_GO,
120 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
121 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
123 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
125 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
127 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
129 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
131 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
133 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_410_GO_M16,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
135 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_8X,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
137 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440SE_8X,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
139 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420_8X,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
141 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_448_GO,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
143 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_488_GO,
144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
145 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_580_XGL,
146 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
147 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_MAC,
148 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
149 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_280_NVS,
150 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
151 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_380_XGL,
152 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
153 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
154 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
155 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
156 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
157 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
159 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
161 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
163 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
165 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
167 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
169 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
171 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
173 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
175 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
177 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800_8X,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
179 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800SE,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
181 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_4200_GO,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
183 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_980_XGL,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
185 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_780_XGL,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
187 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700_GOGL,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
189 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800_ULTRA,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
191 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
193 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_2000,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
195 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1000,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
197 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600_ULTRA,
198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
199 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600,
200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
201 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600SE,
202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
203 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5600,
204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
205 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5650,
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
207 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO700,
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
209 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200,
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
211 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_ULTRA,
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
213 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_1,
214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
215 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200SE,
216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
217 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200,
218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
219 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250,
220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
221 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250_32,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
223 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
225 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_NVS_280_PCI,
226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
227 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_500,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
229 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5300,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
231 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5100,
232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
233 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900_ULTRA,
234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
235 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900,
236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
237 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900XT,
238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
239 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5950_ULTRA,
240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
241 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_3000,
242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
243 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700_ULTRA,
244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
245 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700,
246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
247 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700LE,
248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
249 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700VE,
250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
251 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_1,
252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
253 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_2,
254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
255 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO1000,
256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
257 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100,
258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
259 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5500,
260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
261 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5100,
262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
263 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_700,
264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
265 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900ZT,
266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
267 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_ULTRA,
268 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
269 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800,
270 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
271 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_LE,
272 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
273 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_GT,
274 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
275 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_4000,
276 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
277 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6600_GT,
278 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
279 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6600,
280 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
281 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6610_XL,
282 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
283 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_FX_540,
284 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
285 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6200,
286 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
287 {PCI_VENDOR_ID_NVIDIA, 0x0252,
288 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
289 {PCI_VENDOR_ID_NVIDIA, 0x0313,
290 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
291 {PCI_VENDOR_ID_NVIDIA, 0x0316,
292 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
293 {PCI_VENDOR_ID_NVIDIA, 0x0317,
294 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
295 {PCI_VENDOR_ID_NVIDIA, 0x031D,
296 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
297 {PCI_VENDOR_ID_NVIDIA, 0x031E,
298 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
299 {PCI_VENDOR_ID_NVIDIA, 0x031F,
300 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
301 {PCI_VENDOR_ID_NVIDIA, 0x0329,
302 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
303 {PCI_VENDOR_ID_NVIDIA, 0x032F,
304 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
305 {PCI_VENDOR_ID_NVIDIA, 0x0345,
306 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
307 {PCI_VENDOR_ID_NVIDIA, 0x0349,
308 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
309 {PCI_VENDOR_ID_NVIDIA, 0x034B,
310 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
311 {PCI_VENDOR_ID_NVIDIA, 0x034F,
312 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
313 {PCI_VENDOR_ID_NVIDIA, 0x00c0,
314 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
315 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_6800A,
316 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
317 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_6800A_LE,
318 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
319 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_GO_6800,
320 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
321 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_GEFORCE_GO_6800_ULTRA,
322 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
323 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_QUADRO_FX_GO1400,
324 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
325 {PCI_VENDOR_ID_NVIDIA, 0x00cd,
326 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
327 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_QUADRO_FX_1400,
328 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
329 {PCI_VENDOR_ID_NVIDIA, 0x0142,
330 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
331 {PCI_VENDOR_ID_NVIDIA, 0x0143,
332 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
333 {PCI_VENDOR_ID_NVIDIA, 0x0144,
334 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
335 {PCI_VENDOR_ID_NVIDIA, 0x0145,
336 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
337 {PCI_VENDOR_ID_NVIDIA, 0x0146,
338 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
339 {PCI_VENDOR_ID_NVIDIA, 0x0147,
340 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
341 {PCI_VENDOR_ID_NVIDIA, 0x0148,
342 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
343 {PCI_VENDOR_ID_NVIDIA, 0x0149,
344 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
345 {PCI_VENDOR_ID_NVIDIA, 0x014b,
346 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
347 {PCI_VENDOR_ID_NVIDIA, 0x14c,
348 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
349 {PCI_VENDOR_ID_NVIDIA, 0x014d,
350 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
351 {PCI_VENDOR_ID_NVIDIA, 0x0160,
352 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
353 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6200_TURBOCACHE,
354 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
355 {PCI_VENDOR_ID_NVIDIA, 0x0162,
356 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
357 {PCI_VENDOR_ID_NVIDIA, 0x0163,
358 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
359 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200,
360 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
361 {PCI_VENDOR_ID_NVIDIA, 0x0165,
362 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
363 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250,
364 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
365 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200_1,
366 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
367 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250_1,
368 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
369 {PCI_VENDOR_ID_NVIDIA, 0x0169,
370 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
371 {PCI_VENDOR_ID_NVIDIA, 0x016b,
372 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
373 {PCI_VENDOR_ID_NVIDIA, 0x016c,
374 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
375 {PCI_VENDOR_ID_NVIDIA, 0x016d,
376 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
377 {PCI_VENDOR_ID_NVIDIA, 0x016e,
378 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
379 {PCI_VENDOR_ID_NVIDIA, 0x0210,
380 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
381 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B,
382 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
383 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_LE,
384 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
385 {PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_GT,
386 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
387 {PCI_VENDOR_ID_NVIDIA, 0x021d,
388 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
389 {PCI_VENDOR_ID_NVIDIA, 0x021e,
390 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
391 {PCI_VENDOR_ID_NVIDIA, 0x0220,
392 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
393 {PCI_VENDOR_ID_NVIDIA, 0x0221,
394 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
395 {PCI_VENDOR_ID_NVIDIA, 0x0222,
396 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
397 {PCI_VENDOR_ID_NVIDIA, 0x0228,
398 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
399 {0,} /* terminate list */
402 MODULE_DEVICE_TABLE(pci, nvidiafb_pci_tbl);
404 /* command line data, set in nvidiafb_setup() */
405 static int flatpanel __devinitdata = -1; /* Autodetect later */
406 static int forceCRTC __devinitdata = -1;
407 static int hwcur __devinitdata = 0;
408 static int noaccel __devinitdata = 0;
409 static int noscale __devinitdata = 0;
410 static int paneltweak __devinitdata = 0;
412 static int nomtrr __devinitdata = 0;
415 static char *mode_option __devinitdata = NULL;
417 static struct fb_fix_screeninfo __devinitdata nvidiafb_fix = {
418 .type = FB_TYPE_PACKED_PIXELS,
423 static struct fb_var_screeninfo __devinitdata nvidiafb_default_var = {
433 .activate = FB_ACTIVATE_NOW,
443 .vmode = FB_VMODE_NONINTERLACED
449 #ifdef CONFIG_PMAC_BACKLIGHT
451 static int nvidia_backlight_levels[] = {
470 /* ------------------------------------------------------------------------- *
472 * Backlight operations
474 * ------------------------------------------------------------------------- */
476 static int nvidia_set_backlight_enable(int on, int level, void *data)
478 struct nvidia_par *par = (struct nvidia_par *)data;
479 u32 tmp_pcrt, tmp_pmc, fpcontrol;
481 tmp_pmc = NV_RD32(par->PMC, 0x10F0) & 0x0000FFFF;
482 tmp_pcrt = NV_RD32(par->PCRTC0, 0x081C) & 0xFFFFFFFC;
483 fpcontrol = NV_RD32(par->PRAMDAC, 0x0848) & 0xCFFFFFCC;
485 if (on && (level > BACKLIGHT_OFF)) {
487 tmp_pmc |= (1 << 31); // backlight bit
488 tmp_pmc |= nvidia_backlight_levels[level - 1] << 16;
492 fpcontrol |= par->fpSyncs;
494 fpcontrol |= 0x20000022;
496 NV_WR32(par->PCRTC0, 0x081C, tmp_pcrt);
497 NV_WR32(par->PMC, 0x10F0, tmp_pmc);
498 NV_WR32(par->PRAMDAC, 0x848, fpcontrol);
503 static int nvidia_set_backlight_level(int level, void *data)
505 return nvidia_set_backlight_enable(1, level, data);
508 static struct backlight_controller nvidia_backlight_controller = {
509 nvidia_set_backlight_enable,
510 nvidia_set_backlight_level
513 #endif /* CONFIG_PMAC_BACKLIGHT */
515 static void nvidiafb_load_cursor_image(struct nvidia_par *par, u8 * data8,
516 u16 bg, u16 fg, u32 w, u32 h)
520 u32 *data = (u32 *) data8;
524 for (i = 0; i < h; i++) {
528 for (j = 0; j < w / 2; j++) {
530 #if defined (__BIG_ENDIAN)
531 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
533 tmp |= (b & (1 << 31)) ? fg : bg;
536 tmp = (b & 1) ? fg : bg;
538 tmp |= (b & 1) ? fg << 16 : bg << 16;
541 NV_WR32(&par->CURSOR[k++], 0, tmp);
543 k += (MAX_CURS - w) / 2;
547 static void nvidia_write_clut(struct nvidia_par *par,
548 u8 regnum, u8 red, u8 green, u8 blue)
550 NVWriteDacMask(par, 0xff);
551 NVWriteDacWriteAddr(par, regnum);
552 NVWriteDacData(par, red);
553 NVWriteDacData(par, green);
554 NVWriteDacData(par, blue);
557 static void nvidia_read_clut(struct nvidia_par *par,
558 u8 regnum, u8 * red, u8 * green, u8 * blue)
560 NVWriteDacMask(par, 0xff);
561 NVWriteDacReadAddr(par, regnum);
562 *red = NVReadDacData(par);
563 *green = NVReadDacData(par);
564 *blue = NVReadDacData(par);
567 static int nvidia_panel_tweak(struct nvidia_par *par,
568 struct _riva_hw_state *state)
572 if (par->paneltweak) {
573 tweak = par->paneltweak;
575 /* begin flat panel hacks */
576 /* This is unfortunate, but some chips need this register
577 tweaked or else you get artifacts where adjacent pixels are
578 swapped. There are no hard rules for what to set here so all
579 we can do is experiment and apply hacks. */
581 if(((par->Chipset & 0xffff) == 0x0328) && (state->bpp == 32)) {
582 /* At least one NV34 laptop needs this workaround. */
586 if((par->Chipset & 0xfff0) == 0x0310) {
589 /* end flat panel hacks */
595 static void nvidia_save_vga(struct nvidia_par *par,
596 struct _riva_hw_state *state)
601 NVLockUnlock(par, 0);
603 NVUnloadStateExt(par, state);
605 state->misc_output = NVReadMiscOut(par);
607 for (i = 0; i < NUM_CRT_REGS; i++)
608 state->crtc[i] = NVReadCrtc(par, i);
610 for (i = 0; i < NUM_ATC_REGS; i++)
611 state->attr[i] = NVReadAttr(par, i);
613 for (i = 0; i < NUM_GRC_REGS; i++)
614 state->gra[i] = NVReadGr(par, i);
616 for (i = 0; i < NUM_SEQ_REGS; i++)
617 state->seq[i] = NVReadSeq(par, i);
621 static void nvidia_write_regs(struct nvidia_par *par)
623 struct _riva_hw_state *state = &par->ModeReg;
627 NVWriteCrtc(par, 0x11, 0x00);
629 NVLockUnlock(par, 0);
631 NVLoadStateExt(par, state);
633 NVWriteMiscOut(par, state->misc_output);
635 for (i = 0; i < NUM_CRT_REGS; i++) {
641 NVWriteCrtc(par, i, state->crtc[i]);
645 for (i = 0; i < NUM_ATC_REGS; i++)
646 NVWriteAttr(par, i, state->attr[i]);
648 for (i = 0; i < NUM_GRC_REGS; i++)
649 NVWriteGr(par, i, state->gra[i]);
651 for (i = 0; i < NUM_SEQ_REGS; i++)
652 NVWriteSeq(par, i, state->seq[i]);
656 static int nvidia_calc_regs(struct fb_info *info)
658 struct nvidia_par *par = info->par;
659 struct _riva_hw_state *state = &par->ModeReg;
660 int i, depth = fb_get_color_depth(&info->var);
661 int h_display = info->var.xres / 8 - 1;
662 int h_start = (info->var.xres + info->var.right_margin) / 8 - 1;
663 int h_end = (info->var.xres + info->var.right_margin +
664 info->var.hsync_len) / 8 - 1;
665 int h_total = (info->var.xres + info->var.right_margin +
666 info->var.hsync_len + info->var.left_margin) / 8 - 5;
667 int h_blank_s = h_display;
668 int h_blank_e = h_total + 4;
669 int v_display = info->var.yres - 1;
670 int v_start = info->var.yres + info->var.lower_margin - 1;
671 int v_end = (info->var.yres + info->var.lower_margin +
672 info->var.vsync_len) - 1;
673 int v_total = (info->var.yres + info->var.lower_margin +
674 info->var.vsync_len + info->var.upper_margin) - 2;
675 int v_blank_s = v_display;
676 int v_blank_e = v_total + 1;
679 * Set all CRTC values.
682 if (info->var.vmode & FB_VMODE_INTERLACED)
685 if (par->FlatPanel == 1) {
686 v_start = v_total - 3;
689 h_start = h_total - 5;
691 h_blank_e = h_total + 4;
694 state->crtc[0x0] = Set8Bits(h_total);
695 state->crtc[0x1] = Set8Bits(h_display);
696 state->crtc[0x2] = Set8Bits(h_blank_s);
697 state->crtc[0x3] = SetBitField(h_blank_e, 4: 0, 4:0)
699 state->crtc[0x4] = Set8Bits(h_start);
700 state->crtc[0x5] = SetBitField(h_blank_e, 5: 5, 7:7)
701 | SetBitField(h_end, 4: 0, 4:0);
702 state->crtc[0x6] = SetBitField(v_total, 7: 0, 7:0);
703 state->crtc[0x7] = SetBitField(v_total, 8: 8, 0:0)
704 | SetBitField(v_display, 8: 8, 1:1)
705 | SetBitField(v_start, 8: 8, 2:2)
706 | SetBitField(v_blank_s, 8: 8, 3:3)
708 | SetBitField(v_total, 9: 9, 5:5)
709 | SetBitField(v_display, 9: 9, 6:6)
710 | SetBitField(v_start, 9: 9, 7:7);
711 state->crtc[0x9] = SetBitField(v_blank_s, 9: 9, 5:5)
713 | ((info->var.vmode & FB_VMODE_DOUBLE) ? 0x80 : 0x00);
714 state->crtc[0x10] = Set8Bits(v_start);
715 state->crtc[0x11] = SetBitField(v_end, 3: 0, 3:0) | SetBit(5);
716 state->crtc[0x12] = Set8Bits(v_display);
717 state->crtc[0x13] = ((info->var.xres_virtual / 8) *
718 (info->var.bits_per_pixel / 8));
719 state->crtc[0x15] = Set8Bits(v_blank_s);
720 state->crtc[0x16] = Set8Bits(v_blank_e);
722 state->attr[0x10] = 0x01;
725 state->attr[0x11] = 0x00;
727 state->screen = SetBitField(h_blank_e, 6: 6, 4:4)
728 | SetBitField(v_blank_s, 10: 10, 3:3)
729 | SetBitField(v_start, 10: 10, 2:2)
730 | SetBitField(v_display, 10: 10, 1:1)
731 | SetBitField(v_total, 10: 10, 0:0);
733 state->horiz = SetBitField(h_total, 8: 8, 0:0)
734 | SetBitField(h_display, 8: 8, 1:1)
735 | SetBitField(h_blank_s, 8: 8, 2:2)
736 | SetBitField(h_start, 8: 8, 3:3);
738 state->extra = SetBitField(v_total, 11: 11, 0:0)
739 | SetBitField(v_display, 11: 11, 2:2)
740 | SetBitField(v_start, 11: 11, 4:4)
741 | SetBitField(v_blank_s, 11: 11, 6:6);
743 if (info->var.vmode & FB_VMODE_INTERLACED) {
744 h_total = (h_total >> 1) & ~1;
745 state->interlace = Set8Bits(h_total);
746 state->horiz |= SetBitField(h_total, 8: 8, 4:4);
748 state->interlace = 0xff; /* interlace off */
752 * Calculate the extended registers.
760 if (par->Architecture >= NV_ARCH_10)
761 par->CURSOR = (volatile u32 __iomem *)(info->screen_base +
764 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
765 state->misc_output &= ~0x40;
767 state->misc_output |= 0x40;
768 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
769 state->misc_output &= ~0x80;
771 state->misc_output |= 0x80;
773 NVCalcStateExt(par, state, i, info->var.xres_virtual,
774 info->var.xres, info->var.yres_virtual,
775 1000000000 / info->var.pixclock, info->var.vmode);
777 state->scale = NV_RD32(par->PRAMDAC, 0x00000848) & 0xfff000ff;
778 if (par->FlatPanel == 1) {
779 state->pixel |= (1 << 7);
781 if (!par->fpScaler || (par->fpWidth <= info->var.xres)
782 || (par->fpHeight <= info->var.yres)) {
783 state->scale |= (1 << 8);
786 if (!par->crtcSync_read) {
787 state->crtcSync = NV_RD32(par->PRAMDAC, 0x0828);
788 par->crtcSync_read = 1;
791 par->PanelTweak = nvidia_panel_tweak(par, state);
794 state->vpll = state->pll;
795 state->vpll2 = state->pll;
796 state->vpllB = state->pllB;
797 state->vpll2B = state->pllB;
799 VGA_WR08(par->PCIO, 0x03D4, 0x1C);
800 state->fifo = VGA_RD08(par->PCIO, 0x03D5) & ~(1<<5);
802 if (par->CRTCnumber) {
803 state->head = NV_RD32(par->PCRTC0, 0x00000860) & ~0x00001000;
804 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) | 0x00001000;
805 state->crtcOwner = 3;
806 state->pllsel |= 0x20000800;
807 state->vpll = NV_RD32(par->PRAMDAC0, 0x00000508);
808 if (par->twoStagePLL)
809 state->vpllB = NV_RD32(par->PRAMDAC0, 0x00000578);
810 } else if (par->twoHeads) {
811 state->head = NV_RD32(par->PCRTC0, 0x00000860) | 0x00001000;
812 state->head2 = NV_RD32(par->PCRTC0, 0x00002860) & ~0x00001000;
813 state->crtcOwner = 0;
814 state->vpll2 = NV_RD32(par->PRAMDAC0, 0x0520);
815 if (par->twoStagePLL)
816 state->vpll2B = NV_RD32(par->PRAMDAC0, 0x057C);
819 state->cursorConfig = 0x00000100;
821 if (info->var.vmode & FB_VMODE_DOUBLE)
822 state->cursorConfig |= (1 << 4);
824 if (par->alphaCursor) {
825 if ((par->Chipset & 0x0ff0) != 0x0110)
826 state->cursorConfig |= 0x04011000;
828 state->cursorConfig |= 0x14011000;
829 state->general |= (1 << 29);
831 state->cursorConfig |= 0x02000000;
834 if ((par->Chipset & 0x0ff0) == 0x0110) {
835 state->dither = NV_RD32(par->PRAMDAC, 0x0528) &
838 state->dither |= 0x00010000;
840 state->dither = NV_RD32(par->PRAMDAC, 0x083C) & ~1;
848 state->displayV = info->var.xres;
853 static void nvidia_init_vga(struct fb_info *info)
855 struct nvidia_par *par = info->par;
856 struct _riva_hw_state *state = &par->ModeReg;
859 for (i = 0; i < 0x10; i++)
861 state->attr[0x10] = 0x41;
862 state->attr[0x11] = 0x01;
863 state->attr[0x12] = 0x0f;
864 state->attr[0x13] = 0x00;
865 state->attr[0x14] = 0x00;
867 memset(state->crtc, 0x00, NUM_CRT_REGS);
868 state->crtc[0x0a] = 0x20;
869 state->crtc[0x17] = 0xe3;
870 state->crtc[0x18] = 0xff;
871 state->crtc[0x28] = 0x40;
873 memset(state->gra, 0x00, NUM_GRC_REGS);
874 state->gra[0x05] = 0x40;
875 state->gra[0x06] = 0x05;
876 state->gra[0x07] = 0x0f;
877 state->gra[0x08] = 0xff;
879 state->seq[0x00] = 0x03;
880 state->seq[0x01] = 0x01;
881 state->seq[0x02] = 0x0f;
882 state->seq[0x03] = 0x00;
883 state->seq[0x04] = 0x0e;
885 state->misc_output = 0xeb;
888 static int nvidiafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
890 struct nvidia_par *par = info->par;
891 u8 data[MAX_CURS * MAX_CURS / 8];
893 int i, set = cursor->set;
895 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
896 return soft_cursor(info, cursor);
898 NVShowHideCursor(par, 0);
900 if (par->cursor_reset) {
902 par->cursor_reset = 0;
905 if (set & FB_CUR_SETSIZE)
906 memset_io(par->CURSOR, 0, MAX_CURS * MAX_CURS * 2);
908 if (set & FB_CUR_SETPOS) {
911 yy = cursor->image.dy - info->var.yoffset;
912 xx = cursor->image.dx - info->var.xoffset;
916 NV_WR32(par->PRAMDAC, 0x0000300, temp);
919 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
920 u32 bg_idx = cursor->image.bg_color;
921 u32 fg_idx = cursor->image.fg_color;
922 u32 s_pitch = (cursor->image.width + 7) >> 3;
923 u32 d_pitch = MAX_CURS / 8;
924 u8 *dat = (u8 *) cursor->image.data;
925 u8 *msk = (u8 *) cursor->mask;
928 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
931 switch (cursor->rop) {
933 for (i = 0; i < s_pitch * cursor->image.height;
935 src[i] = dat[i] ^ msk[i];
939 for (i = 0; i < s_pitch * cursor->image.height;
941 src[i] = dat[i] & msk[i];
945 fb_sysmove_buf_aligned(info, &info->pixmap, data,
946 d_pitch, src, s_pitch,
947 cursor->image.height);
949 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
950 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
951 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) | 1 << 15;
953 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
954 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
955 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) | 1 << 15;
957 NVLockUnlock(par, 0);
959 nvidiafb_load_cursor_image(par, data, bg, fg,
961 cursor->image.height);
967 NVShowHideCursor(par, 1);
972 static int nvidiafb_set_par(struct fb_info *info)
974 struct nvidia_par *par = info->par;
978 NVLockUnlock(par, 1);
979 if (!par->FlatPanel || (info->var.bits_per_pixel != 24) ||
983 nvidia_init_vga(info);
984 nvidia_calc_regs(info);
985 nvidia_write_regs(par);
987 NVLockUnlock(par, 0);
989 VGA_WR08(par->PCIO, 0x03D4, 0x44);
990 VGA_WR08(par->PCIO, 0x03D5, par->ModeReg.crtcOwner);
991 NVLockUnlock(par, 0);
994 NVWriteCrtc(par, 0x11, 0x00);
995 info->fix.line_length = (info->var.xres_virtual *
996 info->var.bits_per_pixel) >> 3;
997 info->fix.visual = (info->var.bits_per_pixel == 8) ?
998 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1000 if (info->var.accel_flags) {
1001 info->fbops->fb_imageblit = nvidiafb_imageblit;
1002 info->fbops->fb_fillrect = nvidiafb_fillrect;
1003 info->fbops->fb_copyarea = nvidiafb_copyarea;
1004 info->fbops->fb_sync = nvidiafb_sync;
1005 info->pixmap.scan_align = 4;
1006 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1007 NVResetGraphics(info);
1009 info->fbops->fb_imageblit = cfb_imageblit;
1010 info->fbops->fb_fillrect = cfb_fillrect;
1011 info->fbops->fb_copyarea = cfb_copyarea;
1012 info->fbops->fb_sync = NULL;
1013 info->pixmap.scan_align = 1;
1014 info->flags |= FBINFO_HWACCEL_DISABLED;
1017 par->cursor_reset = 1;
1019 NVWriteCrtc(par, 0x11, 0xff);
1025 static int nvidiafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1026 unsigned blue, unsigned transp,
1027 struct fb_info *info)
1029 struct nvidia_par *par = info->par;
1033 if (regno >= (1 << info->var.green.length))
1036 if (info->var.grayscale) {
1037 /* gray = 0.30*R + 0.59*G + 0.11*B */
1038 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
1041 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1042 ((u32 *) info->pseudo_palette)[regno] =
1043 (regno << info->var.red.offset) |
1044 (regno << info->var.green.offset) |
1045 (regno << info->var.blue.offset);
1048 switch (info->var.bits_per_pixel) {
1050 /* "transparent" stuff is completely ignored. */
1051 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
1054 if (info->var.green.length == 5) {
1055 for (i = 0; i < 8; i++) {
1056 nvidia_write_clut(par, regno * 8 + i, red >> 8,
1057 green >> 8, blue >> 8);
1063 for (i = 0; i < 8; i++) {
1064 nvidia_write_clut(par, regno * 8 + i,
1065 red >> 8, green >> 8,
1070 nvidia_read_clut(par, regno * 4, &r, &g, &b);
1072 for (i = 0; i < 4; i++)
1073 nvidia_write_clut(par, regno * 4 + i, r,
1078 nvidia_write_clut(par, regno, red >> 8, green >> 8, blue >> 8);
1089 static int nvidiafb_check_var(struct fb_var_screeninfo *var,
1090 struct fb_info *info)
1092 struct nvidia_par *par = info->par;
1093 int memlen, vramlen, mode_valid = 0;
1098 var->transp.offset = 0;
1099 var->transp.length = 0;
1103 if (var->bits_per_pixel <= 8)
1104 var->bits_per_pixel = 8;
1105 else if (var->bits_per_pixel <= 16)
1106 var->bits_per_pixel = 16;
1108 var->bits_per_pixel = 32;
1110 switch (var->bits_per_pixel) {
1112 var->red.offset = 0;
1113 var->red.length = 8;
1114 var->green.offset = 0;
1115 var->green.length = 8;
1116 var->blue.offset = 0;
1117 var->blue.length = 8;
1118 var->transp.offset = 0;
1119 var->transp.length = 0;
1122 var->green.length = (var->green.length < 6) ? 5 : 6;
1123 var->red.length = 5;
1124 var->blue.length = 5;
1125 var->transp.length = 6 - var->green.length;
1126 var->blue.offset = 0;
1127 var->green.offset = 5;
1128 var->red.offset = 5 + var->green.length;
1129 var->transp.offset = (5 + var->red.offset) & 15;
1131 case 32: /* RGBA 8888 */
1132 var->red.offset = 16;
1133 var->red.length = 8;
1134 var->green.offset = 8;
1135 var->green.length = 8;
1136 var->blue.offset = 0;
1137 var->blue.length = 8;
1138 var->transp.length = 8;
1139 var->transp.offset = 24;
1143 var->red.msb_right = 0;
1144 var->green.msb_right = 0;
1145 var->blue.msb_right = 0;
1146 var->transp.msb_right = 0;
1148 if (!info->monspecs.hfmax || !info->monspecs.vfmax ||
1149 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
1152 /* calculate modeline if supported by monitor */
1153 if (!mode_valid && info->monspecs.gtf) {
1154 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1159 struct fb_videomode *mode;
1161 mode = fb_find_best_mode(var, &info->modelist);
1163 fb_videomode_to_var(var, mode);
1168 if (!mode_valid && info->monspecs.modedb_len)
1171 if (par->fpWidth && par->fpHeight && (par->fpWidth < var->xres ||
1172 par->fpHeight < var->yres))
1175 if (var->yres_virtual < var->yres)
1176 var->yres_virtual = var->yres;
1178 if (var->xres_virtual < var->xres)
1179 var->xres_virtual = var->xres;
1181 var->xres_virtual = (var->xres_virtual + 63) & ~63;
1183 vramlen = info->fix.smem_len;
1184 pitch = ((var->xres_virtual * var->bits_per_pixel) + 7) / 8;
1185 memlen = pitch * var->yres_virtual;
1187 if (memlen > vramlen) {
1188 var->yres_virtual = vramlen / pitch;
1190 if (var->yres_virtual < var->yres) {
1191 var->yres_virtual = var->yres;
1192 var->xres_virtual = vramlen / var->yres_virtual;
1193 var->xres_virtual /= var->bits_per_pixel / 8;
1194 var->xres_virtual &= ~63;
1195 pitch = (var->xres_virtual *
1196 var->bits_per_pixel + 7) / 8;
1197 memlen = pitch * var->yres;
1199 if (var->xres_virtual < var->xres) {
1200 printk("nvidiafb: required video memory, "
1201 "%d bytes, for %dx%d-%d (virtual) "
1202 "is out of range\n",
1203 memlen, var->xres_virtual,
1204 var->yres_virtual, var->bits_per_pixel);
1210 if (var->accel_flags) {
1211 if (var->yres_virtual > 0x7fff)
1212 var->yres_virtual = 0x7fff;
1213 if (var->xres_virtual > 0x7fff)
1214 var->xres_virtual = 0x7fff;
1217 var->xres_virtual &= ~63;
1224 static int nvidiafb_pan_display(struct fb_var_screeninfo *var,
1225 struct fb_info *info)
1227 struct nvidia_par *par = info->par;
1230 total = info->var.yoffset * info->fix.line_length + info->var.xoffset;
1232 NVSetStartAddress(par, total);
1237 static int nvidiafb_blank(int blank, struct fb_info *info)
1239 struct nvidia_par *par = info->par;
1240 unsigned char tmp, vesa;
1242 tmp = NVReadSeq(par, 0x01) & ~0x20; /* screen on/off */
1243 vesa = NVReadCrtc(par, 0x1a) & ~0xc0; /* sync on/off */
1251 case FB_BLANK_UNBLANK:
1252 case FB_BLANK_NORMAL:
1254 case FB_BLANK_VSYNC_SUSPEND:
1257 case FB_BLANK_HSYNC_SUSPEND:
1260 case FB_BLANK_POWERDOWN:
1265 NVWriteSeq(par, 0x01, tmp);
1266 NVWriteCrtc(par, 0x1a, vesa);
1268 #ifdef CONFIG_PMAC_BACKLIGHT
1269 if (par->FlatPanel && _machine == _MACH_Pmac) {
1270 set_backlight_enable(!blank);
1279 static struct fb_ops nvidia_fb_ops = {
1280 .owner = THIS_MODULE,
1281 .fb_check_var = nvidiafb_check_var,
1282 .fb_set_par = nvidiafb_set_par,
1283 .fb_setcolreg = nvidiafb_setcolreg,
1284 .fb_pan_display = nvidiafb_pan_display,
1285 .fb_blank = nvidiafb_blank,
1286 .fb_fillrect = nvidiafb_fillrect,
1287 .fb_copyarea = nvidiafb_copyarea,
1288 .fb_imageblit = nvidiafb_imageblit,
1289 .fb_cursor = nvidiafb_cursor,
1290 .fb_sync = nvidiafb_sync,
1293 static int __devinit nvidia_set_fbinfo(struct fb_info *info)
1295 struct fb_monspecs *specs = &info->monspecs;
1296 struct fb_videomode modedb;
1297 struct nvidia_par *par = info->par;
1301 info->flags = FBINFO_DEFAULT
1302 | FBINFO_HWACCEL_IMAGEBLIT
1303 | FBINFO_HWACCEL_FILLRECT
1304 | FBINFO_HWACCEL_COPYAREA
1305 | FBINFO_HWACCEL_YPAN;
1307 fb_videomode_to_modelist(info->monspecs.modedb,
1308 info->monspecs.modedb_len, &info->modelist);
1309 fb_var_to_videomode(&modedb, &nvidiafb_default_var);
1311 if (specs->modedb != NULL) {
1312 /* get preferred timing */
1313 if (specs->misc & FB_MISC_1ST_DETAIL) {
1316 for (i = 0; i < specs->modedb_len; i++) {
1317 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1318 modedb = specs->modedb[i];
1323 /* otherwise, get first mode in database */
1324 modedb = specs->modedb[0];
1327 fb_videomode_to_var(&nvidiafb_default_var, &modedb);
1328 nvidiafb_default_var.bits_per_pixel = 8;
1332 fb_find_mode(&nvidiafb_default_var, info, mode_option,
1333 specs->modedb, specs->modedb_len, &modedb, 8);
1335 info->var = nvidiafb_default_var;
1336 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1337 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1338 info->pseudo_palette = par->pseudo_palette;
1339 fb_alloc_cmap(&info->cmap, 256, 0);
1340 fb_destroy_modedb(info->monspecs.modedb);
1341 info->monspecs.modedb = NULL;
1343 /* maximize virtual vertical length */
1344 lpitch = info->var.xres_virtual *
1345 ((info->var.bits_per_pixel + 7) >> 3);
1346 info->var.yres_virtual = info->fix.smem_len / lpitch;
1348 info->pixmap.scan_align = 4;
1349 info->pixmap.buf_align = 4;
1350 info->pixmap.size = 8 * 1024;
1351 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1354 info->fbops->fb_cursor = soft_cursor;
1355 info->var.accel_flags = (!noaccel);
1357 switch (par->Architecture) {
1359 info->fix.accel = FB_ACCEL_NV4;
1362 info->fix.accel = FB_ACCEL_NV_10;
1365 info->fix.accel = FB_ACCEL_NV_20;
1368 info->fix.accel = FB_ACCEL_NV_30;
1371 info->fix.accel = FB_ACCEL_NV_40;
1377 return nvidiafb_check_var(&info->var, info);
1380 static u32 __devinit nvidia_get_arch(struct pci_dev *pd)
1384 switch (pd->device & 0x0ff0) {
1385 case 0x0100: /* GeForce 256 */
1386 case 0x0110: /* GeForce2 MX */
1387 case 0x0150: /* GeForce2 */
1388 case 0x0170: /* GeForce4 MX */
1389 case 0x0180: /* GeForce4 MX (8x AGP) */
1390 case 0x01A0: /* nForce */
1391 case 0x01F0: /* nForce2 */
1394 case 0x0200: /* GeForce3 */
1395 case 0x0250: /* GeForce4 Ti */
1396 case 0x0280: /* GeForce4 Ti (8x AGP) */
1399 case 0x0300: /* GeForceFX 5800 */
1400 case 0x0310: /* GeForceFX 5600 */
1401 case 0x0320: /* GeForceFX 5200 */
1402 case 0x0330: /* GeForceFX 5900 */
1403 case 0x0340: /* GeForceFX 5700 */
1419 case 0x0020: /* TNT, TNT2 */
1422 default: /* unknown architecture */
1429 static int __devinit nvidiafb_probe(struct pci_dev *pd,
1430 const struct pci_device_id *ent)
1432 struct nvidia_par *par;
1433 struct fb_info *info;
1440 info = framebuffer_alloc(sizeof(struct nvidia_par), &pd->dev);
1445 par = (struct nvidia_par *)info->par;
1448 info->pixmap.addr = kmalloc(8 * 1024, GFP_KERNEL);
1450 if (info->pixmap.addr == NULL)
1453 memset(info->pixmap.addr, 0, 8 * 1024);
1455 if (pci_enable_device(pd)) {
1456 printk(KERN_ERR PFX "cannot enable PCI device\n");
1457 goto err_out_enable;
1460 if (pci_request_regions(pd, "nvidiafb")) {
1461 printk(KERN_ERR PFX "cannot request PCI regions\n");
1462 goto err_out_request;
1465 par->Architecture = nvidia_get_arch(pd);
1467 par->Chipset = (pd->vendor << 16) | pd->device;
1468 printk(KERN_INFO PFX "nVidia device/chipset %X\n", par->Chipset);
1470 #ifdef CONFIG_PCI_NAMES
1471 printk(KERN_INFO PFX "%s\n", pd->pretty_name);
1474 if (par->Architecture == 0) {
1475 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1476 goto err_out_free_base0;
1479 sprintf(nvidiafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
1481 par->FlatPanel = flatpanel;
1484 printk(KERN_INFO PFX "flatpanel support enabled\n");
1486 par->CRTCnumber = forceCRTC;
1487 par->FpScale = (!noscale);
1488 par->paneltweak = paneltweak;
1490 /* enable IO and mem if not already done */
1491 pci_read_config_word(pd, PCI_COMMAND, &cmd);
1492 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
1493 pci_write_config_word(pd, PCI_COMMAND, cmd);
1495 nvidiafb_fix.mmio_start = pci_resource_start(pd, 0);
1496 nvidiafb_fix.smem_start = pci_resource_start(pd, 1);
1497 nvidiafb_fix.mmio_len = pci_resource_len(pd, 0);
1499 par->REGS = ioremap(nvidiafb_fix.mmio_start, nvidiafb_fix.mmio_len);
1502 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
1503 goto err_out_free_base0;
1506 NVCommonSetup(info);
1508 par->FbAddress = nvidiafb_fix.smem_start;
1509 par->FbMapSize = par->RamAmountKBytes * 1024;
1510 par->FbUsableSize = par->FbMapSize - (128 * 1024);
1511 par->ScratchBufferSize = (par->Architecture < NV_ARCH_10) ? 8 * 1024 :
1513 par->ScratchBufferStart = par->FbUsableSize - par->ScratchBufferSize;
1514 info->screen_base = ioremap(nvidiafb_fix.smem_start, par->FbMapSize);
1515 nvidiafb_fix.smem_len = par->FbUsableSize;
1517 if (!info->screen_base) {
1518 printk(KERN_ERR PFX "cannot ioremap FB base\n");
1519 goto err_out_free_base1;
1522 par->FbStart = info->screen_base;
1526 par->mtrr.vram = mtrr_add(nvidiafb_fix.smem_start,
1527 par->FbMapSize, MTRR_TYPE_WRCOMB, 1);
1528 if (par->mtrr.vram < 0) {
1529 printk(KERN_ERR PFX "unable to setup MTRR\n");
1531 par->mtrr.vram_valid = 1;
1532 /* let there be speed */
1533 printk(KERN_INFO PFX "MTRR set to ON\n");
1536 #endif /* CONFIG_MTRR */
1538 info->fbops = &nvidia_fb_ops;
1539 info->fix = nvidiafb_fix;
1541 if (nvidia_set_fbinfo(info) < 0) {
1542 printk(KERN_ERR PFX "error setting initial video mode\n");
1543 goto err_out_iounmap_fb;
1546 nvidia_save_vga(par, &par->SavedReg);
1548 if (register_framebuffer(info) < 0) {
1549 printk(KERN_ERR PFX "error registering nVidia framebuffer\n");
1550 goto err_out_iounmap_fb;
1553 pci_set_drvdata(pd, info);
1555 printk(KERN_INFO PFX
1556 "PCI nVidia %s framebuffer (%dMB @ 0x%lX)\n",
1558 par->FbMapSize / (1024 * 1024), info->fix.smem_start);
1559 #ifdef CONFIG_PMAC_BACKLIGHT
1560 if (par->FlatPanel && _machine == _MACH_Pmac)
1561 register_backlight_controller(&nvidia_backlight_controller,
1568 iounmap(info->screen_base);
1569 fb_destroy_modedb(info->monspecs.modedb);
1570 nvidia_delete_i2c_busses(par);
1574 pci_release_regions(pd);
1576 pci_disable_device(pd);
1578 kfree(info->pixmap.addr);
1580 framebuffer_release(info);
1585 static void __exit nvidiafb_remove(struct pci_dev *pd)
1587 struct fb_info *info = pci_get_drvdata(pd);
1588 struct nvidia_par *par = info->par;
1594 unregister_framebuffer(info);
1596 if (par->mtrr.vram_valid)
1597 mtrr_del(par->mtrr.vram, info->fix.smem_start,
1598 info->fix.smem_len);
1599 #endif /* CONFIG_MTRR */
1601 iounmap(info->screen_base);
1602 fb_destroy_modedb(info->monspecs.modedb);
1603 nvidia_delete_i2c_busses(par);
1605 pci_release_regions(pd);
1606 pci_disable_device(pd);
1607 kfree(info->pixmap.addr);
1608 framebuffer_release(info);
1609 pci_set_drvdata(pd, NULL);
1613 /* ------------------------------------------------------------------------- *
1617 * ------------------------------------------------------------------------- */
1620 static int __devinit nvidiafb_setup(char *options)
1625 if (!options || !*options)
1628 while ((this_opt = strsep(&options, ",")) != NULL) {
1629 if (!strncmp(this_opt, "forceCRTC", 9)) {
1635 forceCRTC = *p - '0';
1636 if (forceCRTC < 0 || forceCRTC > 1)
1638 } else if (!strncmp(this_opt, "flatpanel", 9)) {
1640 } else if (!strncmp(this_opt, "hwcur", 5)) {
1642 } else if (!strncmp(this_opt, "noaccel", 6)) {
1644 } else if (!strncmp(this_opt, "noscale", 7)) {
1646 } else if (!strncmp(this_opt, "paneltweak:", 11)) {
1647 paneltweak = simple_strtoul(this_opt+11, NULL, 0);
1649 } else if (!strncmp(this_opt, "nomtrr", 6)) {
1653 mode_option = this_opt;
1658 #endif /* !MODULE */
1660 static struct pci_driver nvidiafb_driver = {
1662 .id_table = nvidiafb_pci_tbl,
1663 .probe = nvidiafb_probe,
1664 .remove = __exit_p(nvidiafb_remove),
1667 /* ------------------------------------------------------------------------- *
1671 * ------------------------------------------------------------------------- */
1673 static int __devinit nvidiafb_init(void)
1676 char *option = NULL;
1678 if (fb_get_options("nvidiafb", &option))
1680 nvidiafb_setup(option);
1682 return pci_register_driver(&nvidiafb_driver);
1685 module_init(nvidiafb_init);
1688 static void __exit nvidiafb_exit(void)
1690 pci_unregister_driver(&nvidiafb_driver);
1693 module_exit(nvidiafb_exit);
1695 module_param(flatpanel, int, 0);
1696 MODULE_PARM_DESC(flatpanel,
1697 "Enables experimental flat panel support for some chipsets. "
1698 "(0 or 1=enabled) (default=0)");
1699 module_param(hwcur, int, 0);
1700 MODULE_PARM_DESC(hwcur,
1701 "Enables hardware cursor implementation. (0 or 1=enabled) "
1703 module_param(noaccel, int, 0);
1704 MODULE_PARM_DESC(noaccel,
1705 "Disables hardware acceleration. (0 or 1=disable) "
1707 module_param(noscale, int, 0);
1708 MODULE_PARM_DESC(noscale,
1709 "Disables screen scaleing. (0 or 1=disable) "
1710 "(default=0, do scaling)");
1711 module_param(paneltweak, int, 0);
1712 MODULE_PARM_DESC(paneltweak,
1713 "Tweak display settings for flatpanels. "
1714 "(default=0, no tweaks)");
1715 module_param(forceCRTC, int, 0);
1716 MODULE_PARM_DESC(forceCRTC,
1717 "Forces usage of a particular CRTC in case autodetection "
1718 "fails. (0 or 1) (default=autodetect)");
1720 module_param(nomtrr, bool, 0);
1721 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) "
1725 MODULE_AUTHOR("Antonino Daplas");
1726 MODULE_DESCRIPTION("Framebuffer driver for nVidia graphics chipset");
1727 MODULE_LICENSE("GPL");