4 * Linux framebuffer driver for Intel(R) 865G integrated graphics chips.
6 * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
9 * This driver consists of two parts. The first part (intelfbdrv.c) provides
10 * the basic fbdev interfaces, is derived in part from the radeonfb and
11 * vesafb drivers, and is covered by the GPL. The second part (intelfbhw.c)
12 * provides the code to program the hardware. Most of it is derived from
13 * the i810/i830 XFree86 driver. The HW-specific code is covered here
14 * under a dual license (GPL and MIT/XFree86 license).
20 /* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */
22 #include <linux/config.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/errno.h>
26 #include <linux/string.h>
28 #include <linux/tty.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
32 #include <linux/ioport.h>
33 #include <linux/init.h>
34 #include <linux/pci.h>
35 #include <linux/vmalloc.h>
36 #include <linux/pagemap.h>
41 #include "intelfbhw.h"
50 int min_vco_freq, max_vco_freq;
51 int p_transition_clock;
52 int p_inc_lo, p_inc_hi;
59 struct pll_min_max plls[PLLS_MAX] = {
60 { 108, 140, 18, 26, 6, 16, 3, 16, 4, 128, 0, 31, 930000, 1400000, 165000, 4, 22 }, //I8xx
61 { 75, 120, 10, 20, 5, 9, 4, 7, 5, 80, 1, 8, 930000, 2800000, 200000, 10, 5 } //I9xx
65 intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
71 switch (pdev->device) {
72 case PCI_DEVICE_ID_INTEL_830M:
73 dinfo->name = "Intel(R) 830M";
74 dinfo->chipset = INTEL_830M;
76 dinfo->pll_index = PLLS_I8xx;
78 case PCI_DEVICE_ID_INTEL_845G:
79 dinfo->name = "Intel(R) 845G";
80 dinfo->chipset = INTEL_845G;
82 dinfo->pll_index = PLLS_I8xx;
84 case PCI_DEVICE_ID_INTEL_85XGM:
87 dinfo->pll_index = PLLS_I8xx;
88 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
89 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
90 INTEL_85X_VARIANT_MASK) {
91 case INTEL_VAR_855GME:
92 dinfo->name = "Intel(R) 855GME";
93 dinfo->chipset = INTEL_855GME;
96 dinfo->name = "Intel(R) 855GM";
97 dinfo->chipset = INTEL_855GM;
99 case INTEL_VAR_852GME:
100 dinfo->name = "Intel(R) 852GME";
101 dinfo->chipset = INTEL_852GME;
103 case INTEL_VAR_852GM:
104 dinfo->name = "Intel(R) 852GM";
105 dinfo->chipset = INTEL_852GM;
108 dinfo->name = "Intel(R) 852GM/855GM";
109 dinfo->chipset = INTEL_85XGM;
113 case PCI_DEVICE_ID_INTEL_865G:
114 dinfo->name = "Intel(R) 865G";
115 dinfo->chipset = INTEL_865G;
117 dinfo->pll_index = PLLS_I8xx;
119 case PCI_DEVICE_ID_INTEL_915G:
120 dinfo->name = "Intel(R) 915G";
121 dinfo->chipset = INTEL_915G;
123 dinfo->pll_index = PLLS_I9xx;
125 case PCI_DEVICE_ID_INTEL_915GM:
126 dinfo->name = "Intel(R) 915GM";
127 dinfo->chipset = INTEL_915GM;
129 dinfo->pll_index = PLLS_I9xx;
131 case PCI_DEVICE_ID_INTEL_945G:
132 dinfo->name = "Intel(R) 945G";
133 dinfo->chipset = INTEL_945G;
135 dinfo->pll_index = PLLS_I9xx;
143 intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
146 struct pci_dev *bridge_dev;
149 if (!pdev || !aperture_size || !stolen_size)
152 /* Find the bridge device. It is always 0:0.0 */
153 if (!(bridge_dev = pci_find_slot(0, PCI_DEVFN(0, 0)))) {
154 ERR_MSG("cannot find bridge device\n");
158 /* Get the fb aperture size and "stolen" memory amount. */
160 pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
161 switch (pdev->device) {
162 case PCI_DEVICE_ID_INTEL_830M:
163 case PCI_DEVICE_ID_INTEL_845G:
164 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
165 *aperture_size = MB(64);
167 *aperture_size = MB(128);
168 switch (tmp & INTEL_830_GMCH_GMS_MASK) {
169 case INTEL_830_GMCH_GMS_STOLEN_512:
170 *stolen_size = KB(512) - KB(132);
172 case INTEL_830_GMCH_GMS_STOLEN_1024:
173 *stolen_size = MB(1) - KB(132);
175 case INTEL_830_GMCH_GMS_STOLEN_8192:
176 *stolen_size = MB(8) - KB(132);
178 case INTEL_830_GMCH_GMS_LOCAL:
179 ERR_MSG("only local memory found\n");
181 case INTEL_830_GMCH_GMS_DISABLED:
182 ERR_MSG("video memory is disabled\n");
185 ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
186 tmp & INTEL_830_GMCH_GMS_MASK);
191 *aperture_size = MB(128);
192 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
193 case INTEL_855_GMCH_GMS_STOLEN_1M:
194 *stolen_size = MB(1) - KB(132);
196 case INTEL_855_GMCH_GMS_STOLEN_4M:
197 *stolen_size = MB(4) - KB(132);
199 case INTEL_855_GMCH_GMS_STOLEN_8M:
200 *stolen_size = MB(8) - KB(132);
202 case INTEL_855_GMCH_GMS_STOLEN_16M:
203 *stolen_size = MB(16) - KB(132);
205 case INTEL_855_GMCH_GMS_STOLEN_32M:
206 *stolen_size = MB(32) - KB(132);
208 case INTEL_915G_GMCH_GMS_STOLEN_48M:
209 *stolen_size = MB(48) - KB(132);
211 case INTEL_915G_GMCH_GMS_STOLEN_64M:
212 *stolen_size = MB(64) - KB(132);
214 case INTEL_855_GMCH_GMS_DISABLED:
215 ERR_MSG("video memory is disabled\n");
218 ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
219 tmp & INTEL_855_GMCH_GMS_MASK);
226 intelfbhw_check_non_crt(struct intelfb_info *dinfo)
230 if (INREG(LVDS) & PORT_ENABLE)
232 if (INREG(DVOA) & PORT_ENABLE)
234 if (INREG(DVOB) & PORT_ENABLE)
236 if (INREG(DVOC) & PORT_ENABLE)
243 intelfbhw_dvo_to_string(int dvo)
247 else if (dvo & DVOB_PORT)
249 else if (dvo & DVOC_PORT)
251 else if (dvo & LVDS_PORT)
259 intelfbhw_validate_mode(struct intelfb_info *dinfo,
260 struct fb_var_screeninfo *var)
266 DBG_MSG("intelfbhw_validate_mode\n");
269 bytes_per_pixel = var->bits_per_pixel / 8;
270 if (bytes_per_pixel == 3)
273 /* Check if enough video memory. */
274 tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;
275 if (tmp > dinfo->fb.size) {
276 WRN_MSG("Not enough video ram for mode "
277 "(%d KByte vs %d KByte).\n",
278 BtoKB(tmp), BtoKB(dinfo->fb.size));
282 /* Check if x/y limits are OK. */
283 if (var->xres - 1 > HACTIVE_MASK) {
284 WRN_MSG("X resolution too large (%d vs %d).\n",
285 var->xres, HACTIVE_MASK + 1);
288 if (var->yres - 1 > VACTIVE_MASK) {
289 WRN_MSG("Y resolution too large (%d vs %d).\n",
290 var->yres, VACTIVE_MASK + 1);
294 /* Check for interlaced/doublescan modes. */
295 if (var->vmode & FB_VMODE_INTERLACED) {
296 WRN_MSG("Mode is interlaced.\n");
299 if (var->vmode & FB_VMODE_DOUBLE) {
300 WRN_MSG("Mode is double-scan.\n");
304 /* Check if clock is OK. */
305 tmp = 1000000000 / var->pixclock;
306 if (tmp < MIN_CLOCK) {
307 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n",
308 (tmp + 500) / 1000, MIN_CLOCK / 1000);
311 if (tmp > MAX_CLOCK) {
312 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n",
313 (tmp + 500) / 1000, MAX_CLOCK / 1000);
321 intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
323 struct intelfb_info *dinfo = GET_DINFO(info);
324 u32 offset, xoffset, yoffset;
327 DBG_MSG("intelfbhw_pan_display\n");
330 xoffset = ROUND_DOWN_TO(var->xoffset, 8);
331 yoffset = var->yoffset;
333 if ((xoffset + var->xres > var->xres_virtual) ||
334 (yoffset + var->yres > var->yres_virtual))
337 offset = (yoffset * dinfo->pitch) +
338 (xoffset * var->bits_per_pixel) / 8;
340 offset += dinfo->fb.offset << 12;
342 OUTREG(DSPABASE, offset);
347 /* Blank the screen. */
349 intelfbhw_do_blank(int blank, struct fb_info *info)
351 struct intelfb_info *dinfo = GET_DINFO(info);
355 DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank);
358 /* Turn plane A on or off */
359 tmp = INREG(DSPACNTR);
361 tmp &= ~DISPPLANE_PLANE_ENABLE;
363 tmp |= DISPPLANE_PLANE_ENABLE;
364 OUTREG(DSPACNTR, tmp);
366 tmp = INREG(DSPABASE);
367 OUTREG(DSPABASE, tmp);
369 /* Turn off/on the HW cursor */
371 DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
373 if (dinfo->cursor_on) {
375 intelfbhw_cursor_hide(dinfo);
377 intelfbhw_cursor_show(dinfo);
379 dinfo->cursor_on = 1;
381 dinfo->cursor_blanked = blank;
384 tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;
386 case FB_BLANK_UNBLANK:
387 case FB_BLANK_NORMAL:
390 case FB_BLANK_VSYNC_SUSPEND:
393 case FB_BLANK_HSYNC_SUSPEND:
396 case FB_BLANK_POWERDOWN:
407 intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
408 unsigned red, unsigned green, unsigned blue,
412 DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
413 regno, red, green, blue);
416 u32 palette_reg = (dinfo->pipe == PIPE_A) ?
417 PALETTE_A : PALETTE_B;
419 OUTREG(palette_reg + (regno << 2),
420 (red << PALETTE_8_RED_SHIFT) |
421 (green << PALETTE_8_GREEN_SHIFT) |
422 (blue << PALETTE_8_BLUE_SHIFT));
427 intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
433 DBG_MSG("intelfbhw_read_hw_state\n");
439 /* Read in as much of the HW state as possible. */
440 hw->vga0_divisor = INREG(VGA0_DIVISOR);
441 hw->vga1_divisor = INREG(VGA1_DIVISOR);
442 hw->vga_pd = INREG(VGAPD);
443 hw->dpll_a = INREG(DPLL_A);
444 hw->dpll_b = INREG(DPLL_B);
445 hw->fpa0 = INREG(FPA0);
446 hw->fpa1 = INREG(FPA1);
447 hw->fpb0 = INREG(FPB0);
448 hw->fpb1 = INREG(FPB1);
454 /* This seems to be a problem with the 852GM/855GM */
455 for (i = 0; i < PALETTE_8_ENTRIES; i++) {
456 hw->palette_a[i] = INREG(PALETTE_A + (i << 2));
457 hw->palette_b[i] = INREG(PALETTE_B + (i << 2));
464 hw->htotal_a = INREG(HTOTAL_A);
465 hw->hblank_a = INREG(HBLANK_A);
466 hw->hsync_a = INREG(HSYNC_A);
467 hw->vtotal_a = INREG(VTOTAL_A);
468 hw->vblank_a = INREG(VBLANK_A);
469 hw->vsync_a = INREG(VSYNC_A);
470 hw->src_size_a = INREG(SRC_SIZE_A);
471 hw->bclrpat_a = INREG(BCLRPAT_A);
472 hw->htotal_b = INREG(HTOTAL_B);
473 hw->hblank_b = INREG(HBLANK_B);
474 hw->hsync_b = INREG(HSYNC_B);
475 hw->vtotal_b = INREG(VTOTAL_B);
476 hw->vblank_b = INREG(VBLANK_B);
477 hw->vsync_b = INREG(VSYNC_B);
478 hw->src_size_b = INREG(SRC_SIZE_B);
479 hw->bclrpat_b = INREG(BCLRPAT_B);
484 hw->adpa = INREG(ADPA);
485 hw->dvoa = INREG(DVOA);
486 hw->dvob = INREG(DVOB);
487 hw->dvoc = INREG(DVOC);
488 hw->dvoa_srcdim = INREG(DVOA_SRCDIM);
489 hw->dvob_srcdim = INREG(DVOB_SRCDIM);
490 hw->dvoc_srcdim = INREG(DVOC_SRCDIM);
491 hw->lvds = INREG(LVDS);
496 hw->pipe_a_conf = INREG(PIPEACONF);
497 hw->pipe_b_conf = INREG(PIPEBCONF);
498 hw->disp_arb = INREG(DISPARB);
503 hw->cursor_a_control = INREG(CURSOR_A_CONTROL);
504 hw->cursor_b_control = INREG(CURSOR_B_CONTROL);
505 hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);
506 hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);
511 for (i = 0; i < 4; i++) {
512 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));
513 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));
519 hw->cursor_size = INREG(CURSOR_SIZE);
524 hw->disp_a_ctrl = INREG(DSPACNTR);
525 hw->disp_b_ctrl = INREG(DSPBCNTR);
526 hw->disp_a_base = INREG(DSPABASE);
527 hw->disp_b_base = INREG(DSPBBASE);
528 hw->disp_a_stride = INREG(DSPASTRIDE);
529 hw->disp_b_stride = INREG(DSPBSTRIDE);
534 hw->vgacntrl = INREG(VGACNTRL);
539 hw->add_id = INREG(ADD_ID);
544 for (i = 0; i < 7; i++) {
545 hw->swf0x[i] = INREG(SWF00 + (i << 2));
546 hw->swf1x[i] = INREG(SWF10 + (i << 2));
548 hw->swf3x[i] = INREG(SWF30 + (i << 2));
551 for (i = 0; i < 8; i++)
552 hw->fence[i] = INREG(FENCE + (i << 2));
554 hw->instpm = INREG(INSTPM);
555 hw->mem_mode = INREG(MEM_MODE);
556 hw->fw_blc_0 = INREG(FW_BLC_0);
557 hw->fw_blc_1 = INREG(FW_BLC_1);
563 static int calc_vclock3(int index, int m, int n, int p)
565 return PLL_REFCLK * m / n / p;
568 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2)
573 return ((PLL_REFCLK * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
574 ((p1)) * (p2 ? 10 : 5)));
577 return ((PLL_REFCLK * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
578 ((p1+2) * (1 << (p2 + 1)))));
583 intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
586 int i, m1, m2, n, p1, p2;
587 int index = dinfo->pll_index;
588 DBG_MSG("intelfbhw_print_hw_state\n");
592 /* Read in as much of the HW state as possible. */
593 printk("hw state dump start\n");
594 printk(" VGA0_DIVISOR: 0x%08x\n", hw->vga0_divisor);
595 printk(" VGA1_DIVISOR: 0x%08x\n", hw->vga1_divisor);
596 printk(" VGAPD: 0x%08x\n", hw->vga_pd);
597 n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
598 m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
599 m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
600 if (hw->vga_pd & VGAPD_0_P1_FORCE_DIV2)
603 p1 = (hw->vga_pd >> VGAPD_0_P1_SHIFT) & DPLL_P1_MASK;
604 p2 = (hw->vga_pd >> VGAPD_0_P2_SHIFT) & DPLL_P2_MASK;
605 printk(" VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
607 printk(" VGA0: clock is %d\n",
608 calc_vclock(index, m1, m2, n, p1, p2));
610 n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
611 m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
612 m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
613 if (hw->vga_pd & VGAPD_1_P1_FORCE_DIV2)
616 p1 = (hw->vga_pd >> VGAPD_1_P1_SHIFT) & DPLL_P1_MASK;
617 p2 = (hw->vga_pd >> VGAPD_1_P2_SHIFT) & DPLL_P2_MASK;
618 printk(" VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
620 printk(" VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2));
622 printk(" DPLL_A: 0x%08x\n", hw->dpll_a);
623 printk(" DPLL_B: 0x%08x\n", hw->dpll_b);
624 printk(" FPA0: 0x%08x\n", hw->fpa0);
625 printk(" FPA1: 0x%08x\n", hw->fpa1);
626 printk(" FPB0: 0x%08x\n", hw->fpb0);
627 printk(" FPB1: 0x%08x\n", hw->fpb1);
629 n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
630 m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
631 m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
632 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
635 p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
636 p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
637 printk(" PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
639 printk(" PLLA0: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2));
641 n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
642 m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
643 m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
644 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
647 p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
648 p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
649 printk(" PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
651 printk(" PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2));
654 printk(" PALETTE_A:\n");
655 for (i = 0; i < PALETTE_8_ENTRIES)
656 printk(" %3d: 0x%08x\n", i, hw->palette_a[i]);
657 printk(" PALETTE_B:\n");
658 for (i = 0; i < PALETTE_8_ENTRIES)
659 printk(" %3d: 0x%08x\n", i, hw->palette_b[i]);
662 printk(" HTOTAL_A: 0x%08x\n", hw->htotal_a);
663 printk(" HBLANK_A: 0x%08x\n", hw->hblank_a);
664 printk(" HSYNC_A: 0x%08x\n", hw->hsync_a);
665 printk(" VTOTAL_A: 0x%08x\n", hw->vtotal_a);
666 printk(" VBLANK_A: 0x%08x\n", hw->vblank_a);
667 printk(" VSYNC_A: 0x%08x\n", hw->vsync_a);
668 printk(" SRC_SIZE_A: 0x%08x\n", hw->src_size_a);
669 printk(" BCLRPAT_A: 0x%08x\n", hw->bclrpat_a);
670 printk(" HTOTAL_B: 0x%08x\n", hw->htotal_b);
671 printk(" HBLANK_B: 0x%08x\n", hw->hblank_b);
672 printk(" HSYNC_B: 0x%08x\n", hw->hsync_b);
673 printk(" VTOTAL_B: 0x%08x\n", hw->vtotal_b);
674 printk(" VBLANK_B: 0x%08x\n", hw->vblank_b);
675 printk(" VSYNC_B: 0x%08x\n", hw->vsync_b);
676 printk(" SRC_SIZE_B: 0x%08x\n", hw->src_size_b);
677 printk(" BCLRPAT_B: 0x%08x\n", hw->bclrpat_b);
679 printk(" ADPA: 0x%08x\n", hw->adpa);
680 printk(" DVOA: 0x%08x\n", hw->dvoa);
681 printk(" DVOB: 0x%08x\n", hw->dvob);
682 printk(" DVOC: 0x%08x\n", hw->dvoc);
683 printk(" DVOA_SRCDIM: 0x%08x\n", hw->dvoa_srcdim);
684 printk(" DVOB_SRCDIM: 0x%08x\n", hw->dvob_srcdim);
685 printk(" DVOC_SRCDIM: 0x%08x\n", hw->dvoc_srcdim);
686 printk(" LVDS: 0x%08x\n", hw->lvds);
688 printk(" PIPEACONF: 0x%08x\n", hw->pipe_a_conf);
689 printk(" PIPEBCONF: 0x%08x\n", hw->pipe_b_conf);
690 printk(" DISPARB: 0x%08x\n", hw->disp_arb);
692 printk(" CURSOR_A_CONTROL: 0x%08x\n", hw->cursor_a_control);
693 printk(" CURSOR_B_CONTROL: 0x%08x\n", hw->cursor_b_control);
694 printk(" CURSOR_A_BASEADDR: 0x%08x\n", hw->cursor_a_base);
695 printk(" CURSOR_B_BASEADDR: 0x%08x\n", hw->cursor_b_base);
697 printk(" CURSOR_A_PALETTE: ");
698 for (i = 0; i < 4; i++) {
699 printk("0x%08x", hw->cursor_a_palette[i]);
704 printk(" CURSOR_B_PALETTE: ");
705 for (i = 0; i < 4; i++) {
706 printk("0x%08x", hw->cursor_b_palette[i]);
712 printk(" CURSOR_SIZE: 0x%08x\n", hw->cursor_size);
714 printk(" DSPACNTR: 0x%08x\n", hw->disp_a_ctrl);
715 printk(" DSPBCNTR: 0x%08x\n", hw->disp_b_ctrl);
716 printk(" DSPABASE: 0x%08x\n", hw->disp_a_base);
717 printk(" DSPBBASE: 0x%08x\n", hw->disp_b_base);
718 printk(" DSPASTRIDE: 0x%08x\n", hw->disp_a_stride);
719 printk(" DSPBSTRIDE: 0x%08x\n", hw->disp_b_stride);
721 printk(" VGACNTRL: 0x%08x\n", hw->vgacntrl);
722 printk(" ADD_ID: 0x%08x\n", hw->add_id);
724 for (i = 0; i < 7; i++) {
725 printk(" SWF0%d 0x%08x\n", i,
728 for (i = 0; i < 7; i++) {
729 printk(" SWF1%d 0x%08x\n", i,
732 for (i = 0; i < 3; i++) {
733 printk(" SWF3%d 0x%08x\n", i,
736 for (i = 0; i < 8; i++)
737 printk(" FENCE%d 0x%08x\n", i,
740 printk(" INSTPM 0x%08x\n", hw->instpm);
741 printk(" MEM_MODE 0x%08x\n", hw->mem_mode);
742 printk(" FW_BLC_0 0x%08x\n", hw->fw_blc_0);
743 printk(" FW_BLC_1 0x%08x\n", hw->fw_blc_1);
745 printk("hw state dump end\n");
751 /* Split the M parameter into M1 and M2. */
753 splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2)
757 /* no point optimising too much - brute force m */
758 for (m1 = plls[index].min_m1; m1 < plls[index].max_m1+1; m1++)
760 for (m2 = plls[index].min_m2; m2 < plls[index].max_m2+1; m2++)
762 testm = ( 5 * ( m1 + 2 )) + (m2 + 2);
765 *retm1 = (unsigned int)m1;
766 *retm2 = (unsigned int)m2;
774 /* Split the P parameter into P1 and P2. */
776 splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2)
780 if (index == PLLS_I9xx)
785 *retp1 = (unsigned int)p1;
786 *retp2 = (unsigned int)p2;
790 if (index == PLLS_I8xx)
796 p1 = (p / (1 << (p2 + 1))) - 2;
797 if (p % 4 == 0 && p1 < plls[index].min_p1) {
799 p1 = (p / (1 << (p2 + 1))) - 2;
801 if (p1 < plls[index].min_p1 || p1 > plls[index].max_p1 || (p1 + 2) * (1 << (p2 + 1)) != p) {
804 *retp1 = (unsigned int)p1;
805 *retp2 = (unsigned int)p2;
813 calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
814 u32 *retp2, u32 *retclock)
816 u32 m1, m2, n, p1, p2, n1;
817 u32 f_vco, p, p_best = 0, m, f_out;
818 u32 err_max, err_target, err_best = 10000000;
819 u32 n_best = 0, m_best = 0, f_best, f_err;
820 u32 p_min, p_max, p_inc, div_min, div_max;
822 /* Accept 0.5% difference, but aim for 0.1% */
823 err_max = 5 * clock / 1000;
824 err_target = clock / 1000;
826 DBG_MSG("Clock is %d\n", clock);
828 div_max = plls[index].max_vco_freq / clock;
829 div_min = ROUND_UP_TO(plls[index].min_vco_freq, clock) / clock;
831 if (clock <= plls[index].p_transition_clock)
832 p_inc = plls[index].p_inc_lo;
834 p_inc = plls[index].p_inc_hi;
835 p_min = ROUND_UP_TO(div_min, p_inc);
836 p_max = ROUND_DOWN_TO(div_max, p_inc);
837 if (p_min < plls[index].min_p)
838 p_min = plls[index].min_p;
839 if (p_max > plls[index].max_p)
840 p_max = plls[index].max_p;
842 DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
846 if (splitp(index, p, &p1, &p2)) {
847 WRN_MSG("cannot split p = %d\n", p);
851 n = plls[index].min_n;
855 m = ROUND_UP_TO(f_vco * n, PLL_REFCLK) / PLL_REFCLK;
856 if (m < plls[index].min_m)
857 m = plls[index].min_m;
858 if (m > plls[index].max_m)
859 m = plls[index].max_m;
860 f_out = calc_vclock3(index, m, n, p);
861 if (splitm(index, m, &m1, &m2)) {
862 WRN_MSG("cannot split m = %d\n", m);
867 f_err = clock - f_out;
869 f_err = f_out - clock;
871 if (f_err < err_best) {
879 } while ((n <= plls[index].max_n) && (f_out >= clock));
881 } while ((p <= p_max));
884 WRN_MSG("cannot find parameters for clock %d\n", clock);
890 splitm(index, m, &m1, &m2);
891 splitp(index, p, &p1, &p2);
894 DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
895 "f: %d (%d), VCO: %d\n",
896 m, m1, m2, n, n1, p, p1, p2,
897 calc_vclock3(index, m, n, p),
898 calc_vclock(index, m1, m2, n1, p1, p2),
899 calc_vclock3(index, m, n, p) * p);
905 *retclock = calc_vclock(index, m1, m2, n1, p1, p2);
910 static __inline__ int
911 check_overflow(u32 value, u32 limit, const char *description)
914 WRN_MSG("%s value %d exceeds limit %d\n",
915 description, value, limit);
921 /* It is assumed that hw is filled in with the initial state information. */
923 intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
924 struct fb_var_screeninfo *var)
927 u32 *dpll, *fp0, *fp1;
928 u32 m1, m2, n, p1, p2, clock_target, clock;
929 u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive;
930 u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive;
931 u32 vsync_pol, hsync_pol;
932 u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf;
934 DBG_MSG("intelfbhw_mode_to_hw\n");
937 hw->vgacntrl |= VGA_DISABLE;
939 /* Check whether pipe A or pipe B is enabled. */
940 if (hw->pipe_a_conf & PIPECONF_ENABLE)
942 else if (hw->pipe_b_conf & PIPECONF_ENABLE)
945 /* Set which pipe's registers will be set. */
946 if (pipe == PIPE_B) {
956 ss = &hw->src_size_b;
957 pipe_conf = &hw->pipe_b_conf;
968 ss = &hw->src_size_a;
969 pipe_conf = &hw->pipe_a_conf;
972 /* Use ADPA register for sync control. */
973 hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
976 hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ?
977 ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
978 vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ?
979 ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
980 hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
981 (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT));
982 hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
983 (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT);
985 /* Connect correct pipe to the analog port DAC */
986 hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
987 hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
989 /* Set DPMS state to D0 (on) */
990 hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
991 hw->adpa |= ADPA_DPMS_D0;
993 hw->adpa |= ADPA_DAC_ENABLE;
995 *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
996 *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
997 *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
999 /* Desired clock in kHz */
1000 clock_target = 1000000000 / var->pixclock;
1002 if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2, &n, &p1, &p2, &clock)) {
1003 WRN_MSG("calc_pll_params failed\n");
1007 /* Check for overflow. */
1008 if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter"))
1010 if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter"))
1012 if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))
1014 if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
1016 if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter"))
1019 *dpll &= ~DPLL_P1_FORCE_DIV2;
1020 *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
1021 (DPLL_P1_MASK << DPLL_P1_SHIFT));
1022 *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
1023 *fp0 = (n << FP_N_DIVISOR_SHIFT) |
1024 (m1 << FP_M1_DIVISOR_SHIFT) |
1025 (m2 << FP_M2_DIVISOR_SHIFT);
1028 hw->dvob &= ~PORT_ENABLE;
1029 hw->dvoc &= ~PORT_ENABLE;
1031 /* Use display plane A. */
1032 hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE;
1033 hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE;
1034 hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK;
1035 switch (intelfb_var_to_depth(var)) {
1037 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE;
1040 hw->disp_a_ctrl |= DISPPLANE_15_16BPP;
1043 hw->disp_a_ctrl |= DISPPLANE_16BPP;
1046 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA;
1049 hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT);
1050 hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT);
1052 /* Set CRTC registers. */
1053 hactive = var->xres;
1054 hsync_start = hactive + var->right_margin;
1055 hsync_end = hsync_start + var->hsync_len;
1056 htotal = hsync_end + var->left_margin;
1057 hblank_start = hactive;
1058 hblank_end = htotal;
1060 DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1061 hactive, hsync_start, hsync_end, htotal, hblank_start,
1064 vactive = var->yres;
1065 vsync_start = vactive + var->lower_margin;
1066 vsync_end = vsync_start + var->vsync_len;
1067 vtotal = vsync_end + var->upper_margin;
1068 vblank_start = vactive;
1069 vblank_end = vtotal;
1070 vblank_end = vsync_end + 1;
1072 DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1073 vactive, vsync_start, vsync_end, vtotal, vblank_start,
1076 /* Adjust for register values, and check for overflow. */
1078 if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive"))
1081 if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start"))
1084 if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end"))
1087 if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal"))
1090 if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start"))
1093 if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end"))
1097 if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive"))
1100 if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start"))
1103 if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end"))
1106 if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal"))
1109 if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start"))
1112 if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end"))
1115 *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT);
1116 *hb = (hblank_start << HBLANKSTART_SHIFT) |
1117 (hblank_end << HSYNCEND_SHIFT);
1118 *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
1120 *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT);
1121 *vb = (vblank_start << VBLANKSTART_SHIFT) |
1122 (vblank_end << VSYNCEND_SHIFT);
1123 *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT);
1124 *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) |
1125 (vactive << SRC_SIZE_VERT_SHIFT);
1127 hw->disp_a_stride = var->xres_virtual * var->bits_per_pixel / 8;
1128 DBG_MSG("pitch is %d\n", hw->disp_a_stride);
1130 hw->disp_a_base = hw->disp_a_stride * var->yoffset +
1131 var->xoffset * var->bits_per_pixel / 8;
1133 hw->disp_a_base += dinfo->fb.offset << 12;
1135 /* Check stride alignment. */
1136 if (hw->disp_a_stride % STRIDE_ALIGNMENT != 0) {
1137 WRN_MSG("display stride %d has bad alignment %d\n",
1138 hw->disp_a_stride, STRIDE_ALIGNMENT);
1142 /* Set the palette to 8-bit mode. */
1143 *pipe_conf &= ~PIPECONF_GAMMA;
1147 /* Program a (non-VGA) video mode. */
1149 intelfbhw_program_mode(struct intelfb_info *dinfo,
1150 const struct intelfb_hwstate *hw, int blank)
1154 const u32 *dpll, *fp0, *fp1, *pipe_conf;
1155 const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
1156 u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg;
1157 u32 hsync_reg, htotal_reg, hblank_reg;
1158 u32 vsync_reg, vtotal_reg, vblank_reg;
1161 /* Assume single pipe, display plane A, analog CRT. */
1164 DBG_MSG("intelfbhw_program_mode\n");
1168 tmp = INREG(VGACNTRL);
1170 OUTREG(VGACNTRL, tmp);
1172 /* Check whether pipe A or pipe B is enabled. */
1173 if (hw->pipe_a_conf & PIPECONF_ENABLE)
1175 else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1180 if (pipe == PIPE_B) {
1184 pipe_conf = &hw->pipe_b_conf;
1191 ss = &hw->src_size_b;
1195 pipe_conf_reg = PIPEBCONF;
1196 hsync_reg = HSYNC_B;
1197 htotal_reg = HTOTAL_B;
1198 hblank_reg = HBLANK_B;
1199 vsync_reg = VSYNC_B;
1200 vtotal_reg = VTOTAL_B;
1201 vblank_reg = VBLANK_B;
1202 src_size_reg = SRC_SIZE_B;
1207 pipe_conf = &hw->pipe_a_conf;
1214 ss = &hw->src_size_a;
1218 pipe_conf_reg = PIPEACONF;
1219 hsync_reg = HSYNC_A;
1220 htotal_reg = HTOTAL_A;
1221 hblank_reg = HBLANK_A;
1222 vsync_reg = VSYNC_A;
1223 vtotal_reg = VTOTAL_A;
1224 vblank_reg = VBLANK_A;
1225 src_size_reg = SRC_SIZE_A;
1228 /* Disable planes A and B. */
1229 tmp = INREG(DSPACNTR);
1230 tmp &= ~DISPPLANE_PLANE_ENABLE;
1231 OUTREG(DSPACNTR, tmp);
1232 tmp = INREG(DSPBCNTR);
1233 tmp &= ~DISPPLANE_PLANE_ENABLE;
1234 OUTREG(DSPBCNTR, tmp);
1236 /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
1241 tmp &= ~ADPA_DPMS_CONTROL_MASK;
1242 tmp |= ADPA_DPMS_D3;
1246 tmp = INREG(pipe_conf_reg);
1247 tmp &= ~PIPECONF_ENABLE;
1248 OUTREG(pipe_conf_reg, tmp);
1251 tmp = INREG(dpll_reg);
1252 dpll_reg &= ~DPLL_VCO_ENABLE;
1253 OUTREG(dpll_reg, tmp);
1255 /* Set PLL parameters */
1256 OUTREG(dpll_reg, *dpll & ~DPLL_VCO_ENABLE);
1257 OUTREG(fp0_reg, *fp0);
1258 OUTREG(fp1_reg, *fp1);
1260 /* Set pipe parameters */
1261 OUTREG(hsync_reg, *hs);
1262 OUTREG(hblank_reg, *hb);
1263 OUTREG(htotal_reg, *ht);
1264 OUTREG(vsync_reg, *vs);
1265 OUTREG(vblank_reg, *vb);
1266 OUTREG(vtotal_reg, *vt);
1267 OUTREG(src_size_reg, *ss);
1270 OUTREG(DVOB, hw->dvob);
1271 OUTREG(DVOC, hw->dvoc);
1274 OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
1277 tmp = INREG(dpll_reg);
1278 tmp |= DPLL_VCO_ENABLE;
1279 OUTREG(dpll_reg, tmp);
1282 OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
1286 tmp &= ~ADPA_DPMS_CONTROL_MASK;
1287 tmp |= ADPA_DPMS_D0;
1290 /* setup display plane */
1291 if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
1293 * i830M errata: the display plane must be enabled
1294 * to allow writes to the other bits in the plane
1297 tmp = INREG(DSPACNTR);
1298 if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {
1299 tmp |= DISPPLANE_PLANE_ENABLE;
1300 OUTREG(DSPACNTR, tmp);
1302 hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
1307 OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
1308 OUTREG(DSPASTRIDE, hw->disp_a_stride);
1309 OUTREG(DSPABASE, hw->disp_a_base);
1313 tmp = INREG(DSPACNTR);
1314 tmp |= DISPPLANE_PLANE_ENABLE;
1315 OUTREG(DSPACNTR, tmp);
1316 OUTREG(DSPABASE, hw->disp_a_base);
1322 /* forward declarations */
1323 static void refresh_ring(struct intelfb_info *dinfo);
1324 static void reset_state(struct intelfb_info *dinfo);
1325 static void do_flush(struct intelfb_info *dinfo);
1328 wait_ring(struct intelfb_info *dinfo, int n)
1332 u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1335 DBG_MSG("wait_ring: %d\n", n);
1338 end = jiffies + (HZ * 3);
1339 while (dinfo->ring_space < n) {
1340 dinfo->ring_head = (u8 __iomem *)(INREG(PRI_RING_HEAD) &
1342 if (dinfo->ring_tail + RING_MIN_FREE <
1343 (u32 __iomem) dinfo->ring_head)
1344 dinfo->ring_space = (u32 __iomem) dinfo->ring_head
1345 - (dinfo->ring_tail + RING_MIN_FREE);
1347 dinfo->ring_space = (dinfo->ring.size +
1348 (u32 __iomem) dinfo->ring_head)
1349 - (dinfo->ring_tail + RING_MIN_FREE);
1350 if ((u32 __iomem) dinfo->ring_head != last_head) {
1351 end = jiffies + (HZ * 3);
1352 last_head = (u32 __iomem) dinfo->ring_head;
1355 if (time_before(end, jiffies)) {
1359 refresh_ring(dinfo);
1361 end = jiffies + (HZ * 3);
1364 WRN_MSG("ring buffer : space: %d wanted %d\n",
1365 dinfo->ring_space, n);
1366 WRN_MSG("lockup - turning off hardware "
1368 dinfo->ring_lockup = 1;
1378 do_flush(struct intelfb_info *dinfo) {
1380 OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
1386 intelfbhw_do_sync(struct intelfb_info *dinfo)
1389 DBG_MSG("intelfbhw_do_sync\n");
1396 * Send a flush, then wait until the ring is empty. This is what
1397 * the XFree86 driver does, and actually it doesn't seem a lot worse
1398 * than the recommended method (both have problems).
1401 wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
1402 dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
1406 refresh_ring(struct intelfb_info *dinfo)
1409 DBG_MSG("refresh_ring\n");
1412 dinfo->ring_head = (u8 __iomem *) (INREG(PRI_RING_HEAD) &
1414 dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1415 if (dinfo->ring_tail + RING_MIN_FREE < (u32 __iomem)dinfo->ring_head)
1416 dinfo->ring_space = (u32 __iomem) dinfo->ring_head
1417 - (dinfo->ring_tail + RING_MIN_FREE);
1419 dinfo->ring_space = (dinfo->ring.size +
1420 (u32 __iomem) dinfo->ring_head)
1421 - (dinfo->ring_tail + RING_MIN_FREE);
1425 reset_state(struct intelfb_info *dinfo)
1431 DBG_MSG("reset_state\n");
1434 for (i = 0; i < FENCE_NUM; i++)
1435 OUTREG(FENCE + (i << 2), 0);
1437 /* Flush the ring buffer if it's enabled. */
1438 tmp = INREG(PRI_RING_LENGTH);
1439 if (tmp & RING_ENABLE) {
1441 DBG_MSG("reset_state: ring was enabled\n");
1443 refresh_ring(dinfo);
1444 intelfbhw_do_sync(dinfo);
1448 OUTREG(PRI_RING_LENGTH, 0);
1449 OUTREG(PRI_RING_HEAD, 0);
1450 OUTREG(PRI_RING_TAIL, 0);
1451 OUTREG(PRI_RING_START, 0);
1454 /* Stop the 2D engine, and turn off the ring buffer. */
1456 intelfbhw_2d_stop(struct intelfb_info *dinfo)
1459 DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n", dinfo->accel,
1460 dinfo->ring_active);
1466 dinfo->ring_active = 0;
1471 * Enable the ring buffer, and initialise the 2D engine.
1472 * It is assumed that the graphics engine has been stopped by previously
1473 * calling intelfb_2d_stop().
1476 intelfbhw_2d_start(struct intelfb_info *dinfo)
1479 DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n",
1480 dinfo->accel, dinfo->ring_active);
1486 /* Initialise the primary ring buffer. */
1487 OUTREG(PRI_RING_LENGTH, 0);
1488 OUTREG(PRI_RING_TAIL, 0);
1489 OUTREG(PRI_RING_HEAD, 0);
1491 OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
1492 OUTREG(PRI_RING_LENGTH,
1493 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1494 RING_NO_REPORT | RING_ENABLE);
1495 refresh_ring(dinfo);
1496 dinfo->ring_active = 1;
1499 /* 2D fillrect (solid fill or invert) */
1501 intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w, u32 h,
1502 u32 color, u32 pitch, u32 bpp, u32 rop)
1504 u32 br00, br09, br13, br14, br16;
1507 DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, "
1508 "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop);
1511 br00 = COLOR_BLT_CMD;
1512 br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
1513 br13 = (rop << ROP_SHIFT) | pitch;
1514 br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT);
1519 br13 |= COLOR_DEPTH_8;
1522 br13 |= COLOR_DEPTH_16;
1525 br13 |= COLOR_DEPTH_32;
1526 br00 |= WRITE_ALPHA | WRITE_RGB;
1540 DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
1541 dinfo->ring_tail, dinfo->ring_space);
1546 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1547 u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp)
1549 u32 br00, br09, br11, br12, br13, br22, br23, br26;
1552 DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n",
1553 curx, cury, dstx, dsty, w, h, pitch, bpp);
1556 br00 = XY_SRC_COPY_BLT_CMD;
1557 br09 = dinfo->fb_start;
1558 br11 = (pitch << PITCH_SHIFT);
1559 br12 = dinfo->fb_start;
1560 br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1561 br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT);
1562 br23 = ((dstx + w) << WIDTH_SHIFT) |
1563 ((dsty + h) << HEIGHT_SHIFT);
1564 br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT);
1568 br13 |= COLOR_DEPTH_8;
1571 br13 |= COLOR_DEPTH_16;
1574 br13 |= COLOR_DEPTH_32;
1575 br00 |= WRITE_ALPHA | WRITE_RGB;
1592 intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
1593 u32 h, const u8* cdat, u32 x, u32 y, u32 pitch, u32 bpp)
1595 int nbytes, ndwords, pad, tmp;
1596 u32 br00, br09, br13, br18, br19, br22, br23;
1597 int dat, ix, iy, iw;
1601 DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h);
1604 /* size in bytes of a padded scanline */
1605 nbytes = ROUND_UP_TO(w, 16) / 8;
1607 /* Total bytes of padded scanline data to write out. */
1608 nbytes = nbytes * h;
1611 * Check if the glyph data exceeds the immediate mode limit.
1612 * It would take a large font (1K pixels) to hit this limit.
1614 if (nbytes > MAX_MONO_IMM_SIZE)
1617 /* Src data is packaged a dword (32-bit) at a time. */
1618 ndwords = ROUND_UP_TO(nbytes, 4) / 4;
1621 * Ring has to be padded to a quad word. But because the command starts
1622 with 7 bytes, pad only if there is an even number of ndwords
1624 pad = !(ndwords % 2);
1626 tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;
1627 br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;
1628 br09 = dinfo->fb_start;
1629 br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1632 br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT);
1633 br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT);
1637 br13 |= COLOR_DEPTH_8;
1640 br13 |= COLOR_DEPTH_16;
1643 br13 |= COLOR_DEPTH_32;
1644 br00 |= WRITE_ALPHA | WRITE_RGB;
1648 START_RING(8 + ndwords);
1657 iw = ROUND_UP_TO(w, 8) / 8;
1660 for (j = 0; j < 2; ++j) {
1661 for (i = 0; i < 2; ++i) {
1662 if (ix != iw || i == 0)
1663 dat |= cdat[iy*iw + ix++] << (i+j*2)*8;
1665 if (ix == iw && iy != (h-1)) {
1679 /* HW cursor functions. */
1681 intelfbhw_cursor_init(struct intelfb_info *dinfo)
1686 DBG_MSG("intelfbhw_cursor_init\n");
1689 if (dinfo->mobile) {
1690 if (!dinfo->cursor.physical)
1692 tmp = INREG(CURSOR_A_CONTROL);
1693 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |
1694 CURSOR_MEM_TYPE_LOCAL |
1695 (1 << CURSOR_PIPE_SELECT_SHIFT));
1696 tmp |= CURSOR_MODE_DISABLE;
1697 OUTREG(CURSOR_A_CONTROL, tmp);
1698 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1700 tmp = INREG(CURSOR_CONTROL);
1701 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
1702 CURSOR_ENABLE | CURSOR_STRIDE_MASK);
1703 tmp = CURSOR_FORMAT_3C;
1704 OUTREG(CURSOR_CONTROL, tmp);
1705 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
1706 tmp = (64 << CURSOR_SIZE_H_SHIFT) |
1707 (64 << CURSOR_SIZE_V_SHIFT);
1708 OUTREG(CURSOR_SIZE, tmp);
1713 intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1718 DBG_MSG("intelfbhw_cursor_hide\n");
1721 dinfo->cursor_on = 0;
1722 if (dinfo->mobile) {
1723 if (!dinfo->cursor.physical)
1725 tmp = INREG(CURSOR_A_CONTROL);
1726 tmp &= ~CURSOR_MODE_MASK;
1727 tmp |= CURSOR_MODE_DISABLE;
1728 OUTREG(CURSOR_A_CONTROL, tmp);
1730 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1732 tmp = INREG(CURSOR_CONTROL);
1733 tmp &= ~CURSOR_ENABLE;
1734 OUTREG(CURSOR_CONTROL, tmp);
1739 intelfbhw_cursor_show(struct intelfb_info *dinfo)
1744 DBG_MSG("intelfbhw_cursor_show\n");
1747 dinfo->cursor_on = 1;
1749 if (dinfo->cursor_blanked)
1752 if (dinfo->mobile) {
1753 if (!dinfo->cursor.physical)
1755 tmp = INREG(CURSOR_A_CONTROL);
1756 tmp &= ~CURSOR_MODE_MASK;
1757 tmp |= CURSOR_MODE_64_4C_AX;
1758 OUTREG(CURSOR_A_CONTROL, tmp);
1760 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1762 tmp = INREG(CURSOR_CONTROL);
1763 tmp |= CURSOR_ENABLE;
1764 OUTREG(CURSOR_CONTROL, tmp);
1769 intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1774 DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y);
1778 * Sets the position. The coordinates are assumed to already
1779 * have any offset adjusted. Assume that the cursor is never
1780 * completely off-screen, and that x, y are always >= 0.
1783 tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
1784 ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1785 OUTREG(CURSOR_A_POSITION, tmp);
1789 intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1792 DBG_MSG("intelfbhw_cursor_setcolor\n");
1795 OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);
1796 OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);
1797 OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);
1798 OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);
1802 intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
1805 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1806 int i, j, w = width / 8;
1807 int mod = width % 8, t_mask, d_mask;
1810 DBG_MSG("intelfbhw_cursor_load\n");
1813 if (!dinfo->cursor.virtual)
1816 t_mask = 0xff >> mod;
1817 d_mask = ~(0xff >> mod);
1818 for (i = height; i--; ) {
1819 for (j = 0; j < w; j++) {
1820 writeb(0x00, addr + j);
1821 writeb(*(data++), addr + j+8);
1824 writeb(t_mask, addr + j);
1825 writeb(*(data++) & d_mask, addr + j+8);
1832 intelfbhw_cursor_reset(struct intelfb_info *dinfo) {
1833 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1837 DBG_MSG("intelfbhw_cursor_reset\n");
1840 if (!dinfo->cursor.virtual)
1843 for (i = 64; i--; ) {
1844 for (j = 0; j < 8; j++) {
1845 writeb(0xff, addr + j+0);
1846 writeb(0x00, addr + j+8);