4 * Linux framebuffer driver for Intel(R) 865G integrated graphics chips.
6 * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
9 * This driver consists of two parts. The first part (intelfbdrv.c) provides
10 * the basic fbdev interfaces, is derived in part from the radeonfb and
11 * vesafb drivers, and is covered by the GPL. The second part (intelfbhw.c)
12 * provides the code to program the hardware. Most of it is derived from
13 * the i810/i830 XFree86 driver. The HW-specific code is covered here
14 * under a dual license (GPL and MIT/XFree86 license).
20 /* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */
22 #include <linux/config.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/errno.h>
26 #include <linux/string.h>
28 #include <linux/tty.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
32 #include <linux/ioport.h>
33 #include <linux/init.h>
34 #include <linux/pci.h>
35 #include <linux/vmalloc.h>
36 #include <linux/pagemap.h>
41 #include "intelfbhw.h"
50 int min_vco_freq, max_vco_freq;
51 int p_transition_clock;
58 struct pll_min_max plls[PLLS_MAX] = {
59 { 108, 140, 18, 26, 6, 16, 3, 16, 4, 128, 0, 31, 930000, 1400000, 165000 }, //I8xx
60 { 75, 120, 10, 20, 5, 9, 4, 7, 5, 80, 1, 8, 930000, 2800000, 200000 } //I9xx
64 intelfbhw_get_chipset(struct pci_dev *pdev, const char **name, int *chipset,
69 if (!pdev || !name || !chipset || !mobile)
72 switch (pdev->device) {
73 case PCI_DEVICE_ID_INTEL_830M:
74 *name = "Intel(R) 830M";
75 *chipset = INTEL_830M;
78 case PCI_DEVICE_ID_INTEL_845G:
79 *name = "Intel(R) 845G";
80 *chipset = INTEL_845G;
83 case PCI_DEVICE_ID_INTEL_85XGM:
86 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
87 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
88 INTEL_85X_VARIANT_MASK) {
89 case INTEL_VAR_855GME:
90 *name = "Intel(R) 855GME";
91 *chipset = INTEL_855GME;
94 *name = "Intel(R) 855GM";
95 *chipset = INTEL_855GM;
97 case INTEL_VAR_852GME:
98 *name = "Intel(R) 852GME";
99 *chipset = INTEL_852GME;
101 case INTEL_VAR_852GM:
102 *name = "Intel(R) 852GM";
103 *chipset = INTEL_852GM;
106 *name = "Intel(R) 852GM/855GM";
107 *chipset = INTEL_85XGM;
111 case PCI_DEVICE_ID_INTEL_865G:
112 *name = "Intel(R) 865G";
113 *chipset = INTEL_865G;
116 case PCI_DEVICE_ID_INTEL_915G:
117 *name = "Intel(R) 915G";
118 *chipset = INTEL_915G;
121 case PCI_DEVICE_ID_INTEL_915GM:
122 *name = "Intel(R) 915GM";
123 *chipset = INTEL_915GM;
132 intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
135 struct pci_dev *bridge_dev;
138 if (!pdev || !aperture_size || !stolen_size)
141 /* Find the bridge device. It is always 0:0.0 */
142 if (!(bridge_dev = pci_find_slot(0, PCI_DEVFN(0, 0)))) {
143 ERR_MSG("cannot find bridge device\n");
147 /* Get the fb aperture size and "stolen" memory amount. */
149 pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
150 switch (pdev->device) {
151 case PCI_DEVICE_ID_INTEL_830M:
152 case PCI_DEVICE_ID_INTEL_845G:
153 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
154 *aperture_size = MB(64);
156 *aperture_size = MB(128);
157 switch (tmp & INTEL_830_GMCH_GMS_MASK) {
158 case INTEL_830_GMCH_GMS_STOLEN_512:
159 *stolen_size = KB(512) - KB(132);
161 case INTEL_830_GMCH_GMS_STOLEN_1024:
162 *stolen_size = MB(1) - KB(132);
164 case INTEL_830_GMCH_GMS_STOLEN_8192:
165 *stolen_size = MB(8) - KB(132);
167 case INTEL_830_GMCH_GMS_LOCAL:
168 ERR_MSG("only local memory found\n");
170 case INTEL_830_GMCH_GMS_DISABLED:
171 ERR_MSG("video memory is disabled\n");
174 ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
175 tmp & INTEL_830_GMCH_GMS_MASK);
180 *aperture_size = MB(128);
181 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
182 case INTEL_855_GMCH_GMS_STOLEN_1M:
183 *stolen_size = MB(1) - KB(132);
185 case INTEL_855_GMCH_GMS_STOLEN_4M:
186 *stolen_size = MB(4) - KB(132);
188 case INTEL_855_GMCH_GMS_STOLEN_8M:
189 *stolen_size = MB(8) - KB(132);
191 case INTEL_855_GMCH_GMS_STOLEN_16M:
192 *stolen_size = MB(16) - KB(132);
194 case INTEL_855_GMCH_GMS_STOLEN_32M:
195 *stolen_size = MB(32) - KB(132);
197 case INTEL_915G_GMCH_GMS_STOLEN_48M:
198 *stolen_size = MB(48) - KB(132);
200 case INTEL_915G_GMCH_GMS_STOLEN_64M:
201 *stolen_size = MB(64) - KB(132);
203 case INTEL_855_GMCH_GMS_DISABLED:
204 ERR_MSG("video memory is disabled\n");
207 ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
208 tmp & INTEL_855_GMCH_GMS_MASK);
215 intelfbhw_check_non_crt(struct intelfb_info *dinfo)
219 if (INREG(LVDS) & PORT_ENABLE)
221 if (INREG(DVOA) & PORT_ENABLE)
223 if (INREG(DVOB) & PORT_ENABLE)
225 if (INREG(DVOC) & PORT_ENABLE)
232 intelfbhw_dvo_to_string(int dvo)
236 else if (dvo & DVOB_PORT)
238 else if (dvo & DVOC_PORT)
240 else if (dvo & LVDS_PORT)
248 intelfbhw_validate_mode(struct intelfb_info *dinfo,
249 struct fb_var_screeninfo *var)
255 DBG_MSG("intelfbhw_validate_mode\n");
258 bytes_per_pixel = var->bits_per_pixel / 8;
259 if (bytes_per_pixel == 3)
262 /* Check if enough video memory. */
263 tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;
264 if (tmp > dinfo->fb.size) {
265 WRN_MSG("Not enough video ram for mode "
266 "(%d KByte vs %d KByte).\n",
267 BtoKB(tmp), BtoKB(dinfo->fb.size));
271 /* Check if x/y limits are OK. */
272 if (var->xres - 1 > HACTIVE_MASK) {
273 WRN_MSG("X resolution too large (%d vs %d).\n",
274 var->xres, HACTIVE_MASK + 1);
277 if (var->yres - 1 > VACTIVE_MASK) {
278 WRN_MSG("Y resolution too large (%d vs %d).\n",
279 var->yres, VACTIVE_MASK + 1);
283 /* Check for interlaced/doublescan modes. */
284 if (var->vmode & FB_VMODE_INTERLACED) {
285 WRN_MSG("Mode is interlaced.\n");
288 if (var->vmode & FB_VMODE_DOUBLE) {
289 WRN_MSG("Mode is double-scan.\n");
293 /* Check if clock is OK. */
294 tmp = 1000000000 / var->pixclock;
295 if (tmp < MIN_CLOCK) {
296 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n",
297 (tmp + 500) / 1000, MIN_CLOCK / 1000);
300 if (tmp > MAX_CLOCK) {
301 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n",
302 (tmp + 500) / 1000, MAX_CLOCK / 1000);
310 intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
312 struct intelfb_info *dinfo = GET_DINFO(info);
313 u32 offset, xoffset, yoffset;
316 DBG_MSG("intelfbhw_pan_display\n");
319 xoffset = ROUND_DOWN_TO(var->xoffset, 8);
320 yoffset = var->yoffset;
322 if ((xoffset + var->xres > var->xres_virtual) ||
323 (yoffset + var->yres > var->yres_virtual))
326 offset = (yoffset * dinfo->pitch) +
327 (xoffset * var->bits_per_pixel) / 8;
329 offset += dinfo->fb.offset << 12;
331 OUTREG(DSPABASE, offset);
336 /* Blank the screen. */
338 intelfbhw_do_blank(int blank, struct fb_info *info)
340 struct intelfb_info *dinfo = GET_DINFO(info);
344 DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank);
347 /* Turn plane A on or off */
348 tmp = INREG(DSPACNTR);
350 tmp &= ~DISPPLANE_PLANE_ENABLE;
352 tmp |= DISPPLANE_PLANE_ENABLE;
353 OUTREG(DSPACNTR, tmp);
355 tmp = INREG(DSPABASE);
356 OUTREG(DSPABASE, tmp);
358 /* Turn off/on the HW cursor */
360 DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
362 if (dinfo->cursor_on) {
364 intelfbhw_cursor_hide(dinfo);
366 intelfbhw_cursor_show(dinfo);
368 dinfo->cursor_on = 1;
370 dinfo->cursor_blanked = blank;
373 tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;
375 case FB_BLANK_UNBLANK:
376 case FB_BLANK_NORMAL:
379 case FB_BLANK_VSYNC_SUSPEND:
382 case FB_BLANK_HSYNC_SUSPEND:
385 case FB_BLANK_POWERDOWN:
396 intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
397 unsigned red, unsigned green, unsigned blue,
401 DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
402 regno, red, green, blue);
405 u32 palette_reg = (dinfo->pipe == PIPE_A) ?
406 PALETTE_A : PALETTE_B;
408 OUTREG(palette_reg + (regno << 2),
409 (red << PALETTE_8_RED_SHIFT) |
410 (green << PALETTE_8_GREEN_SHIFT) |
411 (blue << PALETTE_8_BLUE_SHIFT));
416 intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
422 DBG_MSG("intelfbhw_read_hw_state\n");
428 /* Read in as much of the HW state as possible. */
429 hw->vga0_divisor = INREG(VGA0_DIVISOR);
430 hw->vga1_divisor = INREG(VGA1_DIVISOR);
431 hw->vga_pd = INREG(VGAPD);
432 hw->dpll_a = INREG(DPLL_A);
433 hw->dpll_b = INREG(DPLL_B);
434 hw->fpa0 = INREG(FPA0);
435 hw->fpa1 = INREG(FPA1);
436 hw->fpb0 = INREG(FPB0);
437 hw->fpb1 = INREG(FPB1);
443 /* This seems to be a problem with the 852GM/855GM */
444 for (i = 0; i < PALETTE_8_ENTRIES; i++) {
445 hw->palette_a[i] = INREG(PALETTE_A + (i << 2));
446 hw->palette_b[i] = INREG(PALETTE_B + (i << 2));
453 hw->htotal_a = INREG(HTOTAL_A);
454 hw->hblank_a = INREG(HBLANK_A);
455 hw->hsync_a = INREG(HSYNC_A);
456 hw->vtotal_a = INREG(VTOTAL_A);
457 hw->vblank_a = INREG(VBLANK_A);
458 hw->vsync_a = INREG(VSYNC_A);
459 hw->src_size_a = INREG(SRC_SIZE_A);
460 hw->bclrpat_a = INREG(BCLRPAT_A);
461 hw->htotal_b = INREG(HTOTAL_B);
462 hw->hblank_b = INREG(HBLANK_B);
463 hw->hsync_b = INREG(HSYNC_B);
464 hw->vtotal_b = INREG(VTOTAL_B);
465 hw->vblank_b = INREG(VBLANK_B);
466 hw->vsync_b = INREG(VSYNC_B);
467 hw->src_size_b = INREG(SRC_SIZE_B);
468 hw->bclrpat_b = INREG(BCLRPAT_B);
473 hw->adpa = INREG(ADPA);
474 hw->dvoa = INREG(DVOA);
475 hw->dvob = INREG(DVOB);
476 hw->dvoc = INREG(DVOC);
477 hw->dvoa_srcdim = INREG(DVOA_SRCDIM);
478 hw->dvob_srcdim = INREG(DVOB_SRCDIM);
479 hw->dvoc_srcdim = INREG(DVOC_SRCDIM);
480 hw->lvds = INREG(LVDS);
485 hw->pipe_a_conf = INREG(PIPEACONF);
486 hw->pipe_b_conf = INREG(PIPEBCONF);
487 hw->disp_arb = INREG(DISPARB);
492 hw->cursor_a_control = INREG(CURSOR_A_CONTROL);
493 hw->cursor_b_control = INREG(CURSOR_B_CONTROL);
494 hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);
495 hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);
500 for (i = 0; i < 4; i++) {
501 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));
502 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));
508 hw->cursor_size = INREG(CURSOR_SIZE);
513 hw->disp_a_ctrl = INREG(DSPACNTR);
514 hw->disp_b_ctrl = INREG(DSPBCNTR);
515 hw->disp_a_base = INREG(DSPABASE);
516 hw->disp_b_base = INREG(DSPBBASE);
517 hw->disp_a_stride = INREG(DSPASTRIDE);
518 hw->disp_b_stride = INREG(DSPBSTRIDE);
523 hw->vgacntrl = INREG(VGACNTRL);
528 hw->add_id = INREG(ADD_ID);
533 for (i = 0; i < 7; i++) {
534 hw->swf0x[i] = INREG(SWF00 + (i << 2));
535 hw->swf1x[i] = INREG(SWF10 + (i << 2));
537 hw->swf3x[i] = INREG(SWF30 + (i << 2));
540 for (i = 0; i < 8; i++)
541 hw->fence[i] = INREG(FENCE + (i << 2));
543 hw->instpm = INREG(INSTPM);
544 hw->mem_mode = INREG(MEM_MODE);
545 hw->fw_blc_0 = INREG(FW_BLC_0);
546 hw->fw_blc_1 = INREG(FW_BLC_1);
553 intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
556 int i, m1, m2, n, p1, p2;
558 DBG_MSG("intelfbhw_print_hw_state\n");
562 /* Read in as much of the HW state as possible. */
563 printk("hw state dump start\n");
564 printk(" VGA0_DIVISOR: 0x%08x\n", hw->vga0_divisor);
565 printk(" VGA1_DIVISOR: 0x%08x\n", hw->vga1_divisor);
566 printk(" VGAPD: 0x%08x\n", hw->vga_pd);
567 n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
568 m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
569 m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
570 if (hw->vga_pd & VGAPD_0_P1_FORCE_DIV2)
573 p1 = (hw->vga_pd >> VGAPD_0_P1_SHIFT) & DPLL_P1_MASK;
574 p2 = (hw->vga_pd >> VGAPD_0_P2_SHIFT) & DPLL_P2_MASK;
575 printk(" VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
577 printk(" VGA0: clock is %d\n", CALC_VCLOCK(m1, m2, n, p1, p2));
579 n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
580 m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
581 m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
582 if (hw->vga_pd & VGAPD_1_P1_FORCE_DIV2)
585 p1 = (hw->vga_pd >> VGAPD_1_P1_SHIFT) & DPLL_P1_MASK;
586 p2 = (hw->vga_pd >> VGAPD_1_P2_SHIFT) & DPLL_P2_MASK;
587 printk(" VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
589 printk(" VGA1: clock is %d\n", CALC_VCLOCK(m1, m2, n, p1, p2));
591 printk(" DPLL_A: 0x%08x\n", hw->dpll_a);
592 printk(" DPLL_B: 0x%08x\n", hw->dpll_b);
593 printk(" FPA0: 0x%08x\n", hw->fpa0);
594 printk(" FPA1: 0x%08x\n", hw->fpa1);
595 printk(" FPB0: 0x%08x\n", hw->fpb0);
596 printk(" FPB1: 0x%08x\n", hw->fpb1);
598 n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
599 m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
600 m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
601 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
604 p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
605 p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
606 printk(" PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
608 printk(" PLLA0: clock is %d\n", CALC_VCLOCK(m1, m2, n, p1, p2));
610 n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
611 m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
612 m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
613 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
616 p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
617 p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
618 printk(" PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
620 printk(" PLLA1: clock is %d\n", CALC_VCLOCK(m1, m2, n, p1, p2));
623 printk(" PALETTE_A:\n");
624 for (i = 0; i < PALETTE_8_ENTRIES)
625 printk(" %3d: 0x%08x\n", i, hw->palette_a[i];
626 printk(" PALETTE_B:\n");
627 for (i = 0; i < PALETTE_8_ENTRIES)
628 printk(" %3d: 0x%08x\n", i, hw->palette_b[i];
631 printk(" HTOTAL_A: 0x%08x\n", hw->htotal_a);
632 printk(" HBLANK_A: 0x%08x\n", hw->hblank_a);
633 printk(" HSYNC_A: 0x%08x\n", hw->hsync_a);
634 printk(" VTOTAL_A: 0x%08x\n", hw->vtotal_a);
635 printk(" VBLANK_A: 0x%08x\n", hw->vblank_a);
636 printk(" VSYNC_A: 0x%08x\n", hw->vsync_a);
637 printk(" SRC_SIZE_A: 0x%08x\n", hw->src_size_a);
638 printk(" BCLRPAT_A: 0x%08x\n", hw->bclrpat_a);
639 printk(" HTOTAL_B: 0x%08x\n", hw->htotal_b);
640 printk(" HBLANK_B: 0x%08x\n", hw->hblank_b);
641 printk(" HSYNC_B: 0x%08x\n", hw->hsync_b);
642 printk(" VTOTAL_B: 0x%08x\n", hw->vtotal_b);
643 printk(" VBLANK_B: 0x%08x\n", hw->vblank_b);
644 printk(" VSYNC_B: 0x%08x\n", hw->vsync_b);
645 printk(" SRC_SIZE_B: 0x%08x\n", hw->src_size_b);
646 printk(" BCLRPAT_B: 0x%08x\n", hw->bclrpat_b);
648 printk(" ADPA: 0x%08x\n", hw->adpa);
649 printk(" DVOA: 0x%08x\n", hw->dvoa);
650 printk(" DVOB: 0x%08x\n", hw->dvob);
651 printk(" DVOC: 0x%08x\n", hw->dvoc);
652 printk(" DVOA_SRCDIM: 0x%08x\n", hw->dvoa_srcdim);
653 printk(" DVOB_SRCDIM: 0x%08x\n", hw->dvob_srcdim);
654 printk(" DVOC_SRCDIM: 0x%08x\n", hw->dvoc_srcdim);
655 printk(" LVDS: 0x%08x\n", hw->lvds);
657 printk(" PIPEACONF: 0x%08x\n", hw->pipe_a_conf);
658 printk(" PIPEBCONF: 0x%08x\n", hw->pipe_b_conf);
659 printk(" DISPARB: 0x%08x\n", hw->disp_arb);
661 printk(" CURSOR_A_CONTROL: 0x%08x\n", hw->cursor_a_control);
662 printk(" CURSOR_B_CONTROL: 0x%08x\n", hw->cursor_b_control);
663 printk(" CURSOR_A_BASEADDR: 0x%08x\n", hw->cursor_a_base);
664 printk(" CURSOR_B_BASEADDR: 0x%08x\n", hw->cursor_b_base);
666 printk(" CURSOR_A_PALETTE: ");
667 for (i = 0; i < 4; i++) {
668 printk("0x%08x", hw->cursor_a_palette[i]);
673 printk(" CURSOR_B_PALETTE: ");
674 for (i = 0; i < 4; i++) {
675 printk("0x%08x", hw->cursor_b_palette[i]);
681 printk(" CURSOR_SIZE: 0x%08x\n", hw->cursor_size);
683 printk(" DSPACNTR: 0x%08x\n", hw->disp_a_ctrl);
684 printk(" DSPBCNTR: 0x%08x\n", hw->disp_b_ctrl);
685 printk(" DSPABASE: 0x%08x\n", hw->disp_a_base);
686 printk(" DSPBBASE: 0x%08x\n", hw->disp_b_base);
687 printk(" DSPASTRIDE: 0x%08x\n", hw->disp_a_stride);
688 printk(" DSPBSTRIDE: 0x%08x\n", hw->disp_b_stride);
690 printk(" VGACNTRL: 0x%08x\n", hw->vgacntrl);
691 printk(" ADD_ID: 0x%08x\n", hw->add_id);
693 for (i = 0; i < 7; i++) {
694 printk(" SWF0%d 0x%08x\n", i,
697 for (i = 0; i < 7; i++) {
698 printk(" SWF1%d 0x%08x\n", i,
701 for (i = 0; i < 3; i++) {
702 printk(" SWF3%d 0x%08x\n", i,
705 for (i = 0; i < 8; i++)
706 printk(" FENCE%d 0x%08x\n", i,
709 printk(" INSTPM 0x%08x\n", hw->instpm);
710 printk(" MEM_MODE 0x%08x\n", hw->mem_mode);
711 printk(" FW_BLC_0 0x%08x\n", hw->fw_blc_0);
712 printk(" FW_BLC_1 0x%08x\n", hw->fw_blc_1);
714 printk("hw state dump end\n");
718 /* Split the M parameter into M1 and M2. */
720 splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2)
724 m1 = (m - 2 - (plls[index].min_m1 + plls[index].max_m2) / 2) / 5 - 2;
725 if (m1 < plls[index].min_m1)
726 m1 = plls[index].min_m1;
727 if (m1 > plls[index].max_m1)
728 m1 = plls[index].max_m1;
729 m2 = m - 5 * (m1 + 2) - 2;
730 if (m2 < plls[index].min_m2 || m2 > plls[index].max_m2 || m2 >= m1) {
733 *retm1 = (unsigned int)m1;
734 *retm2 = (unsigned int)m2;
739 /* Split the P parameter into P1 and P2. */
741 splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2)
745 if (index==PLLS_I8xx)
751 p1 = (p / (1 << (p2 + 1))) - 2;
752 if (p % 4 == 0 && p1 < plls[index].min_p1) {
754 p1 = (p / (1 << (p2 + 1))) - 2;
756 if (p1 < plls[index].min_p1 || p1 > plls[index].max_p1 || (p1 + 2) * (1 << (p2 + 1)) != p) {
759 *retp1 = (unsigned int)p1;
760 *retp2 = (unsigned int)p2;
768 calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
769 u32 *retp2, u32 *retclock)
771 u32 m1, m2, n, p1, p2, n1;
772 u32 f_vco, p, p_best = 0, m, f_out;
773 u32 err_max, err_target, err_best = 10000000;
774 u32 n_best = 0, m_best = 0, f_best, f_err;
775 u32 p_min, p_max, p_inc, div_min, div_max;
777 /* Accept 0.5% difference, but aim for 0.1% */
778 err_max = 5 * clock / 1000;
779 err_target = clock / 1000;
781 DBG_MSG("Clock is %d\n", clock);
783 div_max = plls[index].max_vco_freq / clock;
784 div_min = ROUND_UP_TO(plls[index].min_vco_freq, clock) / clock;
786 if (clock <= plls[index].p_transition_clock)
790 p_min = ROUND_UP_TO(div_min, p_inc);
791 p_max = ROUND_DOWN_TO(div_max, p_inc);
792 if (p_min < plls[index].min_p)
794 if (p_max > plls[index].max_p)
797 DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
801 if (splitp(index, p, &p1, &p2)) {
802 WRN_MSG("cannot split p = %d\n", p);
806 n = plls[index].min_n;
810 m = ROUND_UP_TO(f_vco * n, PLL_REFCLK) / PLL_REFCLK;
811 if (m < plls[index].min_m)
812 m = plls[index].min_m;
813 if (m > plls[index].max_m)
814 m = plls[index].max_m;
815 f_out = CALC_VCLOCK3(m, n, p);
816 if (splitm(index, m, &m1, &m2)) {
817 WRN_MSG("cannot split m = %d\n", m);
822 f_err = clock - f_out;
824 f_err = f_out - clock;
826 if (f_err < err_best) {
834 } while ((n <= plls[index].max_n) && (f_out >= clock));
836 } while ((p <= p_max));
839 WRN_MSG("cannot find parameters for clock %d\n", clock);
845 splitm(index, m, &m1, &m2);
846 splitp(index, p, &p1, &p2);
849 DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
850 "f: %d (%d), VCO: %d\n",
851 m, m1, m2, n, n1, p, p1, p2,
852 CALC_VCLOCK3(m, n, p), CALC_VCLOCK(m1, m2, n1, p1, p2),
853 CALC_VCLOCK3(m, n, p) * p);
859 *retclock = CALC_VCLOCK(m1, m2, n1, p1, p2);
864 static __inline__ int
865 check_overflow(u32 value, u32 limit, const char *description)
868 WRN_MSG("%s value %d exceeds limit %d\n",
869 description, value, limit);
875 /* It is assumed that hw is filled in with the initial state information. */
877 intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
878 struct fb_var_screeninfo *var)
881 u32 *dpll, *fp0, *fp1;
882 u32 m1, m2, n, p1, p2, clock_target, clock;
883 u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive;
884 u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive;
885 u32 vsync_pol, hsync_pol;
886 u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf;
888 DBG_MSG("intelfbhw_mode_to_hw\n");
891 hw->vgacntrl |= VGA_DISABLE;
893 /* Check whether pipe A or pipe B is enabled. */
894 if (hw->pipe_a_conf & PIPECONF_ENABLE)
896 else if (hw->pipe_b_conf & PIPECONF_ENABLE)
899 /* Set which pipe's registers will be set. */
900 if (pipe == PIPE_B) {
910 ss = &hw->src_size_b;
911 pipe_conf = &hw->pipe_b_conf;
922 ss = &hw->src_size_a;
923 pipe_conf = &hw->pipe_a_conf;
926 /* Use ADPA register for sync control. */
927 hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
930 hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ?
931 ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
932 vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ?
933 ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
934 hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
935 (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT));
936 hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
937 (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT);
939 /* Connect correct pipe to the analog port DAC */
940 hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
941 hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
943 /* Set DPMS state to D0 (on) */
944 hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
945 hw->adpa |= ADPA_DPMS_D0;
947 hw->adpa |= ADPA_DAC_ENABLE;
949 *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
950 *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
951 *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
953 /* Desired clock in kHz */
954 clock_target = 1000000000 / var->pixclock;
956 if (calc_pll_params(PLLS_I8xx, clock_target, &m1, &m2, &n, &p1, &p2, &clock)) {
957 WRN_MSG("calc_pll_params failed\n");
961 /* Check for overflow. */
962 if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter"))
964 if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter"))
966 if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))
968 if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
970 if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter"))
973 *dpll &= ~DPLL_P1_FORCE_DIV2;
974 *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
975 (DPLL_P1_MASK << DPLL_P1_SHIFT));
976 *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
977 *fp0 = (n << FP_N_DIVISOR_SHIFT) |
978 (m1 << FP_M1_DIVISOR_SHIFT) |
979 (m2 << FP_M2_DIVISOR_SHIFT);
982 hw->dvob &= ~PORT_ENABLE;
983 hw->dvoc &= ~PORT_ENABLE;
985 /* Use display plane A. */
986 hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE;
987 hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE;
988 hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK;
989 switch (intelfb_var_to_depth(var)) {
991 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE;
994 hw->disp_a_ctrl |= DISPPLANE_15_16BPP;
997 hw->disp_a_ctrl |= DISPPLANE_16BPP;
1000 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA;
1003 hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT);
1004 hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT);
1006 /* Set CRTC registers. */
1007 hactive = var->xres;
1008 hsync_start = hactive + var->right_margin;
1009 hsync_end = hsync_start + var->hsync_len;
1010 htotal = hsync_end + var->left_margin;
1011 hblank_start = hactive;
1012 hblank_end = htotal;
1014 DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1015 hactive, hsync_start, hsync_end, htotal, hblank_start,
1018 vactive = var->yres;
1019 vsync_start = vactive + var->lower_margin;
1020 vsync_end = vsync_start + var->vsync_len;
1021 vtotal = vsync_end + var->upper_margin;
1022 vblank_start = vactive;
1023 vblank_end = vtotal;
1024 vblank_end = vsync_end + 1;
1026 DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1027 vactive, vsync_start, vsync_end, vtotal, vblank_start,
1030 /* Adjust for register values, and check for overflow. */
1032 if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive"))
1035 if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start"))
1038 if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end"))
1041 if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal"))
1044 if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start"))
1047 if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end"))
1051 if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive"))
1054 if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start"))
1057 if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end"))
1060 if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal"))
1063 if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start"))
1066 if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end"))
1069 *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT);
1070 *hb = (hblank_start << HBLANKSTART_SHIFT) |
1071 (hblank_end << HSYNCEND_SHIFT);
1072 *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
1074 *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT);
1075 *vb = (vblank_start << VBLANKSTART_SHIFT) |
1076 (vblank_end << VSYNCEND_SHIFT);
1077 *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT);
1078 *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) |
1079 (vactive << SRC_SIZE_VERT_SHIFT);
1081 hw->disp_a_stride = var->xres_virtual * var->bits_per_pixel / 8;
1082 DBG_MSG("pitch is %d\n", hw->disp_a_stride);
1084 hw->disp_a_base = hw->disp_a_stride * var->yoffset +
1085 var->xoffset * var->bits_per_pixel / 8;
1087 hw->disp_a_base += dinfo->fb.offset << 12;
1089 /* Check stride alignment. */
1090 if (hw->disp_a_stride % STRIDE_ALIGNMENT != 0) {
1091 WRN_MSG("display stride %d has bad alignment %d\n",
1092 hw->disp_a_stride, STRIDE_ALIGNMENT);
1096 /* Set the palette to 8-bit mode. */
1097 *pipe_conf &= ~PIPECONF_GAMMA;
1101 /* Program a (non-VGA) video mode. */
1103 intelfbhw_program_mode(struct intelfb_info *dinfo,
1104 const struct intelfb_hwstate *hw, int blank)
1108 const u32 *dpll, *fp0, *fp1, *pipe_conf;
1109 const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
1110 u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg;
1111 u32 hsync_reg, htotal_reg, hblank_reg;
1112 u32 vsync_reg, vtotal_reg, vblank_reg;
1115 /* Assume single pipe, display plane A, analog CRT. */
1118 DBG_MSG("intelfbhw_program_mode\n");
1122 tmp = INREG(VGACNTRL);
1124 OUTREG(VGACNTRL, tmp);
1126 /* Check whether pipe A or pipe B is enabled. */
1127 if (hw->pipe_a_conf & PIPECONF_ENABLE)
1129 else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1134 if (pipe == PIPE_B) {
1138 pipe_conf = &hw->pipe_b_conf;
1145 ss = &hw->src_size_b;
1149 pipe_conf_reg = PIPEBCONF;
1150 hsync_reg = HSYNC_B;
1151 htotal_reg = HTOTAL_B;
1152 hblank_reg = HBLANK_B;
1153 vsync_reg = VSYNC_B;
1154 vtotal_reg = VTOTAL_B;
1155 vblank_reg = VBLANK_B;
1156 src_size_reg = SRC_SIZE_B;
1161 pipe_conf = &hw->pipe_a_conf;
1168 ss = &hw->src_size_a;
1172 pipe_conf_reg = PIPEACONF;
1173 hsync_reg = HSYNC_A;
1174 htotal_reg = HTOTAL_A;
1175 hblank_reg = HBLANK_A;
1176 vsync_reg = VSYNC_A;
1177 vtotal_reg = VTOTAL_A;
1178 vblank_reg = VBLANK_A;
1179 src_size_reg = SRC_SIZE_A;
1182 /* Disable planes A and B. */
1183 tmp = INREG(DSPACNTR);
1184 tmp &= ~DISPPLANE_PLANE_ENABLE;
1185 OUTREG(DSPACNTR, tmp);
1186 tmp = INREG(DSPBCNTR);
1187 tmp &= ~DISPPLANE_PLANE_ENABLE;
1188 OUTREG(DSPBCNTR, tmp);
1190 /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
1195 tmp &= ~ADPA_DPMS_CONTROL_MASK;
1196 tmp |= ADPA_DPMS_D3;
1200 tmp = INREG(pipe_conf_reg);
1201 tmp &= ~PIPECONF_ENABLE;
1202 OUTREG(pipe_conf_reg, tmp);
1205 tmp = INREG(dpll_reg);
1206 dpll_reg &= ~DPLL_VCO_ENABLE;
1207 OUTREG(dpll_reg, tmp);
1209 /* Set PLL parameters */
1210 OUTREG(dpll_reg, *dpll & ~DPLL_VCO_ENABLE);
1211 OUTREG(fp0_reg, *fp0);
1212 OUTREG(fp1_reg, *fp1);
1214 /* Set pipe parameters */
1215 OUTREG(hsync_reg, *hs);
1216 OUTREG(hblank_reg, *hb);
1217 OUTREG(htotal_reg, *ht);
1218 OUTREG(vsync_reg, *vs);
1219 OUTREG(vblank_reg, *vb);
1220 OUTREG(vtotal_reg, *vt);
1221 OUTREG(src_size_reg, *ss);
1224 OUTREG(DVOB, hw->dvob);
1225 OUTREG(DVOC, hw->dvoc);
1228 OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
1231 tmp = INREG(dpll_reg);
1232 tmp |= DPLL_VCO_ENABLE;
1233 OUTREG(dpll_reg, tmp);
1236 OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
1240 tmp &= ~ADPA_DPMS_CONTROL_MASK;
1241 tmp |= ADPA_DPMS_D0;
1244 /* setup display plane */
1245 if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
1247 * i830M errata: the display plane must be enabled
1248 * to allow writes to the other bits in the plane
1251 tmp = INREG(DSPACNTR);
1252 if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {
1253 tmp |= DISPPLANE_PLANE_ENABLE;
1254 OUTREG(DSPACNTR, tmp);
1256 hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
1261 OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
1262 OUTREG(DSPASTRIDE, hw->disp_a_stride);
1263 OUTREG(DSPABASE, hw->disp_a_base);
1267 tmp = INREG(DSPACNTR);
1268 tmp |= DISPPLANE_PLANE_ENABLE;
1269 OUTREG(DSPACNTR, tmp);
1270 OUTREG(DSPABASE, hw->disp_a_base);
1276 /* forward declarations */
1277 static void refresh_ring(struct intelfb_info *dinfo);
1278 static void reset_state(struct intelfb_info *dinfo);
1279 static void do_flush(struct intelfb_info *dinfo);
1282 wait_ring(struct intelfb_info *dinfo, int n)
1286 u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1289 DBG_MSG("wait_ring: %d\n", n);
1292 end = jiffies + (HZ * 3);
1293 while (dinfo->ring_space < n) {
1294 dinfo->ring_head = (u8 __iomem *)(INREG(PRI_RING_HEAD) &
1296 if (dinfo->ring_tail + RING_MIN_FREE <
1297 (u32 __iomem) dinfo->ring_head)
1298 dinfo->ring_space = (u32 __iomem) dinfo->ring_head
1299 - (dinfo->ring_tail + RING_MIN_FREE);
1301 dinfo->ring_space = (dinfo->ring.size +
1302 (u32 __iomem) dinfo->ring_head)
1303 - (dinfo->ring_tail + RING_MIN_FREE);
1304 if ((u32 __iomem) dinfo->ring_head != last_head) {
1305 end = jiffies + (HZ * 3);
1306 last_head = (u32 __iomem) dinfo->ring_head;
1309 if (time_before(end, jiffies)) {
1313 refresh_ring(dinfo);
1315 end = jiffies + (HZ * 3);
1318 WRN_MSG("ring buffer : space: %d wanted %d\n",
1319 dinfo->ring_space, n);
1320 WRN_MSG("lockup - turning off hardware "
1322 dinfo->ring_lockup = 1;
1332 do_flush(struct intelfb_info *dinfo) {
1334 OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
1340 intelfbhw_do_sync(struct intelfb_info *dinfo)
1343 DBG_MSG("intelfbhw_do_sync\n");
1350 * Send a flush, then wait until the ring is empty. This is what
1351 * the XFree86 driver does, and actually it doesn't seem a lot worse
1352 * than the recommended method (both have problems).
1355 wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
1356 dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
1360 refresh_ring(struct intelfb_info *dinfo)
1363 DBG_MSG("refresh_ring\n");
1366 dinfo->ring_head = (u8 __iomem *) (INREG(PRI_RING_HEAD) &
1368 dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1369 if (dinfo->ring_tail + RING_MIN_FREE < (u32 __iomem)dinfo->ring_head)
1370 dinfo->ring_space = (u32 __iomem) dinfo->ring_head
1371 - (dinfo->ring_tail + RING_MIN_FREE);
1373 dinfo->ring_space = (dinfo->ring.size +
1374 (u32 __iomem) dinfo->ring_head)
1375 - (dinfo->ring_tail + RING_MIN_FREE);
1379 reset_state(struct intelfb_info *dinfo)
1385 DBG_MSG("reset_state\n");
1388 for (i = 0; i < FENCE_NUM; i++)
1389 OUTREG(FENCE + (i << 2), 0);
1391 /* Flush the ring buffer if it's enabled. */
1392 tmp = INREG(PRI_RING_LENGTH);
1393 if (tmp & RING_ENABLE) {
1395 DBG_MSG("reset_state: ring was enabled\n");
1397 refresh_ring(dinfo);
1398 intelfbhw_do_sync(dinfo);
1402 OUTREG(PRI_RING_LENGTH, 0);
1403 OUTREG(PRI_RING_HEAD, 0);
1404 OUTREG(PRI_RING_TAIL, 0);
1405 OUTREG(PRI_RING_START, 0);
1408 /* Stop the 2D engine, and turn off the ring buffer. */
1410 intelfbhw_2d_stop(struct intelfb_info *dinfo)
1413 DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n", dinfo->accel,
1414 dinfo->ring_active);
1420 dinfo->ring_active = 0;
1425 * Enable the ring buffer, and initialise the 2D engine.
1426 * It is assumed that the graphics engine has been stopped by previously
1427 * calling intelfb_2d_stop().
1430 intelfbhw_2d_start(struct intelfb_info *dinfo)
1433 DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n",
1434 dinfo->accel, dinfo->ring_active);
1440 /* Initialise the primary ring buffer. */
1441 OUTREG(PRI_RING_LENGTH, 0);
1442 OUTREG(PRI_RING_TAIL, 0);
1443 OUTREG(PRI_RING_HEAD, 0);
1445 OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
1446 OUTREG(PRI_RING_LENGTH,
1447 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1448 RING_NO_REPORT | RING_ENABLE);
1449 refresh_ring(dinfo);
1450 dinfo->ring_active = 1;
1453 /* 2D fillrect (solid fill or invert) */
1455 intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w, u32 h,
1456 u32 color, u32 pitch, u32 bpp, u32 rop)
1458 u32 br00, br09, br13, br14, br16;
1461 DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, "
1462 "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop);
1465 br00 = COLOR_BLT_CMD;
1466 br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
1467 br13 = (rop << ROP_SHIFT) | pitch;
1468 br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT);
1473 br13 |= COLOR_DEPTH_8;
1476 br13 |= COLOR_DEPTH_16;
1479 br13 |= COLOR_DEPTH_32;
1480 br00 |= WRITE_ALPHA | WRITE_RGB;
1494 DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
1495 dinfo->ring_tail, dinfo->ring_space);
1500 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1501 u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp)
1503 u32 br00, br09, br11, br12, br13, br22, br23, br26;
1506 DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n",
1507 curx, cury, dstx, dsty, w, h, pitch, bpp);
1510 br00 = XY_SRC_COPY_BLT_CMD;
1511 br09 = dinfo->fb_start;
1512 br11 = (pitch << PITCH_SHIFT);
1513 br12 = dinfo->fb_start;
1514 br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1515 br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT);
1516 br23 = ((dstx + w) << WIDTH_SHIFT) |
1517 ((dsty + h) << HEIGHT_SHIFT);
1518 br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT);
1522 br13 |= COLOR_DEPTH_8;
1525 br13 |= COLOR_DEPTH_16;
1528 br13 |= COLOR_DEPTH_32;
1529 br00 |= WRITE_ALPHA | WRITE_RGB;
1546 intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
1547 u32 h, const u8* cdat, u32 x, u32 y, u32 pitch, u32 bpp)
1549 int nbytes, ndwords, pad, tmp;
1550 u32 br00, br09, br13, br18, br19, br22, br23;
1551 int dat, ix, iy, iw;
1555 DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h);
1558 /* size in bytes of a padded scanline */
1559 nbytes = ROUND_UP_TO(w, 16) / 8;
1561 /* Total bytes of padded scanline data to write out. */
1562 nbytes = nbytes * h;
1565 * Check if the glyph data exceeds the immediate mode limit.
1566 * It would take a large font (1K pixels) to hit this limit.
1568 if (nbytes > MAX_MONO_IMM_SIZE)
1571 /* Src data is packaged a dword (32-bit) at a time. */
1572 ndwords = ROUND_UP_TO(nbytes, 4) / 4;
1575 * Ring has to be padded to a quad word. But because the command starts
1576 with 7 bytes, pad only if there is an even number of ndwords
1578 pad = !(ndwords % 2);
1580 tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;
1581 br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;
1582 br09 = dinfo->fb_start;
1583 br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1586 br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT);
1587 br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT);
1591 br13 |= COLOR_DEPTH_8;
1594 br13 |= COLOR_DEPTH_16;
1597 br13 |= COLOR_DEPTH_32;
1598 br00 |= WRITE_ALPHA | WRITE_RGB;
1602 START_RING(8 + ndwords);
1611 iw = ROUND_UP_TO(w, 8) / 8;
1614 for (j = 0; j < 2; ++j) {
1615 for (i = 0; i < 2; ++i) {
1616 if (ix != iw || i == 0)
1617 dat |= cdat[iy*iw + ix++] << (i+j*2)*8;
1619 if (ix == iw && iy != (h-1)) {
1633 /* HW cursor functions. */
1635 intelfbhw_cursor_init(struct intelfb_info *dinfo)
1640 DBG_MSG("intelfbhw_cursor_init\n");
1643 if (dinfo->mobile) {
1644 if (!dinfo->cursor.physical)
1646 tmp = INREG(CURSOR_A_CONTROL);
1647 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |
1648 CURSOR_MEM_TYPE_LOCAL |
1649 (1 << CURSOR_PIPE_SELECT_SHIFT));
1650 tmp |= CURSOR_MODE_DISABLE;
1651 OUTREG(CURSOR_A_CONTROL, tmp);
1652 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1654 tmp = INREG(CURSOR_CONTROL);
1655 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
1656 CURSOR_ENABLE | CURSOR_STRIDE_MASK);
1657 tmp = CURSOR_FORMAT_3C;
1658 OUTREG(CURSOR_CONTROL, tmp);
1659 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
1660 tmp = (64 << CURSOR_SIZE_H_SHIFT) |
1661 (64 << CURSOR_SIZE_V_SHIFT);
1662 OUTREG(CURSOR_SIZE, tmp);
1667 intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1672 DBG_MSG("intelfbhw_cursor_hide\n");
1675 dinfo->cursor_on = 0;
1676 if (dinfo->mobile) {
1677 if (!dinfo->cursor.physical)
1679 tmp = INREG(CURSOR_A_CONTROL);
1680 tmp &= ~CURSOR_MODE_MASK;
1681 tmp |= CURSOR_MODE_DISABLE;
1682 OUTREG(CURSOR_A_CONTROL, tmp);
1684 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1686 tmp = INREG(CURSOR_CONTROL);
1687 tmp &= ~CURSOR_ENABLE;
1688 OUTREG(CURSOR_CONTROL, tmp);
1693 intelfbhw_cursor_show(struct intelfb_info *dinfo)
1698 DBG_MSG("intelfbhw_cursor_show\n");
1701 dinfo->cursor_on = 1;
1703 if (dinfo->cursor_blanked)
1706 if (dinfo->mobile) {
1707 if (!dinfo->cursor.physical)
1709 tmp = INREG(CURSOR_A_CONTROL);
1710 tmp &= ~CURSOR_MODE_MASK;
1711 tmp |= CURSOR_MODE_64_4C_AX;
1712 OUTREG(CURSOR_A_CONTROL, tmp);
1714 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1716 tmp = INREG(CURSOR_CONTROL);
1717 tmp |= CURSOR_ENABLE;
1718 OUTREG(CURSOR_CONTROL, tmp);
1723 intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1728 DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y);
1732 * Sets the position. The coordinates are assumed to already
1733 * have any offset adjusted. Assume that the cursor is never
1734 * completely off-screen, and that x, y are always >= 0.
1737 tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
1738 ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1739 OUTREG(CURSOR_A_POSITION, tmp);
1743 intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1746 DBG_MSG("intelfbhw_cursor_setcolor\n");
1749 OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);
1750 OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);
1751 OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);
1752 OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);
1756 intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
1759 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1760 int i, j, w = width / 8;
1761 int mod = width % 8, t_mask, d_mask;
1764 DBG_MSG("intelfbhw_cursor_load\n");
1767 if (!dinfo->cursor.virtual)
1770 t_mask = 0xff >> mod;
1771 d_mask = ~(0xff >> mod);
1772 for (i = height; i--; ) {
1773 for (j = 0; j < w; j++) {
1774 writeb(0x00, addr + j);
1775 writeb(*(data++), addr + j+8);
1778 writeb(t_mask, addr + j);
1779 writeb(*(data++) & d_mask, addr + j+8);
1786 intelfbhw_cursor_reset(struct intelfb_info *dinfo) {
1787 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1791 DBG_MSG("intelfbhw_cursor_reset\n");
1794 if (!dinfo->cursor.virtual)
1797 for (i = 64; i--; ) {
1798 for (j = 0; j < 8; j++) {
1799 writeb(0xff, addr + j+0);
1800 writeb(0x00, addr + j+8);