2 * linux/drivers/video/i810_main.c -- Intel 810 frame buffer device
4 * Copyright (C) 2001 Antonino Daplas<adaplas@pol.net>
8 * Michael Vogt <mvogt@acm.org> - added support for Intel 815 chipsets
9 * and enabling the power-on state of
10 * external VGA connectors for
13 * Fredrik Andersson <krueger@shell.linux.se> - alpha testing of
16 * Brad Corrion <bcorrion@web-co.com> - alpha testing of customized
19 * The code framework is a modification of vfb.c by Geert Uytterhoeven.
20 * DotClock and PLL calculations are partly based on i810_driver.c
21 * in xfree86 v4.0.3 by Precision Insight.
22 * Watermark calculation and tables are based on i810_wmark.c
23 * in xfre86 v4.0.3 by Precision Insight. Slight modifications
24 * only to allow for integer operations instead of floating point.
26 * This file is subject to the terms and conditions of the GNU General Public
27 * License. See the file COPYING in the main directory of this archive for
31 #include <linux/module.h>
32 #include <linux/config.h>
33 #include <linux/kernel.h>
34 #include <linux/errno.h>
35 #include <linux/string.h>
37 #include <linux/tty.h>
38 #include <linux/slab.h>
40 #include <linux/init.h>
41 #include <linux/pci.h>
42 #include <linux/pci_ids.h>
43 #include <linux/resource.h>
44 #include <linux/unistd.h>
47 #include <asm/div64.h>
55 #include "i810_regs.h"
57 #include "i810_main.h"
60 static const char *i810_pci_list[] __devinitdata = {
61 "Intel(R) 810 Framebuffer Device" ,
62 "Intel(R) 810-DC100 Framebuffer Device" ,
63 "Intel(R) 810E Framebuffer Device" ,
64 "Intel(R) 815 (Internal Graphics 100Mhz FSB) Framebuffer Device" ,
65 "Intel(R) 815 (Internal Graphics only) Framebuffer Device" ,
66 "Intel(R) 815 (Internal Graphics with AGP) Framebuffer Device"
69 static struct pci_device_id i810fb_pci_tbl[] = {
70 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG1,
71 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
72 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3,
73 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1 },
74 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_IG,
75 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2 },
76 /* mvo: added i815 PCI-ID */
77 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_100,
78 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3 },
79 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_NOAGP,
80 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 4 },
81 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC,
82 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 5 },
86 static struct pci_driver i810fb_driver = {
88 .id_table = i810fb_pci_tbl,
89 .probe = i810fb_init_pci,
90 .remove = __exit_p(i810fb_remove_pci),
91 .suspend = i810fb_suspend,
92 .resume = i810fb_resume,
95 static int vram __initdata = 4;
96 static int bpp __initdata = 8;
97 static int mtrr __initdata = 0;
98 static int accel __initdata = 0;
99 static int hsync1 __initdata = 0;
100 static int hsync2 __initdata = 0;
101 static int vsync1 __initdata = 0;
102 static int vsync2 __initdata = 0;
103 static int xres __initdata = 640;
104 static int yres __initdata = 480;
105 static int vyres __initdata = 0;
106 static int sync __initdata = 0;
107 static int ext_vga __initdata = 0;
108 static int dcolor __initdata = 0;
110 /*------------------------------------------------------------*/
112 /**************************************************************
113 * Hardware Low Level Routines *
114 **************************************************************/
117 * i810_screen_off - turns off/on display
118 * @mmio: address of register space
122 * Blanks/unblanks the display
124 static void i810_screen_off(u8 __iomem *mmio, u8 mode)
126 u32 count = WAIT_COUNT;
129 i810_writeb(SR_INDEX, mmio, SR01);
130 val = i810_readb(SR_DATA, mmio);
131 val = (mode == OFF) ? val | SCR_OFF :
134 while((i810_readw(DISP_SL, mmio) & 0xFFF) && count--);
135 i810_writeb(SR_INDEX, mmio, SR01);
136 i810_writeb(SR_DATA, mmio, val);
140 * i810_dram_off - turns off/on dram refresh
141 * @mmio: address of register space
145 * Turns off DRAM refresh. Must be off for only 2 vsyncs
146 * before data becomes corrupt
148 static void i810_dram_off(u8 __iomem *mmio, u8 mode)
152 val = i810_readb(DRAMCH, mmio);
154 val = (mode == OFF) ? val : val | DRAM_ON;
155 i810_writeb(DRAMCH, mmio, val);
159 * i810_protect_regs - allows rw/ro mode of certain VGA registers
160 * @mmio: address of register space
161 * @mode: protect/unprotect
164 * The IBM VGA standard allows protection of certain VGA registers.
165 * This will protect or unprotect them.
167 static void i810_protect_regs(u8 __iomem *mmio, int mode)
171 i810_writeb(CR_INDEX_CGA, mmio, CR11);
172 reg = i810_readb(CR_DATA_CGA, mmio);
173 reg = (mode == OFF) ? reg & ~0x80 :
176 i810_writeb(CR_INDEX_CGA, mmio, CR11);
177 i810_writeb(CR_DATA_CGA, mmio, reg);
181 * i810_load_pll - loads values for the hardware PLL clock
182 * @par: pointer to i810fb_par structure
185 * Loads the P, M, and N registers.
187 static void i810_load_pll(struct i810fb_par *par)
190 u8 __iomem *mmio = par->mmio_start_virtual;
192 tmp1 = par->regs.M | par->regs.N << 16;
193 tmp2 = i810_readl(DCLK_2D, mmio);
195 i810_writel(DCLK_2D, mmio, tmp1 | tmp2);
198 tmp2 = i810_readl(DCLK_0DS, mmio);
199 tmp2 &= ~(P_OR << 16);
200 i810_writel(DCLK_0DS, mmio, (tmp1 << 16) | tmp2);
202 i810_writeb(MSR_WRITE, mmio, par->regs.msr | 0xC8 | 1);
207 * i810_load_vga - load standard VGA registers
208 * @par: pointer to i810fb_par structure
211 * Load values to VGA registers
213 static void i810_load_vga(struct i810fb_par *par)
215 u8 __iomem *mmio = par->mmio_start_virtual;
218 i810_writeb(CR_INDEX_CGA, mmio, CR70);
219 i810_writeb(CR_DATA_CGA, mmio, par->interlace);
221 i810_writeb(CR_INDEX_CGA, mmio, CR00);
222 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr00);
223 i810_writeb(CR_INDEX_CGA, mmio, CR01);
224 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr01);
225 i810_writeb(CR_INDEX_CGA, mmio, CR02);
226 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr02);
227 i810_writeb(CR_INDEX_CGA, mmio, CR03);
228 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr03);
229 i810_writeb(CR_INDEX_CGA, mmio, CR04);
230 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr04);
231 i810_writeb(CR_INDEX_CGA, mmio, CR05);
232 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr05);
233 i810_writeb(CR_INDEX_CGA, mmio, CR06);
234 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr06);
235 i810_writeb(CR_INDEX_CGA, mmio, CR09);
236 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr09);
237 i810_writeb(CR_INDEX_CGA, mmio, CR10);
238 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr10);
239 i810_writeb(CR_INDEX_CGA, mmio, CR11);
240 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr11);
241 i810_writeb(CR_INDEX_CGA, mmio, CR12);
242 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr12);
243 i810_writeb(CR_INDEX_CGA, mmio, CR15);
244 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr15);
245 i810_writeb(CR_INDEX_CGA, mmio, CR16);
246 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr16);
250 * i810_load_vgax - load extended VGA registers
251 * @par: pointer to i810fb_par structure
254 * Load values to extended VGA registers
256 static void i810_load_vgax(struct i810fb_par *par)
258 u8 __iomem *mmio = par->mmio_start_virtual;
260 i810_writeb(CR_INDEX_CGA, mmio, CR30);
261 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr30);
262 i810_writeb(CR_INDEX_CGA, mmio, CR31);
263 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr31);
264 i810_writeb(CR_INDEX_CGA, mmio, CR32);
265 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr32);
266 i810_writeb(CR_INDEX_CGA, mmio, CR33);
267 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr33);
268 i810_writeb(CR_INDEX_CGA, mmio, CR35);
269 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr35);
270 i810_writeb(CR_INDEX_CGA, mmio, CR39);
271 i810_writeb(CR_DATA_CGA, mmio, par->regs.cr39);
275 * i810_load_2d - load grahics registers
276 * @par: pointer to i810fb_par structure
279 * Load values to graphics registers
281 static void i810_load_2d(struct i810fb_par *par)
285 u8 __iomem *mmio = par->mmio_start_virtual;
287 i810_writel(FW_BLC, mmio, par->watermark);
288 tmp = i810_readl(PIXCONF, mmio);
290 i810_writel(PIXCONF, mmio, tmp);
292 i810_writel(OVRACT, mmio, par->ovract);
294 i810_writeb(GR_INDEX, mmio, GR10);
295 tmp8 = i810_readb(GR_DATA, mmio);
297 i810_writeb(GR_INDEX, mmio, GR10);
298 i810_writeb(GR_DATA, mmio, tmp8);
302 * i810_hires - enables high resolution mode
303 * @mmio: address of register space
305 static void i810_hires(u8 __iomem *mmio)
309 i810_writeb(CR_INDEX_CGA, mmio, CR80);
310 val = i810_readb(CR_DATA_CGA, mmio);
311 i810_writeb(CR_INDEX_CGA, mmio, CR80);
312 i810_writeb(CR_DATA_CGA, mmio, val | 1);
316 * i810_load_pitch - loads the characters per line of the display
317 * @par: pointer to i810fb_par structure
320 * Loads the characters per line
322 static void i810_load_pitch(struct i810fb_par *par)
326 u8 __iomem *mmio = par->mmio_start_virtual;
328 pitch = par->pitch >> 3;
329 i810_writeb(SR_INDEX, mmio, SR01);
330 val = i810_readb(SR_DATA, mmio);
333 i810_writeb(SR_INDEX, mmio, SR01);
334 i810_writeb(SR_DATA, mmio, val);
337 i810_writeb(CR_INDEX_CGA, mmio, CR13);
338 i810_writeb(CR_DATA_CGA, mmio, (u8) tmp);
341 i810_writeb(CR_INDEX_CGA, mmio, CR41);
342 val = i810_readb(CR_DATA_CGA, mmio) & ~0x0F;
343 i810_writeb(CR_INDEX_CGA, mmio, CR41);
344 i810_writeb(CR_DATA_CGA, mmio, (u8) tmp | val);
348 * i810_load_color - loads the color depth of the display
349 * @par: pointer to i810fb_par structure
352 * Loads the color depth of the display and the graphics engine
354 static void i810_load_color(struct i810fb_par *par)
356 u8 __iomem *mmio = par->mmio_start_virtual;
360 reg1 = i810_readl(PIXCONF, mmio) & ~(0xF0000 | 1 << 27);
361 reg2 = i810_readw(BLTCNTL, mmio) & ~0x30;
363 reg1 |= 0x8000 | par->pixconf;
364 reg2 |= par->bltcntl;
365 i810_writel(PIXCONF, mmio, reg1);
366 i810_writew(BLTCNTL, mmio, reg2);
370 * i810_load_regs - loads all registers for the mode
371 * @par: pointer to i810fb_par structure
376 static void i810_load_regs(struct i810fb_par *par)
378 u8 __iomem *mmio = par->mmio_start_virtual;
380 i810_screen_off(mmio, OFF);
381 i810_protect_regs(mmio, OFF);
382 i810_dram_off(mmio, OFF);
386 i810_dram_off(mmio, ON);
389 i810_screen_off(mmio, ON);
390 i810_protect_regs(mmio, ON);
391 i810_load_color(par);
392 i810_load_pitch(par);
395 static void i810_write_dac(u8 regno, u8 red, u8 green, u8 blue,
398 i810_writeb(CLUT_INDEX_WRITE, mmio, regno);
399 i810_writeb(CLUT_DATA, mmio, red);
400 i810_writeb(CLUT_DATA, mmio, green);
401 i810_writeb(CLUT_DATA, mmio, blue);
404 static void i810_read_dac(u8 regno, u8 *red, u8 *green, u8 *blue,
407 i810_writeb(CLUT_INDEX_READ, mmio, regno);
408 *red = i810_readb(CLUT_DATA, mmio);
409 *green = i810_readb(CLUT_DATA, mmio);
410 *blue = i810_readb(CLUT_DATA, mmio);
413 /************************************************************
414 * VGA State Restore *
415 ************************************************************/
416 static void i810_restore_pll(struct i810fb_par *par)
419 u8 __iomem *mmio = par->mmio_start_virtual;
421 tmp1 = par->hw_state.dclk_2d;
422 tmp2 = i810_readl(DCLK_2D, mmio);
425 i810_writel(DCLK_2D, mmio, tmp1 | tmp2);
427 tmp1 = par->hw_state.dclk_1d;
428 tmp2 = i810_readl(DCLK_1D, mmio);
431 i810_writel(DCLK_1D, mmio, tmp1 | tmp2);
433 i810_writel(DCLK_0DS, mmio, par->hw_state.dclk_0ds);
436 static void i810_restore_dac(struct i810fb_par *par)
439 u8 __iomem *mmio = par->mmio_start_virtual;
441 tmp1 = par->hw_state.pixconf;
442 tmp2 = i810_readl(PIXCONF, mmio);
445 i810_writel(PIXCONF, mmio, tmp1 | tmp2);
448 static void i810_restore_vgax(struct i810fb_par *par)
451 u8 __iomem *mmio = par->mmio_start_virtual;
453 for (i = 0; i < 4; i++) {
454 i810_writeb(CR_INDEX_CGA, mmio, CR30+i);
455 i810_writeb(CR_DATA_CGA, mmio, *(&(par->hw_state.cr30) + i));
457 i810_writeb(CR_INDEX_CGA, mmio, CR35);
458 i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr35);
459 i810_writeb(CR_INDEX_CGA, mmio, CR39);
460 i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr39);
461 i810_writeb(CR_INDEX_CGA, mmio, CR41);
462 i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr39);
464 /*restore interlace*/
465 i810_writeb(CR_INDEX_CGA, mmio, CR70);
466 i = par->hw_state.cr70;
468 j = i810_readb(CR_DATA_CGA, mmio);
469 i810_writeb(CR_INDEX_CGA, mmio, CR70);
470 i810_writeb(CR_DATA_CGA, mmio, j | i);
472 i810_writeb(CR_INDEX_CGA, mmio, CR80);
473 i810_writeb(CR_DATA_CGA, mmio, par->hw_state.cr80);
474 i810_writeb(MSR_WRITE, mmio, par->hw_state.msr);
475 i810_writeb(SR_INDEX, mmio, SR01);
476 i = (par->hw_state.sr01) & ~0xE0 ;
477 j = i810_readb(SR_DATA, mmio) & 0xE0;
478 i810_writeb(SR_INDEX, mmio, SR01);
479 i810_writeb(SR_DATA, mmio, i | j);
482 static void i810_restore_vga(struct i810fb_par *par)
485 u8 __iomem *mmio = par->mmio_start_virtual;
487 for (i = 0; i < 10; i++) {
488 i810_writeb(CR_INDEX_CGA, mmio, CR00 + i);
489 i810_writeb(CR_DATA_CGA, mmio, *((&par->hw_state.cr00) + i));
491 for (i = 0; i < 8; i++) {
492 i810_writeb(CR_INDEX_CGA, mmio, CR10 + i);
493 i810_writeb(CR_DATA_CGA, mmio, *((&par->hw_state.cr10) + i));
497 static void i810_restore_addr_map(struct i810fb_par *par)
500 u8 __iomem *mmio = par->mmio_start_virtual;
502 i810_writeb(GR_INDEX, mmio, GR10);
503 tmp = i810_readb(GR_DATA, mmio);
504 tmp &= ADDR_MAP_MASK;
505 tmp |= par->hw_state.gr10;
506 i810_writeb(GR_INDEX, mmio, GR10);
507 i810_writeb(GR_DATA, mmio, tmp);
510 static void i810_restore_2d(struct i810fb_par *par)
514 u8 __iomem *mmio = par->mmio_start_virtual;
516 tmp_word = i810_readw(BLTCNTL, mmio);
517 tmp_word &= ~(3 << 4);
518 tmp_word |= par->hw_state.bltcntl;
519 i810_writew(BLTCNTL, mmio, tmp_word);
521 i810_dram_off(mmio, OFF);
522 i810_writel(PIXCONF, mmio, par->hw_state.pixconf);
523 i810_dram_off(mmio, ON);
525 tmp_word = i810_readw(HWSTAM, mmio);
527 tmp_word |= par->hw_state.hwstam;
528 i810_writew(HWSTAM, mmio, tmp_word);
530 tmp_long = i810_readl(FW_BLC, mmio);
531 tmp_long &= FW_BLC_MASK;
532 tmp_long |= par->hw_state.fw_blc;
533 i810_writel(FW_BLC, mmio, tmp_long);
535 i810_writel(HWS_PGA, mmio, par->hw_state.hws_pga);
536 i810_writew(IER, mmio, par->hw_state.ier);
537 i810_writew(IMR, mmio, par->hw_state.imr);
538 i810_writel(DPLYSTAS, mmio, par->hw_state.dplystas);
541 static void i810_restore_vga_state(struct i810fb_par *par)
543 u8 __iomem *mmio = par->mmio_start_virtual;
545 i810_screen_off(mmio, OFF);
546 i810_protect_regs(mmio, OFF);
547 i810_dram_off(mmio, OFF);
548 i810_restore_pll(par);
549 i810_restore_dac(par);
550 i810_restore_vga(par);
551 i810_restore_vgax(par);
552 i810_restore_addr_map(par);
553 i810_dram_off(mmio, ON);
554 i810_restore_2d(par);
555 i810_screen_off(mmio, ON);
556 i810_protect_regs(mmio, ON);
559 /***********************************************************************
561 ***********************************************************************/
563 static void i810_save_vgax(struct i810fb_par *par)
566 u8 __iomem *mmio = par->mmio_start_virtual;
568 for (i = 0; i < 4; i++) {
569 i810_writeb(CR_INDEX_CGA, mmio, CR30 + i);
570 *(&(par->hw_state.cr30) + i) = i810_readb(CR_DATA_CGA, mmio);
572 i810_writeb(CR_INDEX_CGA, mmio, CR35);
573 par->hw_state.cr35 = i810_readb(CR_DATA_CGA, mmio);
574 i810_writeb(CR_INDEX_CGA, mmio, CR39);
575 par->hw_state.cr39 = i810_readb(CR_DATA_CGA, mmio);
576 i810_writeb(CR_INDEX_CGA, mmio, CR41);
577 par->hw_state.cr41 = i810_readb(CR_DATA_CGA, mmio);
578 i810_writeb(CR_INDEX_CGA, mmio, CR70);
579 par->hw_state.cr70 = i810_readb(CR_DATA_CGA, mmio);
580 par->hw_state.msr = i810_readb(MSR_READ, mmio);
581 i810_writeb(CR_INDEX_CGA, mmio, CR80);
582 par->hw_state.cr80 = i810_readb(CR_DATA_CGA, mmio);
583 i810_writeb(SR_INDEX, mmio, SR01);
584 par->hw_state.sr01 = i810_readb(SR_DATA, mmio);
587 static void i810_save_vga(struct i810fb_par *par)
590 u8 __iomem *mmio = par->mmio_start_virtual;
592 for (i = 0; i < 10; i++) {
593 i810_writeb(CR_INDEX_CGA, mmio, CR00 + i);
594 *((&par->hw_state.cr00) + i) = i810_readb(CR_DATA_CGA, mmio);
596 for (i = 0; i < 8; i++) {
597 i810_writeb(CR_INDEX_CGA, mmio, CR10 + i);
598 *((&par->hw_state.cr10) + i) = i810_readb(CR_DATA_CGA, mmio);
602 static void i810_save_2d(struct i810fb_par *par)
604 u8 __iomem *mmio = par->mmio_start_virtual;
606 par->hw_state.dclk_2d = i810_readl(DCLK_2D, mmio);
607 par->hw_state.dclk_1d = i810_readl(DCLK_1D, mmio);
608 par->hw_state.dclk_0ds = i810_readl(DCLK_0DS, mmio);
609 par->hw_state.pixconf = i810_readl(PIXCONF, mmio);
610 par->hw_state.fw_blc = i810_readl(FW_BLC, mmio);
611 par->hw_state.bltcntl = i810_readw(BLTCNTL, mmio);
612 par->hw_state.hwstam = i810_readw(HWSTAM, mmio);
613 par->hw_state.hws_pga = i810_readl(HWS_PGA, mmio);
614 par->hw_state.ier = i810_readw(IER, mmio);
615 par->hw_state.imr = i810_readw(IMR, mmio);
616 par->hw_state.dplystas = i810_readl(DPLYSTAS, mmio);
619 static void i810_save_vga_state(struct i810fb_par *par)
626 /************************************************************
628 ************************************************************/
630 * get_line_length - calculates buffer pitch in bytes
631 * @par: pointer to i810fb_par structure
632 * @xres_virtual: virtual resolution of the frame
633 * @bpp: bits per pixel
636 * Calculates buffer pitch in bytes.
638 static u32 get_line_length(struct i810fb_par *par, int xres_virtual, int bpp)
642 length = xres_virtual*bpp;
643 length = (length+31)&-32;
649 * i810_calc_dclk - calculates the P, M, and N values of a pixelclock value
650 * @freq: target pixelclock in picoseconds
651 * @m: where to write M register
652 * @n: where to write N register
653 * @p: where to write P register
656 * Based on the formula Freq_actual = (4*M*Freq_ref)/(N^P)
657 * Repeatedly computes the Freq until the actual Freq is equal to
658 * the target Freq or until the loop count is zero. In the latter
659 * case, the actual frequency nearest the target will be used.
661 static void i810_calc_dclk(u32 freq, u32 *m, u32 *n, u32 *p)
663 u32 m_reg, n_reg, p_divisor, n_target_max;
664 u32 m_target, n_target, p_target, n_best, m_best, mod;
665 u32 f_out, target_freq, diff = 0, mod_min, diff_min;
667 diff_min = mod_min = 0xFFFFFFFF;
668 n_best = m_best = m_target = f_out = 0;
674 * find P such that target freq is 16x reference freq (Hz).
678 while(!((1000000 * p_divisor)/(16 * 24 * target_freq)) &&
684 n_reg = m_reg = n_target = 3;
685 while (diff_min && mod_min && (n_target < n_target_max)) {
686 f_out = (p_divisor * n_reg * 1000000)/(4 * 24 * m_reg);
687 mod = (p_divisor * n_reg * 1000000) % (4 * 24 * m_reg);
690 if (f_out <= target_freq) {
692 diff = target_freq - f_out;
695 diff = f_out - target_freq;
698 if (diff_min > diff) {
704 if (!diff && mod_min > mod) {
710 if (m) *m = (m_best - 2) & 0x3FF;
711 if (n) *n = (n_best - 2) & 0x3FF;
712 if (p) *p = (p_target << 4);
715 /*************************************************************
716 * Hardware Cursor Routines *
717 *************************************************************/
720 * i810_enable_cursor - show or hide the hardware cursor
721 * @mmio: address of register space
722 * @mode: show (1) or hide (0)
725 * Shows or hides the hardware cursor
727 static void i810_enable_cursor(u8 __iomem *mmio, int mode)
731 temp = i810_readl(PIXCONF, mmio);
732 temp = (mode == ON) ? temp | CURSOR_ENABLE_MASK :
733 temp & ~CURSOR_ENABLE_MASK;
735 i810_writel(PIXCONF, mmio, temp);
738 static void i810_reset_cursor_image(struct i810fb_par *par)
740 u8 __iomem *addr = par->cursor_heap.virtual;
743 for (i = 64; i--; ) {
744 for (j = 0; j < 8; j++) {
745 i810_writeb(j, addr, 0xff);
746 i810_writeb(j+8, addr, 0x00);
752 static void i810_load_cursor_image(int width, int height, u8 *data,
753 struct i810fb_par *par)
755 u8 __iomem *addr = par->cursor_heap.virtual;
756 int i, j, w = width/8;
757 int mod = width % 8, t_mask, d_mask;
759 t_mask = 0xff >> mod;
760 d_mask = ~(0xff >> mod);
761 for (i = height; i--; ) {
762 for (j = 0; j < w; j++) {
763 i810_writeb(j+0, addr, 0x00);
764 i810_writeb(j+8, addr, *data++);
767 i810_writeb(j+0, addr, t_mask);
768 i810_writeb(j+8, addr, *data++ & d_mask);
774 static void i810_load_cursor_colors(int fg, int bg, struct fb_info *info)
776 struct i810fb_par *par = (struct i810fb_par *) info->par;
777 u8 __iomem *mmio = par->mmio_start_virtual;
778 u8 red, green, blue, trans, temp;
780 i810fb_getcolreg(bg, &red, &green, &blue, &trans, info);
782 temp = i810_readb(PIXCONF1, mmio);
783 i810_writeb(PIXCONF1, mmio, temp | EXTENDED_PALETTE);
785 i810_write_dac(4, red, green, blue, mmio);
787 i810_writeb(PIXCONF1, mmio, temp);
789 i810fb_getcolreg(fg, &red, &green, &blue, &trans, info);
790 temp = i810_readb(PIXCONF1, mmio);
791 i810_writeb(PIXCONF1, mmio, temp | EXTENDED_PALETTE);
793 i810_write_dac(5, red, green, blue, mmio);
795 i810_writeb(PIXCONF1, mmio, temp);
799 * i810_init_cursor - initializes the cursor
800 * @par: pointer to i810fb_par structure
803 * Initializes the cursor registers
805 static void i810_init_cursor(struct i810fb_par *par)
807 u8 __iomem *mmio = par->mmio_start_virtual;
809 i810_enable_cursor(mmio, OFF);
810 i810_writel(CURBASE, mmio, par->cursor_heap.physical);
811 i810_writew(CURCNTR, mmio, COORD_ACTIVE | CURSOR_MODE_64_XOR);
814 /*********************************************************************
815 * Framebuffer hook helpers *
816 *********************************************************************/
818 * i810_round_off - Round off values to capability of hardware
819 * @var: pointer to fb_var_screeninfo structure
822 * @var contains user-defined information for the mode to be set.
823 * This will try modify those values to ones nearest the
824 * capability of the hardware
826 static void i810_round_off(struct fb_var_screeninfo *var)
828 u32 xres, yres, vxres, vyres;
831 * Presently supports only these configurations
836 vxres = var->xres_virtual;
837 vyres = var->yres_virtual;
839 var->bits_per_pixel += 7;
840 var->bits_per_pixel &= ~7;
842 if (var->bits_per_pixel < 8)
843 var->bits_per_pixel = 8;
844 if (var->bits_per_pixel > 32)
845 var->bits_per_pixel = 32;
847 round_off_xres(&xres);
852 xres = (xres + 7) & ~7;
857 round_off_yres(&xres, &yres);
866 if (var->bits_per_pixel == 32)
867 var->accel_flags = 0;
869 /* round of horizontal timings to nearest 8 pixels */
870 var->left_margin = (var->left_margin + 4) & ~7;
871 var->right_margin = (var->right_margin + 4) & ~7;
872 var->hsync_len = (var->hsync_len + 4) & ~7;
874 if (var->vmode & FB_VMODE_INTERLACED) {
875 if (!((yres + var->upper_margin + var->vsync_len +
876 var->lower_margin) & 1))
882 var->xres_virtual = vxres;
883 var->yres_virtual = vyres;
887 * set_color_bitfields - sets rgba fields
888 * @var: pointer to fb_var_screeninfo
891 * The length, offset and ordering for each color field
892 * (red, green, blue) will be set as specified
895 static void set_color_bitfields(struct fb_var_screeninfo *var)
897 switch (var->bits_per_pixel) {
901 var->green.offset = 0;
902 var->green.length = 8;
903 var->blue.offset = 0;
904 var->blue.length = 8;
905 var->transp.offset = 0;
906 var->transp.length = 0;
909 var->green.length = (var->green.length == 5) ? 5 : 6;
911 var->blue.length = 5;
912 var->transp.length = 6 - var->green.length;
913 var->blue.offset = 0;
914 var->green.offset = 5;
915 var->red.offset = 5 + var->green.length;
916 var->transp.offset = (5 + var->red.offset) & 15;
918 case 24: /* RGB 888 */
919 case 32: /* RGBA 8888 */
920 var->red.offset = 16;
922 var->green.offset = 8;
923 var->green.length = 8;
924 var->blue.offset = 0;
925 var->blue.length = 8;
926 var->transp.length = var->bits_per_pixel - 24;
927 var->transp.offset = (var->transp.length) ? 24 : 0;
930 var->red.msb_right = 0;
931 var->green.msb_right = 0;
932 var->blue.msb_right = 0;
933 var->transp.msb_right = 0;
937 * i810_check_params - check if contents in var are valid
938 * @var: pointer to fb_var_screeninfo
939 * @info: pointer to fb_info
942 * This will check if the framebuffer size is sufficient
943 * for the current mode and if the user's monitor has the
944 * required specifications to display the current mode.
946 static int i810_check_params(struct fb_var_screeninfo *var,
947 struct fb_info *info)
949 struct i810fb_par *par = (struct i810fb_par *) info->par;
950 int line_length, vidmem;
951 u32 xres, yres, vxres, vyres;
955 vxres = var->xres_virtual;
956 vyres = var->yres_virtual;
961 line_length = get_line_length(par, vxres,
962 var->bits_per_pixel);
964 vidmem = line_length*vyres;
965 if (vidmem > par->fb.size) {
966 vyres = par->fb.size/line_length;
969 vxres = par->fb.size/vyres;
970 vxres /= var->bits_per_pixel >> 3;
971 line_length = get_line_length(par, vxres,
972 var->bits_per_pixel);
973 vidmem = line_length * yres;
975 printk("i810fb: required video memory, "
976 "%d bytes, for %dx%d-%d (virtual) "
978 vidmem, vxres, vyres,
979 var->bits_per_pixel);
987 switch (var->bits_per_pixel) {
989 info->monspecs.dclkmax = 234000000;
992 info->monspecs.dclkmax = 229000000;
996 info->monspecs.dclkmax = 204000000;
999 info->monspecs.dclkmin = 15000000;
1001 if (fb_validate_mode(var, info)) {
1002 if (fb_get_mode(FB_MAXTIMINGS, 0, var, info)) {
1003 int default_sync = (hsync1-HFMIN)|(hsync2-HFMAX)
1004 |(vsync1-VFMIN)|(vsync2-VFMAX);
1005 printk("i810fb: invalid video mode%s\n",
1007 ". Specifying vsyncN/hsyncN parameters may help");
1014 var->xres_virtual = vxres;
1015 var->yres_virtual = vyres;
1020 * encode_fix - fill up fb_fix_screeninfo structure
1021 * @fix: pointer to fb_fix_screeninfo
1022 * @info: pointer to fb_info
1025 * This will set up parameters that are unmodifiable by the user.
1027 static int encode_fix(struct fb_fix_screeninfo *fix, struct fb_info *info)
1029 struct i810fb_par *par = (struct i810fb_par *) info->par;
1031 memset(fix, 0, sizeof(struct fb_fix_screeninfo));
1033 strcpy(fix->id, "I810");
1034 fix->smem_start = par->fb.physical;
1035 fix->smem_len = par->fb.size;
1036 fix->type = FB_TYPE_PACKED_PIXELS;
1041 switch (info->var.bits_per_pixel) {
1043 fix->visual = FB_VISUAL_PSEUDOCOLOR;
1048 if (info->var.nonstd)
1049 fix->visual = FB_VISUAL_DIRECTCOLOR;
1051 fix->visual = FB_VISUAL_TRUECOLOR;
1057 fix->line_length = par->pitch;
1058 fix->mmio_start = par->mmio_start_phys;
1059 fix->mmio_len = MMIO_SIZE;
1060 fix->accel = FB_ACCEL_I810;
1066 * decode_var - modify par according to contents of var
1067 * @var: pointer to fb_var_screeninfo
1068 * @par: pointer to i810fb_par
1071 * Based on the contents of @var, @par will be dynamically filled up.
1072 * @par contains all information necessary to modify the hardware.
1074 static void decode_var(const struct fb_var_screeninfo *var,
1075 struct i810fb_par *par)
1077 u32 xres, yres, vxres, vyres;
1081 vxres = var->xres_virtual;
1082 vyres = var->yres_virtual;
1084 switch (var->bits_per_pixel) {
1086 par->pixconf = PIXCONF8;
1089 par->blit_bpp = BPP8;
1092 if (var->green.length == 5)
1093 par->pixconf = PIXCONF15;
1095 par->pixconf = PIXCONF16;
1098 par->blit_bpp = BPP16;
1101 par->pixconf = PIXCONF24;
1104 par->blit_bpp = BPP24;
1107 par->pixconf = PIXCONF32;
1110 par->blit_bpp = 3 << 24;
1113 if (var->nonstd && var->bits_per_pixel != 8)
1114 par->pixconf |= 1 << 27;
1116 i810_calc_dclk(var->pixclock, &par->regs.M,
1117 &par->regs.N, &par->regs.P);
1118 i810fb_encode_registers(var, par, xres, yres);
1120 par->watermark = i810_get_watermark(var, par);
1121 par->pitch = get_line_length(par, vxres, var->bits_per_pixel);
1125 * i810fb_getcolreg - gets red, green and blue values of the hardware DAC
1130 * @transp: transparency (alpha)
1131 * @info: pointer to fb_info
1134 * Gets the red, green and blue values of the hardware DAC as pointed by @regno
1135 * and writes them to @red, @green and @blue respectively
1137 static int i810fb_getcolreg(u8 regno, u8 *red, u8 *green, u8 *blue,
1138 u8 *transp, struct fb_info *info)
1140 struct i810fb_par *par = (struct i810fb_par *) info->par;
1141 u8 __iomem *mmio = par->mmio_start_virtual;
1144 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1145 if ((info->var.green.length == 5 && regno > 31) ||
1146 (info->var.green.length == 6 && regno > 63))
1150 temp = i810_readb(PIXCONF1, mmio);
1151 i810_writeb(PIXCONF1, mmio, temp & ~EXTENDED_PALETTE);
1153 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR &&
1154 info->var.green.length == 5)
1155 i810_read_dac(regno * 8, red, green, blue, mmio);
1157 else if (info->fix.visual == FB_VISUAL_DIRECTCOLOR &&
1158 info->var.green.length == 6) {
1161 i810_read_dac(regno * 8, red, &tmp, blue, mmio);
1162 i810_read_dac(regno * 4, &tmp, green, &tmp, mmio);
1165 i810_read_dac(regno, red, green, blue, mmio);
1168 i810_writeb(PIXCONF1, mmio, temp);
1173 /******************************************************************
1174 * Framebuffer device-specific hooks *
1175 ******************************************************************/
1177 static int i810fb_open(struct fb_info *info, int user)
1179 struct i810fb_par *par = (struct i810fb_par *) info->par;
1180 u32 count = atomic_read(&par->use_count);
1183 memset(&par->state, 0, sizeof(struct vgastate));
1184 par->state.flags = VGA_SAVE_CMAP;
1185 par->state.vgabase = par->mmio_start_virtual;
1186 save_vga(&par->state);
1188 i810_save_vga_state(par);
1191 atomic_inc(&par->use_count);
1196 static int i810fb_release(struct fb_info *info, int user)
1198 struct i810fb_par *par = (struct i810fb_par *) info->par;
1201 count = atomic_read(&par->use_count);
1206 i810_restore_vga_state(par);
1207 restore_vga(&par->state);
1210 atomic_dec(&par->use_count);
1216 static int i810fb_setcolreg(unsigned regno, unsigned red, unsigned green,
1217 unsigned blue, unsigned transp,
1218 struct fb_info *info)
1220 struct i810fb_par *par = (struct i810fb_par *) info->par;
1221 u8 __iomem *mmio = par->mmio_start_virtual;
1225 if (regno > 255) return 1;
1227 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1228 if ((info->var.green.length == 5 && regno > 31) ||
1229 (info->var.green.length == 6 && regno > 63))
1233 if (info->var.grayscale)
1234 red = green = blue = (19595 * red + 38470 * green +
1237 temp = i810_readb(PIXCONF1, mmio);
1238 i810_writeb(PIXCONF1, mmio, temp & ~EXTENDED_PALETTE);
1240 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR &&
1241 info->var.green.length == 5) {
1242 for (i = 0; i < 8; i++)
1243 i810_write_dac((u8) (regno * 8) + i, (u8) red,
1244 (u8) green, (u8) blue, mmio);
1245 } else if (info->fix.visual == FB_VISUAL_DIRECTCOLOR &&
1246 info->var.green.length == 6) {
1250 for (i = 0; i < 8; i++)
1251 i810_write_dac((u8) (regno * 8) + i,
1252 (u8) red, (u8) green,
1255 i810_read_dac((u8) (regno*4), &r, &g, &b, mmio);
1256 for (i = 0; i < 4; i++)
1257 i810_write_dac((u8) (regno*4) + i, r, (u8) green,
1259 } else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR) {
1260 i810_write_dac((u8) regno, (u8) red, (u8) green,
1264 i810_writeb(PIXCONF1, mmio, temp);
1267 switch (info->var.bits_per_pixel) {
1269 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1270 if (info->var.green.length == 5)
1271 ((u32 *)info->pseudo_palette)[regno] =
1272 (regno << 10) | (regno << 5) |
1275 ((u32 *)info->pseudo_palette)[regno] =
1276 (regno << 11) | (regno << 5) |
1279 if (info->var.green.length == 5) {
1281 ((u32 *)info->pseudo_palette)[regno] =
1282 ((red & 0xf800) >> 1) |
1283 ((green & 0xf800) >> 6) |
1284 ((blue & 0xf800) >> 11);
1287 ((u32 *)info->pseudo_palette)[regno] =
1289 ((green & 0xf800) >> 5) |
1290 ((blue & 0xf800) >> 11);
1294 case 24: /* RGB 888 */
1295 case 32: /* RGBA 8888 */
1296 if (info->fix.visual == FB_VISUAL_DIRECTCOLOR)
1297 ((u32 *)info->pseudo_palette)[regno] =
1298 (regno << 16) | (regno << 8) |
1301 ((u32 *)info->pseudo_palette)[regno] =
1302 ((red & 0xff00) << 8) |
1304 ((blue & 0xff00) >> 8);
1311 static int i810fb_pan_display(struct fb_var_screeninfo *var,
1312 struct fb_info *info)
1314 struct i810fb_par *par = (struct i810fb_par *) info->par;
1317 total = var->xoffset * par->depth +
1318 var->yoffset * info->fix.line_length;
1319 i810fb_load_front(total, info);
1324 static int i810fb_blank (int blank_mode, struct fb_info *info)
1326 struct i810fb_par *par = (struct i810fb_par *) info->par;
1327 u8 __iomem *mmio = par->mmio_start_virtual;
1328 int mode = 0, pwr, scr_off = 0;
1330 pwr = i810_readl(PWR_CLKC, mmio);
1332 switch (blank_mode) {
1333 case FB_BLANK_UNBLANK:
1338 case FB_BLANK_NORMAL:
1343 case FB_BLANK_VSYNC_SUSPEND:
1348 case FB_BLANK_HSYNC_SUSPEND:
1353 case FB_BLANK_POWERDOWN:
1362 i810_screen_off(mmio, scr_off);
1363 i810_writel(HVSYNC, mmio, mode);
1364 i810_writel(PWR_CLKC, mmio, pwr);
1369 static int i810fb_set_par(struct fb_info *info)
1371 struct i810fb_par *par = (struct i810fb_par *) info->par;
1373 decode_var(&info->var, par);
1374 i810_load_regs(par);
1375 i810_init_cursor(par);
1377 encode_fix(&info->fix, info);
1379 if (info->var.accel_flags && !(par->dev_flags & LOCKUP)) {
1380 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN |
1381 FBINFO_HWACCEL_COPYAREA | FBINFO_HWACCEL_FILLRECT |
1382 FBINFO_HWACCEL_IMAGEBLIT;
1383 info->pixmap.scan_align = 2;
1385 info->pixmap.scan_align = 1;
1386 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1391 static int i810fb_check_var(struct fb_var_screeninfo *var,
1392 struct fb_info *info)
1397 var->vmode &= ~FB_VMODE_MASK;
1398 var->vmode |= FB_VMODE_NONINTERLACED;
1400 if (var->vmode & FB_VMODE_DOUBLE) {
1401 var->vmode &= ~FB_VMODE_MASK;
1402 var->vmode |= FB_VMODE_NONINTERLACED;
1405 i810_round_off(var);
1406 if ((err = i810_check_params(var, info)))
1409 i810fb_fill_var_timings(var);
1410 set_color_bitfields(var);
1414 static int i810fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1416 struct i810fb_par *par = (struct i810fb_par *)info->par;
1417 u8 __iomem *mmio = par->mmio_start_virtual;
1419 if (!(par->dev_flags & USE_HWCUR) || !info->var.accel_flags ||
1420 par->dev_flags & LOCKUP)
1421 return soft_cursor(info, cursor);
1423 if (cursor->image.width > 64 || cursor->image.height > 64)
1426 if ((i810_readl(CURBASE, mmio) & 0xf) != par->cursor_heap.physical) {
1427 i810_init_cursor(par);
1428 cursor->set |= FB_CUR_SETALL;
1431 i810_enable_cursor(mmio, OFF);
1433 if (cursor->set & FB_CUR_SETPOS) {
1436 tmp = (cursor->image.dx - info->var.xoffset) & 0xffff;
1437 tmp |= (cursor->image.dy - info->var.yoffset) << 16;
1438 i810_writel(CURPOS, mmio, tmp);
1441 if (cursor->set & FB_CUR_SETSIZE)
1442 i810_reset_cursor_image(par);
1444 if (cursor->set & FB_CUR_SETCMAP)
1445 i810_load_cursor_colors(cursor->image.fg_color,
1446 cursor->image.bg_color,
1449 if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) {
1450 int size = ((cursor->image.width + 7) >> 3) *
1451 cursor->image.height;
1453 u8 *data = kmalloc(64 * 8, GFP_KERNEL);
1458 switch (cursor->rop) {
1460 for (i = 0; i < size; i++)
1461 data[i] = cursor->image.data[i] ^ cursor->mask[i];
1465 for (i = 0; i < size; i++)
1466 data[i] = cursor->image.data[i] & cursor->mask[i];
1470 i810_load_cursor_image(cursor->image.width,
1471 cursor->image.height, data,
1477 i810_enable_cursor(mmio, ON);
1482 static struct fb_ops i810fb_ops __devinitdata = {
1483 .owner = THIS_MODULE,
1484 .fb_open = i810fb_open,
1485 .fb_release = i810fb_release,
1486 .fb_check_var = i810fb_check_var,
1487 .fb_set_par = i810fb_set_par,
1488 .fb_setcolreg = i810fb_setcolreg,
1489 .fb_blank = i810fb_blank,
1490 .fb_pan_display = i810fb_pan_display,
1491 .fb_fillrect = i810fb_fillrect,
1492 .fb_copyarea = i810fb_copyarea,
1493 .fb_imageblit = i810fb_imageblit,
1494 .fb_cursor = i810fb_cursor,
1495 .fb_sync = i810fb_sync,
1498 /***********************************************************************
1499 * Power Management *
1500 ***********************************************************************/
1501 static int i810fb_suspend(struct pci_dev *dev, pm_message_t state)
1503 struct fb_info *info = pci_get_drvdata(dev);
1504 struct i810fb_par *par = (struct i810fb_par *) info->par;
1505 int blank = 0, prev_state = par->cur_state;
1507 if (state == prev_state)
1510 par->cur_state = state;
1514 blank = VESA_VSYNC_SUSPEND;
1517 blank = VESA_HSYNC_SUSPEND;
1520 blank = VESA_POWERDOWN;
1525 info->fbops->fb_blank(blank, info);
1528 agp_unbind_memory(par->i810_gtt.i810_fb_memory);
1529 agp_unbind_memory(par->i810_gtt.i810_cursor_memory);
1530 pci_disable_device(dev);
1532 pci_save_state(dev);
1533 pci_set_power_state(dev, pci_choose_state(dev, state));
1538 static int i810fb_resume(struct pci_dev *dev)
1540 struct fb_info *info = pci_get_drvdata(dev);
1541 struct i810fb_par *par = (struct i810fb_par *) info->par;
1543 if (par->cur_state == 0)
1546 pci_restore_state(dev);
1547 pci_set_power_state(dev, PCI_D0);
1548 pci_enable_device(dev);
1549 agp_bind_memory(par->i810_gtt.i810_fb_memory,
1551 agp_bind_memory(par->i810_gtt.i810_cursor_memory,
1552 par->cursor_heap.offset);
1554 info->fbops->fb_blank(VESA_NO_BLANKING, info);
1560 /***********************************************************************
1561 * AGP resource allocation *
1562 ***********************************************************************/
1564 static void __devinit i810_fix_pointers(struct i810fb_par *par)
1566 par->fb.physical = par->aperture.physical+(par->fb.offset << 12);
1567 par->fb.virtual = par->aperture.virtual+(par->fb.offset << 12);
1568 par->iring.physical = par->aperture.physical +
1569 (par->iring.offset << 12);
1570 par->iring.virtual = par->aperture.virtual +
1571 (par->iring.offset << 12);
1572 par->cursor_heap.virtual = par->aperture.virtual+
1573 (par->cursor_heap.offset << 12);
1576 static void __devinit i810_fix_offsets(struct i810fb_par *par)
1578 if (vram + 1 > par->aperture.size >> 20)
1579 vram = (par->aperture.size >> 20) - 1;
1580 if (v_offset_default > (par->aperture.size >> 20))
1581 v_offset_default = (par->aperture.size >> 20);
1582 if (vram + v_offset_default + 1 > par->aperture.size >> 20)
1583 v_offset_default = (par->aperture.size >> 20) - (vram + 1);
1585 par->fb.size = vram << 20;
1586 par->fb.offset = v_offset_default << 20;
1587 par->fb.offset >>= 12;
1589 par->iring.offset = par->fb.offset + (par->fb.size >> 12);
1590 par->iring.size = RINGBUFFER_SIZE;
1592 par->cursor_heap.offset = par->iring.offset + (RINGBUFFER_SIZE >> 12);
1593 par->cursor_heap.size = 4096;
1596 static int __devinit i810_alloc_agp_mem(struct fb_info *info)
1598 struct i810fb_par *par = (struct i810fb_par *) info->par;
1600 struct agp_bridge_data *bridge;
1602 i810_fix_offsets(par);
1603 size = par->fb.size + par->iring.size;
1605 if (!(bridge = agp_backend_acquire(par->dev))) {
1606 printk("i810fb_alloc_fbmem: cannot acquire agpgart\n");
1609 if (!(par->i810_gtt.i810_fb_memory =
1610 agp_allocate_memory(bridge, size >> 12, AGP_NORMAL_MEMORY))) {
1611 printk("i810fb_alloc_fbmem: can't allocate framebuffer "
1613 agp_backend_release(bridge);
1616 if (agp_bind_memory(par->i810_gtt.i810_fb_memory,
1618 printk("i810fb_alloc_fbmem: can't bind framebuffer memory\n");
1619 agp_backend_release(bridge);
1623 if (!(par->i810_gtt.i810_cursor_memory =
1624 agp_allocate_memory(bridge, par->cursor_heap.size >> 12,
1625 AGP_PHYSICAL_MEMORY))) {
1626 printk("i810fb_alloc_cursormem: can't allocate"
1628 agp_backend_release(bridge);
1631 if (agp_bind_memory(par->i810_gtt.i810_cursor_memory,
1632 par->cursor_heap.offset)) {
1633 printk("i810fb_alloc_cursormem: cannot bind cursor memory\n");
1634 agp_backend_release(bridge);
1638 par->cursor_heap.physical = par->i810_gtt.i810_cursor_memory->physical;
1640 i810_fix_pointers(par);
1642 agp_backend_release(bridge);
1647 /***************************************************************
1649 ***************************************************************/
1652 * i810_init_monspecs
1653 * @info: pointer to device specific info structure
1656 * Sets the the user monitor's horizontal and vertical
1659 static void __devinit i810_init_monspecs(struct fb_info *info)
1665 if (!info->monspecs.hfmax)
1666 info->monspecs.hfmax = hsync2;
1667 if (!info->monspecs.hfmin)
1668 info->monspecs.hfmin = hsync1;
1669 if (hsync2 < hsync1)
1670 info->monspecs.hfmin = hsync2;
1676 if (IS_DVT && vsync1 < 60)
1678 if (!info->monspecs.vfmax)
1679 info->monspecs.vfmax = vsync2;
1680 if (!info->monspecs.vfmin)
1681 info->monspecs.vfmin = vsync1;
1682 if (vsync2 < vsync1)
1683 info->monspecs.vfmin = vsync2;
1687 * i810_init_defaults - initializes default values to use
1688 * @par: pointer to i810fb_par structure
1689 * @info: pointer to current fb_info structure
1691 static void __devinit i810_init_defaults(struct i810fb_par *par,
1692 struct fb_info *info)
1695 v_offset_default = voffset;
1696 else if (par->aperture.size > 32 * 1024 * 1024)
1697 v_offset_default = 16;
1699 v_offset_default = 8;
1705 par->dev_flags |= HAS_ACCELERATION;
1708 par->dev_flags |= ALWAYS_SYNC;
1714 vyres = (vram << 20)/(xres*bpp >> 3);
1716 par->i810fb_ops = i810fb_ops;
1717 info->var.xres = xres;
1718 info->var.yres = yres;
1719 info->var.yres_virtual = vyres;
1720 info->var.bits_per_pixel = bpp;
1723 info->var.nonstd = 1;
1725 if (par->dev_flags & HAS_ACCELERATION)
1726 info->var.accel_flags = 1;
1728 i810_init_monspecs(info);
1732 * i810_init_device - initialize device
1733 * @par: pointer to i810fb_par structure
1735 static void __devinit i810_init_device(struct i810fb_par *par)
1738 u8 __iomem *mmio = par->mmio_start_virtual;
1740 if (mtrr) set_mtrr(par);
1742 i810_init_cursor(par);
1744 /* mvo: enable external vga-connector (for laptops) */
1746 i810_writel(HVSYNC, mmio, 0);
1747 i810_writel(PWR_CLKC, mmio, 3);
1750 pci_read_config_byte(par->dev, 0x50, ®);
1752 par->mem_freq = (reg) ? 133 : 100;
1756 static int __devinit
1757 i810_allocate_pci_resource(struct i810fb_par *par,
1758 const struct pci_device_id *entry)
1762 if ((err = pci_enable_device(par->dev))) {
1763 printk("i810fb_init: cannot enable device\n");
1766 par->res_flags |= PCI_DEVICE_ENABLED;
1768 if (pci_resource_len(par->dev, 0) > 512 * 1024) {
1769 par->aperture.physical = pci_resource_start(par->dev, 0);
1770 par->aperture.size = pci_resource_len(par->dev, 0);
1771 par->mmio_start_phys = pci_resource_start(par->dev, 1);
1773 par->aperture.physical = pci_resource_start(par->dev, 1);
1774 par->aperture.size = pci_resource_len(par->dev, 1);
1775 par->mmio_start_phys = pci_resource_start(par->dev, 0);
1777 if (!par->aperture.size) {
1778 printk("i810fb_init: device is disabled\n");
1782 if (!request_mem_region(par->aperture.physical,
1784 i810_pci_list[entry->driver_data])) {
1785 printk("i810fb_init: cannot request framebuffer region\n");
1788 par->res_flags |= FRAMEBUFFER_REQ;
1790 par->aperture.virtual = ioremap_nocache(par->aperture.physical,
1791 par->aperture.size);
1792 if (!par->aperture.virtual) {
1793 printk("i810fb_init: cannot remap framebuffer region\n");
1797 if (!request_mem_region(par->mmio_start_phys,
1799 i810_pci_list[entry->driver_data])) {
1800 printk("i810fb_init: cannot request mmio region\n");
1803 par->res_flags |= MMIO_REQ;
1805 par->mmio_start_virtual = ioremap_nocache(par->mmio_start_phys,
1807 if (!par->mmio_start_virtual) {
1808 printk("i810fb_init: cannot remap mmio region\n");
1816 static int __init i810fb_setup(char *options)
1818 char *this_opt, *suffix = NULL;
1820 if (!options || !*options)
1823 while ((this_opt = strsep(&options, ",")) != NULL) {
1824 if (!strncmp(this_opt, "mtrr", 4))
1826 else if (!strncmp(this_opt, "accel", 5))
1828 else if (!strncmp(this_opt, "ext_vga", 7))
1830 else if (!strncmp(this_opt, "sync", 4))
1832 else if (!strncmp(this_opt, "vram:", 5))
1833 vram = (simple_strtoul(this_opt+5, NULL, 0));
1834 else if (!strncmp(this_opt, "voffset:", 8))
1835 voffset = (simple_strtoul(this_opt+8, NULL, 0));
1836 else if (!strncmp(this_opt, "xres:", 5))
1837 xres = simple_strtoul(this_opt+5, NULL, 0);
1838 else if (!strncmp(this_opt, "yres:", 5))
1839 yres = simple_strtoul(this_opt+5, NULL, 0);
1840 else if (!strncmp(this_opt, "vyres:", 6))
1841 vyres = simple_strtoul(this_opt+6, NULL, 0);
1842 else if (!strncmp(this_opt, "bpp:", 4))
1843 bpp = simple_strtoul(this_opt+4, NULL, 0);
1844 else if (!strncmp(this_opt, "hsync1:", 7)) {
1845 hsync1 = simple_strtoul(this_opt+7, &suffix, 0);
1846 if (strncmp(suffix, "H", 1))
1848 } else if (!strncmp(this_opt, "hsync2:", 7)) {
1849 hsync2 = simple_strtoul(this_opt+7, &suffix, 0);
1850 if (strncmp(suffix, "H", 1))
1852 } else if (!strncmp(this_opt, "vsync1:", 7))
1853 vsync1 = simple_strtoul(this_opt+7, NULL, 0);
1854 else if (!strncmp(this_opt, "vsync2:", 7))
1855 vsync2 = simple_strtoul(this_opt+7, NULL, 0);
1856 else if (!strncmp(this_opt, "dcolor", 6))
1863 static int __devinit i810fb_init_pci (struct pci_dev *dev,
1864 const struct pci_device_id *entry)
1866 struct fb_info *info;
1867 struct i810fb_par *par = NULL;
1868 int i, err = -1, vfreq, hfreq, pixclock;
1872 info = framebuffer_alloc(sizeof(struct i810fb_par), &dev->dev);
1876 par = (struct i810fb_par *) info->par;
1879 if (!(info->pixmap.addr = kmalloc(8*1024, GFP_KERNEL))) {
1880 i810fb_release_resource(info, par);
1883 memset(info->pixmap.addr, 0, 8*1024);
1884 info->pixmap.size = 8*1024;
1885 info->pixmap.buf_align = 8;
1886 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1888 if ((err = i810_allocate_pci_resource(par, entry))) {
1889 i810fb_release_resource(info, par);
1893 i810_init_defaults(par, info);
1895 if ((err = i810_alloc_agp_mem(info))) {
1896 i810fb_release_resource(info, par);
1900 i810_init_device(par);
1902 info->screen_base = par->fb.virtual;
1903 info->fbops = &par->i810fb_ops;
1904 info->pseudo_palette = par->pseudo_palette;
1905 fb_alloc_cmap(&info->cmap, 256, 0);
1907 if ((err = info->fbops->fb_check_var(&info->var, info))) {
1908 i810fb_release_resource(info, par);
1911 encode_fix(&info->fix, info);
1913 i810fb_init_ringbuffer(info);
1914 err = register_framebuffer(info);
1916 i810fb_release_resource(info, par);
1917 printk("i810fb_init: cannot register framebuffer device\n");
1921 pci_set_drvdata(dev, info);
1922 pixclock = 1000000000/(info->var.pixclock);
1924 hfreq = pixclock/(info->var.xres + info->var.left_margin +
1925 info->var.hsync_len + info->var.right_margin);
1926 vfreq = hfreq/(info->var.yres + info->var.upper_margin +
1927 info->var.vsync_len + info->var.lower_margin);
1929 printk("I810FB: fb%d : %s v%d.%d.%d%s\n"
1930 "I810FB: Video RAM : %dK\n"
1931 "I810FB: Monitor : H: %d-%d KHz V: %d-%d Hz\n"
1932 "I810FB: Mode : %dx%d-%dbpp@%dHz\n",
1934 i810_pci_list[entry->driver_data],
1935 VERSION_MAJOR, VERSION_MINOR, VERSION_TEENIE, BRANCH_VERSION,
1936 (int) par->fb.size>>10, info->monspecs.hfmin/1000,
1937 info->monspecs.hfmax/1000, info->monspecs.vfmin,
1938 info->monspecs.vfmax, info->var.xres,
1939 info->var.yres, info->var.bits_per_pixel, vfreq);
1943 /***************************************************************
1944 * De-initialization *
1945 ***************************************************************/
1947 static void i810fb_release_resource(struct fb_info *info,
1948 struct i810fb_par *par)
1950 struct gtt_data *gtt = &par->i810_gtt;
1953 if (par->i810_gtt.i810_cursor_memory)
1954 agp_free_memory(gtt->i810_cursor_memory);
1955 if (par->i810_gtt.i810_fb_memory)
1956 agp_free_memory(gtt->i810_fb_memory);
1958 if (par->mmio_start_virtual)
1959 iounmap(par->mmio_start_virtual);
1960 if (par->aperture.virtual)
1961 iounmap(par->aperture.virtual);
1963 if (par->res_flags & FRAMEBUFFER_REQ)
1964 release_mem_region(par->aperture.physical,
1965 par->aperture.size);
1966 if (par->res_flags & MMIO_REQ)
1967 release_mem_region(par->mmio_start_phys, MMIO_SIZE);
1969 if (par->res_flags & PCI_DEVICE_ENABLED)
1970 pci_disable_device(par->dev);
1972 framebuffer_release(info);
1976 static void __exit i810fb_remove_pci(struct pci_dev *dev)
1978 struct fb_info *info = pci_get_drvdata(dev);
1979 struct i810fb_par *par = (struct i810fb_par *) info->par;
1981 unregister_framebuffer(info);
1982 i810fb_release_resource(info, par);
1983 pci_set_drvdata(dev, NULL);
1984 printk("cleanup_module: unloaded i810 framebuffer device\n");
1988 static int __init i810fb_init(void)
1990 char *option = NULL;
1992 if (fb_get_options("i810fb", &option))
1994 i810fb_setup(option);
1996 return pci_register_driver(&i810fb_driver);
2000 /*********************************************************************
2002 *********************************************************************/
2006 static int __init i810fb_init(void)
2011 return pci_register_driver(&i810fb_driver);
2014 module_param(vram, int, 0);
2015 MODULE_PARM_DESC(vram, "System RAM to allocate to framebuffer in MiB"
2017 module_param(voffset, int, 0);
2018 MODULE_PARM_DESC(voffset, "at what offset to place start of framebuffer "
2019 "memory (0 to maximum aperture size), in MiB (default = 48)");
2020 module_param(bpp, int, 0);
2021 MODULE_PARM_DESC(bpp, "Color depth for display in bits per pixel"
2023 module_param(xres, int, 0);
2024 MODULE_PARM_DESC(xres, "Horizontal resolution in pixels (default = 640)");
2025 module_param(yres, int, 0);
2026 MODULE_PARM_DESC(yres, "Vertical resolution in scanlines (default = 480)");
2027 module_param(vyres,int, 0);
2028 MODULE_PARM_DESC(vyres, "Virtual vertical resolution in scanlines"
2029 " (default = 480)");
2030 module_param(hsync1, int, 0);
2031 MODULE_PARM_DESC(hsync1, "Minimum horizontal frequency of monitor in KHz"
2033 module_param(hsync2, int, 0);
2034 MODULE_PARM_DESC(hsync2, "Maximum horizontal frequency of monitor in KHz"
2036 module_param(vsync1, int, 0);
2037 MODULE_PARM_DESC(vsync1, "Minimum vertical frequency of monitor in Hz"
2039 module_param(vsync2, int, 0);
2040 MODULE_PARM_DESC(vsync2, "Maximum vertical frequency of monitor in Hz"
2042 module_param(accel, bool, 0);
2043 MODULE_PARM_DESC(accel, "Use Acceleration (BLIT) engine (default = 0)");
2044 module_param(mtrr, bool, 0);
2045 MODULE_PARM_DESC(mtrr, "Use MTRR (default = 0)");
2046 module_param(ext_vga, bool, 0);
2047 MODULE_PARM_DESC(ext_vga, "Enable external VGA connector (default = 0)");
2048 module_param(sync, bool, 0);
2049 MODULE_PARM_DESC(sync, "wait for accel engine to finish drawing"
2051 module_param(dcolor, bool, 0);
2052 MODULE_PARM_DESC(dcolor, "use DirectColor visuals"
2053 " (default = 0 = TrueColor)");
2055 MODULE_AUTHOR("Tony A. Daplas");
2056 MODULE_DESCRIPTION("Framebuffer device for the Intel 810/815 and"
2057 " compatible cards");
2058 MODULE_LICENSE("GPL");
2060 static void __exit i810fb_exit(void)
2062 pci_unregister_driver(&i810fb_driver);
2064 module_exit(i810fb_exit);
2068 module_init(i810fb_init);