1 /* Geode LX framebuffer driver
3 * Copyright (C) 2006-2007, Advanced Micro Devices,Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
14 #include <linux/uaccess.h>
15 #include <linux/delay.h>
16 #include <asm/geode.h>
21 * Support panel scaling
23 * Add support for interlacing (TV out)
27 /* This is the complete list of PLL frequencies that we can set -
28 * we will choose the closest match to the incoming clock.
29 * freq is the frequency of the dotclock * 1000 (for example,
30 * 24823 = 24.983 Mhz).
31 * pllval is the corresponding PLL value
51 { 0x00010045, 10000 },
52 { 0x00010089, 10791 },
53 { 0x000110E7, 11225 },
54 { 0x00012136, 11430 },
55 { 0x00013207, 12375 },
56 { 0x00012187, 12500 },
57 { 0x00014286, 14063 },
58 { 0x000110E5, 15016 },
59 { 0x00014214, 16250 },
60 { 0x00011105, 17045 },
61 { 0x000131E4, 18563 },
62 { 0x00013183, 18750 },
63 { 0x00014284, 19688 },
64 { 0x00011104, 20400 },
65 { 0x00016363, 23625 },
66 { 0x00015303, 24380 },
67 { 0x000031AC, 24923 },
68 { 0x0000215D, 25175 },
69 { 0x00001087, 27000 },
70 { 0x0000216C, 28322 },
71 { 0x0000218D, 28560 },
72 { 0x00010041, 29913 },
73 { 0x000010C9, 31200 },
74 { 0x00003147, 31500 },
75 { 0x000141A1, 32400 },
76 { 0x000010A7, 33032 },
77 { 0x00012182, 33375 },
78 { 0x000141B1, 33750 },
79 { 0x00002159, 35112 },
80 { 0x00004249, 35500 },
81 { 0x00000057, 36000 },
82 { 0x000141E1, 37125 },
83 { 0x0000219A, 37889 },
84 { 0x00002158, 39168 },
85 { 0x00000045, 40000 },
86 { 0x000131A1, 40500 },
87 { 0x00010061, 42301 },
88 { 0x00000089, 43163 },
89 { 0x00012151, 43875 },
90 { 0x000010E7, 44900 },
91 { 0x00002136, 45720 },
92 { 0x000152E1, 47250 },
93 { 0x00010071, 48000 },
94 { 0x00003207, 49500 },
95 { 0x00002187, 50000 },
96 { 0x00014291, 50625 },
97 { 0x00011101, 51188 },
98 { 0x00017481, 54563 },
99 { 0x00004286, 56250 },
100 { 0x00014170, 57375 },
101 { 0x00016210, 58500 },
102 { 0x000010E5, 60065 },
103 { 0x00013140, 62796 },
104 { 0x00004214, 65000 },
105 { 0x00016250, 65250 },
106 { 0x00001105, 68179 },
107 { 0x000141C0, 69600 },
108 { 0x00015220, 70160 },
109 { 0x00010050, 72000 },
110 { 0x000031E4, 74250 },
111 { 0x00003183, 75000 },
112 { 0x00004284, 78750 },
113 { 0x00012130, 80052 },
114 { 0x00001104, 81600 },
115 { 0x00006363, 94500 },
116 { 0x00005303, 97520 },
117 { 0x00002183, 100187 },
118 { 0x00002122, 101420 },
119 { 0x00001081, 108000 },
120 { 0x00006201, 113310 },
121 { 0x00000041, 119650 },
122 { 0x000041A1, 129600 },
123 { 0x00002182, 133500 },
124 { 0x000041B1, 135000 },
125 { 0x00000051, 144000 },
126 { 0x000041E1, 148500 },
127 { 0x000062D1, 157500 },
128 { 0x000031A1, 162000 },
129 { 0x00000061, 169203 },
130 { 0x00004231, 172800 },
131 { 0x00002151, 175500 },
132 { 0x000052E1, 189000 },
133 { 0x00000071, 192000 },
134 { 0x00003201, 198000 },
135 { 0x00004291, 202500 },
136 { 0x00001101, 204750 },
137 { 0x00007481, 218250 },
138 { 0x00004170, 229500 },
139 { 0x00006210, 234000 },
140 { 0x00003140, 251182 },
141 { 0x00006250, 261000 },
142 { 0x000041C0, 278400 },
143 { 0x00005220, 280640 },
144 { 0x00000050, 288000 },
145 { 0x000041E0, 297000 },
146 { 0x00002130, 320207 }
150 static void lx_set_dotpll(u32 pllval)
152 u32 dotpll_lo, dotpll_hi;
155 rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
157 if ((dotpll_lo & GLCP_DOTPLL_LOCK) && (dotpll_hi == pllval))
161 dotpll_lo &= ~(GLCP_DOTPLL_BYPASS | GLCP_DOTPLL_HALFPIX);
162 dotpll_lo |= GLCP_DOTPLL_RESET;
164 wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
166 /* Wait 100us for the PLL to lock */
170 /* Now, loop for the lock bit */
172 for (i = 0; i < 1000; i++) {
173 rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
174 if (dotpll_lo & GLCP_DOTPLL_LOCK)
178 /* Clear the reset bit */
180 dotpll_lo &= ~GLCP_DOTPLL_RESET;
181 wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
184 /* Set the clock based on the frequency specified by the current mode */
186 static void lx_set_clock(struct fb_info *info)
188 unsigned int diff, min, best = 0;
189 unsigned int freq, i;
191 freq = (unsigned int) (1000000000 / info->var.pixclock);
193 min = abs(pll_table[0].freq - freq);
195 for (i = 0; i < ARRAY_SIZE(pll_table); i++) {
196 diff = abs(pll_table[i].freq - freq);
203 lx_set_dotpll(pll_table[best].pllval & 0x00017FFF);
206 static void lx_graphics_disable(struct fb_info *info)
208 struct lxfb_par *par = info->par;
209 unsigned int val, gcfg;
211 /* Note: This assumes that the video is in a quitet state */
213 write_vp(par, DF_ALPHA_CONTROL_1, 0);
214 write_vp(par, DF_ALPHA_CONTROL_1 + 32, 0);
215 write_vp(par, DF_ALPHA_CONTROL_1 + 64, 0);
217 /* Turn off the VGA and video enable */
218 val = read_dc(par, DC_GENERAL_CFG) & ~(DC_GCFG_VGAE | DC_GCFG_VIDE);
220 write_dc(par, DC_GENERAL_CFG, val);
222 val = read_vp(par, DF_VIDEO_CFG) & ~DF_VCFG_VID_EN;
223 write_vp(par, DF_VIDEO_CFG, val);
225 write_dc(par, DC_IRQ, DC_IRQ_MASK | DC_VSYNC_IRQ_MASK | DC_IRQ_STATUS |
226 DC_VSYNC_IRQ_STATUS);
228 val = read_dc(par, DC_GENLCK_CTRL) & ~DC_GENLCK_ENABLE;
229 write_dc(par, DC_GENLCK_CTRL, val);
231 val = read_dc(par, DC_COLOR_KEY) & ~DC_CLR_KEY_ENABLE;
232 write_dc(par, DC_COLOR_KEY, val & ~DC_CLR_KEY_ENABLE);
234 /* We don't actually blank the panel, due to the long latency
235 involved with bringing it back */
237 val = read_vp(par, DF_MISC) | DF_MISC_DAC_PWRDN;
238 write_vp(par, DF_MISC, val);
240 /* Turn off the display */
242 val = read_vp(par, DF_DISPLAY_CFG);
243 write_vp(par, DF_DISPLAY_CFG, val &
244 ~(DF_DCFG_CRT_EN | DF_DCFG_HSYNC_EN |
245 DF_DCFG_VSYNC_EN | DF_DCFG_DAC_BL_EN));
247 gcfg = read_dc(par, DC_GENERAL_CFG);
248 gcfg &= ~(DC_GCFG_CMPE | DC_GCFG_DECE);
249 write_dc(par, DC_GENERAL_CFG, gcfg);
251 /* Turn off the TGEN */
252 val = read_dc(par, DC_DISPLAY_CFG);
253 val &= ~DC_DCFG_TGEN;
254 write_dc(par, DC_DISPLAY_CFG, val);
256 /* Wait 1000 usecs to ensure that the TGEN is clear */
259 /* Turn off the FIFO loader */
261 gcfg &= ~DC_GCFG_DFLE;
262 write_dc(par, DC_GENERAL_CFG, gcfg);
264 /* Lastly, wait for the GP to go idle */
267 val = read_gp(par, GP_BLT_STATUS);
268 } while ((val & GP_BS_BLT_BUSY) || !(val & GP_BS_CB_EMPTY));
271 static void lx_graphics_enable(struct fb_info *info)
273 struct lxfb_par *par = info->par;
276 /* Set the video request register */
277 write_vp(par, DF_VIDEO_REQUEST, 0);
279 /* Set up the polarities */
281 config = read_vp(par, DF_DISPLAY_CFG);
283 config &= ~(DF_DCFG_CRT_SYNC_SKW_MASK | DF_DCFG_PWR_SEQ_DLY_MASK |
284 DF_DCFG_CRT_HSYNC_POL | DF_DCFG_CRT_VSYNC_POL);
286 config |= (DF_DCFG_CRT_SYNC_SKW_INIT | DF_DCFG_PWR_SEQ_DLY_INIT |
289 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
290 config |= DF_DCFG_CRT_HSYNC_POL;
292 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
293 config |= DF_DCFG_CRT_VSYNC_POL;
295 if (par->output & OUTPUT_PANEL) {
298 write_fp(par, DF_PANEL_TIM1, DF_DEFAULT_TFT_PMTIM1);
299 write_fp(par, DF_PANEL_TIM2, DF_DEFAULT_TFT_PMTIM2);
300 write_fp(par, DF_DITHER_CONTROL, DF_DEFAULT_TFT_DITHCTL);
302 msrlo = DF_DEFAULT_TFT_PAD_SEL_LOW;
303 msrhi = DF_DEFAULT_TFT_PAD_SEL_HIGH;
305 wrmsr(MSR_LX_MSR_PADSEL, msrlo, msrhi);
308 if (par->output & OUTPUT_CRT) {
309 config |= DF_DCFG_CRT_EN | DF_DCFG_HSYNC_EN |
310 DF_DCFG_VSYNC_EN | DF_DCFG_DAC_BL_EN;
313 write_vp(par, DF_DISPLAY_CFG, config);
315 /* Turn the CRT dacs back on */
317 if (par->output & OUTPUT_CRT) {
318 temp = read_vp(par, DF_MISC);
319 temp &= ~(DF_MISC_DAC_PWRDN | DF_MISC_A_PWRDN);
320 write_vp(par, DF_MISC, temp);
323 /* Turn the panel on (if it isn't already) */
325 if (par->output & OUTPUT_PANEL) {
326 temp = read_fp(par, DF_FP_PM);
329 write_fp(par, DF_FP_PM, temp | DF_FP_PM_P);
333 unsigned int lx_framebuffer_size(void)
337 /* The frame buffer size is reported by a VSM in VSA II */
338 /* Virtual Register Class = 0x02 */
339 /* VG_MEM_SIZE (1MB units) = 0x00 */
341 outw(0xFC53, 0xAC1C);
342 outw(0x0200, 0xAC1C);
344 val = (unsigned int)(inw(0xAC1E)) & 0xFE;
348 void lx_set_mode(struct fb_info *info)
350 struct lxfb_par *par = info->par;
353 unsigned int max, dv, val, size;
355 unsigned int gcfg, dcfg;
356 int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
357 int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
359 /* Unlock the DC registers */
360 write_dc(par, DC_UNLOCK, DC_UNLOCK_CODE);
362 lx_graphics_disable(info);
366 /* Set output mode */
368 rdmsrl(MSR_LX_GLD_MSR_CONFIG, msrval);
369 msrval &= ~DF_CONFIG_OUTPUT_MASK;
371 if (par->output & OUTPUT_PANEL) {
372 msrval |= DF_OUTPUT_PANEL;
374 if (par->output & OUTPUT_CRT)
375 msrval |= DF_SIMULTANEOUS_CRT_AND_FP;
377 msrval &= ~DF_SIMULTANEOUS_CRT_AND_FP;
379 msrval |= DF_OUTPUT_CRT;
382 wrmsrl(MSR_LX_GLD_MSR_CONFIG, msrval);
384 /* Clear the various buffers */
385 /* FIXME: Adjust for panning here */
387 write_dc(par, DC_FB_START, 0);
388 write_dc(par, DC_CB_START, 0);
389 write_dc(par, DC_CURSOR_START, 0);
391 /* FIXME: Add support for interlacing */
392 /* FIXME: Add support for scaling */
394 val = read_dc(par, DC_GENLCK_CTRL);
395 val &= ~(DC_GC_ALPHA_FLICK_ENABLE |
396 DC_GC_FLICKER_FILTER_ENABLE | DC_GC_FLICKER_FILTER_MASK);
398 /* Default scaling params */
400 write_dc(par, DC_GFX_SCALE, (0x4000 << 16) | 0x4000);
401 write_dc(par, DC_IRQ_FILT_CTL, 0);
402 write_dc(par, DC_GENLCK_CTRL, val);
404 /* FIXME: Support compression */
406 if (info->fix.line_length > 4096)
407 dv = DC_DV_LINE_SIZE_8192;
408 else if (info->fix.line_length > 2048)
409 dv = DC_DV_LINE_SIZE_4096;
410 else if (info->fix.line_length > 1024)
411 dv = DC_DV_LINE_SIZE_2048;
413 dv = DC_DV_LINE_SIZE_1024;
415 max = info->fix.line_length * info->var.yres;
416 max = (max + 0x3FF) & 0xFFFFFC00;
418 write_dc(par, DC_DV_TOP, max | DC_DV_TOP_ENABLE);
420 val = read_dc(par, DC_DV_CTL) & ~DC_DV_LINE_SIZE_MASK;
421 write_dc(par, DC_DV_CTL, val | dv);
423 size = info->var.xres * (info->var.bits_per_pixel >> 3);
425 write_dc(par, DC_GRAPHICS_PITCH, info->fix.line_length >> 3);
426 write_dc(par, DC_LINE_SIZE, (size + 7) >> 3);
428 /* Set default watermark values */
430 rdmsrl(MSR_LX_SPARE_MSR, msrval);
432 msrval &= ~(DC_SPARE_DISABLE_CFIFO_HGO | DC_SPARE_VFIFO_ARB_SELECT |
433 DC_SPARE_LOAD_WM_LPEN_MASK | DC_SPARE_WM_LPEN_OVRD |
434 DC_SPARE_DISABLE_INIT_VID_PRI | DC_SPARE_DISABLE_VFIFO_WM);
435 msrval |= DC_SPARE_DISABLE_VFIFO_WM | DC_SPARE_DISABLE_INIT_VID_PRI;
436 wrmsrl(MSR_LX_SPARE_MSR, msrval);
438 gcfg = DC_GCFG_DFLE; /* Display fifo enable */
439 gcfg |= 0xB600; /* Set default priority */
440 gcfg |= DC_GCFG_FDTY; /* Set the frame dirty mode */
442 dcfg = DC_DCFG_VDEN; /* Enable video data */
443 dcfg |= DC_DCFG_GDEN; /* Enable graphics */
444 dcfg |= DC_DCFG_TGEN; /* Turn on the timing generator */
445 dcfg |= DC_DCFG_TRUP; /* Update timings immediately */
446 dcfg |= DC_DCFG_PALB; /* Palette bypass in > 8 bpp modes */
447 dcfg |= DC_DCFG_VISL;
448 dcfg |= DC_DCFG_DCEN; /* Always center the display */
450 /* Set the current BPP mode */
452 switch (info->var.bits_per_pixel) {
454 dcfg |= DC_DCFG_DISP_MODE_8BPP;
458 dcfg |= DC_DCFG_DISP_MODE_16BPP | DC_DCFG_16BPP;
463 dcfg |= DC_DCFG_DISP_MODE_24BPP;
467 /* Now - set up the timings */
469 hactive = info->var.xres;
470 hblankstart = hactive;
471 hsyncstart = hblankstart + info->var.right_margin;
472 hsyncend = hsyncstart + info->var.hsync_len;
473 hblankend = hsyncend + info->var.left_margin;
476 vactive = info->var.yres;
477 vblankstart = vactive;
478 vsyncstart = vblankstart + info->var.lower_margin;
479 vsyncend = vsyncstart + info->var.vsync_len;
480 vblankend = vsyncend + info->var.upper_margin;
483 write_dc(par, DC_H_ACTIVE_TIMING, (hactive - 1) | ((htotal - 1) << 16));
484 write_dc(par, DC_H_BLANK_TIMING,
485 (hblankstart - 1) | ((hblankend - 1) << 16));
486 write_dc(par, DC_H_SYNC_TIMING,
487 (hsyncstart - 1) | ((hsyncend - 1) << 16));
489 write_dc(par, DC_V_ACTIVE_TIMING, (vactive - 1) | ((vtotal - 1) << 16));
490 write_dc(par, DC_V_BLANK_TIMING,
491 (vblankstart - 1) | ((vblankend - 1) << 16));
492 write_dc(par, DC_V_SYNC_TIMING,
493 (vsyncstart - 1) | ((vsyncend - 1) << 16));
495 write_dc(par, DC_FB_ACTIVE,
496 (info->var.xres - 1) << 16 | (info->var.yres - 1));
498 /* And re-enable the graphics output */
499 lx_graphics_enable(info);
501 /* Write the two main configuration registers */
502 write_dc(par, DC_DISPLAY_CFG, dcfg);
503 write_dc(par, DC_ARB_CFG, 0);
504 write_dc(par, DC_GENERAL_CFG, gcfg);
506 /* Lock the DC registers */
507 write_dc(par, DC_UNLOCK, 0);
510 void lx_set_palette_reg(struct fb_info *info, unsigned regno,
511 unsigned red, unsigned green, unsigned blue)
513 struct lxfb_par *par = info->par;
516 /* Hardware palette is in RGB 8-8-8 format. */
518 val = (red << 8) & 0xff0000;
519 val |= (green) & 0x00ff00;
520 val |= (blue >> 8) & 0x0000ff;
522 write_dc(par, DC_PAL_ADDRESS, regno);
523 write_dc(par, DC_PAL_DATA, val);
526 int lx_blank_display(struct fb_info *info, int blank_mode)
528 struct lxfb_par *par = info->par;
530 int blank, hsync, vsync;
532 /* CRT power saving modes. */
533 switch (blank_mode) {
534 case FB_BLANK_UNBLANK:
535 blank = 0; hsync = 1; vsync = 1;
537 case FB_BLANK_NORMAL:
538 blank = 1; hsync = 1; vsync = 1;
540 case FB_BLANK_VSYNC_SUSPEND:
541 blank = 1; hsync = 1; vsync = 0;
543 case FB_BLANK_HSYNC_SUSPEND:
544 blank = 1; hsync = 0; vsync = 1;
546 case FB_BLANK_POWERDOWN:
547 blank = 1; hsync = 0; vsync = 0;
553 dcfg = read_vp(par, DF_DISPLAY_CFG);
554 dcfg &= ~(DF_DCFG_DAC_BL_EN
555 | DF_DCFG_HSYNC_EN | DF_DCFG_VSYNC_EN);
557 dcfg |= DF_DCFG_DAC_BL_EN;
559 dcfg |= DF_DCFG_HSYNC_EN;
561 dcfg |= DF_DCFG_VSYNC_EN;
562 write_vp(par, DF_DISPLAY_CFG, dcfg);
564 /* Power on/off flat panel */
566 if (par->output & OUTPUT_PANEL) {
567 fp_pm = read_fp(par, DF_FP_PM);
568 if (blank_mode == FB_BLANK_POWERDOWN)
569 fp_pm &= ~DF_FP_PM_P;
572 write_fp(par, DF_FP_PM, fp_pm);