1 /* Geode LX framebuffer driver
3 * Copyright (C) 2006-2007, Advanced Micro Devices,Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
11 #include <linux/kernel.h>
12 #include <linux/errno.h>
14 #include <linux/uaccess.h>
15 #include <linux/delay.h>
16 #include <asm/geode.h>
21 * Support panel scaling
23 * Add support for interlacing (TV out)
27 /* This is the complete list of PLL frequencies that we can set -
28 * we will choose the closest match to the incoming clock.
29 * freq is the frequency of the dotclock * 1000 (for example,
30 * 24823 = 24.983 Mhz).
31 * pllval is the corresponding PLL value
51 { 0x00010045, 10000 },
52 { 0x00010089, 10791 },
53 { 0x000110E7, 11225 },
54 { 0x00012136, 11430 },
55 { 0x00013207, 12375 },
56 { 0x00012187, 12500 },
57 { 0x00014286, 14063 },
58 { 0x000110E5, 15016 },
59 { 0x00014214, 16250 },
60 { 0x00011105, 17045 },
61 { 0x000131E4, 18563 },
62 { 0x00013183, 18750 },
63 { 0x00014284, 19688 },
64 { 0x00011104, 20400 },
65 { 0x00016363, 23625 },
66 { 0x00015303, 24380 },
67 { 0x000031AC, 24923 },
68 { 0x0000215D, 25175 },
69 { 0x00001087, 27000 },
70 { 0x0000216C, 28322 },
71 { 0x0000218D, 28560 },
72 { 0x00010041, 29913 },
73 { 0x000010C9, 31200 },
74 { 0x00003147, 31500 },
75 { 0x000141A1, 32400 },
76 { 0x000010A7, 33032 },
77 { 0x00012182, 33375 },
78 { 0x000141B1, 33750 },
79 { 0x00002159, 35112 },
80 { 0x00004249, 35500 },
81 { 0x00000057, 36000 },
82 { 0x000141E1, 37125 },
83 { 0x0000219A, 37889 },
84 { 0x00002158, 39168 },
85 { 0x00000045, 40000 },
86 { 0x000131A1, 40500 },
87 { 0x00010061, 42301 },
88 { 0x00000089, 43163 },
89 { 0x00012151, 43875 },
90 { 0x000010E7, 44900 },
91 { 0x00002136, 45720 },
92 { 0x000152E1, 47250 },
93 { 0x00010071, 48000 },
94 { 0x00003207, 49500 },
95 { 0x00002187, 50000 },
96 { 0x00014291, 50625 },
97 { 0x00011101, 51188 },
98 { 0x00017481, 54563 },
99 { 0x00004286, 56250 },
100 { 0x00014170, 57375 },
101 { 0x00016210, 58500 },
102 { 0x000010E5, 60065 },
103 { 0x00013140, 62796 },
104 { 0x00004214, 65000 },
105 { 0x00016250, 65250 },
106 { 0x00001105, 68179 },
107 { 0x000141C0, 69600 },
108 { 0x00015220, 70160 },
109 { 0x00010050, 72000 },
110 { 0x000031E4, 74250 },
111 { 0x00003183, 75000 },
112 { 0x00004284, 78750 },
113 { 0x00012130, 80052 },
114 { 0x00001104, 81600 },
115 { 0x00006363, 94500 },
116 { 0x00005303, 97520 },
117 { 0x00002183, 100187 },
118 { 0x00002122, 101420 },
119 { 0x00001081, 108000 },
120 { 0x00006201, 113310 },
121 { 0x00000041, 119650 },
122 { 0x000041A1, 129600 },
123 { 0x00002182, 133500 },
124 { 0x000041B1, 135000 },
125 { 0x00000051, 144000 },
126 { 0x000041E1, 148500 },
127 { 0x000062D1, 157500 },
128 { 0x000031A1, 162000 },
129 { 0x00000061, 169203 },
130 { 0x00004231, 172800 },
131 { 0x00002151, 175500 },
132 { 0x000052E1, 189000 },
133 { 0x00000071, 192000 },
134 { 0x00003201, 198000 },
135 { 0x00004291, 202500 },
136 { 0x00001101, 204750 },
137 { 0x00007481, 218250 },
138 { 0x00004170, 229500 },
139 { 0x00006210, 234000 },
140 { 0x00003140, 251182 },
141 { 0x00006250, 261000 },
142 { 0x000041C0, 278400 },
143 { 0x00005220, 280640 },
144 { 0x00000050, 288000 },
145 { 0x000041E0, 297000 },
146 { 0x00002130, 320207 }
150 static void lx_set_dotpll(u32 pllval)
152 u32 dotpll_lo, dotpll_hi;
155 rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
157 if ((dotpll_lo & GLCP_DOTPLL_LOCK) && (dotpll_hi == pllval))
161 dotpll_lo &= ~(GLCP_DOTPLL_BYPASS | GLCP_DOTPLL_HALFPIX);
162 dotpll_lo |= GLCP_DOTPLL_RESET;
164 wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
166 /* Wait 100us for the PLL to lock */
170 /* Now, loop for the lock bit */
172 for (i = 0; i < 1000; i++) {
173 rdmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
174 if (dotpll_lo & GLCP_DOTPLL_LOCK)
178 /* Clear the reset bit */
180 dotpll_lo &= ~GLCP_DOTPLL_RESET;
181 wrmsr(MSR_GLCP_DOTPLL, dotpll_lo, dotpll_hi);
184 /* Set the clock based on the frequency specified by the current mode */
186 static void lx_set_clock(struct fb_info *info)
188 unsigned int diff, min, best = 0;
189 unsigned int freq, i;
191 freq = (unsigned int) (1000000000 / info->var.pixclock);
193 min = abs(pll_table[0].freq - freq);
195 for (i = 0; i < ARRAY_SIZE(pll_table); i++) {
196 diff = abs(pll_table[i].freq - freq);
203 lx_set_dotpll(pll_table[best].pllval & 0x00017FFF);
206 static void lx_graphics_disable(struct fb_info *info)
208 struct lxfb_par *par = info->par;
209 unsigned int val, gcfg;
211 /* Note: This assumes that the video is in a quitet state */
213 writel(0, par->df_regs + DF_ALPHA_CONTROL_1);
214 writel(0, par->df_regs + DF_ALPHA_CONTROL_1 + 32);
215 writel(0, par->df_regs + DF_ALPHA_CONTROL_1 + 64);
217 /* Turn off the VGA and video enable */
218 val = readl (par->dc_regs + DC_GENERAL_CFG) &
219 ~(DC_GCFG_VGAE | DC_GCFG_VIDE);
221 writel(val, par->dc_regs + DC_GENERAL_CFG);
223 val = readl(par->df_regs + DF_VIDEO_CFG) & ~DF_VCFG_VID_EN;
224 writel(val, par->df_regs + DF_VIDEO_CFG);
226 writel( DC_IRQ_MASK | DC_VSYNC_IRQ_MASK |
227 DC_IRQ_STATUS | DC_VSYNC_IRQ_STATUS,
228 par->dc_regs + DC_IRQ);
230 val = readl(par->dc_regs + DC_GENLCK_CTRL) & ~DC_GENLCK_ENABLE;
231 writel(val, par->dc_regs + DC_GENLCK_CTRL);
233 val = readl(par->dc_regs + DC_COLOR_KEY) & ~DC_CLR_KEY_ENABLE;
234 writel(val & ~DC_CLR_KEY_ENABLE, par->dc_regs + DC_COLOR_KEY);
236 /* We don't actually blank the panel, due to the long latency
237 involved with bringing it back */
239 val = readl(par->df_regs + DF_MISC) | DF_MISC_DAC_PWRDN;
240 writel(val, par->df_regs + DF_MISC);
242 /* Turn off the display */
244 val = readl(par->df_regs + DF_DISPLAY_CFG);
245 writel(val & ~(DF_DCFG_CRT_EN | DF_DCFG_HSYNC_EN | DF_DCFG_VSYNC_EN |
246 DF_DCFG_DAC_BL_EN), par->df_regs + DF_DISPLAY_CFG);
248 gcfg = readl(par->dc_regs + DC_GENERAL_CFG);
249 gcfg &= ~(DC_GCFG_CMPE | DC_GCFG_DECE);
250 writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
252 /* Turn off the TGEN */
253 val = readl(par->dc_regs + DC_DISPLAY_CFG);
254 val &= ~DC_DCFG_TGEN;
255 writel(val, par->dc_regs + DC_DISPLAY_CFG);
257 /* Wait 1000 usecs to ensure that the TGEN is clear */
260 /* Turn off the FIFO loader */
262 gcfg &= ~DC_GCFG_DFLE;
263 writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
265 /* Lastly, wait for the GP to go idle */
268 val = readl(par->gp_regs + GP_BLT_STATUS);
269 } while ((val & GP_BS_BLT_BUSY) || !(val & GP_BS_CB_EMPTY));
272 static void lx_graphics_enable(struct fb_info *info)
274 struct lxfb_par *par = info->par;
277 /* Set the video request register */
278 writel(0, par->df_regs + DF_VIDEO_REQUEST);
280 /* Set up the polarities */
282 config = readl(par->df_regs + DF_DISPLAY_CFG);
284 config &= ~(DF_DCFG_CRT_SYNC_SKW_MASK | DF_DCFG_PWR_SEQ_DLY_MASK |
285 DF_DCFG_CRT_HSYNC_POL | DF_DCFG_CRT_VSYNC_POL);
287 config |= (DF_DCFG_CRT_SYNC_SKW_INIT | DF_DCFG_PWR_SEQ_DLY_INIT |
290 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
291 config |= DF_DCFG_CRT_HSYNC_POL;
293 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
294 config |= DF_DCFG_CRT_VSYNC_POL;
296 if (par->output & OUTPUT_PANEL) {
299 writel(DF_DEFAULT_TFT_PMTIM1,
300 par->df_regs + DF_PANEL_TIM1);
301 writel(DF_DEFAULT_TFT_PMTIM2,
302 par->df_regs + DF_PANEL_TIM2);
303 writel(DF_DEFAULT_TFT_DITHCTL,
304 par->df_regs + DF_DITHER_CONTROL);
306 msrlo = DF_DEFAULT_TFT_PAD_SEL_LOW;
307 msrhi = DF_DEFAULT_TFT_PAD_SEL_HIGH;
309 wrmsr(MSR_LX_MSR_PADSEL, msrlo, msrhi);
312 if (par->output & OUTPUT_CRT) {
313 config |= DF_DCFG_CRT_EN | DF_DCFG_HSYNC_EN |
314 DF_DCFG_VSYNC_EN | DF_DCFG_DAC_BL_EN;
317 writel(config, par->df_regs + DF_DISPLAY_CFG);
319 /* Turn the CRT dacs back on */
321 if (par->output & OUTPUT_CRT) {
322 temp = readl(par->df_regs + DF_MISC);
323 temp &= ~(DF_MISC_DAC_PWRDN | DF_MISC_A_PWRDN);
324 writel(temp, par->df_regs + DF_MISC);
327 /* Turn the panel on (if it isn't already) */
329 if (par->output & OUTPUT_PANEL) {
330 temp = readl(par->df_regs + DF_FP_PM);
333 writel(temp | DF_FP_PM_P, par->df_regs + DF_FP_PM);
336 temp = readl(par->df_regs + DF_MISC);
337 temp = readl(par->df_regs + DF_DISPLAY_CFG);
340 unsigned int lx_framebuffer_size(void)
344 /* The frame buffer size is reported by a VSM in VSA II */
345 /* Virtual Register Class = 0x02 */
346 /* VG_MEM_SIZE (1MB units) = 0x00 */
348 outw(0xFC53, 0xAC1C);
349 outw(0x0200, 0xAC1C);
351 val = (unsigned int)(inw(0xAC1E)) & 0xFE;
355 void lx_set_mode(struct fb_info *info)
357 struct lxfb_par *par = info->par;
360 unsigned int max, dv, val, size;
362 unsigned int gcfg, dcfg;
363 int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
364 int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
366 /* Unlock the DC registers */
367 writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK);
369 lx_graphics_disable(info);
373 /* Set output mode */
375 rdmsrl(MSR_LX_GLD_MSR_CONFIG, msrval);
376 msrval &= ~DF_CONFIG_OUTPUT_MASK;
378 if (par->output & OUTPUT_PANEL) {
379 msrval |= DF_OUTPUT_PANEL;
381 if (par->output & OUTPUT_CRT)
382 msrval |= DF_SIMULTANEOUS_CRT_AND_FP;
384 msrval &= ~DF_SIMULTANEOUS_CRT_AND_FP;
386 msrval |= DF_OUTPUT_CRT;
389 wrmsrl(MSR_LX_GLD_MSR_CONFIG, msrval);
391 /* Clear the various buffers */
392 /* FIXME: Adjust for panning here */
394 writel(0, par->dc_regs + DC_FB_START);
395 writel(0, par->dc_regs + DC_CB_START);
396 writel(0, par->dc_regs + DC_CURSOR_START);
398 /* FIXME: Add support for interlacing */
399 /* FIXME: Add support for scaling */
401 val = readl(par->dc_regs + DC_GENLCK_CTRL);
402 val &= ~(DC_GC_ALPHA_FLICK_ENABLE |
403 DC_GC_FLICKER_FILTER_ENABLE | DC_GC_FLICKER_FILTER_MASK);
405 /* Default scaling params */
407 writel((0x4000 << 16) | 0x4000, par->dc_regs + DC_GFX_SCALE);
408 writel(0, par->dc_regs + DC_IRQ_FILT_CTL);
409 writel(val, par->dc_regs + DC_GENLCK_CTRL);
411 /* FIXME: Support compression */
413 if (info->fix.line_length > 4096)
414 dv = DC_DV_LINE_SIZE_8192;
415 else if (info->fix.line_length > 2048)
416 dv = DC_DV_LINE_SIZE_4096;
417 else if (info->fix.line_length > 1024)
418 dv = DC_DV_LINE_SIZE_2048;
420 dv = DC_DV_LINE_SIZE_1024;
422 max = info->fix.line_length * info->var.yres;
423 max = (max + 0x3FF) & 0xFFFFFC00;
425 writel(max | DC_DV_TOP_ENABLE, par->dc_regs + DC_DV_TOP);
427 val = readl(par->dc_regs + DC_DV_CTL) & ~DC_DV_LINE_SIZE_MASK;
428 writel(val | dv, par->dc_regs + DC_DV_CTL);
430 size = info->var.xres * (info->var.bits_per_pixel >> 3);
432 writel(info->fix.line_length >> 3, par->dc_regs + DC_GRAPHICS_PITCH);
433 writel((size + 7) >> 3, par->dc_regs + DC_LINE_SIZE);
435 /* Set default watermark values */
437 rdmsrl(MSR_LX_SPARE_MSR, msrval);
439 msrval &= ~(DC_SPARE_DISABLE_CFIFO_HGO | DC_SPARE_VFIFO_ARB_SELECT |
440 DC_SPARE_LOAD_WM_LPEN_MASK | DC_SPARE_WM_LPEN_OVRD |
441 DC_SPARE_DISABLE_INIT_VID_PRI | DC_SPARE_DISABLE_VFIFO_WM);
442 msrval |= DC_SPARE_DISABLE_VFIFO_WM | DC_SPARE_DISABLE_INIT_VID_PRI;
443 wrmsrl(MSR_LX_SPARE_MSR, msrval);
445 gcfg = DC_GCFG_DFLE; /* Display fifo enable */
446 gcfg |= 0xB600; /* Set default priority */
447 gcfg |= DC_GCFG_FDTY; /* Set the frame dirty mode */
449 dcfg = DC_DCFG_VDEN; /* Enable video data */
450 dcfg |= DC_DCFG_GDEN; /* Enable graphics */
451 dcfg |= DC_DCFG_TGEN; /* Turn on the timing generator */
452 dcfg |= DC_DCFG_TRUP; /* Update timings immediately */
453 dcfg |= DC_DCFG_PALB; /* Palette bypass in > 8 bpp modes */
454 dcfg |= DC_DCFG_VISL;
455 dcfg |= DC_DCFG_DCEN; /* Always center the display */
457 /* Set the current BPP mode */
459 switch (info->var.bits_per_pixel) {
461 dcfg |= DC_DCFG_DISP_MODE_8BPP;
465 dcfg |= DC_DCFG_DISP_MODE_16BPP | DC_DCFG_16BPP;
470 dcfg |= DC_DCFG_DISP_MODE_24BPP;
474 /* Now - set up the timings */
476 hactive = info->var.xres;
477 hblankstart = hactive;
478 hsyncstart = hblankstart + info->var.right_margin;
479 hsyncend = hsyncstart + info->var.hsync_len;
480 hblankend = hsyncend + info->var.left_margin;
483 vactive = info->var.yres;
484 vblankstart = vactive;
485 vsyncstart = vblankstart + info->var.lower_margin;
486 vsyncend = vsyncstart + info->var.vsync_len;
487 vblankend = vsyncend + info->var.upper_margin;
490 writel((hactive - 1) | ((htotal - 1) << 16),
491 par->dc_regs + DC_H_ACTIVE_TIMING);
492 writel((hblankstart - 1) | ((hblankend - 1) << 16),
493 par->dc_regs + DC_H_BLANK_TIMING);
494 writel((hsyncstart - 1) | ((hsyncend - 1) << 16),
495 par->dc_regs + DC_H_SYNC_TIMING);
497 writel((vactive - 1) | ((vtotal - 1) << 16),
498 par->dc_regs + DC_V_ACTIVE_TIMING);
500 writel((vblankstart - 1) | ((vblankend - 1) << 16),
501 par->dc_regs + DC_V_BLANK_TIMING);
503 writel((vsyncstart - 1) | ((vsyncend - 1) << 16),
504 par->dc_regs + DC_V_SYNC_TIMING);
506 writel( (info->var.xres - 1) << 16 | (info->var.yres - 1),
507 par->dc_regs + DC_FB_ACTIVE);
509 /* And re-enable the graphics output */
510 lx_graphics_enable(info);
512 /* Write the two main configuration registers */
513 writel(dcfg, par->dc_regs + DC_DISPLAY_CFG);
514 writel(0, par->dc_regs + DC_ARB_CFG);
515 writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
517 /* Lock the DC registers */
518 writel(0, par->dc_regs + DC_UNLOCK);
521 void lx_set_palette_reg(struct fb_info *info, unsigned regno,
522 unsigned red, unsigned green, unsigned blue)
524 struct lxfb_par *par = info->par;
527 /* Hardware palette is in RGB 8-8-8 format. */
529 val = (red << 8) & 0xff0000;
530 val |= (green) & 0x00ff00;
531 val |= (blue >> 8) & 0x0000ff;
533 writel(regno, par->dc_regs + DC_PAL_ADDRESS);
534 writel(val, par->dc_regs + DC_PAL_DATA);
537 int lx_blank_display(struct fb_info *info, int blank_mode)
539 struct lxfb_par *par = info->par;
541 int blank, hsync, vsync;
543 /* CRT power saving modes. */
544 switch (blank_mode) {
545 case FB_BLANK_UNBLANK:
546 blank = 0; hsync = 1; vsync = 1;
548 case FB_BLANK_NORMAL:
549 blank = 1; hsync = 1; vsync = 1;
551 case FB_BLANK_VSYNC_SUSPEND:
552 blank = 1; hsync = 1; vsync = 0;
554 case FB_BLANK_HSYNC_SUSPEND:
555 blank = 1; hsync = 0; vsync = 1;
557 case FB_BLANK_POWERDOWN:
558 blank = 1; hsync = 0; vsync = 0;
564 dcfg = readl(par->df_regs + DF_DISPLAY_CFG);
565 dcfg &= ~(DF_DCFG_DAC_BL_EN
566 | DF_DCFG_HSYNC_EN | DF_DCFG_VSYNC_EN);
568 dcfg |= DF_DCFG_DAC_BL_EN;
570 dcfg |= DF_DCFG_HSYNC_EN;
572 dcfg |= DF_DCFG_VSYNC_EN;
573 writel(dcfg, par->df_regs + DF_DISPLAY_CFG);
575 /* Power on/off flat panel */
577 if (par->output & OUTPUT_PANEL) {
578 fp_pm = readl(par->df_regs + DF_FP_PM);
579 if (blank_mode == FB_BLANK_POWERDOWN)
580 fp_pm &= ~DF_FP_PM_P;
583 writel(fp_pm, par->df_regs + DF_FP_PM);