6 #define OUTPUT_CRT 0x01
7 #define OUTPUT_PANEL 0x02
14 void __iomem *gp_regs;
15 void __iomem *dc_regs;
16 void __iomem *df_regs;
19 static inline unsigned int lx_get_pitch(unsigned int xres, int bpp)
21 return (((xres * (bpp >> 3)) + 7) & ~7);
24 void lx_set_mode(struct fb_info *);
25 void lx_get_gamma(struct fb_info *, unsigned int *, int);
26 void lx_set_gamma(struct fb_info *, unsigned int *, int);
27 unsigned int lx_framebuffer_size(void);
28 int lx_blank_display(struct fb_info *, int);
29 void lx_set_palette_reg(struct fb_info *, unsigned int, unsigned int,
30 unsigned int, unsigned int);
34 #define GLCP_DOTPLL_RESET (1 << 0)
35 #define GLCP_DOTPLL_BYPASS (1 << 15)
36 #define GLCP_DOTPLL_HALFPIX (1 << 24)
37 #define GLCP_DOTPLL_LOCK (1 << 25)
39 #define DF_CONFIG_OUTPUT_MASK 0x38
40 #define DF_OUTPUT_PANEL 0x08
41 #define DF_OUTPUT_CRT 0x00
42 #define DF_SIMULTANEOUS_CRT_AND_FP (1 << 15)
44 #define DF_DEFAULT_TFT_PAD_SEL_LOW 0xDFFFFFFF
45 #define DF_DEFAULT_TFT_PAD_SEL_HIGH 0x0000003F
47 #define DC_SPARE_DISABLE_CFIFO_HGO 0x00000800
48 #define DC_SPARE_VFIFO_ARB_SELECT 0x00000400
49 #define DC_SPARE_WM_LPEN_OVRD 0x00000200
50 #define DC_SPARE_LOAD_WM_LPEN_MASK 0x00000100
51 #define DC_SPARE_DISABLE_INIT_VID_PRI 0x00000080
52 #define DC_SPARE_DISABLE_VFIFO_WM 0x00000040
53 #define DC_SPARE_DISABLE_CWD_CHECK 0x00000020
54 #define DC_SPARE_PIX8_PAN_FIX 0x00000010
55 #define DC_SPARE_FIRST_REQ_MASK 0x00000002
59 #define DC_UNLOCK 0x00
60 #define DC_UNLOCK_CODE 0x4758
62 #define DC_GENERAL_CFG 0x04
63 #define DC_GCFG_DFLE (1 << 0)
64 #define DC_GCFG_VIDE (1 << 3)
65 #define DC_GCFG_VGAE (1 << 7)
66 #define DC_GCFG_CMPE (1 << 5)
67 #define DC_GCFG_DECE (1 << 6)
68 #define DC_GCFG_FDTY (1 << 17)
70 #define DC_DISPLAY_CFG 0x08
71 #define DC_DCFG_TGEN (1 << 0)
72 #define DC_DCFG_GDEN (1 << 3)
73 #define DC_DCFG_VDEN (1 << 4)
74 #define DC_DCFG_TRUP (1 << 6)
75 #define DC_DCFG_DCEN (1 << 24)
76 #define DC_DCFG_PALB (1 << 25)
77 #define DC_DCFG_VISL (1 << 27)
79 #define DC_DCFG_16BPP 0x0
81 #define DC_DCFG_DISP_MODE_MASK 0x00000300
82 #define DC_DCFG_DISP_MODE_8BPP 0x00000000
83 #define DC_DCFG_DISP_MODE_16BPP 0x00000100
84 #define DC_DCFG_DISP_MODE_24BPP 0x00000200
85 #define DC_DCFG_DISP_MODE_32BPP 0x00000300
88 #define DC_ARB_CFG 0x0C
90 #define DC_FB_START 0x10
91 #define DC_CB_START 0x14
92 #define DC_CURSOR_START 0x18
94 #define DC_DV_TOP 0x2C
95 #define DC_DV_TOP_ENABLE (1 << 0)
97 #define DC_LINE_SIZE 0x30
98 #define DC_GRAPHICS_PITCH 0x34
99 #define DC_H_ACTIVE_TIMING 0x40
100 #define DC_H_BLANK_TIMING 0x44
101 #define DC_H_SYNC_TIMING 0x48
102 #define DC_V_ACTIVE_TIMING 0x50
103 #define DC_V_BLANK_TIMING 0x54
104 #define DC_V_SYNC_TIMING 0x58
105 #define DC_FB_ACTIVE 0x5C
107 #define DC_PAL_ADDRESS 0x70
108 #define DC_PAL_DATA 0x74
110 #define DC_PHY_MEM_OFFSET 0x84
112 #define DC_DV_CTL 0x88
113 #define DC_DV_LINE_SIZE_MASK 0x00000C00
114 #define DC_DV_LINE_SIZE_1024 0x00000000
115 #define DC_DV_LINE_SIZE_2048 0x00000400
116 #define DC_DV_LINE_SIZE_4096 0x00000800
117 #define DC_DV_LINE_SIZE_8192 0x00000C00
120 #define DC_GFX_SCALE 0x90
121 #define DC_IRQ_FILT_CTL 0x94
125 #define DC_IRQ_MASK (1 << 0)
126 #define DC_VSYNC_IRQ_MASK (1 << 1)
127 #define DC_IRQ_STATUS (1 << 20)
128 #define DC_VSYNC_IRQ_STATUS (1 << 21)
130 #define DC_GENLCK_CTRL 0xD4
131 #define DC_GENLCK_ENABLE (1 << 18)
132 #define DC_GC_ALPHA_FLICK_ENABLE (1 << 25)
133 #define DC_GC_FLICKER_FILTER_ENABLE (1 << 24)
134 #define DC_GC_FLICKER_FILTER_MASK (0x0F << 28)
136 #define DC_COLOR_KEY 0xB8
137 #define DC_CLR_KEY_ENABLE (1 << 24)
140 #define DC3_DV_LINE_SIZE_MASK 0x00000C00
141 #define DC3_DV_LINE_SIZE_1024 0x00000000
142 #define DC3_DV_LINE_SIZE_2048 0x00000400
143 #define DC3_DV_LINE_SIZE_4096 0x00000800
144 #define DC3_DV_LINE_SIZE_8192 0x00000C00
146 #define DF_VIDEO_CFG 0x0
147 #define DF_VCFG_VID_EN (1 << 0)
149 #define DF_DISPLAY_CFG 0x08
151 #define DF_DCFG_CRT_EN (1 << 0)
152 #define DF_DCFG_HSYNC_EN (1 << 1)
153 #define DF_DCFG_VSYNC_EN (1 << 2)
154 #define DF_DCFG_DAC_BL_EN (1 << 3)
155 #define DF_DCFG_CRT_HSYNC_POL (1 << 8)
156 #define DF_DCFG_CRT_VSYNC_POL (1 << 9)
157 #define DF_DCFG_GV_PAL_BYP (1 << 21)
159 #define DF_DCFG_CRT_SYNC_SKW_INIT 0x10000
160 #define DF_DCFG_CRT_SYNC_SKW_MASK 0x1c000
162 #define DF_DCFG_PWR_SEQ_DLY_INIT 0x80000
163 #define DF_DCFG_PWR_SEQ_DLY_MASK 0xe0000
167 #define DF_MISC_GAM_BYPASS (1 << 0)
168 #define DF_MISC_DAC_PWRDN (1 << 10)
169 #define DF_MISC_A_PWRDN (1 << 11)
173 #define DF_ALPHA_CONTROL_1 0xD8
174 #define DF_VIDEO_REQUEST 0x120
176 #define DF_PANEL_TIM1 0x400
177 #define DF_DEFAULT_TFT_PMTIM1 0x0
179 #define DF_PANEL_TIM2 0x408
180 #define DF_DEFAULT_TFT_PMTIM2 0x08000000
182 #define DF_FP_PM 0x410
183 #define DF_FP_PM_P (1 << 24)
185 #define DF_DITHER_CONTROL 0x418
186 #define DF_DEFAULT_TFT_DITHCTL 0x00000070
187 #define GP_BLT_STATUS 0x44
188 #define GP_BS_BLT_BUSY (1 << 0)
189 #define GP_BS_CB_EMPTY (1 << 4)