2 * Geode GX display controller.
4 * Copyright (C) 2005 Arcom Control Systems Ltd.
6 * Portions from AMD's original 2.4 driver:
7 * Copyright (C) 2004 Advanced Micro Devices, Inc.
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by * the
11 * Free Software Foundation; either version 2 of the License, or * (at your
12 * option) any later version.
14 #include <linux/spinlock.h>
16 #include <linux/delay.h>
18 #include <asm/div64.h>
19 #include <asm/delay.h>
22 #include "display_gx.h"
24 unsigned int gx_frame_buffer_size(void)
28 /* FB size is reported by a virtual register */
29 /* Virtual register class = 0x02 */
30 /* VG_MEM_SIZE(512Kb units) = 0x00 */
35 val = (unsigned int)(inw(0xAC1E)) & 0xFFl;
39 int gx_line_delta(int xres, int bpp)
41 /* Must be a multiple of 8 bytes. */
42 return (xres * (bpp >> 3) + 7) & ~0x7;
45 static void gx_set_mode(struct fb_info *info)
47 struct geodefb_par *par = info->par;
49 int hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
50 int vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
52 /* Unlock the display controller registers. */
53 readl(par->dc_regs + DC_UNLOCK);
54 writel(DC_UNLOCK_CODE, par->dc_regs + DC_UNLOCK);
56 gcfg = readl(par->dc_regs + DC_GENERAL_CFG);
57 dcfg = readl(par->dc_regs + DC_DISPLAY_CFG);
59 /* Disable the timing generator. */
60 dcfg &= ~(DC_DCFG_TGEN);
61 writel(dcfg, par->dc_regs + DC_DISPLAY_CFG);
63 /* Wait for pending memory requests before disabling the FIFO load. */
66 /* Disable FIFO load and compression. */
67 gcfg &= ~(DC_GCFG_DFLE | DC_GCFG_CMPE | DC_GCFG_DECE);
68 writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
70 /* Setup DCLK and its divisor. */
71 par->vid_ops->set_dclk(info);
77 /* Clear all unused feature bits. */
78 gcfg &= DC_GCFG_YUVM | DC_GCFG_VDSE;
81 /* Set FIFO priority (default 6/5) and enable. */
82 /* FIXME: increase fifo priority for 1280x1024 and higher modes? */
83 gcfg |= (6 << DC_GCFG_DFHPEL_POS) | (5 << DC_GCFG_DFHPSL_POS) | DC_GCFG_DFLE;
85 /* Framebuffer start offset. */
86 writel(0, par->dc_regs + DC_FB_ST_OFFSET);
88 /* Line delta and line buffer length. */
89 writel(info->fix.line_length >> 3, par->dc_regs + DC_GFX_PITCH);
90 writel(((info->var.xres * info->var.bits_per_pixel/8) >> 3) + 2,
91 par->dc_regs + DC_LINE_SIZE);
93 /* Enable graphics and video data and unmask address lines. */
94 dcfg |= DC_DCFG_GDEN | DC_DCFG_VDEN | DC_DCFG_A20M | DC_DCFG_A18M;
96 /* Set pixel format. */
97 switch (info->var.bits_per_pixel) {
99 dcfg |= DC_DCFG_DISP_MODE_8BPP;
102 dcfg |= DC_DCFG_DISP_MODE_16BPP;
103 dcfg |= DC_DCFG_16BPP_MODE_565;
106 dcfg |= DC_DCFG_DISP_MODE_24BPP;
107 dcfg |= DC_DCFG_PALB;
111 /* Enable timing generator. */
112 dcfg |= DC_DCFG_TGEN;
114 /* Horizontal and vertical timings. */
115 hactive = info->var.xres;
116 hblankstart = hactive;
117 hsyncstart = hblankstart + info->var.right_margin;
118 hsyncend = hsyncstart + info->var.hsync_len;
119 hblankend = hsyncend + info->var.left_margin;
122 vactive = info->var.yres;
123 vblankstart = vactive;
124 vsyncstart = vblankstart + info->var.lower_margin;
125 vsyncend = vsyncstart + info->var.vsync_len;
126 vblankend = vsyncend + info->var.upper_margin;
129 writel((hactive - 1) | ((htotal - 1) << 16), par->dc_regs + DC_H_ACTIVE_TIMING);
130 writel((hblankstart - 1) | ((hblankend - 1) << 16), par->dc_regs + DC_H_BLANK_TIMING);
131 writel((hsyncstart - 1) | ((hsyncend - 1) << 16), par->dc_regs + DC_H_SYNC_TIMING);
133 writel((vactive - 1) | ((vtotal - 1) << 16), par->dc_regs + DC_V_ACTIVE_TIMING);
134 writel((vblankstart - 1) | ((vblankend - 1) << 16), par->dc_regs + DC_V_BLANK_TIMING);
135 writel((vsyncstart - 1) | ((vsyncend - 1) << 16), par->dc_regs + DC_V_SYNC_TIMING);
137 /* Write final register values. */
138 writel(dcfg, par->dc_regs + DC_DISPLAY_CFG);
139 writel(gcfg, par->dc_regs + DC_GENERAL_CFG);
141 par->vid_ops->configure_display(info);
143 /* Relock display controller registers */
144 writel(0, par->dc_regs + DC_UNLOCK);
147 static void gx_set_hw_palette_reg(struct fb_info *info, unsigned regno,
148 unsigned red, unsigned green, unsigned blue)
150 struct geodefb_par *par = info->par;
153 /* Hardware palette is in RGB 8-8-8 format. */
154 val = (red << 8) & 0xff0000;
155 val |= (green) & 0x00ff00;
156 val |= (blue >> 8) & 0x0000ff;
158 writel(regno, par->dc_regs + DC_PAL_ADDRESS);
159 writel(val, par->dc_regs + DC_PAL_DATA);
162 struct geode_dc_ops gx_dc_ops = {
163 .set_mode = gx_set_mode,
164 .set_palette_reg = gx_set_hw_palette_reg,