2 * drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets
4 * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
6 * Contributors (thanks, all!)
9 * Overhaul for Linux 2.6
12 * Major contributions; Motorola PowerStack (PPC and PCI) support,
13 * GD54xx, 1280x1024 mode support, change MCLK based on VCLK.
16 * Excellent code review.
19 * Amiga updates and testing.
21 * Original cirrusfb author: Frank Neumann
23 * Based on retz3fb.c and cirrusfb.c:
24 * Copyright (C) 1997 Jes Sorensen
25 * Copyright (C) 1996 Frank Neumann
27 ***************************************************************
29 * Format this code with GNU indent '-kr -i8 -pcs' options.
31 * This file is subject to the terms and conditions of the GNU General Public
32 * License. See the file COPYING in the main directory of this archive
37 #define CIRRUSFB_VERSION "2.0-pre2"
39 #include <linux/module.h>
40 #include <linux/kernel.h>
41 #include <linux/errno.h>
42 #include <linux/string.h>
44 #include <linux/slab.h>
45 #include <linux/delay.h>
47 #include <linux/init.h>
48 #include <linux/selection.h>
49 #include <asm/pgtable.h>
52 #include <linux/zorro.h>
55 #include <linux/pci.h>
58 #include <asm/amigahw.h>
60 #ifdef CONFIG_PPC_PREP
61 #include <asm/machdep.h>
62 #define isPReP machine_is(prep)
67 #include "video/vga.h"
68 #include "video/cirrus.h"
70 /*****************************************************************
72 * debugging and utility macros
76 /* enable debug output? */
77 /* #define CIRRUSFB_DEBUG 1 */
79 /* disable runtime assertions? */
80 /* #define CIRRUSFB_NDEBUG */
84 #define DPRINTK(fmt, args...) \
85 printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
87 #define DPRINTK(fmt, args...)
90 /* debugging assertions */
91 #ifndef CIRRUSFB_NDEBUG
92 #define assert(expr) \
94 printk("Assertion failed! %s,%s,%s,line=%d\n", \
95 #expr, __FILE__, __FUNCTION__, __LINE__); \
101 #define MB_ (1024 * 1024)
104 #define MAX_NUM_BOARDS 7
106 /*****************************************************************
108 * chipset information
119 BT_PICASSO4, /* GD5446 */
120 BT_ALPINE, /* GD543x/4x */
122 BT_LAGUNA, /* GD546x */
126 * per-board-type information, used for enumerating and abstracting
127 * chip-specific information
128 * NOTE: MUST be in the same order as enum cirrus_board in order to
129 * use direct indexing on this array
130 * NOTE: '__initdata' cannot be used as some of this info
131 * is required at runtime. Maybe separate into an init-only and
134 static const struct cirrusfb_board_info_rec {
135 char *name; /* ASCII name of chipset */
136 long maxclock[5]; /* maximum video clock */
137 /* for 1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */
138 bool init_sr07 : 1; /* init SR07 during init_vgachip() */
139 bool init_sr1f : 1; /* write SR1F during init_vgachip() */
140 /* construct bit 19 of screen start address */
141 bool scrn_start_bit19 : 1;
143 /* initial SR07 value, then for each mode */
145 unsigned char sr07_1bpp;
146 unsigned char sr07_1bpp_mux;
147 unsigned char sr07_8bpp;
148 unsigned char sr07_8bpp_mux;
150 unsigned char sr1f; /* SR1F VGA initial register value */
151 } cirrusfb_board_info[] = {
156 /* the SD64/P4 have a higher max. videoclock */
157 140000, 140000, 140000, 140000, 140000,
161 .scrn_start_bit19 = true,
168 .name = "CL Piccolo",
171 90000, 90000, 90000, 90000, 90000
175 .scrn_start_bit19 = false,
182 .name = "CL Picasso",
185 90000, 90000, 90000, 90000, 90000
189 .scrn_start_bit19 = false,
196 .name = "CL Spectrum",
199 90000, 90000, 90000, 90000, 90000
203 .scrn_start_bit19 = false,
210 .name = "CL Picasso4",
212 135100, 135100, 85500, 85500, 0
216 .scrn_start_bit19 = true,
225 /* for the GD5430. GD5446 can do more... */
226 85500, 85500, 50000, 28500, 0
230 .scrn_start_bit19 = true,
233 .sr07_1bpp_mux = 0xA7,
235 .sr07_8bpp_mux = 0xA7,
241 135100, 200000, 200000, 135100, 135100
245 .scrn_start_bit19 = true,
255 135100, 135100, 135100, 135100, 135100,
259 .scrn_start_bit19 = true,
264 #define CHIP(id, btype) \
265 { PCI_VENDOR_ID_CIRRUS, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (btype) }
267 static struct pci_device_id cirrusfb_pci_table[] = {
268 CHIP(PCI_DEVICE_ID_CIRRUS_5436, BT_ALPINE),
269 CHIP(PCI_DEVICE_ID_CIRRUS_5434_8, BT_ALPINE),
270 CHIP(PCI_DEVICE_ID_CIRRUS_5434_4, BT_ALPINE),
271 CHIP(PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE), /* GD-5440 is same id */
272 CHIP(PCI_DEVICE_ID_CIRRUS_7543, BT_ALPINE),
273 CHIP(PCI_DEVICE_ID_CIRRUS_7548, BT_ALPINE),
274 CHIP(PCI_DEVICE_ID_CIRRUS_5480, BT_GD5480), /* MacPicasso likely */
275 CHIP(PCI_DEVICE_ID_CIRRUS_5446, BT_PICASSO4), /* Picasso 4 is 5446 */
276 CHIP(PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA), /* CL Laguna */
277 CHIP(PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA), /* CL Laguna 3D */
278 CHIP(PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNA), /* CL Laguna 3DA*/
281 MODULE_DEVICE_TABLE(pci, cirrusfb_pci_table);
283 #endif /* CONFIG_PCI */
286 static const struct zorro_device_id cirrusfb_zorro_table[] = {
288 .id = ZORRO_PROD_HELFRICH_SD64_RAM,
289 .driver_data = BT_SD64,
291 .id = ZORRO_PROD_HELFRICH_PICCOLO_RAM,
292 .driver_data = BT_PICCOLO,
294 .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_RAM,
295 .driver_data = BT_PICASSO,
297 .id = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_RAM,
298 .driver_data = BT_SPECTRUM,
300 .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z3,
301 .driver_data = BT_PICASSO4,
306 static const struct {
309 } cirrusfb_zorro_table2[] = {
311 .id2 = ZORRO_PROD_HELFRICH_SD64_REG,
315 .id2 = ZORRO_PROD_HELFRICH_PICCOLO_REG,
319 .id2 = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_REG,
323 .id2 = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_REG,
331 #endif /* CONFIG_ZORRO */
333 struct cirrusfb_regs {
334 __u32 line_length; /* in BYTES! */
346 long HorizRes; /* The x resolution in pixel */
349 long HorizBlankStart;
354 long VertRes; /* the physical y resolution in scanlines */
363 #ifdef CIRRUSFB_DEBUG
364 enum cirrusfb_dbg_reg_class {
368 #endif /* CIRRUSFB_DEBUG */
370 /* info about board */
371 struct cirrusfb_info {
373 enum cirrus_board btype;
374 unsigned char SFR; /* Shadow of special function register */
376 struct cirrusfb_regs currentmode;
379 u32 pseudo_palette[16];
382 struct zorro_dev *zdev;
385 struct pci_dev *pdev;
387 void (*unmap)(struct fb_info *info);
390 static unsigned cirrusfb_def_mode = 1;
394 * Predefined Video Modes
397 static const struct {
399 struct fb_var_screeninfo var;
400 } cirrusfb_predefined[] = {
402 /* autodetect mode */
403 .name = "Autodetect",
405 /* 640x480, 31.25 kHz, 60 Hz, 25 MHz PixClock */
413 .red = { .length = 8 },
414 .green = { .length = 8 },
415 .blue = { .length = 8 },
425 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
426 .vmode = FB_VMODE_NONINTERLACED
429 /* 800x600, 48 kHz, 76 Hz, 50 MHz PixClock */
437 .red = { .length = 8 },
438 .green = { .length = 8 },
439 .blue = { .length = 8 },
449 .vmode = FB_VMODE_NONINTERLACED
453 * Modeline from XF86Config:
454 * Mode "1024x768" 80 1024 1136 1340 1432 768 770 774 805
456 /* 1024x768, 55.8 kHz, 70 Hz, 80 MHz PixClock */
461 .xres_virtual = 1024,
464 .red = { .length = 8 },
465 .green = { .length = 8 },
466 .blue = { .length = 8 },
476 .vmode = FB_VMODE_NONINTERLACED
481 #define NUM_TOTAL_MODES ARRAY_SIZE(cirrusfb_predefined)
483 /****************************************************************************/
484 /**** BEGIN PROTOTYPES ******************************************************/
486 /*--- Interface used by the world ------------------------------------------*/
487 static int cirrusfb_init(void);
489 static int cirrusfb_setup(char *options);
492 static int cirrusfb_open(struct fb_info *info, int user);
493 static int cirrusfb_release(struct fb_info *info, int user);
494 static int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green,
495 unsigned blue, unsigned transp,
496 struct fb_info *info);
497 static int cirrusfb_check_var(struct fb_var_screeninfo *var,
498 struct fb_info *info);
499 static int cirrusfb_set_par(struct fb_info *info);
500 static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
501 struct fb_info *info);
502 static int cirrusfb_blank(int blank_mode, struct fb_info *info);
503 static void cirrusfb_fillrect(struct fb_info *info,
504 const struct fb_fillrect *region);
505 static void cirrusfb_copyarea(struct fb_info *info,
506 const struct fb_copyarea *area);
507 static void cirrusfb_imageblit(struct fb_info *info,
508 const struct fb_image *image);
510 /* function table of the above functions */
511 static struct fb_ops cirrusfb_ops = {
512 .owner = THIS_MODULE,
513 .fb_open = cirrusfb_open,
514 .fb_release = cirrusfb_release,
515 .fb_setcolreg = cirrusfb_setcolreg,
516 .fb_check_var = cirrusfb_check_var,
517 .fb_set_par = cirrusfb_set_par,
518 .fb_pan_display = cirrusfb_pan_display,
519 .fb_blank = cirrusfb_blank,
520 .fb_fillrect = cirrusfb_fillrect,
521 .fb_copyarea = cirrusfb_copyarea,
522 .fb_imageblit = cirrusfb_imageblit,
525 /*--- Hardware Specific Routines -------------------------------------------*/
526 static int cirrusfb_decode_var(const struct fb_var_screeninfo *var,
527 struct cirrusfb_regs *regs,
528 const struct fb_info *info);
529 /*--- Internal routines ----------------------------------------------------*/
530 static void init_vgachip(struct fb_info *info);
531 static void switch_monitor(struct cirrusfb_info *cinfo, int on);
532 static void WGen(const struct cirrusfb_info *cinfo,
533 int regnum, unsigned char val);
534 static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum);
535 static void AttrOn(const struct cirrusfb_info *cinfo);
536 static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val);
537 static void WSFR(struct cirrusfb_info *cinfo, unsigned char val);
538 static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val);
539 static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum,
540 unsigned char red, unsigned char green, unsigned char blue);
542 static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum,
543 unsigned char *red, unsigned char *green,
544 unsigned char *blue);
546 static void cirrusfb_WaitBLT(u8 __iomem *regbase);
547 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
548 u_short curx, u_short cury,
549 u_short destx, u_short desty,
550 u_short width, u_short height,
551 u_short line_length);
552 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
553 u_short x, u_short y,
554 u_short width, u_short height,
555 u_char color, u_short line_length);
557 static void bestclock(long freq, long *best,
558 long *nom, long *den,
559 long *div, long maxfreq);
561 #ifdef CIRRUSFB_DEBUG
562 static void cirrusfb_dump(void);
563 static void cirrusfb_dbg_reg_dump(caddr_t regbase);
564 static void cirrusfb_dbg_print_regs(caddr_t regbase,
565 enum cirrusfb_dbg_reg_class reg_class, ...);
566 static void cirrusfb_dbg_print_byte(const char *name, unsigned char val);
567 #endif /* CIRRUSFB_DEBUG */
569 /*** END PROTOTYPES ********************************************************/
570 /*****************************************************************************/
571 /*** BEGIN Interface Used by the World ***************************************/
573 static int opencount;
575 /*--- Open /dev/fbx ---------------------------------------------------------*/
576 static int cirrusfb_open(struct fb_info *info, int user)
578 if (opencount++ == 0)
579 switch_monitor(info->par, 1);
583 /*--- Close /dev/fbx --------------------------------------------------------*/
584 static int cirrusfb_release(struct fb_info *info, int user)
586 if (--opencount == 0)
587 switch_monitor(info->par, 0);
591 /**** END Interface used by the World *************************************/
592 /****************************************************************************/
593 /**** BEGIN Hardware specific Routines **************************************/
595 /* Get a good MCLK value */
596 static long cirrusfb_get_mclk(long freq, int bpp, long *div)
602 /* Calculate MCLK, in case VCLK is high enough to require > 50MHz.
603 * Assume a 64-bit data path for now. The formula is:
604 * ((B * PCLK * 2)/W) * 1.2
605 * B = bytes per pixel, PCLK = pixclock, W = data width in bytes */
606 mclk = ((bpp / 8) * freq * 2) / 4;
607 mclk = (mclk * 12) / 10;
610 DPRINTK("Use MCLK of %ld kHz\n", mclk);
612 /* Calculate value for SR1F. Multiply by 2 so we can round up. */
613 mclk = ((mclk * 16) / 14318);
614 mclk = (mclk + 1) / 2;
615 DPRINTK("Set SR1F[5:0] to 0x%lx\n", mclk);
617 /* Determine if we should use MCLK instead of VCLK, and if so, what we
618 * should divide it by to get VCLK */
620 case 24751 ... 25249:
622 DPRINTK("Using VCLK = MCLK/2\n");
624 case 49501 ... 50499:
626 DPRINTK("Using VCLK = MCLK\n");
636 static int cirrusfb_check_var(struct fb_var_screeninfo *var,
637 struct fb_info *info)
639 int nom, den; /* translyting from pixels->bytes */
641 static struct { int xres, yres; } modes[] =
649 switch (var->bits_per_pixel) {
651 var->bits_per_pixel = 1;
654 break; /* 8 pixel per byte, only 1/4th of mem usable */
656 var->bits_per_pixel = 8;
659 break; /* 1 pixel == 1 byte */
661 var->bits_per_pixel = 16;
664 break; /* 2 bytes per pixel */
666 var->bits_per_pixel = 24;
669 break; /* 3 bytes per pixel */
671 var->bits_per_pixel = 32;
674 break; /* 4 bytes per pixel */
676 printk(KERN_ERR "cirrusfb: mode %dx%dx%d rejected..."
677 "color depth not supported.\n",
678 var->xres, var->yres, var->bits_per_pixel);
679 DPRINTK("EXIT - EINVAL error\n");
683 if (var->xres * nom / den * var->yres > info->screen_size) {
684 printk(KERN_ERR "cirrusfb: mode %dx%dx%d rejected..."
685 "resolution too high to fit into video memory!\n",
686 var->xres, var->yres, var->bits_per_pixel);
687 DPRINTK("EXIT - EINVAL error\n");
691 /* use highest possible virtual resolution */
692 if (var->xres_virtual == -1 &&
693 var->yres_virtual == -1) {
695 "cirrusfb: using maximum available virtual resolution\n");
696 for (i = 0; modes[i].xres != -1; i++) {
697 int size = modes[i].xres * nom / den * modes[i].yres;
698 if (size < info->screen_size / 2)
701 if (modes[i].xres == -1) {
702 printk(KERN_ERR "cirrusfb: could not find a virtual "
703 "resolution that fits into video memory!!\n");
704 DPRINTK("EXIT - EINVAL error\n");
707 var->xres_virtual = modes[i].xres;
708 var->yres_virtual = modes[i].yres;
710 printk(KERN_INFO "cirrusfb: virtual resolution set to "
711 "maximum of %dx%d\n", var->xres_virtual,
715 if (var->xres_virtual < var->xres)
716 var->xres_virtual = var->xres;
717 if (var->yres_virtual < var->yres)
718 var->yres_virtual = var->yres;
720 if (var->xoffset < 0)
722 if (var->yoffset < 0)
725 /* truncate xoffset and yoffset to maximum if too high */
726 if (var->xoffset > var->xres_virtual - var->xres)
727 var->xoffset = var->xres_virtual - var->xres - 1;
728 if (var->yoffset > var->yres_virtual - var->yres)
729 var->yoffset = var->yres_virtual - var->yres - 1;
731 switch (var->bits_per_pixel) {
735 var->green.offset = 0;
736 var->green.length = 1;
737 var->blue.offset = 0;
738 var->blue.length = 1;
744 var->green.offset = 0;
745 var->green.length = 6;
746 var->blue.offset = 0;
747 var->blue.length = 6;
753 var->green.offset = -3;
754 var->blue.offset = 8;
756 var->red.offset = 10;
757 var->green.offset = 5;
758 var->blue.offset = 0;
761 var->green.length = 5;
762 var->blue.length = 5;
768 var->green.offset = 16;
769 var->blue.offset = 24;
771 var->red.offset = 16;
772 var->green.offset = 8;
773 var->blue.offset = 0;
776 var->green.length = 8;
777 var->blue.length = 8;
783 var->green.offset = 16;
784 var->blue.offset = 24;
786 var->red.offset = 16;
787 var->green.offset = 8;
788 var->blue.offset = 0;
791 var->green.length = 8;
792 var->blue.length = 8;
796 DPRINTK("Unsupported bpp size: %d\n", var->bits_per_pixel);
798 /* should never occur */
803 var->green.msb_right =
804 var->blue.msb_right =
807 var->transp.msb_right = 0;
810 if (var->vmode & FB_VMODE_DOUBLE)
812 else if (var->vmode & FB_VMODE_INTERLACED)
813 yres = (yres + 1) / 2;
816 printk(KERN_ERR "cirrusfb: ERROR: VerticalTotal >= 1280; "
817 "special treatment required! (TODO)\n");
818 DPRINTK("EXIT - EINVAL error\n");
825 static int cirrusfb_decode_var(const struct fb_var_screeninfo *var,
826 struct cirrusfb_regs *regs,
827 const struct fb_info *info)
832 struct cirrusfb_info *cinfo = info->par;
833 int xres, hfront, hsync, hback;
834 int yres, vfront, vsync, vback;
836 switch (var->bits_per_pixel) {
838 regs->line_length = var->xres_virtual / 8;
839 regs->visual = FB_VISUAL_MONO10;
844 regs->line_length = var->xres_virtual;
845 regs->visual = FB_VISUAL_PSEUDOCOLOR;
850 regs->line_length = var->xres_virtual * 2;
851 regs->visual = FB_VISUAL_DIRECTCOLOR;
856 regs->line_length = var->xres_virtual * 3;
857 regs->visual = FB_VISUAL_DIRECTCOLOR;
862 regs->line_length = var->xres_virtual * 4;
863 regs->visual = FB_VISUAL_DIRECTCOLOR;
868 DPRINTK("Unsupported bpp size: %d\n", var->bits_per_pixel);
870 /* should never occur */
874 regs->type = FB_TYPE_PACKED_PIXELS;
876 /* convert from ps to kHz */
877 freq = 1000000000 / var->pixclock;
879 DPRINTK("desired pixclock: %ld kHz\n", freq);
881 maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx];
882 regs->multiplexing = 0;
884 /* If the frequency is greater than we can support, we might be able
885 * to use multiplexing for the video mode */
886 if (freq > maxclock) {
887 switch (cinfo->btype) {
890 regs->multiplexing = 1;
894 printk(KERN_ERR "cirrusfb: Frequency greater "
895 "than maxclock (%ld kHz)\n", maxclock);
896 DPRINTK("EXIT - return -EINVAL\n");
901 /* TODO: If we have a 1MB 5434, we need to put ourselves in a mode where
902 * the VCLK is double the pixel clock. */
903 switch (var->bits_per_pixel) {
906 if (regs->HorizRes <= 800)
907 /* Xbh has this type of clock for 32-bit */
913 bestclock(freq, ®s->freq, ®s->nom, ®s->den, ®s->div,
915 regs->mclk = cirrusfb_get_mclk(freq, var->bits_per_pixel,
919 hfront = var->right_margin;
920 hsync = var->hsync_len;
921 hback = var->left_margin;
924 vfront = var->lower_margin;
925 vsync = var->vsync_len;
926 vback = var->upper_margin;
928 if (var->vmode & FB_VMODE_DOUBLE) {
933 } else if (var->vmode & FB_VMODE_INTERLACED) {
934 yres = (yres + 1) / 2;
935 vfront = (vfront + 1) / 2;
936 vsync = (vsync + 1) / 2;
937 vback = (vback + 1) / 2;
939 regs->HorizRes = xres;
940 regs->HorizTotal = (xres + hfront + hsync + hback) / 8 - 5;
941 regs->HorizDispEnd = xres / 8 - 1;
942 regs->HorizBlankStart = xres / 8;
943 /* does not count with "-5" */
944 regs->HorizBlankEnd = regs->HorizTotal + 5;
945 regs->HorizSyncStart = (xres + hfront) / 8 + 1;
946 regs->HorizSyncEnd = (xres + hfront + hsync) / 8 + 1;
948 regs->VertRes = yres;
949 regs->VertTotal = yres + vfront + vsync + vback - 2;
950 regs->VertDispEnd = yres - 1;
951 regs->VertBlankStart = yres;
952 regs->VertBlankEnd = regs->VertTotal;
953 regs->VertSyncStart = yres + vfront - 1;
954 regs->VertSyncEnd = yres + vfront + vsync - 1;
956 if (regs->VertRes >= 1024) {
957 regs->VertTotal /= 2;
958 regs->VertSyncStart /= 2;
959 regs->VertSyncEnd /= 2;
960 regs->VertDispEnd /= 2;
962 if (regs->multiplexing) {
963 regs->HorizTotal /= 2;
964 regs->HorizSyncStart /= 2;
965 regs->HorizSyncEnd /= 2;
966 regs->HorizDispEnd /= 2;
972 static void cirrusfb_set_mclk(const struct cirrusfb_info *cinfo, int val,
975 assert(cinfo != NULL);
979 unsigned char old = vga_rseq(cinfo->regbase, CL_SEQR1E);
980 vga_wseq(cinfo->regbase, CL_SEQR1E, old | 0x1);
981 vga_wseq(cinfo->regbase, CL_SEQR1F, 0x40 | (val & 0x3f));
982 } else if (div == 1) {
984 unsigned char old = vga_rseq(cinfo->regbase, CL_SEQR1E);
985 vga_wseq(cinfo->regbase, CL_SEQR1E, old & ~0x1);
986 vga_wseq(cinfo->regbase, CL_SEQR1F, 0x40 | (val & 0x3f));
988 vga_wseq(cinfo->regbase, CL_SEQR1F, val & 0x3f);
992 /*************************************************************************
993 cirrusfb_set_par_foo()
995 actually writes the values for a new video mode into the hardware,
996 **************************************************************************/
997 static int cirrusfb_set_par_foo(struct fb_info *info)
999 struct cirrusfb_info *cinfo = info->par;
1000 struct fb_var_screeninfo *var = &info->var;
1001 struct cirrusfb_regs regs;
1002 u8 __iomem *regbase = cinfo->regbase;
1004 int offset = 0, err;
1005 const struct cirrusfb_board_info_rec *bi;
1008 DPRINTK("Requested mode: %dx%dx%d\n",
1009 var->xres, var->yres, var->bits_per_pixel);
1010 DPRINTK("pixclock: %d\n", var->pixclock);
1014 err = cirrusfb_decode_var(var, ®s, info);
1016 /* should never happen */
1017 DPRINTK("mode change aborted. invalid var.\n");
1021 bi = &cirrusfb_board_info[cinfo->btype];
1023 /* unlock register VGA_CRTC_H_TOTAL..CRT7 */
1024 vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20); /* previously: 0x00) */
1026 /* if debugging is enabled, all parameters get output before writing */
1027 DPRINTK("CRT0: %ld\n", regs.HorizTotal);
1028 vga_wcrt(regbase, VGA_CRTC_H_TOTAL, regs.HorizTotal);
1030 DPRINTK("CRT1: %ld\n", regs.HorizDispEnd);
1031 vga_wcrt(regbase, VGA_CRTC_H_DISP, regs.HorizDispEnd);
1033 DPRINTK("CRT2: %ld\n", regs.HorizBlankStart);
1034 vga_wcrt(regbase, VGA_CRTC_H_BLANK_START, regs.HorizBlankStart);
1036 /* + 128: Compatible read */
1037 DPRINTK("CRT3: 128+%ld\n", regs.HorizBlankEnd % 32);
1038 vga_wcrt(regbase, VGA_CRTC_H_BLANK_END,
1039 128 + (regs.HorizBlankEnd % 32));
1041 DPRINTK("CRT4: %ld\n", regs.HorizSyncStart);
1042 vga_wcrt(regbase, VGA_CRTC_H_SYNC_START, regs.HorizSyncStart);
1044 tmp = regs.HorizSyncEnd % 32;
1045 if (regs.HorizBlankEnd & 32)
1047 DPRINTK("CRT5: %d\n", tmp);
1048 vga_wcrt(regbase, VGA_CRTC_H_SYNC_END, tmp);
1050 DPRINTK("CRT6: %ld\n", regs.VertTotal & 0xff);
1051 vga_wcrt(regbase, VGA_CRTC_V_TOTAL, (regs.VertTotal & 0xff));
1053 tmp = 16; /* LineCompare bit #9 */
1054 if (regs.VertTotal & 256)
1056 if (regs.VertDispEnd & 256)
1058 if (regs.VertSyncStart & 256)
1060 if (regs.VertBlankStart & 256)
1062 if (regs.VertTotal & 512)
1064 if (regs.VertDispEnd & 512)
1066 if (regs.VertSyncStart & 512)
1068 DPRINTK("CRT7: %d\n", tmp);
1069 vga_wcrt(regbase, VGA_CRTC_OVERFLOW, tmp);
1071 tmp = 0x40; /* LineCompare bit #8 */
1072 if (regs.VertBlankStart & 512)
1074 if (var->vmode & FB_VMODE_DOUBLE)
1076 DPRINTK("CRT9: %d\n", tmp);
1077 vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, tmp);
1079 DPRINTK("CRT10: %ld\n", regs.VertSyncStart & 0xff);
1080 vga_wcrt(regbase, VGA_CRTC_V_SYNC_START, regs.VertSyncStart & 0xff);
1082 DPRINTK("CRT11: 64+32+%ld\n", regs.VertSyncEnd % 16);
1083 vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, regs.VertSyncEnd % 16 + 64 + 32);
1085 DPRINTK("CRT12: %ld\n", regs.VertDispEnd & 0xff);
1086 vga_wcrt(regbase, VGA_CRTC_V_DISP_END, regs.VertDispEnd & 0xff);
1088 DPRINTK("CRT15: %ld\n", regs.VertBlankStart & 0xff);
1089 vga_wcrt(regbase, VGA_CRTC_V_BLANK_START, regs.VertBlankStart & 0xff);
1091 DPRINTK("CRT16: %ld\n", regs.VertBlankEnd & 0xff);
1092 vga_wcrt(regbase, VGA_CRTC_V_BLANK_END, regs.VertBlankEnd & 0xff);
1094 DPRINTK("CRT18: 0xff\n");
1095 vga_wcrt(regbase, VGA_CRTC_LINE_COMPARE, 0xff);
1098 if (var->vmode & FB_VMODE_INTERLACED)
1100 if (regs.HorizBlankEnd & 64)
1102 if (regs.HorizBlankEnd & 128)
1104 if (regs.VertBlankEnd & 256)
1106 if (regs.VertBlankEnd & 512)
1109 DPRINTK("CRT1a: %d\n", tmp);
1110 vga_wcrt(regbase, CL_CRT1A, tmp);
1113 /* hardware RefClock: 14.31818 MHz */
1114 /* formula: VClk = (OSC * N) / (D * (1+P)) */
1115 /* Example: VClk = (14.31818 * 91) / (23 * (1+1)) = 28.325 MHz */
1117 vga_wseq(regbase, CL_SEQRB, regs.nom);
1118 tmp = regs.den << 1;
1122 /* 6 bit denom; ONLY 5434!!! (bugged me 10 days) */
1123 if ((cinfo->btype == BT_SD64) ||
1124 (cinfo->btype == BT_ALPINE) ||
1125 (cinfo->btype == BT_GD5480))
1128 DPRINTK("CL_SEQR1B: %ld\n", (long) tmp);
1129 vga_wseq(regbase, CL_SEQR1B, tmp);
1131 if (regs.VertRes >= 1024)
1133 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc7);
1135 /* mode control: VGA_CRTC_START_HI enable, ROTATE(?), 16bit
1136 * address wrap, no compat. */
1137 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc3);
1139 /* HAEH? vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20);
1140 * previously: 0x00 unlock VGA_CRTC_H_TOTAL..CRT7 */
1142 /* don't know if it would hurt to also program this if no interlaced */
1143 /* mode is used, but I feel better this way.. :-) */
1144 if (var->vmode & FB_VMODE_INTERLACED)
1145 vga_wcrt(regbase, VGA_CRTC_REGS, regs.HorizTotal / 2);
1147 vga_wcrt(regbase, VGA_CRTC_REGS, 0x00); /* interlace control */
1149 vga_wseq(regbase, VGA_SEQ_CHARACTER_MAP, 0);
1151 /* adjust horizontal/vertical sync type (low/high) */
1152 /* enable display memory & CRTC I/O address for color mode */
1154 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
1156 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
1158 WGen(cinfo, VGA_MIS_W, tmp);
1160 /* Screen A Preset Row-Scan register */
1161 vga_wcrt(regbase, VGA_CRTC_PRESET_ROW, 0);
1162 /* text cursor on and start line */
1163 vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0);
1164 /* text cursor end line */
1165 vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 31);
1167 /******************************************************
1173 /* programming for different color depths */
1174 if (var->bits_per_pixel == 1) {
1175 DPRINTK("cirrusfb: preparing for 1 bit deep display\n");
1176 vga_wgfx(regbase, VGA_GFX_MODE, 0); /* mode register */
1179 switch (cinfo->btype) {
1187 DPRINTK(" (for GD54xx)\n");
1188 vga_wseq(regbase, CL_SEQR7,
1190 bi->sr07_1bpp_mux : bi->sr07_1bpp);
1194 DPRINTK(" (for GD546x)\n");
1195 vga_wseq(regbase, CL_SEQR7,
1196 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1200 printk(KERN_WARNING "cirrusfb: unknown Board\n");
1204 /* Extended Sequencer Mode */
1205 switch (cinfo->btype) {
1207 /* setting the SEQRF on SD64 is not necessary
1208 * (only during init)
1210 DPRINTK("(for SD64)\n");
1212 vga_wseq(regbase, CL_SEQR1F, 0x1a);
1216 DPRINTK("(for Piccolo)\n");
1217 /* ### ueberall 0x22? */
1218 /* ##vorher 1c MCLK select */
1219 vga_wseq(regbase, CL_SEQR1F, 0x22);
1220 /* evtl d0 bei 1 bit? avoid FIFO underruns..? */
1221 vga_wseq(regbase, CL_SEQRF, 0xb0);
1225 DPRINTK("(for Picasso)\n");
1226 /* ##vorher 22 MCLK select */
1227 vga_wseq(regbase, CL_SEQR1F, 0x22);
1228 /* ## vorher d0 avoid FIFO underruns..? */
1229 vga_wseq(regbase, CL_SEQRF, 0xd0);
1233 DPRINTK("(for Spectrum)\n");
1234 /* ### ueberall 0x22? */
1235 /* ##vorher 1c MCLK select */
1236 vga_wseq(regbase, CL_SEQR1F, 0x22);
1237 /* evtl d0? avoid FIFO underruns..? */
1238 vga_wseq(regbase, CL_SEQRF, 0xb0);
1245 DPRINTK(" (for GD54xx)\n");
1250 printk(KERN_WARNING "cirrusfb: unknown Board\n");
1254 /* pixel mask: pass-through for first plane */
1255 WGen(cinfo, VGA_PEL_MSK, 0x01);
1256 if (regs.multiplexing)
1257 /* hidden dac reg: 1280x1024 */
1260 /* hidden dac: nothing */
1262 /* memory mode: odd/even, ext. memory */
1263 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x06);
1264 /* plane mask: only write to first plane */
1265 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x01);
1266 offset = var->xres_virtual / 16;
1269 /******************************************************
1275 else if (var->bits_per_pixel == 8) {
1276 DPRINTK("cirrusfb: preparing for 8 bit deep display\n");
1277 switch (cinfo->btype) {
1285 DPRINTK(" (for GD54xx)\n");
1286 vga_wseq(regbase, CL_SEQR7,
1288 bi->sr07_8bpp_mux : bi->sr07_8bpp);
1292 DPRINTK(" (for GD546x)\n");
1293 vga_wseq(regbase, CL_SEQR7,
1294 vga_rseq(regbase, CL_SEQR7) | 0x01);
1298 printk(KERN_WARNING "cirrusfb: unknown Board\n");
1302 switch (cinfo->btype) {
1305 vga_wseq(regbase, CL_SEQR1F, 0x1d);
1309 /* ### vorher 1c MCLK select */
1310 vga_wseq(regbase, CL_SEQR1F, 0x22);
1311 /* Fast Page-Mode writes */
1312 vga_wseq(regbase, CL_SEQRF, 0xb0);
1316 /* ### vorher 1c MCLK select */
1317 vga_wseq(regbase, CL_SEQR1F, 0x22);
1318 /* Fast Page-Mode writes */
1319 vga_wseq(regbase, CL_SEQRF, 0xb0);
1323 /* ### vorher 1c MCLK select */
1324 vga_wseq(regbase, CL_SEQR1F, 0x22);
1325 /* Fast Page-Mode writes */
1326 vga_wseq(regbase, CL_SEQRF, 0xb0);
1331 /* ### INCOMPLETE!! */
1332 vga_wseq(regbase, CL_SEQRF, 0xb8);
1334 /* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
1338 DPRINTK(" (for GD543x)\n");
1339 cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK);
1340 /* We already set SRF and SR1F */
1345 DPRINTK(" (for GD54xx)\n");
1350 printk(KERN_WARNING "cirrusfb: unknown Board\n");
1354 /* mode register: 256 color mode */
1355 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1356 /* pixel mask: pass-through all planes */
1357 WGen(cinfo, VGA_PEL_MSK, 0xff);
1358 if (regs.multiplexing)
1359 /* hidden dac reg: 1280x1024 */
1362 /* hidden dac: nothing */
1364 /* memory mode: chain4, ext. memory */
1365 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
1366 /* plane mask: enable writing to all 4 planes */
1367 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1368 offset = var->xres_virtual / 8;
1371 /******************************************************
1377 else if (var->bits_per_pixel == 16) {
1378 DPRINTK("cirrusfb: preparing for 16 bit deep display\n");
1379 switch (cinfo->btype) {
1381 /* Extended Sequencer Mode: 256c col. mode */
1382 vga_wseq(regbase, CL_SEQR7, 0xf7);
1384 vga_wseq(regbase, CL_SEQR1F, 0x1e);
1388 vga_wseq(regbase, CL_SEQR7, 0x87);
1389 /* Fast Page-Mode writes */
1390 vga_wseq(regbase, CL_SEQRF, 0xb0);
1392 vga_wseq(regbase, CL_SEQR1F, 0x22);
1396 vga_wseq(regbase, CL_SEQR7, 0x27);
1397 /* Fast Page-Mode writes */
1398 vga_wseq(regbase, CL_SEQRF, 0xb0);
1400 vga_wseq(regbase, CL_SEQR1F, 0x22);
1404 vga_wseq(regbase, CL_SEQR7, 0x87);
1405 /* Fast Page-Mode writes */
1406 vga_wseq(regbase, CL_SEQRF, 0xb0);
1408 vga_wseq(regbase, CL_SEQR1F, 0x22);
1412 vga_wseq(regbase, CL_SEQR7, 0x27);
1413 /* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
1417 DPRINTK(" (for GD543x)\n");
1418 if (regs.HorizRes >= 1024)
1419 vga_wseq(regbase, CL_SEQR7, 0xa7);
1421 vga_wseq(regbase, CL_SEQR7, 0xa3);
1422 cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK);
1426 DPRINTK(" (for GD5480)\n");
1427 vga_wseq(regbase, CL_SEQR7, 0x17);
1428 /* We already set SRF and SR1F */
1432 DPRINTK(" (for GD546x)\n");
1433 vga_wseq(regbase, CL_SEQR7,
1434 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1438 printk(KERN_WARNING "CIRRUSFB: unknown Board\n");
1442 /* mode register: 256 color mode */
1443 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1444 /* pixel mask: pass-through all planes */
1445 WGen(cinfo, VGA_PEL_MSK, 0xff);
1447 WHDR(cinfo, 0xc0); /* Copy Xbh */
1448 #elif defined(CONFIG_ZORRO)
1449 /* FIXME: CONFIG_PCI and CONFIG_ZORRO may be defined both */
1450 WHDR(cinfo, 0xa0); /* hidden dac reg: nothing special */
1452 /* memory mode: chain4, ext. memory */
1453 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
1454 /* plane mask: enable writing to all 4 planes */
1455 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1456 offset = var->xres_virtual / 4;
1459 /******************************************************
1465 else if (var->bits_per_pixel == 32) {
1466 DPRINTK("cirrusfb: preparing for 24/32 bit deep display\n");
1467 switch (cinfo->btype) {
1469 /* Extended Sequencer Mode: 256c col. mode */
1470 vga_wseq(regbase, CL_SEQR7, 0xf9);
1472 vga_wseq(regbase, CL_SEQR1F, 0x1e);
1476 vga_wseq(regbase, CL_SEQR7, 0x85);
1477 /* Fast Page-Mode writes */
1478 vga_wseq(regbase, CL_SEQRF, 0xb0);
1480 vga_wseq(regbase, CL_SEQR1F, 0x22);
1484 vga_wseq(regbase, CL_SEQR7, 0x25);
1485 /* Fast Page-Mode writes */
1486 vga_wseq(regbase, CL_SEQRF, 0xb0);
1488 vga_wseq(regbase, CL_SEQR1F, 0x22);
1492 vga_wseq(regbase, CL_SEQR7, 0x85);
1493 /* Fast Page-Mode writes */
1494 vga_wseq(regbase, CL_SEQRF, 0xb0);
1496 vga_wseq(regbase, CL_SEQR1F, 0x22);
1500 vga_wseq(regbase, CL_SEQR7, 0x25);
1501 /* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
1505 DPRINTK(" (for GD543x)\n");
1506 vga_wseq(regbase, CL_SEQR7, 0xa9);
1507 cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK);
1511 DPRINTK(" (for GD5480)\n");
1512 vga_wseq(regbase, CL_SEQR7, 0x19);
1513 /* We already set SRF and SR1F */
1517 DPRINTK(" (for GD546x)\n");
1518 vga_wseq(regbase, CL_SEQR7,
1519 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1523 printk(KERN_WARNING "cirrusfb: unknown Board\n");
1527 /* mode register: 256 color mode */
1528 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1529 /* pixel mask: pass-through all planes */
1530 WGen(cinfo, VGA_PEL_MSK, 0xff);
1531 /* hidden dac reg: 8-8-8 mode (24 or 32) */
1533 /* memory mode: chain4, ext. memory */
1534 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
1535 /* plane mask: enable writing to all 4 planes */
1536 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1537 offset = var->xres_virtual / 4;
1540 /******************************************************
1542 * unknown/unsupported bpp
1547 printk(KERN_ERR "cirrusfb: What's this?? "
1548 " requested color depth == %d.\n",
1549 var->bits_per_pixel);
1551 vga_wcrt(regbase, VGA_CRTC_OFFSET, offset & 0xff);
1554 tmp |= 0x10; /* offset overflow bit */
1556 /* screen start addr #16-18, fastpagemode cycles */
1557 vga_wcrt(regbase, CL_CRT1B, tmp);
1559 if (cinfo->btype == BT_SD64 ||
1560 cinfo->btype == BT_PICASSO4 ||
1561 cinfo->btype == BT_ALPINE ||
1562 cinfo->btype == BT_GD5480)
1563 /* screen start address bit 19 */
1564 vga_wcrt(regbase, CL_CRT1D, 0x00);
1566 /* text cursor location high */
1567 vga_wcrt(regbase, VGA_CRTC_CURSOR_HI, 0);
1568 /* text cursor location low */
1569 vga_wcrt(regbase, VGA_CRTC_CURSOR_LO, 0);
1570 /* underline row scanline = at very bottom */
1571 vga_wcrt(regbase, VGA_CRTC_UNDERLINE, 0);
1573 /* controller mode */
1574 vga_wattr(regbase, VGA_ATC_MODE, 1);
1575 /* overscan (border) color */
1576 vga_wattr(regbase, VGA_ATC_OVERSCAN, 0);
1577 /* color plane enable */
1578 vga_wattr(regbase, VGA_ATC_PLANE_ENABLE, 15);
1580 vga_wattr(regbase, CL_AR33, 0);
1582 vga_wattr(regbase, VGA_ATC_COLOR_PAGE, 0);
1584 /* [ EGS: SetOffset(); ] */
1585 /* From SetOffset(): Turn on VideoEnable bit in Attribute controller */
1588 /* set/reset register */
1589 vga_wgfx(regbase, VGA_GFX_SR_VALUE, 0);
1590 /* set/reset enable */
1591 vga_wgfx(regbase, VGA_GFX_SR_ENABLE, 0);
1593 vga_wgfx(regbase, VGA_GFX_COMPARE_VALUE, 0);
1595 vga_wgfx(regbase, VGA_GFX_DATA_ROTATE, 0);
1596 /* read map select */
1597 vga_wgfx(regbase, VGA_GFX_PLANE_READ, 0);
1598 /* miscellaneous register */
1599 vga_wgfx(regbase, VGA_GFX_MISC, 1);
1600 /* color don't care */
1601 vga_wgfx(regbase, VGA_GFX_COMPARE_MASK, 15);
1603 vga_wgfx(regbase, VGA_GFX_BIT_MASK, 255);
1605 /* graphics cursor attributes: nothing special */
1606 vga_wseq(regbase, CL_SEQR12, 0x0);
1608 /* finally, turn on everything - turn off "FullBandwidth" bit */
1609 /* also, set "DotClock%2" bit where requested */
1612 /*** FB_VMODE_CLOCK_HALVE in linux/fb.h not defined anymore ?
1613 if (var->vmode & FB_VMODE_CLOCK_HALVE)
1617 vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, tmp);
1618 DPRINTK("CL_SEQR1: %d\n", tmp);
1620 cinfo->currentmode = regs;
1621 info->fix.type = regs.type;
1622 info->fix.visual = regs.visual;
1623 info->fix.line_length = regs.line_length;
1625 /* pan to requested offset */
1626 cirrusfb_pan_display(var, info);
1628 #ifdef CIRRUSFB_DEBUG
1636 /* for some reason incomprehensible to me, cirrusfb requires that you write
1637 * the registers twice for the settings to take..grr. -dte */
1638 static int cirrusfb_set_par(struct fb_info *info)
1640 cirrusfb_set_par_foo(info);
1641 return cirrusfb_set_par_foo(info);
1644 static int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1645 unsigned blue, unsigned transp,
1646 struct fb_info *info)
1648 struct cirrusfb_info *cinfo = info->par;
1653 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
1655 red >>= (16 - info->var.red.length);
1656 green >>= (16 - info->var.green.length);
1657 blue >>= (16 - info->var.blue.length);
1661 v = (red << info->var.red.offset) |
1662 (green << info->var.green.offset) |
1663 (blue << info->var.blue.offset);
1665 switch (info->var.bits_per_pixel) {
1667 cinfo->pseudo_palette[regno] = v;
1670 cinfo->pseudo_palette[regno] = v;
1674 cinfo->pseudo_palette[regno] = v;
1680 if (info->var.bits_per_pixel == 8)
1681 WClut(cinfo, regno, red >> 10, green >> 10, blue >> 10);
1687 /*************************************************************************
1688 cirrusfb_pan_display()
1690 performs display panning - provided hardware permits this
1691 **************************************************************************/
1692 static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
1693 struct fb_info *info)
1698 unsigned char tmp = 0, tmp2 = 0, xpix;
1699 struct cirrusfb_info *cinfo = info->par;
1702 DPRINTK("virtual offset: (%d,%d)\n", var->xoffset, var->yoffset);
1704 /* no range checks for xoffset and yoffset, */
1705 /* as fb_pan_display has already done this */
1706 if (var->vmode & FB_VMODE_YWRAP)
1709 info->var.xoffset = var->xoffset;
1710 info->var.yoffset = var->yoffset;
1712 xoffset = var->xoffset * info->var.bits_per_pixel / 8;
1713 yoffset = var->yoffset;
1715 base = yoffset * cinfo->currentmode.line_length + xoffset;
1717 if (info->var.bits_per_pixel == 1) {
1718 /* base is already correct */
1719 xpix = (unsigned char) (var->xoffset % 8);
1722 xpix = (unsigned char) ((xoffset % 4) * 2);
1725 cirrusfb_WaitBLT(cinfo->regbase); /* make sure all the BLT's are done */
1727 /* lower 8 + 8 bits of screen start address */
1728 vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO,
1729 (unsigned char) (base & 0xff));
1730 vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI,
1731 (unsigned char) (base >> 8));
1733 /* construct bits 16, 17 and 18 of screen start address */
1741 /* 0xf2 is %11110010, exclude tmp bits */
1742 tmp2 = (vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2) | tmp;
1743 vga_wcrt(cinfo->regbase, CL_CRT1B, tmp2);
1745 /* construct bit 19 of screen start address */
1746 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) {
1750 vga_wcrt(cinfo->regbase, CL_CRT1D, tmp2);
1753 /* write pixel panning value to AR33; this does not quite work in 8bpp
1755 * ### Piccolo..? Will this work?
1757 if (info->var.bits_per_pixel == 1)
1758 vga_wattr(cinfo->regbase, CL_AR33, xpix);
1760 cirrusfb_WaitBLT(cinfo->regbase);
1766 static int cirrusfb_blank(int blank_mode, struct fb_info *info)
1769 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
1770 * then the caller blanks by setting the CLUT (Color Look Up Table)
1771 * to all black. Return 0 if blanking succeeded, != 0 if un-/blanking
1772 * failed due to e.g. a video mode which doesn't support it.
1773 * Implements VESA suspend and powerdown modes on hardware that
1774 * supports disabling hsync/vsync:
1775 * blank_mode == 2: suspend vsync
1776 * blank_mode == 3: suspend hsync
1777 * blank_mode == 4: powerdown
1780 struct cirrusfb_info *cinfo = info->par;
1781 int current_mode = cinfo->blank_mode;
1783 DPRINTK("ENTER, blank mode = %d\n", blank_mode);
1785 if (info->state != FBINFO_STATE_RUNNING ||
1786 current_mode == blank_mode) {
1787 DPRINTK("EXIT, returning 0\n");
1792 if (current_mode == FB_BLANK_NORMAL ||
1793 current_mode == FB_BLANK_UNBLANK) {
1794 /* unblank the screen */
1795 val = vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE);
1796 /* clear "FullBandwidth" bit */
1797 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val & 0xdf);
1798 /* and undo VESA suspend trickery */
1799 vga_wgfx(cinfo->regbase, CL_GRE, 0x00);
1803 if (blank_mode > FB_BLANK_NORMAL) {
1804 /* blank the screen */
1805 val = vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE);
1806 /* set "FullBandwidth" bit */
1807 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val | 0x20);
1810 switch (blank_mode) {
1811 case FB_BLANK_UNBLANK:
1812 case FB_BLANK_NORMAL:
1814 case FB_BLANK_VSYNC_SUSPEND:
1815 vga_wgfx(cinfo->regbase, CL_GRE, 0x04);
1817 case FB_BLANK_HSYNC_SUSPEND:
1818 vga_wgfx(cinfo->regbase, CL_GRE, 0x02);
1820 case FB_BLANK_POWERDOWN:
1821 vga_wgfx(cinfo->regbase, CL_GRE, 0x06);
1824 DPRINTK("EXIT, returning 1\n");
1828 cinfo->blank_mode = blank_mode;
1829 DPRINTK("EXIT, returning 0\n");
1831 /* Let fbcon do a soft blank for us */
1832 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1834 /**** END Hardware specific Routines **************************************/
1835 /****************************************************************************/
1836 /**** BEGIN Internal Routines ***********************************************/
1838 static void init_vgachip(struct fb_info *info)
1840 struct cirrusfb_info *cinfo = info->par;
1841 const struct cirrusfb_board_info_rec *bi;
1845 assert(cinfo != NULL);
1847 bi = &cirrusfb_board_info[cinfo->btype];
1849 /* reset board globally */
1850 switch (cinfo->btype) {
1869 /* disable flickerfixer */
1870 vga_wcrt(cinfo->regbase, CL_CRT51, 0x00);
1872 /* from Klaus' NetBSD driver: */
1873 vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
1874 /* put blitter into 542x compat */
1875 vga_wgfx(cinfo->regbase, CL_GR33, 0x00);
1877 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
1881 /* from Klaus' NetBSD driver: */
1882 vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
1886 /* Nothing to do to reset the board. */
1890 printk(KERN_ERR "cirrusfb: Warning: Unknown board type\n");
1894 /* make sure RAM size set by this point */
1895 assert(info->screen_size > 0);
1897 /* the P4 is not fully initialized here; I rely on it having been */
1898 /* inited under AmigaOS already, which seems to work just fine */
1899 /* (Klaus advised to do it this way) */
1901 if (cinfo->btype != BT_PICASSO4) {
1902 WGen(cinfo, CL_VSSM, 0x10); /* EGS: 0x16 */
1903 WGen(cinfo, CL_POS102, 0x01);
1904 WGen(cinfo, CL_VSSM, 0x08); /* EGS: 0x0e */
1906 if (cinfo->btype != BT_SD64)
1907 WGen(cinfo, CL_VSSM2, 0x01);
1909 /* reset sequencer logic */
1910 vga_wseq(cinfo->regbase, CL_SEQR0, 0x03);
1912 /* FullBandwidth (video off) and 8/9 dot clock */
1913 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21);
1914 /* polarity (-/-), disable access to display memory,
1915 * VGA_CRTC_START_HI base address: color
1917 WGen(cinfo, VGA_MIS_W, 0xc1);
1919 /* "magic cookie" - doesn't make any sense to me.. */
1920 /* vga_wgfx(cinfo->regbase, CL_GRA, 0xce); */
1921 /* unlock all extension registers */
1922 vga_wseq(cinfo->regbase, CL_SEQR6, 0x12);
1925 vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
1927 switch (cinfo->btype) {
1929 vga_wseq(cinfo->regbase, CL_SEQRF, 0x98);
1934 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8);
1937 vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f);
1938 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb0);
1942 /* plane mask: nothing */
1943 vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1944 /* character map select: doesn't even matter in gx mode */
1945 vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00);
1946 /* memory mode: chain-4, no odd/even, ext. memory */
1947 vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0e);
1949 /* controller-internal base address of video memory */
1951 vga_wseq(cinfo->regbase, CL_SEQR7, bi->sr07);
1953 /* vga_wseq(cinfo->regbase, CL_SEQR8, 0x00); */
1954 /* EEPROM control: shouldn't be necessary to write to this at all.. */
1956 /* graphics cursor X position (incomplete; position gives rem. 3 bits */
1957 vga_wseq(cinfo->regbase, CL_SEQR10, 0x00);
1958 /* graphics cursor Y position (..."... ) */
1959 vga_wseq(cinfo->regbase, CL_SEQR11, 0x00);
1960 /* graphics cursor attributes */
1961 vga_wseq(cinfo->regbase, CL_SEQR12, 0x00);
1962 /* graphics cursor pattern address */
1963 vga_wseq(cinfo->regbase, CL_SEQR13, 0x00);
1965 /* writing these on a P4 might give problems.. */
1966 if (cinfo->btype != BT_PICASSO4) {
1967 /* configuration readback and ext. color */
1968 vga_wseq(cinfo->regbase, CL_SEQR17, 0x00);
1969 /* signature generator */
1970 vga_wseq(cinfo->regbase, CL_SEQR18, 0x02);
1973 /* MCLK select etc. */
1975 vga_wseq(cinfo->regbase, CL_SEQR1F, bi->sr1f);
1977 /* Screen A preset row scan: none */
1978 vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00);
1979 /* Text cursor start: disable text cursor */
1980 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20);
1981 /* Text cursor end: - */
1982 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00);
1983 /* Screen start address high: 0 */
1984 vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, 0x00);
1985 /* Screen start address low: 0 */
1986 vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, 0x00);
1987 /* text cursor location high: 0 */
1988 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00);
1989 /* text cursor location low: 0 */
1990 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00);
1992 /* Underline Row scanline: - */
1993 vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00);
1994 /* mode control: timing enable, byte mode, no compat modes */
1995 vga_wcrt(cinfo->regbase, VGA_CRTC_MODE, 0xc3);
1996 /* Line Compare: not needed */
1997 vga_wcrt(cinfo->regbase, VGA_CRTC_LINE_COMPARE, 0x00);
1998 /* ### add 0x40 for text modes with > 30 MHz pixclock */
1999 /* ext. display controls: ext.adr. wrap */
2000 vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02);
2002 /* Set/Reset registes: - */
2003 vga_wgfx(cinfo->regbase, VGA_GFX_SR_VALUE, 0x00);
2004 /* Set/Reset enable: - */
2005 vga_wgfx(cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00);
2006 /* Color Compare: - */
2007 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00);
2008 /* Data Rotate: - */
2009 vga_wgfx(cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00);
2010 /* Read Map Select: - */
2011 vga_wgfx(cinfo->regbase, VGA_GFX_PLANE_READ, 0x00);
2012 /* Mode: conf. for 16/4/2 color mode, no odd/even, read/write mode 0 */
2013 vga_wgfx(cinfo->regbase, VGA_GFX_MODE, 0x00);
2014 /* Miscellaneous: memory map base address, graphics mode */
2015 vga_wgfx(cinfo->regbase, VGA_GFX_MISC, 0x01);
2016 /* Color Don't care: involve all planes */
2017 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f);
2018 /* Bit Mask: no mask at all */
2019 vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff);
2020 if (cinfo->btype == BT_ALPINE)
2021 /* (5434 can't have bit 3 set for bitblt) */
2022 vga_wgfx(cinfo->regbase, CL_GRB, 0x20);
2024 /* Graphics controller mode extensions: finer granularity,
2025 * 8byte data latches
2027 vga_wgfx(cinfo->regbase, CL_GRB, 0x28);
2029 vga_wgfx(cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */
2030 vga_wgfx(cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */
2031 vga_wgfx(cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */
2032 /* Background color byte 1: - */
2033 /* vga_wgfx (cinfo->regbase, CL_GR10, 0x00); */
2034 /* vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */
2036 /* Attribute Controller palette registers: "identity mapping" */
2037 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE0, 0x00);
2038 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE1, 0x01);
2039 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE2, 0x02);
2040 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE3, 0x03);
2041 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE4, 0x04);
2042 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE5, 0x05);
2043 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE6, 0x06);
2044 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE7, 0x07);
2045 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE8, 0x08);
2046 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE9, 0x09);
2047 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEA, 0x0a);
2048 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEB, 0x0b);
2049 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEC, 0x0c);
2050 vga_wattr(cinfo->regbase, VGA_ATC_PALETTED, 0x0d);
2051 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEE, 0x0e);
2052 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEF, 0x0f);
2054 /* Attribute Controller mode: graphics mode */
2055 vga_wattr(cinfo->regbase, VGA_ATC_MODE, 0x01);
2056 /* Overscan color reg.: reg. 0 */
2057 vga_wattr(cinfo->regbase, VGA_ATC_OVERSCAN, 0x00);
2058 /* Color Plane enable: Enable all 4 planes */
2059 vga_wattr(cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f);
2060 /* ### vga_wattr(cinfo->regbase, CL_AR33, 0x00); * Pixel Panning: - */
2061 /* Color Select: - */
2062 vga_wattr(cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00);
2064 WGen(cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask */
2066 if (cinfo->btype != BT_ALPINE && cinfo->btype != BT_GD5480)
2067 /* polarity (-/-), enable display mem,
2068 * VGA_CRTC_START_HI i/o base = color
2070 WGen(cinfo, VGA_MIS_W, 0xc3);
2072 /* BLT Start/status: Blitter reset */
2073 vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
2074 /* - " - : "end-of-reset" */
2075 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
2078 WHDR(cinfo, 0); /* Hidden DAC register: - */
2080 printk(KERN_DEBUG "cirrusfb: This board has %ld bytes of DRAM memory\n",
2086 static void switch_monitor(struct cirrusfb_info *cinfo, int on)
2088 #ifdef CONFIG_ZORRO /* only works on Zorro boards */
2089 static int IsOn = 0; /* XXX not ok for multiple boards */
2093 if (cinfo->btype == BT_PICASSO4)
2094 return; /* nothing to switch */
2095 if (cinfo->btype == BT_ALPINE)
2096 return; /* nothing to switch */
2097 if (cinfo->btype == BT_GD5480)
2098 return; /* nothing to switch */
2099 if (cinfo->btype == BT_PICASSO) {
2100 if ((on && !IsOn) || (!on && IsOn))
2107 switch (cinfo->btype) {
2109 WSFR(cinfo, cinfo->SFR | 0x21);
2112 WSFR(cinfo, cinfo->SFR | 0x28);
2117 default: /* do nothing */ break;
2120 switch (cinfo->btype) {
2122 WSFR(cinfo, cinfo->SFR & 0xde);
2125 WSFR(cinfo, cinfo->SFR & 0xd7);
2130 default: /* do nothing */ break;
2135 #endif /* CONFIG_ZORRO */
2138 /******************************************/
2139 /* Linux 2.6-style accelerated functions */
2140 /******************************************/
2142 static void cirrusfb_prim_fillrect(struct fb_info *info,
2143 const struct fb_fillrect *region)
2145 struct cirrusfb_info *cinfo = info->par;
2146 int m; /* bytes per pixel */
2147 u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
2148 cinfo->pseudo_palette[region->color] : region->color;
2150 if (info->var.bits_per_pixel == 1) {
2151 cirrusfb_RectFill(cinfo->regbase,
2152 info->var.bits_per_pixel,
2153 region->dx / 8, region->dy,
2154 region->width / 8, region->height,
2156 cinfo->currentmode.line_length);
2158 m = (info->var.bits_per_pixel + 7) / 8;
2159 cirrusfb_RectFill(cinfo->regbase,
2160 info->var.bits_per_pixel,
2161 region->dx * m, region->dy,
2162 region->width * m, region->height,
2164 cinfo->currentmode.line_length);
2169 static void cirrusfb_fillrect(struct fb_info *info,
2170 const struct fb_fillrect *region)
2172 struct fb_fillrect modded;
2175 if (info->state != FBINFO_STATE_RUNNING)
2177 if (info->flags & FBINFO_HWACCEL_DISABLED) {
2178 cfb_fillrect(info, region);
2182 vxres = info->var.xres_virtual;
2183 vyres = info->var.yres_virtual;
2185 memcpy(&modded, region, sizeof(struct fb_fillrect));
2187 if (!modded.width || !modded.height ||
2188 modded.dx >= vxres || modded.dy >= vyres)
2191 if (modded.dx + modded.width > vxres)
2192 modded.width = vxres - modded.dx;
2193 if (modded.dy + modded.height > vyres)
2194 modded.height = vyres - modded.dy;
2196 cirrusfb_prim_fillrect(info, &modded);
2199 static void cirrusfb_prim_copyarea(struct fb_info *info,
2200 const struct fb_copyarea *area)
2202 struct cirrusfb_info *cinfo = info->par;
2203 int m; /* bytes per pixel */
2205 if (info->var.bits_per_pixel == 1) {
2206 cirrusfb_BitBLT(cinfo->regbase, info->var.bits_per_pixel,
2207 area->sx / 8, area->sy,
2208 area->dx / 8, area->dy,
2209 area->width / 8, area->height,
2210 cinfo->currentmode.line_length);
2212 m = (info->var.bits_per_pixel + 7) / 8;
2213 cirrusfb_BitBLT(cinfo->regbase, info->var.bits_per_pixel,
2214 area->sx * m, area->sy,
2215 area->dx * m, area->dy,
2216 area->width * m, area->height,
2217 cinfo->currentmode.line_length);
2222 static void cirrusfb_copyarea(struct fb_info *info,
2223 const struct fb_copyarea *area)
2225 struct fb_copyarea modded;
2228 modded.sx = area->sx;
2229 modded.sy = area->sy;
2230 modded.dx = area->dx;
2231 modded.dy = area->dy;
2232 modded.width = area->width;
2233 modded.height = area->height;
2235 if (info->state != FBINFO_STATE_RUNNING)
2237 if (info->flags & FBINFO_HWACCEL_DISABLED) {
2238 cfb_copyarea(info, area);
2242 vxres = info->var.xres_virtual;
2243 vyres = info->var.yres_virtual;
2245 if (!modded.width || !modded.height ||
2246 modded.sx >= vxres || modded.sy >= vyres ||
2247 modded.dx >= vxres || modded.dy >= vyres)
2250 if (modded.sx + modded.width > vxres)
2251 modded.width = vxres - modded.sx;
2252 if (modded.dx + modded.width > vxres)
2253 modded.width = vxres - modded.dx;
2254 if (modded.sy + modded.height > vyres)
2255 modded.height = vyres - modded.sy;
2256 if (modded.dy + modded.height > vyres)
2257 modded.height = vyres - modded.dy;
2259 cirrusfb_prim_copyarea(info, &modded);
2262 static void cirrusfb_imageblit(struct fb_info *info,
2263 const struct fb_image *image)
2265 struct cirrusfb_info *cinfo = info->par;
2267 cirrusfb_WaitBLT(cinfo->regbase);
2268 cfb_imageblit(info, image);
2271 #ifdef CONFIG_PPC_PREP
2272 #define PREP_VIDEO_BASE ((volatile unsigned long) 0xC0000000)
2273 #define PREP_IO_BASE ((volatile unsigned char *) 0x80000000)
2274 static void get_prep_addrs(unsigned long *display, unsigned long *registers)
2278 *display = PREP_VIDEO_BASE;
2279 *registers = (unsigned long) PREP_IO_BASE;
2284 #endif /* CONFIG_PPC_PREP */
2287 static int release_io_ports;
2289 /* Pulled the logic from XFree86 Cirrus driver to get the memory size,
2290 * based on the DRAM bandwidth bit and DRAM bank switching bit. This
2291 * works with 1MB, 2MB and 4MB configurations (which the Motorola boards
2293 static unsigned int cirrusfb_get_memsize(u8 __iomem *regbase)
2300 SRF = vga_rseq(regbase, CL_SEQRF);
2301 switch ((SRF & 0x18)) {
2308 /* 64-bit DRAM data bus width; assume 2MB. Also indicates 2MB memory
2315 printk(KERN_WARNING "CLgenfb: Unknown memory size!\n");
2319 /* If DRAM bank switching is enabled, there must be twice as much
2320 * memory installed. (4MB on the 5434)
2324 /* TODO: Handling of GD5446/5480 (see XF86 sources ...) */
2330 static void get_pci_addrs(const struct pci_dev *pdev,
2331 unsigned long *display, unsigned long *registers)
2333 assert(pdev != NULL);
2334 assert(display != NULL);
2335 assert(registers != NULL);
2342 /* This is a best-guess for now */
2344 if (pci_resource_flags(pdev, 0) & IORESOURCE_IO) {
2345 *display = pci_resource_start(pdev, 1);
2346 *registers = pci_resource_start(pdev, 0);
2348 *display = pci_resource_start(pdev, 0);
2349 *registers = pci_resource_start(pdev, 1);
2352 assert(*display != 0);
2357 static void cirrusfb_pci_unmap(struct fb_info *info)
2359 struct cirrusfb_info *cinfo = info->par;
2360 struct pci_dev *pdev = cinfo->pdev;
2362 iounmap(info->screen_base);
2363 #if 0 /* if system didn't claim this region, we would... */
2364 release_mem_region(0xA0000, 65535);
2366 if (release_io_ports)
2367 release_region(0x3C0, 32);
2368 pci_release_regions(pdev);
2369 framebuffer_release(info);
2371 #endif /* CONFIG_PCI */
2374 static void __devexit cirrusfb_zorro_unmap(struct cirrusfb_info *cinfo)
2376 zorro_release_device(cinfo->zdev);
2378 if (cinfo->btype == BT_PICASSO4) {
2379 cinfo->regbase -= 0x600000;
2380 iounmap((void *)cinfo->regbase);
2381 iounmap(info->screen_base);
2383 if (zorro_resource_start(cinfo->zdev) > 0x01000000)
2384 iounmap(info->screen_base);
2386 framebuffer_release(cinfo->info);
2388 #endif /* CONFIG_ZORRO */
2390 static int cirrusfb_set_fbinfo(struct fb_info *info)
2392 struct cirrusfb_info *cinfo = info->par;
2393 struct fb_var_screeninfo *var = &info->var;
2395 info->pseudo_palette = cinfo->pseudo_palette;
2396 info->flags = FBINFO_DEFAULT
2397 | FBINFO_HWACCEL_XPAN
2398 | FBINFO_HWACCEL_YPAN
2399 | FBINFO_HWACCEL_FILLRECT
2400 | FBINFO_HWACCEL_COPYAREA;
2402 info->flags |= FBINFO_HWACCEL_DISABLED;
2403 info->fbops = &cirrusfb_ops;
2404 if (cinfo->btype == BT_GD5480) {
2405 if (var->bits_per_pixel == 16)
2406 info->screen_base += 1 * MB_;
2407 if (var->bits_per_pixel == 24 || var->bits_per_pixel == 32)
2408 info->screen_base += 2 * MB_;
2411 /* Fill fix common fields */
2412 strlcpy(info->fix.id, cirrusfb_board_info[cinfo->btype].name,
2413 sizeof(info->fix.id));
2415 /* monochrome: only 1 memory plane */
2416 /* 8 bit and above: Use whole memory area */
2417 info->fix.smem_len = info->screen_size;
2418 if (var->bits_per_pixel == 1)
2419 info->fix.smem_len /= 4;
2420 info->fix.type = cinfo->currentmode.type;
2421 info->fix.type_aux = 0;
2422 info->fix.visual = cinfo->currentmode.visual;
2423 info->fix.xpanstep = 1;
2424 info->fix.ypanstep = 1;
2425 info->fix.ywrapstep = 0;
2426 info->fix.line_length = cinfo->currentmode.line_length;
2428 /* FIXME: map region at 0xB8000 if available, fill in here */
2429 info->fix.mmio_len = 0;
2430 info->fix.accel = FB_ACCEL_NONE;
2432 fb_alloc_cmap(&info->cmap, 256, 0);
2437 static int cirrusfb_register(struct fb_info *info)
2439 struct cirrusfb_info *cinfo = info->par;
2441 enum cirrus_board btype;
2445 printk(KERN_INFO "cirrusfb: Driver for Cirrus Logic based "
2446 "graphic boards, v" CIRRUSFB_VERSION "\n");
2448 btype = cinfo->btype;
2451 assert(btype != BT_NONE);
2453 DPRINTK("cirrusfb: (RAM start set to: 0x%p)\n", info->screen_base);
2455 /* Make pretend we've set the var so our structures are in a "good" */
2456 /* state, even though we haven't written the mode to the hw yet... */
2457 info->var = cirrusfb_predefined[cirrusfb_def_mode].var;
2458 info->var.activate = FB_ACTIVATE_NOW;
2460 err = cirrusfb_decode_var(&info->var, &cinfo->currentmode, info);
2462 /* should never happen */
2463 DPRINTK("choking on default var... umm, no good.\n");
2464 goto err_unmap_cirrusfb;
2467 /* set all the vital stuff */
2468 cirrusfb_set_fbinfo(info);
2470 err = register_framebuffer(info);
2472 printk(KERN_ERR "cirrusfb: could not register "
2473 "fb device; err = %d!\n", err);
2474 goto err_dealloc_cmap;
2477 DPRINTK("EXIT, returning 0\n");
2481 fb_dealloc_cmap(&info->cmap);
2487 static void __devexit cirrusfb_cleanup(struct fb_info *info)
2489 struct cirrusfb_info *cinfo = info->par;
2492 switch_monitor(cinfo, 0);
2494 unregister_framebuffer(info);
2495 fb_dealloc_cmap(&info->cmap);
2496 printk("Framebuffer unregistered\n");
2503 static int cirrusfb_pci_register(struct pci_dev *pdev,
2504 const struct pci_device_id *ent)
2506 struct cirrusfb_info *cinfo;
2507 struct fb_info *info;
2508 enum cirrus_board btype;
2509 unsigned long board_addr, board_size;
2512 ret = pci_enable_device(pdev);
2514 printk(KERN_ERR "cirrusfb: Cannot enable PCI device\n");
2518 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &pdev->dev);
2520 printk(KERN_ERR "cirrusfb: could not allocate memory\n");
2527 cinfo->btype = btype = (enum cirrus_board) ent->driver_data;
2529 DPRINTK(" Found PCI device, base address 0 is 0x%x, btype set to %d\n",
2530 pdev->resource[0].start, btype);
2531 DPRINTK(" base address 1 is 0x%x\n", pdev->resource[1].start);
2534 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, 0x00000000);
2535 #ifdef CONFIG_PPC_PREP
2536 get_prep_addrs(&board_addr, &info->fix.mmio_start);
2538 /* PReP dies if we ioremap the IO registers, but it works w/out... */
2539 cinfo->regbase = (char __iomem *) info->fix.mmio_start;
2541 DPRINTK("Attempt to get PCI info for Cirrus Graphics Card\n");
2542 get_pci_addrs(pdev, &board_addr, &info->fix.mmio_start);
2543 /* FIXME: this forces VGA. alternatives? */
2544 cinfo->regbase = NULL;
2547 DPRINTK("Board address: 0x%lx, register address: 0x%lx\n",
2548 board_addr, info->fix.mmio_start);
2550 board_size = (btype == BT_GD5480) ?
2551 32 * MB_ : cirrusfb_get_memsize(cinfo->regbase);
2553 ret = pci_request_regions(pdev, "cirrusfb");
2555 printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, "
2558 goto err_release_fb;
2560 #if 0 /* if the system didn't claim this region, we would... */
2561 if (!request_mem_region(0xA0000, 65535, "cirrusfb")) {
2562 printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, abort\n"
2566 goto err_release_regions;
2569 if (request_region(0x3C0, 32, "cirrusfb"))
2570 release_io_ports = 1;
2572 info->screen_base = ioremap(board_addr, board_size);
2573 if (!info->screen_base) {
2575 goto err_release_legacy;
2578 info->fix.smem_start = board_addr;
2579 info->screen_size = board_size;
2580 cinfo->unmap = cirrusfb_pci_unmap;
2582 printk(KERN_INFO " RAM (%lu kB) at 0xx%lx, ",
2583 info->screen_size / KB_, board_addr);
2584 printk(KERN_INFO "Cirrus Logic chipset on PCI bus\n");
2585 pci_set_drvdata(pdev, info);
2587 ret = cirrusfb_register(info);
2589 iounmap(info->screen_base);
2593 if (release_io_ports)
2594 release_region(0x3C0, 32);
2596 release_mem_region(0xA0000, 65535);
2597 err_release_regions:
2599 pci_release_regions(pdev);
2601 framebuffer_release(info);
2607 static void __devexit cirrusfb_pci_unregister(struct pci_dev *pdev)
2609 struct fb_info *info = pci_get_drvdata(pdev);
2612 cirrusfb_cleanup(info);
2617 static struct pci_driver cirrusfb_pci_driver = {
2619 .id_table = cirrusfb_pci_table,
2620 .probe = cirrusfb_pci_register,
2621 .remove = __devexit_p(cirrusfb_pci_unregister),
2624 .suspend = cirrusfb_pci_suspend,
2625 .resume = cirrusfb_pci_resume,
2629 #endif /* CONFIG_PCI */
2632 static int cirrusfb_zorro_register(struct zorro_dev *z,
2633 const struct zorro_device_id *ent)
2635 struct cirrusfb_info *cinfo;
2636 struct fb_info *info;
2637 enum cirrus_board btype;
2638 struct zorro_dev *z2 = NULL;
2639 unsigned long board_addr, board_size, size;
2642 btype = ent->driver_data;
2643 if (cirrusfb_zorro_table2[btype].id2)
2644 z2 = zorro_find_device(cirrusfb_zorro_table2[btype].id2, NULL);
2645 size = cirrusfb_zorro_table2[btype].size;
2646 printk(KERN_INFO "cirrusfb: %s board detected; ",
2647 cirrusfb_board_info[btype].name);
2649 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &z->dev);
2651 printk(KERN_ERR "cirrusfb: could not allocate memory\n");
2658 cinfo->btype = btype;
2662 assert(btype != BT_NONE);
2665 board_addr = zorro_resource_start(z);
2666 board_size = zorro_resource_len(z);
2667 info->screen_size = size;
2669 if (!zorro_request_device(z, "cirrusfb")) {
2670 printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, "
2674 goto err_release_fb;
2677 printk(" RAM (%lu MB) at $%lx, ", board_size / MB_, board_addr);
2681 if (btype == BT_PICASSO4) {
2682 printk(KERN_INFO " REG at $%lx\n", board_addr + 0x600000);
2684 /* To be precise, for the P4 this is not the */
2685 /* begin of the board, but the begin of RAM. */
2686 /* for P4, map in its address space in 2 chunks (### TEST! ) */
2687 /* (note the ugly hardcoded 16M number) */
2688 cinfo->regbase = ioremap(board_addr, 16777216);
2689 if (!cinfo->regbase)
2690 goto err_release_region;
2692 DPRINTK("cirrusfb: Virtual address for board set to: $%p\n",
2694 cinfo->regbase += 0x600000;
2695 info->fix.mmio_start = board_addr + 0x600000;
2697 info->fix.smem_start = board_addr + 16777216;
2698 info->screen_base = ioremap(info->fix.smem_start, 16777216);
2699 if (!info->screen_base)
2700 goto err_unmap_regbase;
2702 printk(KERN_INFO " REG at $%lx\n",
2703 (unsigned long) z2->resource.start);
2705 info->fix.smem_start = board_addr;
2706 if (board_addr > 0x01000000)
2707 info->screen_base = ioremap(board_addr, board_size);
2709 info->screen_base = (caddr_t) ZTWO_VADDR(board_addr);
2710 if (!info->screen_base)
2711 goto err_release_region;
2713 /* set address for REG area of board */
2714 cinfo->regbase = (caddr_t) ZTWO_VADDR(z2->resource.start);
2715 info->fix.mmio_start = z2->resource.start;
2717 DPRINTK("cirrusfb: Virtual address for board set to: $%p\n",
2720 cinfo->unmap = cirrusfb_zorro_unmap;
2722 printk(KERN_INFO "Cirrus Logic chipset on Zorro bus\n");
2723 zorro_set_drvdata(z, info);
2725 ret = cirrusfb_register(cinfo);
2727 if (btype == BT_PICASSO4) {
2728 iounmap(info->screen_base);
2729 iounmap(cinfo->regbase - 0x600000);
2730 } else if (board_addr > 0x01000000)
2731 iounmap(info->screen_base);
2736 /* Parental advisory: explicit hack */
2737 iounmap(cinfo->regbase - 0x600000);
2739 release_region(board_addr, board_size);
2741 framebuffer_release(info);
2746 void __devexit cirrusfb_zorro_unregister(struct zorro_dev *z)
2748 struct fb_info *info = zorro_get_drvdata(z);
2751 cirrusfb_cleanup(info);
2756 static struct zorro_driver cirrusfb_zorro_driver = {
2758 .id_table = cirrusfb_zorro_table,
2759 .probe = cirrusfb_zorro_register,
2760 .remove = __devexit_p(cirrusfb_zorro_unregister),
2762 #endif /* CONFIG_ZORRO */
2764 static int __init cirrusfb_init(void)
2769 char *option = NULL;
2771 if (fb_get_options("cirrusfb", &option))
2773 cirrusfb_setup(option);
2777 error |= zorro_register_driver(&cirrusfb_zorro_driver);
2780 error |= pci_register_driver(&cirrusfb_pci_driver);
2786 static int __init cirrusfb_setup(char *options) {
2787 char *this_opt, s[32];
2792 if (!options || !*options)
2795 while ((this_opt = strsep(&options, ",")) != NULL) {
2796 if (!*this_opt) continue;
2798 DPRINTK("cirrusfb_setup: option '%s'\n", this_opt);
2800 for (i = 0; i < NUM_TOTAL_MODES; i++) {
2801 sprintf(s, "mode:%s", cirrusfb_predefined[i].name);
2802 if (strcmp(this_opt, s) == 0)
2803 cirrusfb_def_mode = i;
2805 if (!strcmp(this_opt, "noaccel"))
2816 MODULE_AUTHOR("Copyright 1999,2000 Jeff Garzik <jgarzik@pobox.com>");
2817 MODULE_DESCRIPTION("Accelerated FBDev driver for Cirrus Logic chips");
2818 MODULE_LICENSE("GPL");
2820 static void __exit cirrusfb_exit(void)
2823 pci_unregister_driver(&cirrusfb_pci_driver);
2826 zorro_unregister_driver(&cirrusfb_zorro_driver);
2830 module_init(cirrusfb_init);
2833 module_exit(cirrusfb_exit);
2836 /**********************************************************************/
2837 /* about the following functions - I have used the same names for the */
2838 /* functions as Markus Wild did in his Retina driver for NetBSD as */
2839 /* they just made sense for this purpose. Apart from that, I wrote */
2840 /* these functions myself. */
2841 /**********************************************************************/
2843 /*** WGen() - write into one of the external/general registers ***/
2844 static void WGen(const struct cirrusfb_info *cinfo,
2845 int regnum, unsigned char val)
2847 unsigned long regofs = 0;
2849 if (cinfo->btype == BT_PICASSO) {
2850 /* Picasso II specific hack */
2851 /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
2852 regnum == CL_VSSM2) */
2853 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
2857 vga_w(cinfo->regbase, regofs + regnum, val);
2860 /*** RGen() - read out one of the external/general registers ***/
2861 static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum)
2863 unsigned long regofs = 0;
2865 if (cinfo->btype == BT_PICASSO) {
2866 /* Picasso II specific hack */
2867 /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
2868 regnum == CL_VSSM2) */
2869 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
2873 return vga_r(cinfo->regbase, regofs + regnum);
2876 /*** AttrOn() - turn on VideoEnable for Attribute controller ***/
2877 static void AttrOn(const struct cirrusfb_info *cinfo)
2879 assert(cinfo != NULL);
2883 if (vga_rcrt(cinfo->regbase, CL_CRT24) & 0x80) {
2884 /* if we're just in "write value" mode, write back the */
2885 /* same value as before to not modify anything */
2886 vga_w(cinfo->regbase, VGA_ATT_IW,
2887 vga_r(cinfo->regbase, VGA_ATT_R));
2889 /* turn on video bit */
2890 /* vga_w(cinfo->regbase, VGA_ATT_IW, 0x20); */
2891 vga_w(cinfo->regbase, VGA_ATT_IW, 0x33);
2893 /* dummy write on Reg0 to be on "write index" mode next time */
2894 vga_w(cinfo->regbase, VGA_ATT_IW, 0x00);
2899 /*** WHDR() - write into the Hidden DAC register ***/
2900 /* as the HDR is the only extension register that requires special treatment
2901 * (the other extension registers are accessible just like the "ordinary"
2902 * registers of their functional group) here is a specialized routine for
2905 static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val)
2907 unsigned char dummy;
2909 if (cinfo->btype == BT_PICASSO) {
2910 /* Klaus' hint for correct access to HDR on some boards */
2911 /* first write 0 to pixel mask (3c6) */
2912 WGen(cinfo, VGA_PEL_MSK, 0x00);
2914 /* next read dummy from pixel address (3c8) */
2915 dummy = RGen(cinfo, VGA_PEL_IW);
2918 /* now do the usual stuff to access the HDR */
2920 dummy = RGen(cinfo, VGA_PEL_MSK);
2922 dummy = RGen(cinfo, VGA_PEL_MSK);
2924 dummy = RGen(cinfo, VGA_PEL_MSK);
2926 dummy = RGen(cinfo, VGA_PEL_MSK);
2929 WGen(cinfo, VGA_PEL_MSK, val);
2932 if (cinfo->btype == BT_PICASSO) {
2933 /* now first reset HDR access counter */
2934 dummy = RGen(cinfo, VGA_PEL_IW);
2937 /* and at the end, restore the mask value */
2938 /* ## is this mask always 0xff? */
2939 WGen(cinfo, VGA_PEL_MSK, 0xff);
2944 /*** WSFR() - write to the "special function register" (SFR) ***/
2945 static void WSFR(struct cirrusfb_info *cinfo, unsigned char val)
2948 assert(cinfo->regbase != NULL);
2950 z_writeb(val, cinfo->regbase + 0x8000);
2954 /* The Picasso has a second register for switching the monitor bit */
2955 static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val)
2958 /* writing an arbitrary value to this one causes the monitor switcher */
2959 /* to flip to Amiga display */
2960 assert(cinfo->regbase != NULL);
2962 z_writeb(val, cinfo->regbase + 0x9000);
2966 /*** WClut - set CLUT entry (range: 0..63) ***/
2967 static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red,
2968 unsigned char green, unsigned char blue)
2970 unsigned int data = VGA_PEL_D;
2972 /* address write mode register is not translated.. */
2973 vga_w(cinfo->regbase, VGA_PEL_IW, regnum);
2975 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2976 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
2977 /* but DAC data register IS, at least for Picasso II */
2978 if (cinfo->btype == BT_PICASSO)
2980 vga_w(cinfo->regbase, data, red);
2981 vga_w(cinfo->regbase, data, green);
2982 vga_w(cinfo->regbase, data, blue);
2984 vga_w(cinfo->regbase, data, blue);
2985 vga_w(cinfo->regbase, data, green);
2986 vga_w(cinfo->regbase, data, red);
2991 /*** RClut - read CLUT entry (range 0..63) ***/
2992 static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red,
2993 unsigned char *green, unsigned char *blue)
2995 unsigned int data = VGA_PEL_D;
2997 vga_w(cinfo->regbase, VGA_PEL_IR, regnum);
2999 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
3000 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
3001 if (cinfo->btype == BT_PICASSO)
3003 *red = vga_r(cinfo->regbase, data);
3004 *green = vga_r(cinfo->regbase, data);
3005 *blue = vga_r(cinfo->regbase, data);
3007 *blue = vga_r(cinfo->regbase, data);
3008 *green = vga_r(cinfo->regbase, data);
3009 *red = vga_r(cinfo->regbase, data);
3014 /*******************************************************************
3017 Wait for the BitBLT engine to complete a possible earlier job
3018 *********************************************************************/
3020 /* FIXME: use interrupts instead */
3021 static void cirrusfb_WaitBLT(u8 __iomem *regbase)
3023 /* now busy-wait until we're done */
3024 while (vga_rgfx(regbase, CL_GR31) & 0x08)
3028 /*******************************************************************
3031 perform accelerated "scrolling"
3032 ********************************************************************/
3034 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
3035 u_short curx, u_short cury,
3036 u_short destx, u_short desty,
3037 u_short width, u_short height,
3038 u_short line_length)
3040 u_short nwidth, nheight;
3047 nheight = height - 1;
3050 /* if source adr < dest addr, do the Blt backwards */
3051 if (cury <= desty) {
3052 if (cury == desty) {
3053 /* if src and dest are on the same line, check x */
3060 /* standard case: forward blitting */
3061 nsrc = (cury * line_length) + curx;
3062 ndest = (desty * line_length) + destx;
3064 /* this means start addresses are at the end,
3065 * counting backwards
3067 nsrc = cury * line_length + curx +
3068 nheight * line_length + nwidth;
3069 ndest = desty * line_length + destx +
3070 nheight * line_length + nwidth;
3074 run-down of registers to be programmed:
3082 VGA_GFX_SR_VALUE / VGA_GFX_SR_ENABLE: "fill color"
3086 cirrusfb_WaitBLT(regbase);
3088 /* pitch: set to line_length */
3089 /* dest pitch low */
3090 vga_wgfx(regbase, CL_GR24, line_length & 0xff);
3092 vga_wgfx(regbase, CL_GR25, line_length >> 8);
3093 /* source pitch low */
3094 vga_wgfx(regbase, CL_GR26, line_length & 0xff);
3095 /* source pitch hi */
3096 vga_wgfx(regbase, CL_GR27, line_length >> 8);
3098 /* BLT width: actual number of pixels - 1 */
3100 vga_wgfx(regbase, CL_GR20, nwidth & 0xff);
3102 vga_wgfx(regbase, CL_GR21, nwidth >> 8);
3104 /* BLT height: actual number of lines -1 */
3105 /* BLT height low */
3106 vga_wgfx(regbase, CL_GR22, nheight & 0xff);
3108 vga_wgfx(regbase, CL_GR23, nheight >> 8);
3110 /* BLT destination */
3112 vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
3114 vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
3116 vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
3120 vga_wgfx(regbase, CL_GR2C, (u_char) (nsrc & 0xff));
3122 vga_wgfx(regbase, CL_GR2D, (u_char) (nsrc >> 8));
3124 vga_wgfx(regbase, CL_GR2E, (u_char) (nsrc >> 16));
3127 vga_wgfx(regbase, CL_GR30, bltmode); /* BLT mode */
3129 /* BLT ROP: SrcCopy */
3130 vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */
3132 /* and finally: GO! */
3133 vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */
3138 /*******************************************************************
3141 perform accelerated rectangle fill
3142 ********************************************************************/
3144 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
3145 u_short x, u_short y, u_short width, u_short height,
3146 u_char color, u_short line_length)
3148 u_short nwidth, nheight;
3155 nheight = height - 1;
3157 ndest = (y * line_length) + x;
3159 cirrusfb_WaitBLT(regbase);
3161 /* pitch: set to line_length */
3162 vga_wgfx(regbase, CL_GR24, line_length & 0xff); /* dest pitch low */
3163 vga_wgfx(regbase, CL_GR25, line_length >> 8); /* dest pitch hi */
3164 vga_wgfx(regbase, CL_GR26, line_length & 0xff); /* source pitch low */
3165 vga_wgfx(regbase, CL_GR27, line_length >> 8); /* source pitch hi */
3167 /* BLT width: actual number of pixels - 1 */
3168 vga_wgfx(regbase, CL_GR20, nwidth & 0xff); /* BLT width low */
3169 vga_wgfx(regbase, CL_GR21, nwidth >> 8); /* BLT width hi */
3171 /* BLT height: actual number of lines -1 */
3172 vga_wgfx(regbase, CL_GR22, nheight & 0xff); /* BLT height low */
3173 vga_wgfx(regbase, CL_GR23, nheight >> 8); /* BLT width hi */
3175 /* BLT destination */
3177 vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
3179 vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
3181 vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
3183 /* BLT source: set to 0 (is a dummy here anyway) */
3184 vga_wgfx(regbase, CL_GR2C, 0x00); /* BLT src low */
3185 vga_wgfx(regbase, CL_GR2D, 0x00); /* BLT src mid */
3186 vga_wgfx(regbase, CL_GR2E, 0x00); /* BLT src hi */
3188 /* This is a ColorExpand Blt, using the */
3189 /* same color for foreground and background */
3190 vga_wgfx(regbase, VGA_GFX_SR_VALUE, color); /* foreground color */
3191 vga_wgfx(regbase, VGA_GFX_SR_ENABLE, color); /* background color */
3194 if (bits_per_pixel == 16) {
3195 vga_wgfx(regbase, CL_GR10, color); /* foreground color */
3196 vga_wgfx(regbase, CL_GR11, color); /* background color */
3199 } else if (bits_per_pixel == 32) {
3200 vga_wgfx(regbase, CL_GR10, color); /* foreground color */
3201 vga_wgfx(regbase, CL_GR11, color); /* background color */
3202 vga_wgfx(regbase, CL_GR12, color); /* foreground color */
3203 vga_wgfx(regbase, CL_GR13, color); /* background color */
3204 vga_wgfx(regbase, CL_GR14, 0); /* foreground color */
3205 vga_wgfx(regbase, CL_GR15, 0); /* background color */
3209 /* BLT mode: color expand, Enable 8x8 copy (faster?) */
3210 vga_wgfx(regbase, CL_GR30, op); /* BLT mode */
3212 /* BLT ROP: SrcCopy */
3213 vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */
3215 /* and finally: GO! */
3216 vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */
3221 /**************************************************************************
3222 * bestclock() - determine closest possible clock lower(?) than the
3223 * desired pixel clock
3224 **************************************************************************/
3225 static void bestclock(long freq, long *best, long *nom,
3226 long *den, long *div, long maxfreq)
3230 assert(best != NULL);
3231 assert(nom != NULL);
3232 assert(den != NULL);
3233 assert(div != NULL);
3234 assert(maxfreq > 0);
3251 for (n = 32; n < 128; n++) {
3252 d = (143181 * n) / f;
3253 if ((d >= 7) && (d <= 63)) {
3256 h = (14318 * n) / d;
3257 if (abs(h - freq) < abs(*best - freq)) {
3269 d = ((143181 * n) + f - 1) / f;
3270 if ((d >= 7) && (d <= 63)) {
3273 h = (14318 * n) / d;
3274 if (abs(h - freq) < abs(*best - freq)) {
3288 DPRINTK("Best possible values for given frequency:\n");
3289 DPRINTK(" best: %ld kHz nom: %ld den: %ld div: %ld\n",
3290 freq, *nom, *den, *div);
3295 /* -------------------------------------------------------------------------
3297 * debugging functions
3299 * -------------------------------------------------------------------------
3302 #ifdef CIRRUSFB_DEBUG
3305 * cirrusfb_dbg_print_byte
3306 * @name: name associated with byte value to be displayed
3307 * @val: byte value to be displayed
3310 * Display an indented string, along with a hexidecimal byte value, and
3311 * its decoded bits. Bits 7 through 0 are listed in left-to-right
3316 void cirrusfb_dbg_print_byte(const char *name, unsigned char val)
3318 DPRINTK("%8s = 0x%02X (bits 7-0: %c%c%c%c%c%c%c%c)\n",
3320 val & 0x80 ? '1' : '0',
3321 val & 0x40 ? '1' : '0',
3322 val & 0x20 ? '1' : '0',
3323 val & 0x10 ? '1' : '0',
3324 val & 0x08 ? '1' : '0',
3325 val & 0x04 ? '1' : '0',
3326 val & 0x02 ? '1' : '0',
3327 val & 0x01 ? '1' : '0');
3331 * cirrusfb_dbg_print_regs
3332 * @base: If using newmmio, the newmmio base address, otherwise %NULL
3333 * @reg_class: type of registers to read: %CRT, or %SEQ
3336 * Dumps the given list of VGA CRTC registers. If @base is %NULL,
3337 * old-style I/O ports are queried for information, otherwise MMIO is
3338 * used at the given @base address to query the information.
3342 void cirrusfb_dbg_print_regs(caddr_t regbase,
3343 enum cirrusfb_dbg_reg_class reg_class, ...)
3346 unsigned char val = 0;
3350 va_start(list, reg_class);
3352 name = va_arg(list, char *);
3353 while (name != NULL) {
3354 reg = va_arg(list, int);
3356 switch (reg_class) {
3358 val = vga_rcrt(regbase, (unsigned char) reg);
3361 val = vga_rseq(regbase, (unsigned char) reg);
3364 /* should never occur */
3369 cirrusfb_dbg_print_byte(name, val);
3371 name = va_arg(list, char *);
3384 static void cirrusfb_dump(void)
3386 cirrusfb_dbg_reg_dump(NULL);
3390 * cirrusfb_dbg_reg_dump
3391 * @base: If using newmmio, the newmmio base address, otherwise %NULL
3394 * Dumps a list of interesting VGA and CIRRUSFB registers. If @base is %NULL,
3395 * old-style I/O ports are queried for information, otherwise MMIO is
3396 * used at the given @base address to query the information.
3400 void cirrusfb_dbg_reg_dump(caddr_t regbase)
3402 DPRINTK("CIRRUSFB VGA CRTC register dump:\n");
3404 cirrusfb_dbg_print_regs(regbase, CRT,
3456 DPRINTK("CIRRUSFB VGA SEQ register dump:\n");
3458 cirrusfb_dbg_print_regs(regbase, SEQ,
3490 #endif /* CIRRUSFB_DEBUG */