2 * drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets
4 * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
6 * Contributors (thanks, all!)
9 * Overhaul for Linux 2.6
12 * Major contributions; Motorola PowerStack (PPC and PCI) support,
13 * GD54xx, 1280x1024 mode support, change MCLK based on VCLK.
16 * Excellent code review.
19 * Amiga updates and testing.
21 * Original cirrusfb author: Frank Neumann
23 * Based on retz3fb.c and cirrusfb.c:
24 * Copyright (C) 1997 Jes Sorensen
25 * Copyright (C) 1996 Frank Neumann
27 ***************************************************************
29 * Format this code with GNU indent '-kr -i8 -pcs' options.
31 * This file is subject to the terms and conditions of the GNU General Public
32 * License. See the file COPYING in the main directory of this archive
37 #define CIRRUSFB_VERSION "2.0-pre2"
39 #include <linux/module.h>
40 #include <linux/kernel.h>
41 #include <linux/errno.h>
42 #include <linux/string.h>
44 #include <linux/slab.h>
45 #include <linux/delay.h>
47 #include <linux/init.h>
48 #include <linux/selection.h>
49 #include <asm/pgtable.h>
52 #include <linux/zorro.h>
55 #include <linux/pci.h>
58 #include <asm/amigahw.h>
60 #ifdef CONFIG_PPC_PREP
61 #include <asm/machdep.h>
62 #define isPReP machine_is(prep)
67 #include "video/vga.h"
68 #include "video/cirrus.h"
70 /*****************************************************************
72 * debugging and utility macros
76 /* enable debug output? */
77 /* #define CIRRUSFB_DEBUG 1 */
79 /* disable runtime assertions? */
80 /* #define CIRRUSFB_NDEBUG */
84 #define DPRINTK(fmt, args...) \
85 printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
87 #define DPRINTK(fmt, args...)
90 /* debugging assertions */
91 #ifndef CIRRUSFB_NDEBUG
92 #define assert(expr) \
94 printk("Assertion failed! %s,%s,%s,line=%d\n", \
95 #expr, __FILE__, __FUNCTION__, __LINE__); \
101 #define MB_ (1024 * 1024)
104 #define MAX_NUM_BOARDS 7
106 /*****************************************************************
108 * chipset information
119 BT_PICASSO4, /* GD5446 */
120 BT_ALPINE, /* GD543x/4x */
122 BT_LAGUNA, /* GD546x */
126 * per-board-type information, used for enumerating and abstracting
127 * chip-specific information
128 * NOTE: MUST be in the same order as enum cirrus_board in order to
129 * use direct indexing on this array
130 * NOTE: '__initdata' cannot be used as some of this info
131 * is required at runtime. Maybe separate into an init-only and
134 static const struct cirrusfb_board_info_rec {
135 char *name; /* ASCII name of chipset */
136 long maxclock[5]; /* maximum video clock */
137 /* for 1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */
138 bool init_sr07 : 1; /* init SR07 during init_vgachip() */
139 bool init_sr1f : 1; /* write SR1F during init_vgachip() */
140 /* construct bit 19 of screen start address */
141 bool scrn_start_bit19 : 1;
143 /* initial SR07 value, then for each mode */
145 unsigned char sr07_1bpp;
146 unsigned char sr07_1bpp_mux;
147 unsigned char sr07_8bpp;
148 unsigned char sr07_8bpp_mux;
150 unsigned char sr1f; /* SR1F VGA initial register value */
151 } cirrusfb_board_info[] = {
156 /* the SD64/P4 have a higher max. videoclock */
157 140000, 140000, 140000, 140000, 140000,
161 .scrn_start_bit19 = true,
168 .name = "CL Piccolo",
171 90000, 90000, 90000, 90000, 90000
175 .scrn_start_bit19 = false,
182 .name = "CL Picasso",
185 90000, 90000, 90000, 90000, 90000
189 .scrn_start_bit19 = false,
196 .name = "CL Spectrum",
199 90000, 90000, 90000, 90000, 90000
203 .scrn_start_bit19 = false,
210 .name = "CL Picasso4",
212 135100, 135100, 85500, 85500, 0
216 .scrn_start_bit19 = true,
225 /* for the GD5430. GD5446 can do more... */
226 85500, 85500, 50000, 28500, 0
230 .scrn_start_bit19 = true,
233 .sr07_1bpp_mux = 0xA7,
235 .sr07_8bpp_mux = 0xA7,
241 135100, 200000, 200000, 135100, 135100
245 .scrn_start_bit19 = true,
255 135100, 135100, 135100, 135100, 135100,
259 .scrn_start_bit19 = true,
264 #define CHIP(id, btype) \
265 { PCI_VENDOR_ID_CIRRUS, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (btype) }
267 static struct pci_device_id cirrusfb_pci_table[] = {
268 CHIP(PCI_DEVICE_ID_CIRRUS_5436, BT_ALPINE),
269 CHIP(PCI_DEVICE_ID_CIRRUS_5434_8, BT_ALPINE),
270 CHIP(PCI_DEVICE_ID_CIRRUS_5434_4, BT_ALPINE),
271 CHIP(PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE), /* GD-5440 is same id */
272 CHIP(PCI_DEVICE_ID_CIRRUS_7543, BT_ALPINE),
273 CHIP(PCI_DEVICE_ID_CIRRUS_7548, BT_ALPINE),
274 CHIP(PCI_DEVICE_ID_CIRRUS_5480, BT_GD5480), /* MacPicasso likely */
275 CHIP(PCI_DEVICE_ID_CIRRUS_5446, BT_PICASSO4), /* Picasso 4 is 5446 */
276 CHIP(PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA), /* CL Laguna */
277 CHIP(PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA), /* CL Laguna 3D */
278 CHIP(PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNA), /* CL Laguna 3DA*/
281 MODULE_DEVICE_TABLE(pci, cirrusfb_pci_table);
283 #endif /* CONFIG_PCI */
286 static const struct zorro_device_id cirrusfb_zorro_table[] = {
288 .id = ZORRO_PROD_HELFRICH_SD64_RAM,
289 .driver_data = BT_SD64,
291 .id = ZORRO_PROD_HELFRICH_PICCOLO_RAM,
292 .driver_data = BT_PICCOLO,
294 .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_RAM,
295 .driver_data = BT_PICASSO,
297 .id = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_RAM,
298 .driver_data = BT_SPECTRUM,
300 .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z3,
301 .driver_data = BT_PICASSO4,
306 static const struct {
309 } cirrusfb_zorro_table2[] = {
311 .id2 = ZORRO_PROD_HELFRICH_SD64_REG,
315 .id2 = ZORRO_PROD_HELFRICH_PICCOLO_REG,
319 .id2 = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_REG,
323 .id2 = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_REG,
331 #endif /* CONFIG_ZORRO */
333 struct cirrusfb_regs {
334 __u32 line_length; /* in BYTES! */
346 long HorizRes; /* The x resolution in pixel */
349 long HorizBlankStart;
354 long VertRes; /* the physical y resolution in scanlines */
363 #ifdef CIRRUSFB_DEBUG
364 enum cirrusfb_dbg_reg_class {
368 #endif /* CIRRUSFB_DEBUG */
370 /* info about board */
371 struct cirrusfb_info {
372 struct fb_info *info;
378 enum cirrus_board btype;
379 unsigned char SFR; /* Shadow of special function register */
381 unsigned long fbmem_phys;
382 unsigned long fbregs_phys;
384 struct cirrusfb_regs currentmode;
387 u32 pseudo_palette[16];
388 struct { u8 red, green, blue, pad; } palette[256];
391 struct zorro_dev *zdev;
394 struct pci_dev *pdev;
396 void (*unmap)(struct cirrusfb_info *cinfo);
399 static unsigned cirrusfb_def_mode = 1;
403 * Predefined Video Modes
406 static const struct {
408 struct fb_var_screeninfo var;
409 } cirrusfb_predefined[] = {
411 /* autodetect mode */
412 .name = "Autodetect",
414 /* 640x480, 31.25 kHz, 60 Hz, 25 MHz PixClock */
422 .red = { .length = 8 },
423 .green = { .length = 8 },
424 .blue = { .length = 8 },
434 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
435 .vmode = FB_VMODE_NONINTERLACED
438 /* 800x600, 48 kHz, 76 Hz, 50 MHz PixClock */
446 .red = { .length = 8 },
447 .green = { .length = 8 },
448 .blue = { .length = 8 },
458 .vmode = FB_VMODE_NONINTERLACED
462 * Modeline from XF86Config:
463 * Mode "1024x768" 80 1024 1136 1340 1432 768 770 774 805
465 /* 1024x768, 55.8 kHz, 70 Hz, 80 MHz PixClock */
470 .xres_virtual = 1024,
473 .red = { .length = 8 },
474 .green = { .length = 8 },
475 .blue = { .length = 8 },
485 .vmode = FB_VMODE_NONINTERLACED
490 #define NUM_TOTAL_MODES ARRAY_SIZE(cirrusfb_predefined)
492 /****************************************************************************/
493 /**** BEGIN PROTOTYPES ******************************************************/
495 /*--- Interface used by the world ------------------------------------------*/
496 static int cirrusfb_init(void);
498 static int cirrusfb_setup(char *options);
501 static int cirrusfb_open(struct fb_info *info, int user);
502 static int cirrusfb_release(struct fb_info *info, int user);
503 static int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green,
504 unsigned blue, unsigned transp,
505 struct fb_info *info);
506 static int cirrusfb_check_var(struct fb_var_screeninfo *var,
507 struct fb_info *info);
508 static int cirrusfb_set_par(struct fb_info *info);
509 static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
510 struct fb_info *info);
511 static int cirrusfb_blank(int blank_mode, struct fb_info *info);
512 static void cirrusfb_fillrect(struct fb_info *info,
513 const struct fb_fillrect *region);
514 static void cirrusfb_copyarea(struct fb_info *info,
515 const struct fb_copyarea *area);
516 static void cirrusfb_imageblit(struct fb_info *info,
517 const struct fb_image *image);
519 /* function table of the above functions */
520 static struct fb_ops cirrusfb_ops = {
521 .owner = THIS_MODULE,
522 .fb_open = cirrusfb_open,
523 .fb_release = cirrusfb_release,
524 .fb_setcolreg = cirrusfb_setcolreg,
525 .fb_check_var = cirrusfb_check_var,
526 .fb_set_par = cirrusfb_set_par,
527 .fb_pan_display = cirrusfb_pan_display,
528 .fb_blank = cirrusfb_blank,
529 .fb_fillrect = cirrusfb_fillrect,
530 .fb_copyarea = cirrusfb_copyarea,
531 .fb_imageblit = cirrusfb_imageblit,
534 /*--- Hardware Specific Routines -------------------------------------------*/
535 static int cirrusfb_decode_var(const struct fb_var_screeninfo *var,
536 struct cirrusfb_regs *regs,
537 const struct fb_info *info);
538 /*--- Internal routines ----------------------------------------------------*/
539 static void init_vgachip(struct cirrusfb_info *cinfo);
540 static void switch_monitor(struct cirrusfb_info *cinfo, int on);
541 static void WGen(const struct cirrusfb_info *cinfo,
542 int regnum, unsigned char val);
543 static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum);
544 static void AttrOn(const struct cirrusfb_info *cinfo);
545 static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val);
546 static void WSFR(struct cirrusfb_info *cinfo, unsigned char val);
547 static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val);
548 static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum,
549 unsigned char red, unsigned char green, unsigned char blue);
551 static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum,
552 unsigned char *red, unsigned char *green,
553 unsigned char *blue);
555 static void cirrusfb_WaitBLT(u8 __iomem *regbase);
556 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
557 u_short curx, u_short cury,
558 u_short destx, u_short desty,
559 u_short width, u_short height,
560 u_short line_length);
561 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
562 u_short x, u_short y,
563 u_short width, u_short height,
564 u_char color, u_short line_length);
566 static void bestclock(long freq, long *best,
567 long *nom, long *den,
568 long *div, long maxfreq);
570 #ifdef CIRRUSFB_DEBUG
571 static void cirrusfb_dump(void);
572 static void cirrusfb_dbg_reg_dump(caddr_t regbase);
573 static void cirrusfb_dbg_print_regs(caddr_t regbase,
574 enum cirrusfb_dbg_reg_class reg_class, ...);
575 static void cirrusfb_dbg_print_byte(const char *name, unsigned char val);
576 #endif /* CIRRUSFB_DEBUG */
578 /*** END PROTOTYPES ********************************************************/
579 /*****************************************************************************/
580 /*** BEGIN Interface Used by the World ***************************************/
582 static int opencount;
584 /*--- Open /dev/fbx ---------------------------------------------------------*/
585 static int cirrusfb_open(struct fb_info *info, int user)
587 if (opencount++ == 0)
588 switch_monitor(info->par, 1);
592 /*--- Close /dev/fbx --------------------------------------------------------*/
593 static int cirrusfb_release(struct fb_info *info, int user)
595 if (--opencount == 0)
596 switch_monitor(info->par, 0);
600 /**** END Interface used by the World *************************************/
601 /****************************************************************************/
602 /**** BEGIN Hardware specific Routines **************************************/
604 /* Get a good MCLK value */
605 static long cirrusfb_get_mclk(long freq, int bpp, long *div)
611 /* Calculate MCLK, in case VCLK is high enough to require > 50MHz.
612 * Assume a 64-bit data path for now. The formula is:
613 * ((B * PCLK * 2)/W) * 1.2
614 * B = bytes per pixel, PCLK = pixclock, W = data width in bytes */
615 mclk = ((bpp / 8) * freq * 2) / 4;
616 mclk = (mclk * 12) / 10;
619 DPRINTK("Use MCLK of %ld kHz\n", mclk);
621 /* Calculate value for SR1F. Multiply by 2 so we can round up. */
622 mclk = ((mclk * 16) / 14318);
623 mclk = (mclk + 1) / 2;
624 DPRINTK("Set SR1F[5:0] to 0x%lx\n", mclk);
626 /* Determine if we should use MCLK instead of VCLK, and if so, what we
627 * should divide it by to get VCLK */
629 case 24751 ... 25249:
631 DPRINTK("Using VCLK = MCLK/2\n");
633 case 49501 ... 50499:
635 DPRINTK("Using VCLK = MCLK\n");
645 static int cirrusfb_check_var(struct fb_var_screeninfo *var,
646 struct fb_info *info)
648 struct cirrusfb_info *cinfo = info->par;
649 int nom, den; /* translyting from pixels->bytes */
651 static struct { int xres, yres; } modes[] =
659 switch (var->bits_per_pixel) {
661 var->bits_per_pixel = 1;
664 break; /* 8 pixel per byte, only 1/4th of mem usable */
666 var->bits_per_pixel = 8;
669 break; /* 1 pixel == 1 byte */
671 var->bits_per_pixel = 16;
674 break; /* 2 bytes per pixel */
676 var->bits_per_pixel = 24;
679 break; /* 3 bytes per pixel */
681 var->bits_per_pixel = 32;
684 break; /* 4 bytes per pixel */
686 printk(KERN_ERR "cirrusfb: mode %dx%dx%d rejected..."
687 "color depth not supported.\n",
688 var->xres, var->yres, var->bits_per_pixel);
689 DPRINTK("EXIT - EINVAL error\n");
693 if (var->xres * nom / den * var->yres > cinfo->size) {
694 printk(KERN_ERR "cirrusfb: mode %dx%dx%d rejected..."
695 "resolution too high to fit into video memory!\n",
696 var->xres, var->yres, var->bits_per_pixel);
697 DPRINTK("EXIT - EINVAL error\n");
701 /* use highest possible virtual resolution */
702 if (var->xres_virtual == -1 &&
703 var->yres_virtual == -1) {
705 "cirrusfb: using maximum available virtual resolution\n");
706 for (i = 0; modes[i].xres != -1; i++) {
707 if (modes[i].xres * nom / den * modes[i].yres < cinfo->size / 2)
710 if (modes[i].xres == -1) {
711 printk(KERN_ERR "cirrusfb: could not find a virtual "
712 "resolution that fits into video memory!!\n");
713 DPRINTK("EXIT - EINVAL error\n");
716 var->xres_virtual = modes[i].xres;
717 var->yres_virtual = modes[i].yres;
719 printk(KERN_INFO "cirrusfb: virtual resolution set to "
720 "maximum of %dx%d\n", var->xres_virtual,
724 if (var->xres_virtual < var->xres)
725 var->xres_virtual = var->xres;
726 if (var->yres_virtual < var->yres)
727 var->yres_virtual = var->yres;
729 if (var->xoffset < 0)
731 if (var->yoffset < 0)
734 /* truncate xoffset and yoffset to maximum if too high */
735 if (var->xoffset > var->xres_virtual - var->xres)
736 var->xoffset = var->xres_virtual - var->xres - 1;
737 if (var->yoffset > var->yres_virtual - var->yres)
738 var->yoffset = var->yres_virtual - var->yres - 1;
740 switch (var->bits_per_pixel) {
744 var->green.offset = 0;
745 var->green.length = 1;
746 var->blue.offset = 0;
747 var->blue.length = 1;
753 var->green.offset = 0;
754 var->green.length = 6;
755 var->blue.offset = 0;
756 var->blue.length = 6;
762 var->green.offset = -3;
763 var->blue.offset = 8;
765 var->red.offset = 10;
766 var->green.offset = 5;
767 var->blue.offset = 0;
770 var->green.length = 5;
771 var->blue.length = 5;
777 var->green.offset = 16;
778 var->blue.offset = 24;
780 var->red.offset = 16;
781 var->green.offset = 8;
782 var->blue.offset = 0;
785 var->green.length = 8;
786 var->blue.length = 8;
792 var->green.offset = 16;
793 var->blue.offset = 24;
795 var->red.offset = 16;
796 var->green.offset = 8;
797 var->blue.offset = 0;
800 var->green.length = 8;
801 var->blue.length = 8;
805 DPRINTK("Unsupported bpp size: %d\n", var->bits_per_pixel);
807 /* should never occur */
812 var->green.msb_right =
813 var->blue.msb_right =
816 var->transp.msb_right = 0;
819 if (var->vmode & FB_VMODE_DOUBLE)
821 else if (var->vmode & FB_VMODE_INTERLACED)
822 yres = (yres + 1) / 2;
825 printk(KERN_ERR "cirrusfb: ERROR: VerticalTotal >= 1280; "
826 "special treatment required! (TODO)\n");
827 DPRINTK("EXIT - EINVAL error\n");
834 static int cirrusfb_decode_var(const struct fb_var_screeninfo *var,
835 struct cirrusfb_regs *regs,
836 const struct fb_info *info)
841 struct cirrusfb_info *cinfo = info->par;
842 int xres, hfront, hsync, hback;
843 int yres, vfront, vsync, vback;
845 switch (var->bits_per_pixel) {
847 regs->line_length = var->xres_virtual / 8;
848 regs->visual = FB_VISUAL_MONO10;
853 regs->line_length = var->xres_virtual;
854 regs->visual = FB_VISUAL_PSEUDOCOLOR;
859 regs->line_length = var->xres_virtual * 2;
860 regs->visual = FB_VISUAL_DIRECTCOLOR;
865 regs->line_length = var->xres_virtual * 3;
866 regs->visual = FB_VISUAL_DIRECTCOLOR;
871 regs->line_length = var->xres_virtual * 4;
872 regs->visual = FB_VISUAL_DIRECTCOLOR;
877 DPRINTK("Unsupported bpp size: %d\n", var->bits_per_pixel);
879 /* should never occur */
883 regs->type = FB_TYPE_PACKED_PIXELS;
885 /* convert from ps to kHz */
886 freq = 1000000000 / var->pixclock;
888 DPRINTK("desired pixclock: %ld kHz\n", freq);
890 maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx];
891 regs->multiplexing = 0;
893 /* If the frequency is greater than we can support, we might be able
894 * to use multiplexing for the video mode */
895 if (freq > maxclock) {
896 switch (cinfo->btype) {
899 regs->multiplexing = 1;
903 printk(KERN_ERR "cirrusfb: Frequency greater "
904 "than maxclock (%ld kHz)\n", maxclock);
905 DPRINTK("EXIT - return -EINVAL\n");
910 /* TODO: If we have a 1MB 5434, we need to put ourselves in a mode where
911 * the VCLK is double the pixel clock. */
912 switch (var->bits_per_pixel) {
915 if (regs->HorizRes <= 800)
916 /* Xbh has this type of clock for 32-bit */
922 bestclock(freq, ®s->freq, ®s->nom, ®s->den, ®s->div,
924 regs->mclk = cirrusfb_get_mclk(freq, var->bits_per_pixel,
928 hfront = var->right_margin;
929 hsync = var->hsync_len;
930 hback = var->left_margin;
933 vfront = var->lower_margin;
934 vsync = var->vsync_len;
935 vback = var->upper_margin;
937 if (var->vmode & FB_VMODE_DOUBLE) {
942 } else if (var->vmode & FB_VMODE_INTERLACED) {
943 yres = (yres + 1) / 2;
944 vfront = (vfront + 1) / 2;
945 vsync = (vsync + 1) / 2;
946 vback = (vback + 1) / 2;
948 regs->HorizRes = xres;
949 regs->HorizTotal = (xres + hfront + hsync + hback) / 8 - 5;
950 regs->HorizDispEnd = xres / 8 - 1;
951 regs->HorizBlankStart = xres / 8;
952 /* does not count with "-5" */
953 regs->HorizBlankEnd = regs->HorizTotal + 5;
954 regs->HorizSyncStart = (xres + hfront) / 8 + 1;
955 regs->HorizSyncEnd = (xres + hfront + hsync) / 8 + 1;
957 regs->VertRes = yres;
958 regs->VertTotal = yres + vfront + vsync + vback - 2;
959 regs->VertDispEnd = yres - 1;
960 regs->VertBlankStart = yres;
961 regs->VertBlankEnd = regs->VertTotal;
962 regs->VertSyncStart = yres + vfront - 1;
963 regs->VertSyncEnd = yres + vfront + vsync - 1;
965 if (regs->VertRes >= 1024) {
966 regs->VertTotal /= 2;
967 regs->VertSyncStart /= 2;
968 regs->VertSyncEnd /= 2;
969 regs->VertDispEnd /= 2;
971 if (regs->multiplexing) {
972 regs->HorizTotal /= 2;
973 regs->HorizSyncStart /= 2;
974 regs->HorizSyncEnd /= 2;
975 regs->HorizDispEnd /= 2;
981 static void cirrusfb_set_mclk(const struct cirrusfb_info *cinfo, int val,
984 assert(cinfo != NULL);
988 unsigned char old = vga_rseq(cinfo->regbase, CL_SEQR1E);
989 vga_wseq(cinfo->regbase, CL_SEQR1E, old | 0x1);
990 vga_wseq(cinfo->regbase, CL_SEQR1F, 0x40 | (val & 0x3f));
991 } else if (div == 1) {
993 unsigned char old = vga_rseq(cinfo->regbase, CL_SEQR1E);
994 vga_wseq(cinfo->regbase, CL_SEQR1E, old & ~0x1);
995 vga_wseq(cinfo->regbase, CL_SEQR1F, 0x40 | (val & 0x3f));
997 vga_wseq(cinfo->regbase, CL_SEQR1F, val & 0x3f);
1001 /*************************************************************************
1002 cirrusfb_set_par_foo()
1004 actually writes the values for a new video mode into the hardware,
1005 **************************************************************************/
1006 static int cirrusfb_set_par_foo(struct fb_info *info)
1008 struct cirrusfb_info *cinfo = info->par;
1009 struct fb_var_screeninfo *var = &info->var;
1010 struct cirrusfb_regs regs;
1011 u8 __iomem *regbase = cinfo->regbase;
1013 int offset = 0, err;
1014 const struct cirrusfb_board_info_rec *bi;
1017 DPRINTK("Requested mode: %dx%dx%d\n",
1018 var->xres, var->yres, var->bits_per_pixel);
1019 DPRINTK("pixclock: %d\n", var->pixclock);
1021 init_vgachip(cinfo);
1023 err = cirrusfb_decode_var(var, ®s, info);
1025 /* should never happen */
1026 DPRINTK("mode change aborted. invalid var.\n");
1030 bi = &cirrusfb_board_info[cinfo->btype];
1032 /* unlock register VGA_CRTC_H_TOTAL..CRT7 */
1033 vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20); /* previously: 0x00) */
1035 /* if debugging is enabled, all parameters get output before writing */
1036 DPRINTK("CRT0: %ld\n", regs.HorizTotal);
1037 vga_wcrt(regbase, VGA_CRTC_H_TOTAL, regs.HorizTotal);
1039 DPRINTK("CRT1: %ld\n", regs.HorizDispEnd);
1040 vga_wcrt(regbase, VGA_CRTC_H_DISP, regs.HorizDispEnd);
1042 DPRINTK("CRT2: %ld\n", regs.HorizBlankStart);
1043 vga_wcrt(regbase, VGA_CRTC_H_BLANK_START, regs.HorizBlankStart);
1045 /* + 128: Compatible read */
1046 DPRINTK("CRT3: 128+%ld\n", regs.HorizBlankEnd % 32);
1047 vga_wcrt(regbase, VGA_CRTC_H_BLANK_END,
1048 128 + (regs.HorizBlankEnd % 32));
1050 DPRINTK("CRT4: %ld\n", regs.HorizSyncStart);
1051 vga_wcrt(regbase, VGA_CRTC_H_SYNC_START, regs.HorizSyncStart);
1053 tmp = regs.HorizSyncEnd % 32;
1054 if (regs.HorizBlankEnd & 32)
1056 DPRINTK("CRT5: %d\n", tmp);
1057 vga_wcrt(regbase, VGA_CRTC_H_SYNC_END, tmp);
1059 DPRINTK("CRT6: %ld\n", regs.VertTotal & 0xff);
1060 vga_wcrt(regbase, VGA_CRTC_V_TOTAL, (regs.VertTotal & 0xff));
1062 tmp = 16; /* LineCompare bit #9 */
1063 if (regs.VertTotal & 256)
1065 if (regs.VertDispEnd & 256)
1067 if (regs.VertSyncStart & 256)
1069 if (regs.VertBlankStart & 256)
1071 if (regs.VertTotal & 512)
1073 if (regs.VertDispEnd & 512)
1075 if (regs.VertSyncStart & 512)
1077 DPRINTK("CRT7: %d\n", tmp);
1078 vga_wcrt(regbase, VGA_CRTC_OVERFLOW, tmp);
1080 tmp = 0x40; /* LineCompare bit #8 */
1081 if (regs.VertBlankStart & 512)
1083 if (var->vmode & FB_VMODE_DOUBLE)
1085 DPRINTK("CRT9: %d\n", tmp);
1086 vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, tmp);
1088 DPRINTK("CRT10: %ld\n", regs.VertSyncStart & 0xff);
1089 vga_wcrt(regbase, VGA_CRTC_V_SYNC_START, regs.VertSyncStart & 0xff);
1091 DPRINTK("CRT11: 64+32+%ld\n", regs.VertSyncEnd % 16);
1092 vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, regs.VertSyncEnd % 16 + 64 + 32);
1094 DPRINTK("CRT12: %ld\n", regs.VertDispEnd & 0xff);
1095 vga_wcrt(regbase, VGA_CRTC_V_DISP_END, regs.VertDispEnd & 0xff);
1097 DPRINTK("CRT15: %ld\n", regs.VertBlankStart & 0xff);
1098 vga_wcrt(regbase, VGA_CRTC_V_BLANK_START, regs.VertBlankStart & 0xff);
1100 DPRINTK("CRT16: %ld\n", regs.VertBlankEnd & 0xff);
1101 vga_wcrt(regbase, VGA_CRTC_V_BLANK_END, regs.VertBlankEnd & 0xff);
1103 DPRINTK("CRT18: 0xff\n");
1104 vga_wcrt(regbase, VGA_CRTC_LINE_COMPARE, 0xff);
1107 if (var->vmode & FB_VMODE_INTERLACED)
1109 if (regs.HorizBlankEnd & 64)
1111 if (regs.HorizBlankEnd & 128)
1113 if (regs.VertBlankEnd & 256)
1115 if (regs.VertBlankEnd & 512)
1118 DPRINTK("CRT1a: %d\n", tmp);
1119 vga_wcrt(regbase, CL_CRT1A, tmp);
1122 /* hardware RefClock: 14.31818 MHz */
1123 /* formula: VClk = (OSC * N) / (D * (1+P)) */
1124 /* Example: VClk = (14.31818 * 91) / (23 * (1+1)) = 28.325 MHz */
1126 vga_wseq(regbase, CL_SEQRB, regs.nom);
1127 tmp = regs.den << 1;
1131 /* 6 bit denom; ONLY 5434!!! (bugged me 10 days) */
1132 if ((cinfo->btype == BT_SD64) ||
1133 (cinfo->btype == BT_ALPINE) ||
1134 (cinfo->btype == BT_GD5480))
1137 DPRINTK("CL_SEQR1B: %ld\n", (long) tmp);
1138 vga_wseq(regbase, CL_SEQR1B, tmp);
1140 if (regs.VertRes >= 1024)
1142 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc7);
1144 /* mode control: VGA_CRTC_START_HI enable, ROTATE(?), 16bit
1145 * address wrap, no compat. */
1146 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc3);
1148 /* HAEH? vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20);
1149 * previously: 0x00 unlock VGA_CRTC_H_TOTAL..CRT7 */
1151 /* don't know if it would hurt to also program this if no interlaced */
1152 /* mode is used, but I feel better this way.. :-) */
1153 if (var->vmode & FB_VMODE_INTERLACED)
1154 vga_wcrt(regbase, VGA_CRTC_REGS, regs.HorizTotal / 2);
1156 vga_wcrt(regbase, VGA_CRTC_REGS, 0x00); /* interlace control */
1158 vga_wseq(regbase, VGA_SEQ_CHARACTER_MAP, 0);
1160 /* adjust horizontal/vertical sync type (low/high) */
1161 /* enable display memory & CRTC I/O address for color mode */
1163 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
1165 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
1167 WGen(cinfo, VGA_MIS_W, tmp);
1169 /* Screen A Preset Row-Scan register */
1170 vga_wcrt(regbase, VGA_CRTC_PRESET_ROW, 0);
1171 /* text cursor on and start line */
1172 vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0);
1173 /* text cursor end line */
1174 vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 31);
1176 /******************************************************
1182 /* programming for different color depths */
1183 if (var->bits_per_pixel == 1) {
1184 DPRINTK("cirrusfb: preparing for 1 bit deep display\n");
1185 vga_wgfx(regbase, VGA_GFX_MODE, 0); /* mode register */
1188 switch (cinfo->btype) {
1196 DPRINTK(" (for GD54xx)\n");
1197 vga_wseq(regbase, CL_SEQR7,
1199 bi->sr07_1bpp_mux : bi->sr07_1bpp);
1203 DPRINTK(" (for GD546x)\n");
1204 vga_wseq(regbase, CL_SEQR7,
1205 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1209 printk(KERN_WARNING "cirrusfb: unknown Board\n");
1213 /* Extended Sequencer Mode */
1214 switch (cinfo->btype) {
1216 /* setting the SEQRF on SD64 is not necessary
1217 * (only during init)
1219 DPRINTK("(for SD64)\n");
1221 vga_wseq(regbase, CL_SEQR1F, 0x1a);
1225 DPRINTK("(for Piccolo)\n");
1226 /* ### ueberall 0x22? */
1227 /* ##vorher 1c MCLK select */
1228 vga_wseq(regbase, CL_SEQR1F, 0x22);
1229 /* evtl d0 bei 1 bit? avoid FIFO underruns..? */
1230 vga_wseq(regbase, CL_SEQRF, 0xb0);
1234 DPRINTK("(for Picasso)\n");
1235 /* ##vorher 22 MCLK select */
1236 vga_wseq(regbase, CL_SEQR1F, 0x22);
1237 /* ## vorher d0 avoid FIFO underruns..? */
1238 vga_wseq(regbase, CL_SEQRF, 0xd0);
1242 DPRINTK("(for Spectrum)\n");
1243 /* ### ueberall 0x22? */
1244 /* ##vorher 1c MCLK select */
1245 vga_wseq(regbase, CL_SEQR1F, 0x22);
1246 /* evtl d0? avoid FIFO underruns..? */
1247 vga_wseq(regbase, CL_SEQRF, 0xb0);
1254 DPRINTK(" (for GD54xx)\n");
1259 printk(KERN_WARNING "cirrusfb: unknown Board\n");
1263 /* pixel mask: pass-through for first plane */
1264 WGen(cinfo, VGA_PEL_MSK, 0x01);
1265 if (regs.multiplexing)
1266 /* hidden dac reg: 1280x1024 */
1269 /* hidden dac: nothing */
1271 /* memory mode: odd/even, ext. memory */
1272 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x06);
1273 /* plane mask: only write to first plane */
1274 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x01);
1275 offset = var->xres_virtual / 16;
1278 /******************************************************
1284 else if (var->bits_per_pixel == 8) {
1285 DPRINTK("cirrusfb: preparing for 8 bit deep display\n");
1286 switch (cinfo->btype) {
1294 DPRINTK(" (for GD54xx)\n");
1295 vga_wseq(regbase, CL_SEQR7,
1297 bi->sr07_8bpp_mux : bi->sr07_8bpp);
1301 DPRINTK(" (for GD546x)\n");
1302 vga_wseq(regbase, CL_SEQR7,
1303 vga_rseq(regbase, CL_SEQR7) | 0x01);
1307 printk(KERN_WARNING "cirrusfb: unknown Board\n");
1311 switch (cinfo->btype) {
1314 vga_wseq(regbase, CL_SEQR1F, 0x1d);
1318 /* ### vorher 1c MCLK select */
1319 vga_wseq(regbase, CL_SEQR1F, 0x22);
1320 /* Fast Page-Mode writes */
1321 vga_wseq(regbase, CL_SEQRF, 0xb0);
1325 /* ### vorher 1c MCLK select */
1326 vga_wseq(regbase, CL_SEQR1F, 0x22);
1327 /* Fast Page-Mode writes */
1328 vga_wseq(regbase, CL_SEQRF, 0xb0);
1332 /* ### vorher 1c MCLK select */
1333 vga_wseq(regbase, CL_SEQR1F, 0x22);
1334 /* Fast Page-Mode writes */
1335 vga_wseq(regbase, CL_SEQRF, 0xb0);
1340 /* ### INCOMPLETE!! */
1341 vga_wseq(regbase, CL_SEQRF, 0xb8);
1343 /* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
1347 DPRINTK(" (for GD543x)\n");
1348 cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK);
1349 /* We already set SRF and SR1F */
1354 DPRINTK(" (for GD54xx)\n");
1359 printk(KERN_WARNING "cirrusfb: unknown Board\n");
1363 /* mode register: 256 color mode */
1364 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1365 /* pixel mask: pass-through all planes */
1366 WGen(cinfo, VGA_PEL_MSK, 0xff);
1367 if (regs.multiplexing)
1368 /* hidden dac reg: 1280x1024 */
1371 /* hidden dac: nothing */
1373 /* memory mode: chain4, ext. memory */
1374 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
1375 /* plane mask: enable writing to all 4 planes */
1376 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1377 offset = var->xres_virtual / 8;
1380 /******************************************************
1386 else if (var->bits_per_pixel == 16) {
1387 DPRINTK("cirrusfb: preparing for 16 bit deep display\n");
1388 switch (cinfo->btype) {
1390 /* Extended Sequencer Mode: 256c col. mode */
1391 vga_wseq(regbase, CL_SEQR7, 0xf7);
1393 vga_wseq(regbase, CL_SEQR1F, 0x1e);
1397 vga_wseq(regbase, CL_SEQR7, 0x87);
1398 /* Fast Page-Mode writes */
1399 vga_wseq(regbase, CL_SEQRF, 0xb0);
1401 vga_wseq(regbase, CL_SEQR1F, 0x22);
1405 vga_wseq(regbase, CL_SEQR7, 0x27);
1406 /* Fast Page-Mode writes */
1407 vga_wseq(regbase, CL_SEQRF, 0xb0);
1409 vga_wseq(regbase, CL_SEQR1F, 0x22);
1413 vga_wseq(regbase, CL_SEQR7, 0x87);
1414 /* Fast Page-Mode writes */
1415 vga_wseq(regbase, CL_SEQRF, 0xb0);
1417 vga_wseq(regbase, CL_SEQR1F, 0x22);
1421 vga_wseq(regbase, CL_SEQR7, 0x27);
1422 /* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
1426 DPRINTK(" (for GD543x)\n");
1427 if (regs.HorizRes >= 1024)
1428 vga_wseq(regbase, CL_SEQR7, 0xa7);
1430 vga_wseq(regbase, CL_SEQR7, 0xa3);
1431 cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK);
1435 DPRINTK(" (for GD5480)\n");
1436 vga_wseq(regbase, CL_SEQR7, 0x17);
1437 /* We already set SRF and SR1F */
1441 DPRINTK(" (for GD546x)\n");
1442 vga_wseq(regbase, CL_SEQR7,
1443 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1447 printk(KERN_WARNING "CIRRUSFB: unknown Board\n");
1451 /* mode register: 256 color mode */
1452 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1453 /* pixel mask: pass-through all planes */
1454 WGen(cinfo, VGA_PEL_MSK, 0xff);
1456 WHDR(cinfo, 0xc0); /* Copy Xbh */
1457 #elif defined(CONFIG_ZORRO)
1458 /* FIXME: CONFIG_PCI and CONFIG_ZORRO may be defined both */
1459 WHDR(cinfo, 0xa0); /* hidden dac reg: nothing special */
1461 /* memory mode: chain4, ext. memory */
1462 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
1463 /* plane mask: enable writing to all 4 planes */
1464 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1465 offset = var->xres_virtual / 4;
1468 /******************************************************
1474 else if (var->bits_per_pixel == 32) {
1475 DPRINTK("cirrusfb: preparing for 24/32 bit deep display\n");
1476 switch (cinfo->btype) {
1478 /* Extended Sequencer Mode: 256c col. mode */
1479 vga_wseq(regbase, CL_SEQR7, 0xf9);
1481 vga_wseq(regbase, CL_SEQR1F, 0x1e);
1485 vga_wseq(regbase, CL_SEQR7, 0x85);
1486 /* Fast Page-Mode writes */
1487 vga_wseq(regbase, CL_SEQRF, 0xb0);
1489 vga_wseq(regbase, CL_SEQR1F, 0x22);
1493 vga_wseq(regbase, CL_SEQR7, 0x25);
1494 /* Fast Page-Mode writes */
1495 vga_wseq(regbase, CL_SEQRF, 0xb0);
1497 vga_wseq(regbase, CL_SEQR1F, 0x22);
1501 vga_wseq(regbase, CL_SEQR7, 0x85);
1502 /* Fast Page-Mode writes */
1503 vga_wseq(regbase, CL_SEQRF, 0xb0);
1505 vga_wseq(regbase, CL_SEQR1F, 0x22);
1509 vga_wseq(regbase, CL_SEQR7, 0x25);
1510 /* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
1514 DPRINTK(" (for GD543x)\n");
1515 vga_wseq(regbase, CL_SEQR7, 0xa9);
1516 cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK);
1520 DPRINTK(" (for GD5480)\n");
1521 vga_wseq(regbase, CL_SEQR7, 0x19);
1522 /* We already set SRF and SR1F */
1526 DPRINTK(" (for GD546x)\n");
1527 vga_wseq(regbase, CL_SEQR7,
1528 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1532 printk(KERN_WARNING "cirrusfb: unknown Board\n");
1536 /* mode register: 256 color mode */
1537 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1538 /* pixel mask: pass-through all planes */
1539 WGen(cinfo, VGA_PEL_MSK, 0xff);
1540 /* hidden dac reg: 8-8-8 mode (24 or 32) */
1542 /* memory mode: chain4, ext. memory */
1543 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
1544 /* plane mask: enable writing to all 4 planes */
1545 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1546 offset = var->xres_virtual / 4;
1549 /******************************************************
1551 * unknown/unsupported bpp
1556 printk(KERN_ERR "cirrusfb: What's this?? "
1557 " requested color depth == %d.\n",
1558 var->bits_per_pixel);
1560 vga_wcrt(regbase, VGA_CRTC_OFFSET, offset & 0xff);
1563 tmp |= 0x10; /* offset overflow bit */
1565 /* screen start addr #16-18, fastpagemode cycles */
1566 vga_wcrt(regbase, CL_CRT1B, tmp);
1568 if (cinfo->btype == BT_SD64 ||
1569 cinfo->btype == BT_PICASSO4 ||
1570 cinfo->btype == BT_ALPINE ||
1571 cinfo->btype == BT_GD5480)
1572 /* screen start address bit 19 */
1573 vga_wcrt(regbase, CL_CRT1D, 0x00);
1575 /* text cursor location high */
1576 vga_wcrt(regbase, VGA_CRTC_CURSOR_HI, 0);
1577 /* text cursor location low */
1578 vga_wcrt(regbase, VGA_CRTC_CURSOR_LO, 0);
1579 /* underline row scanline = at very bottom */
1580 vga_wcrt(regbase, VGA_CRTC_UNDERLINE, 0);
1582 /* controller mode */
1583 vga_wattr(regbase, VGA_ATC_MODE, 1);
1584 /* overscan (border) color */
1585 vga_wattr(regbase, VGA_ATC_OVERSCAN, 0);
1586 /* color plane enable */
1587 vga_wattr(regbase, VGA_ATC_PLANE_ENABLE, 15);
1589 vga_wattr(regbase, CL_AR33, 0);
1591 vga_wattr(regbase, VGA_ATC_COLOR_PAGE, 0);
1593 /* [ EGS: SetOffset(); ] */
1594 /* From SetOffset(): Turn on VideoEnable bit in Attribute controller */
1597 /* set/reset register */
1598 vga_wgfx(regbase, VGA_GFX_SR_VALUE, 0);
1599 /* set/reset enable */
1600 vga_wgfx(regbase, VGA_GFX_SR_ENABLE, 0);
1602 vga_wgfx(regbase, VGA_GFX_COMPARE_VALUE, 0);
1604 vga_wgfx(regbase, VGA_GFX_DATA_ROTATE, 0);
1605 /* read map select */
1606 vga_wgfx(regbase, VGA_GFX_PLANE_READ, 0);
1607 /* miscellaneous register */
1608 vga_wgfx(regbase, VGA_GFX_MISC, 1);
1609 /* color don't care */
1610 vga_wgfx(regbase, VGA_GFX_COMPARE_MASK, 15);
1612 vga_wgfx(regbase, VGA_GFX_BIT_MASK, 255);
1614 /* graphics cursor attributes: nothing special */
1615 vga_wseq(regbase, CL_SEQR12, 0x0);
1617 /* finally, turn on everything - turn off "FullBandwidth" bit */
1618 /* also, set "DotClock%2" bit where requested */
1621 /*** FB_VMODE_CLOCK_HALVE in linux/fb.h not defined anymore ?
1622 if (var->vmode & FB_VMODE_CLOCK_HALVE)
1626 vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, tmp);
1627 DPRINTK("CL_SEQR1: %d\n", tmp);
1629 cinfo->currentmode = regs;
1630 info->fix.type = regs.type;
1631 info->fix.visual = regs.visual;
1632 info->fix.line_length = regs.line_length;
1634 /* pan to requested offset */
1635 cirrusfb_pan_display(var, info);
1637 #ifdef CIRRUSFB_DEBUG
1645 /* for some reason incomprehensible to me, cirrusfb requires that you write
1646 * the registers twice for the settings to take..grr. -dte */
1647 static int cirrusfb_set_par(struct fb_info *info)
1649 cirrusfb_set_par_foo(info);
1650 return cirrusfb_set_par_foo(info);
1653 static int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1654 unsigned blue, unsigned transp,
1655 struct fb_info *info)
1657 struct cirrusfb_info *cinfo = info->par;
1662 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
1664 red >>= (16 - info->var.red.length);
1665 green >>= (16 - info->var.green.length);
1666 blue >>= (16 - info->var.blue.length);
1670 v = (red << info->var.red.offset) |
1671 (green << info->var.green.offset) |
1672 (blue << info->var.blue.offset);
1674 switch (info->var.bits_per_pixel) {
1676 cinfo->pseudo_palette[regno] = v;
1679 cinfo->pseudo_palette[regno] = v;
1683 cinfo->pseudo_palette[regno] = v;
1689 cinfo->palette[regno].red = red;
1690 cinfo->palette[regno].green = green;
1691 cinfo->palette[regno].blue = blue;
1693 if (info->var.bits_per_pixel == 8)
1694 WClut(cinfo, regno, red >> 10, green >> 10, blue >> 10);
1700 /*************************************************************************
1701 cirrusfb_pan_display()
1703 performs display panning - provided hardware permits this
1704 **************************************************************************/
1705 static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
1706 struct fb_info *info)
1711 unsigned char tmp = 0, tmp2 = 0, xpix;
1712 struct cirrusfb_info *cinfo = info->par;
1715 DPRINTK("virtual offset: (%d,%d)\n", var->xoffset, var->yoffset);
1717 /* no range checks for xoffset and yoffset, */
1718 /* as fb_pan_display has already done this */
1719 if (var->vmode & FB_VMODE_YWRAP)
1722 info->var.xoffset = var->xoffset;
1723 info->var.yoffset = var->yoffset;
1725 xoffset = var->xoffset * info->var.bits_per_pixel / 8;
1726 yoffset = var->yoffset;
1728 base = yoffset * cinfo->currentmode.line_length + xoffset;
1730 if (info->var.bits_per_pixel == 1) {
1731 /* base is already correct */
1732 xpix = (unsigned char) (var->xoffset % 8);
1735 xpix = (unsigned char) ((xoffset % 4) * 2);
1738 cirrusfb_WaitBLT(cinfo->regbase); /* make sure all the BLT's are done */
1740 /* lower 8 + 8 bits of screen start address */
1741 vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO,
1742 (unsigned char) (base & 0xff));
1743 vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI,
1744 (unsigned char) (base >> 8));
1746 /* construct bits 16, 17 and 18 of screen start address */
1754 /* 0xf2 is %11110010, exclude tmp bits */
1755 tmp2 = (vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2) | tmp;
1756 vga_wcrt(cinfo->regbase, CL_CRT1B, tmp2);
1758 /* construct bit 19 of screen start address */
1759 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) {
1763 vga_wcrt(cinfo->regbase, CL_CRT1D, tmp2);
1766 /* write pixel panning value to AR33; this does not quite work in 8bpp
1768 * ### Piccolo..? Will this work?
1770 if (info->var.bits_per_pixel == 1)
1771 vga_wattr(cinfo->regbase, CL_AR33, xpix);
1773 cirrusfb_WaitBLT(cinfo->regbase);
1779 static int cirrusfb_blank(int blank_mode, struct fb_info *info)
1782 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
1783 * then the caller blanks by setting the CLUT (Color Look Up Table)
1784 * to all black. Return 0 if blanking succeeded, != 0 if un-/blanking
1785 * failed due to e.g. a video mode which doesn't support it.
1786 * Implements VESA suspend and powerdown modes on hardware that
1787 * supports disabling hsync/vsync:
1788 * blank_mode == 2: suspend vsync
1789 * blank_mode == 3: suspend hsync
1790 * blank_mode == 4: powerdown
1793 struct cirrusfb_info *cinfo = info->par;
1794 int current_mode = cinfo->blank_mode;
1796 DPRINTK("ENTER, blank mode = %d\n", blank_mode);
1798 if (info->state != FBINFO_STATE_RUNNING ||
1799 current_mode == blank_mode) {
1800 DPRINTK("EXIT, returning 0\n");
1805 if (current_mode == FB_BLANK_NORMAL ||
1806 current_mode == FB_BLANK_UNBLANK) {
1807 /* unblank the screen */
1808 val = vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE);
1809 /* clear "FullBandwidth" bit */
1810 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val & 0xdf);
1811 /* and undo VESA suspend trickery */
1812 vga_wgfx(cinfo->regbase, CL_GRE, 0x00);
1816 if (blank_mode > FB_BLANK_NORMAL) {
1817 /* blank the screen */
1818 val = vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE);
1819 /* set "FullBandwidth" bit */
1820 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val | 0x20);
1823 switch (blank_mode) {
1824 case FB_BLANK_UNBLANK:
1825 case FB_BLANK_NORMAL:
1827 case FB_BLANK_VSYNC_SUSPEND:
1828 vga_wgfx(cinfo->regbase, CL_GRE, 0x04);
1830 case FB_BLANK_HSYNC_SUSPEND:
1831 vga_wgfx(cinfo->regbase, CL_GRE, 0x02);
1833 case FB_BLANK_POWERDOWN:
1834 vga_wgfx(cinfo->regbase, CL_GRE, 0x06);
1837 DPRINTK("EXIT, returning 1\n");
1841 cinfo->blank_mode = blank_mode;
1842 DPRINTK("EXIT, returning 0\n");
1844 /* Let fbcon do a soft blank for us */
1845 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1847 /**** END Hardware specific Routines **************************************/
1848 /****************************************************************************/
1849 /**** BEGIN Internal Routines ***********************************************/
1851 static void init_vgachip(struct cirrusfb_info *cinfo)
1853 const struct cirrusfb_board_info_rec *bi;
1857 assert(cinfo != NULL);
1859 bi = &cirrusfb_board_info[cinfo->btype];
1861 /* reset board globally */
1862 switch (cinfo->btype) {
1881 /* disable flickerfixer */
1882 vga_wcrt(cinfo->regbase, CL_CRT51, 0x00);
1884 /* from Klaus' NetBSD driver: */
1885 vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
1886 /* put blitter into 542x compat */
1887 vga_wgfx(cinfo->regbase, CL_GR33, 0x00);
1889 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
1893 /* from Klaus' NetBSD driver: */
1894 vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
1898 /* Nothing to do to reset the board. */
1902 printk(KERN_ERR "cirrusfb: Warning: Unknown board type\n");
1906 assert(cinfo->size > 0); /* make sure RAM size set by this point */
1908 /* the P4 is not fully initialized here; I rely on it having been */
1909 /* inited under AmigaOS already, which seems to work just fine */
1910 /* (Klaus advised to do it this way) */
1912 if (cinfo->btype != BT_PICASSO4) {
1913 WGen(cinfo, CL_VSSM, 0x10); /* EGS: 0x16 */
1914 WGen(cinfo, CL_POS102, 0x01);
1915 WGen(cinfo, CL_VSSM, 0x08); /* EGS: 0x0e */
1917 if (cinfo->btype != BT_SD64)
1918 WGen(cinfo, CL_VSSM2, 0x01);
1920 /* reset sequencer logic */
1921 vga_wseq(cinfo->regbase, CL_SEQR0, 0x03);
1923 /* FullBandwidth (video off) and 8/9 dot clock */
1924 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21);
1925 /* polarity (-/-), disable access to display memory,
1926 * VGA_CRTC_START_HI base address: color
1928 WGen(cinfo, VGA_MIS_W, 0xc1);
1930 /* "magic cookie" - doesn't make any sense to me.. */
1931 /* vga_wgfx(cinfo->regbase, CL_GRA, 0xce); */
1932 /* unlock all extension registers */
1933 vga_wseq(cinfo->regbase, CL_SEQR6, 0x12);
1936 vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
1938 switch (cinfo->btype) {
1940 vga_wseq(cinfo->regbase, CL_SEQRF, 0x98);
1945 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8);
1948 vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f);
1949 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb0);
1953 /* plane mask: nothing */
1954 vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1955 /* character map select: doesn't even matter in gx mode */
1956 vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00);
1957 /* memory mode: chain-4, no odd/even, ext. memory */
1958 vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0e);
1960 /* controller-internal base address of video memory */
1962 vga_wseq(cinfo->regbase, CL_SEQR7, bi->sr07);
1964 /* vga_wseq(cinfo->regbase, CL_SEQR8, 0x00); */
1965 /* EEPROM control: shouldn't be necessary to write to this at all.. */
1967 /* graphics cursor X position (incomplete; position gives rem. 3 bits */
1968 vga_wseq(cinfo->regbase, CL_SEQR10, 0x00);
1969 /* graphics cursor Y position (..."... ) */
1970 vga_wseq(cinfo->regbase, CL_SEQR11, 0x00);
1971 /* graphics cursor attributes */
1972 vga_wseq(cinfo->regbase, CL_SEQR12, 0x00);
1973 /* graphics cursor pattern address */
1974 vga_wseq(cinfo->regbase, CL_SEQR13, 0x00);
1976 /* writing these on a P4 might give problems.. */
1977 if (cinfo->btype != BT_PICASSO4) {
1978 /* configuration readback and ext. color */
1979 vga_wseq(cinfo->regbase, CL_SEQR17, 0x00);
1980 /* signature generator */
1981 vga_wseq(cinfo->regbase, CL_SEQR18, 0x02);
1984 /* MCLK select etc. */
1986 vga_wseq(cinfo->regbase, CL_SEQR1F, bi->sr1f);
1988 /* Screen A preset row scan: none */
1989 vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00);
1990 /* Text cursor start: disable text cursor */
1991 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20);
1992 /* Text cursor end: - */
1993 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00);
1994 /* Screen start address high: 0 */
1995 vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, 0x00);
1996 /* Screen start address low: 0 */
1997 vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, 0x00);
1998 /* text cursor location high: 0 */
1999 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00);
2000 /* text cursor location low: 0 */
2001 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00);
2003 /* Underline Row scanline: - */
2004 vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00);
2005 /* mode control: timing enable, byte mode, no compat modes */
2006 vga_wcrt(cinfo->regbase, VGA_CRTC_MODE, 0xc3);
2007 /* Line Compare: not needed */
2008 vga_wcrt(cinfo->regbase, VGA_CRTC_LINE_COMPARE, 0x00);
2009 /* ### add 0x40 for text modes with > 30 MHz pixclock */
2010 /* ext. display controls: ext.adr. wrap */
2011 vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02);
2013 /* Set/Reset registes: - */
2014 vga_wgfx(cinfo->regbase, VGA_GFX_SR_VALUE, 0x00);
2015 /* Set/Reset enable: - */
2016 vga_wgfx(cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00);
2017 /* Color Compare: - */
2018 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00);
2019 /* Data Rotate: - */
2020 vga_wgfx(cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00);
2021 /* Read Map Select: - */
2022 vga_wgfx(cinfo->regbase, VGA_GFX_PLANE_READ, 0x00);
2023 /* Mode: conf. for 16/4/2 color mode, no odd/even, read/write mode 0 */
2024 vga_wgfx(cinfo->regbase, VGA_GFX_MODE, 0x00);
2025 /* Miscellaneous: memory map base address, graphics mode */
2026 vga_wgfx(cinfo->regbase, VGA_GFX_MISC, 0x01);
2027 /* Color Don't care: involve all planes */
2028 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f);
2029 /* Bit Mask: no mask at all */
2030 vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff);
2031 if (cinfo->btype == BT_ALPINE)
2032 /* (5434 can't have bit 3 set for bitblt) */
2033 vga_wgfx(cinfo->regbase, CL_GRB, 0x20);
2035 /* Graphics controller mode extensions: finer granularity,
2036 * 8byte data latches
2038 vga_wgfx(cinfo->regbase, CL_GRB, 0x28);
2040 vga_wgfx(cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */
2041 vga_wgfx(cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */
2042 vga_wgfx(cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */
2043 /* Background color byte 1: - */
2044 /* vga_wgfx (cinfo->regbase, CL_GR10, 0x00); */
2045 /* vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */
2047 /* Attribute Controller palette registers: "identity mapping" */
2048 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE0, 0x00);
2049 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE1, 0x01);
2050 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE2, 0x02);
2051 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE3, 0x03);
2052 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE4, 0x04);
2053 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE5, 0x05);
2054 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE6, 0x06);
2055 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE7, 0x07);
2056 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE8, 0x08);
2057 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE9, 0x09);
2058 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEA, 0x0a);
2059 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEB, 0x0b);
2060 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEC, 0x0c);
2061 vga_wattr(cinfo->regbase, VGA_ATC_PALETTED, 0x0d);
2062 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEE, 0x0e);
2063 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEF, 0x0f);
2065 /* Attribute Controller mode: graphics mode */
2066 vga_wattr(cinfo->regbase, VGA_ATC_MODE, 0x01);
2067 /* Overscan color reg.: reg. 0 */
2068 vga_wattr(cinfo->regbase, VGA_ATC_OVERSCAN, 0x00);
2069 /* Color Plane enable: Enable all 4 planes */
2070 vga_wattr(cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f);
2071 /* ### vga_wattr(cinfo->regbase, CL_AR33, 0x00); * Pixel Panning: - */
2072 /* Color Select: - */
2073 vga_wattr(cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00);
2075 WGen(cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask */
2077 if (cinfo->btype != BT_ALPINE && cinfo->btype != BT_GD5480)
2078 /* polarity (-/-), enable display mem,
2079 * VGA_CRTC_START_HI i/o base = color
2081 WGen(cinfo, VGA_MIS_W, 0xc3);
2083 /* BLT Start/status: Blitter reset */
2084 vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
2085 /* - " - : "end-of-reset" */
2086 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
2089 WHDR(cinfo, 0); /* Hidden DAC register: - */
2091 printk(KERN_DEBUG "cirrusfb: This board has %ld bytes of DRAM memory\n",
2097 static void switch_monitor(struct cirrusfb_info *cinfo, int on)
2099 #ifdef CONFIG_ZORRO /* only works on Zorro boards */
2100 static int IsOn = 0; /* XXX not ok for multiple boards */
2104 if (cinfo->btype == BT_PICASSO4)
2105 return; /* nothing to switch */
2106 if (cinfo->btype == BT_ALPINE)
2107 return; /* nothing to switch */
2108 if (cinfo->btype == BT_GD5480)
2109 return; /* nothing to switch */
2110 if (cinfo->btype == BT_PICASSO) {
2111 if ((on && !IsOn) || (!on && IsOn))
2118 switch (cinfo->btype) {
2120 WSFR(cinfo, cinfo->SFR | 0x21);
2123 WSFR(cinfo, cinfo->SFR | 0x28);
2128 default: /* do nothing */ break;
2131 switch (cinfo->btype) {
2133 WSFR(cinfo, cinfo->SFR & 0xde);
2136 WSFR(cinfo, cinfo->SFR & 0xd7);
2141 default: /* do nothing */ break;
2146 #endif /* CONFIG_ZORRO */
2149 /******************************************/
2150 /* Linux 2.6-style accelerated functions */
2151 /******************************************/
2153 static void cirrusfb_prim_fillrect(struct cirrusfb_info *cinfo,
2154 const struct fb_fillrect *region)
2156 int m; /* bytes per pixel */
2157 u32 color = (cinfo->info->fix.visual == FB_VISUAL_TRUECOLOR) ?
2158 cinfo->pseudo_palette[region->color] : region->color;
2160 if (cinfo->info->var.bits_per_pixel == 1) {
2161 cirrusfb_RectFill(cinfo->regbase,
2162 cinfo->info->var.bits_per_pixel,
2163 region->dx / 8, region->dy,
2164 region->width / 8, region->height,
2166 cinfo->currentmode.line_length);
2168 m = (cinfo->info->var.bits_per_pixel + 7) / 8;
2169 cirrusfb_RectFill(cinfo->regbase,
2170 cinfo->info->var.bits_per_pixel,
2171 region->dx * m, region->dy,
2172 region->width * m, region->height,
2174 cinfo->currentmode.line_length);
2179 static void cirrusfb_fillrect(struct fb_info *info,
2180 const struct fb_fillrect *region)
2182 struct cirrusfb_info *cinfo = info->par;
2183 struct fb_fillrect modded;
2186 if (info->state != FBINFO_STATE_RUNNING)
2188 if (info->flags & FBINFO_HWACCEL_DISABLED) {
2189 cfb_fillrect(info, region);
2193 vxres = info->var.xres_virtual;
2194 vyres = info->var.yres_virtual;
2196 memcpy(&modded, region, sizeof(struct fb_fillrect));
2198 if (!modded.width || !modded.height ||
2199 modded.dx >= vxres || modded.dy >= vyres)
2202 if (modded.dx + modded.width > vxres)
2203 modded.width = vxres - modded.dx;
2204 if (modded.dy + modded.height > vyres)
2205 modded.height = vyres - modded.dy;
2207 cirrusfb_prim_fillrect(cinfo, &modded);
2210 static void cirrusfb_prim_copyarea(struct cirrusfb_info *cinfo,
2211 const struct fb_copyarea *area)
2213 int m; /* bytes per pixel */
2214 if (cinfo->info->var.bits_per_pixel == 1) {
2215 cirrusfb_BitBLT(cinfo->regbase, cinfo->info->var.bits_per_pixel,
2216 area->sx / 8, area->sy,
2217 area->dx / 8, area->dy,
2218 area->width / 8, area->height,
2219 cinfo->currentmode.line_length);
2221 m = (cinfo->info->var.bits_per_pixel + 7) / 8;
2222 cirrusfb_BitBLT(cinfo->regbase, cinfo->info->var.bits_per_pixel,
2223 area->sx * m, area->sy,
2224 area->dx * m, area->dy,
2225 area->width * m, area->height,
2226 cinfo->currentmode.line_length);
2231 static void cirrusfb_copyarea(struct fb_info *info,
2232 const struct fb_copyarea *area)
2234 struct cirrusfb_info *cinfo = info->par;
2235 struct fb_copyarea modded;
2237 modded.sx = area->sx;
2238 modded.sy = area->sy;
2239 modded.dx = area->dx;
2240 modded.dy = area->dy;
2241 modded.width = area->width;
2242 modded.height = area->height;
2244 if (info->state != FBINFO_STATE_RUNNING)
2246 if (info->flags & FBINFO_HWACCEL_DISABLED) {
2247 cfb_copyarea(info, area);
2251 vxres = info->var.xres_virtual;
2252 vyres = info->var.yres_virtual;
2254 if (!modded.width || !modded.height ||
2255 modded.sx >= vxres || modded.sy >= vyres ||
2256 modded.dx >= vxres || modded.dy >= vyres)
2259 if (modded.sx + modded.width > vxres)
2260 modded.width = vxres - modded.sx;
2261 if (modded.dx + modded.width > vxres)
2262 modded.width = vxres - modded.dx;
2263 if (modded.sy + modded.height > vyres)
2264 modded.height = vyres - modded.sy;
2265 if (modded.dy + modded.height > vyres)
2266 modded.height = vyres - modded.dy;
2268 cirrusfb_prim_copyarea(cinfo, &modded);
2271 static void cirrusfb_imageblit(struct fb_info *info,
2272 const struct fb_image *image)
2274 struct cirrusfb_info *cinfo = info->par;
2276 cirrusfb_WaitBLT(cinfo->regbase);
2277 cfb_imageblit(info, image);
2280 #ifdef CONFIG_PPC_PREP
2281 #define PREP_VIDEO_BASE ((volatile unsigned long) 0xC0000000)
2282 #define PREP_IO_BASE ((volatile unsigned char *) 0x80000000)
2283 static void get_prep_addrs(unsigned long *display, unsigned long *registers)
2287 *display = PREP_VIDEO_BASE;
2288 *registers = (unsigned long) PREP_IO_BASE;
2293 #endif /* CONFIG_PPC_PREP */
2296 static int release_io_ports;
2298 /* Pulled the logic from XFree86 Cirrus driver to get the memory size,
2299 * based on the DRAM bandwidth bit and DRAM bank switching bit. This
2300 * works with 1MB, 2MB and 4MB configurations (which the Motorola boards
2302 static unsigned int cirrusfb_get_memsize(u8 __iomem *regbase)
2309 SRF = vga_rseq(regbase, CL_SEQRF);
2310 switch ((SRF & 0x18)) {
2317 /* 64-bit DRAM data bus width; assume 2MB. Also indicates 2MB memory
2324 printk(KERN_WARNING "CLgenfb: Unknown memory size!\n");
2328 /* If DRAM bank switching is enabled, there must be twice as much
2329 * memory installed. (4MB on the 5434)
2333 /* TODO: Handling of GD5446/5480 (see XF86 sources ...) */
2339 static void get_pci_addrs(const struct pci_dev *pdev,
2340 unsigned long *display, unsigned long *registers)
2342 assert(pdev != NULL);
2343 assert(display != NULL);
2344 assert(registers != NULL);
2351 /* This is a best-guess for now */
2353 if (pci_resource_flags(pdev, 0) & IORESOURCE_IO) {
2354 *display = pci_resource_start(pdev, 1);
2355 *registers = pci_resource_start(pdev, 0);
2357 *display = pci_resource_start(pdev, 0);
2358 *registers = pci_resource_start(pdev, 1);
2361 assert(*display != 0);
2366 static void cirrusfb_pci_unmap(struct cirrusfb_info *cinfo)
2368 struct pci_dev *pdev = cinfo->pdev;
2370 iounmap(cinfo->fbmem);
2371 #if 0 /* if system didn't claim this region, we would... */
2372 release_mem_region(0xA0000, 65535);
2374 if (release_io_ports)
2375 release_region(0x3C0, 32);
2376 pci_release_regions(pdev);
2377 framebuffer_release(cinfo->info);
2379 #endif /* CONFIG_PCI */
2382 static void __devexit cirrusfb_zorro_unmap(struct cirrusfb_info *cinfo)
2384 zorro_release_device(cinfo->zdev);
2386 if (cinfo->btype == BT_PICASSO4) {
2387 cinfo->regbase -= 0x600000;
2388 iounmap((void *)cinfo->regbase);
2389 iounmap((void *)cinfo->fbmem);
2391 if (zorro_resource_start(cinfo->zdev) > 0x01000000)
2392 iounmap((void *)cinfo->fbmem);
2394 framebuffer_release(cinfo->info);
2396 #endif /* CONFIG_ZORRO */
2398 static int cirrusfb_set_fbinfo(struct cirrusfb_info *cinfo)
2400 struct fb_info *info = cinfo->info;
2401 struct fb_var_screeninfo *var = &info->var;
2404 info->pseudo_palette = cinfo->pseudo_palette;
2405 info->flags = FBINFO_DEFAULT
2406 | FBINFO_HWACCEL_XPAN
2407 | FBINFO_HWACCEL_YPAN
2408 | FBINFO_HWACCEL_FILLRECT
2409 | FBINFO_HWACCEL_COPYAREA;
2411 info->flags |= FBINFO_HWACCEL_DISABLED;
2412 info->fbops = &cirrusfb_ops;
2413 info->screen_base = cinfo->fbmem;
2414 if (cinfo->btype == BT_GD5480) {
2415 if (var->bits_per_pixel == 16)
2416 info->screen_base += 1 * MB_;
2417 if (var->bits_per_pixel == 24 || var->bits_per_pixel == 32)
2418 info->screen_base += 2 * MB_;
2421 /* Fill fix common fields */
2422 strlcpy(info->fix.id, cirrusfb_board_info[cinfo->btype].name,
2423 sizeof(info->fix.id));
2425 /* monochrome: only 1 memory plane */
2426 /* 8 bit and above: Use whole memory area */
2427 info->fix.smem_start = cinfo->fbmem_phys;
2428 info->fix.smem_len =
2429 (var->bits_per_pixel == 1) ? cinfo->size / 4 : cinfo->size;
2430 info->fix.type = cinfo->currentmode.type;
2431 info->fix.type_aux = 0;
2432 info->fix.visual = cinfo->currentmode.visual;
2433 info->fix.xpanstep = 1;
2434 info->fix.ypanstep = 1;
2435 info->fix.ywrapstep = 0;
2436 info->fix.line_length = cinfo->currentmode.line_length;
2438 /* FIXME: map region at 0xB8000 if available, fill in here */
2439 info->fix.mmio_start = cinfo->fbregs_phys;
2440 info->fix.mmio_len = 0;
2441 info->fix.accel = FB_ACCEL_NONE;
2443 fb_alloc_cmap(&info->cmap, 256, 0);
2448 static int cirrusfb_register(struct cirrusfb_info *cinfo)
2450 struct fb_info *info;
2452 enum cirrus_board btype;
2456 printk(KERN_INFO "cirrusfb: Driver for Cirrus Logic based "
2457 "graphic boards, v" CIRRUSFB_VERSION "\n");
2460 btype = cinfo->btype;
2463 assert(btype != BT_NONE);
2465 DPRINTK("cirrusfb: (RAM start set to: 0x%p)\n", cinfo->fbmem);
2467 /* Make pretend we've set the var so our structures are in a "good" */
2468 /* state, even though we haven't written the mode to the hw yet... */
2469 info->var = cirrusfb_predefined[cirrusfb_def_mode].var;
2470 info->var.activate = FB_ACTIVATE_NOW;
2472 err = cirrusfb_decode_var(&info->var, &cinfo->currentmode, info);
2474 /* should never happen */
2475 DPRINTK("choking on default var... umm, no good.\n");
2476 goto err_unmap_cirrusfb;
2479 /* set all the vital stuff */
2480 cirrusfb_set_fbinfo(cinfo);
2482 err = register_framebuffer(info);
2484 printk(KERN_ERR "cirrusfb: could not register "
2485 "fb device; err = %d!\n", err);
2486 goto err_dealloc_cmap;
2489 DPRINTK("EXIT, returning 0\n");
2493 fb_dealloc_cmap(&info->cmap);
2495 cinfo->unmap(cinfo);
2499 static void __devexit cirrusfb_cleanup(struct fb_info *info)
2501 struct cirrusfb_info *cinfo = info->par;
2504 switch_monitor(cinfo, 0);
2506 unregister_framebuffer(info);
2507 fb_dealloc_cmap(&info->cmap);
2508 printk("Framebuffer unregistered\n");
2509 cinfo->unmap(cinfo);
2515 static int cirrusfb_pci_register(struct pci_dev *pdev,
2516 const struct pci_device_id *ent)
2518 struct cirrusfb_info *cinfo;
2519 struct fb_info *info;
2520 enum cirrus_board btype;
2521 unsigned long board_addr, board_size;
2524 ret = pci_enable_device(pdev);
2526 printk(KERN_ERR "cirrusfb: Cannot enable PCI device\n");
2530 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &pdev->dev);
2532 printk(KERN_ERR "cirrusfb: could not allocate memory\n");
2540 cinfo->btype = btype = (enum cirrus_board) ent->driver_data;
2542 DPRINTK(" Found PCI device, base address 0 is 0x%x, btype set to %d\n",
2543 pdev->resource[0].start, btype);
2544 DPRINTK(" base address 1 is 0x%x\n", pdev->resource[1].start);
2547 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, 0x00000000);
2548 #ifdef CONFIG_PPC_PREP
2549 get_prep_addrs(&board_addr, &cinfo->fbregs_phys);
2551 /* PReP dies if we ioremap the IO registers, but it works w/out... */
2552 cinfo->regbase = (char __iomem *) cinfo->fbregs_phys;
2554 DPRINTK("Attempt to get PCI info for Cirrus Graphics Card\n");
2555 get_pci_addrs(pdev, &board_addr, &cinfo->fbregs_phys);
2556 /* FIXME: this forces VGA. alternatives? */
2557 cinfo->regbase = NULL;
2560 DPRINTK("Board address: 0x%lx, register address: 0x%lx\n",
2561 board_addr, cinfo->fbregs_phys);
2563 board_size = (btype == BT_GD5480) ?
2564 32 * MB_ : cirrusfb_get_memsize(cinfo->regbase);
2566 ret = pci_request_regions(pdev, "cirrusfb");
2568 printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, "
2571 goto err_release_fb;
2573 #if 0 /* if the system didn't claim this region, we would... */
2574 if (!request_mem_region(0xA0000, 65535, "cirrusfb")) {
2575 printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, abort\n"
2579 goto err_release_regions;
2582 if (request_region(0x3C0, 32, "cirrusfb"))
2583 release_io_ports = 1;
2585 cinfo->fbmem = ioremap(board_addr, board_size);
2586 if (!cinfo->fbmem) {
2588 goto err_release_legacy;
2591 cinfo->fbmem_phys = board_addr;
2592 cinfo->size = board_size;
2593 cinfo->unmap = cirrusfb_pci_unmap;
2595 printk(KERN_INFO " RAM (%lu kB) at 0xx%lx, ",
2596 cinfo->size / KB_, board_addr);
2597 printk(KERN_INFO "Cirrus Logic chipset on PCI bus\n");
2598 pci_set_drvdata(pdev, info);
2600 ret = cirrusfb_register(cinfo);
2602 iounmap(cinfo->fbmem);
2606 if (release_io_ports)
2607 release_region(0x3C0, 32);
2609 release_mem_region(0xA0000, 65535);
2610 err_release_regions:
2612 pci_release_regions(pdev);
2614 framebuffer_release(info);
2620 static void __devexit cirrusfb_pci_unregister(struct pci_dev *pdev)
2622 struct fb_info *info = pci_get_drvdata(pdev);
2625 cirrusfb_cleanup(info);
2630 static struct pci_driver cirrusfb_pci_driver = {
2632 .id_table = cirrusfb_pci_table,
2633 .probe = cirrusfb_pci_register,
2634 .remove = __devexit_p(cirrusfb_pci_unregister),
2637 .suspend = cirrusfb_pci_suspend,
2638 .resume = cirrusfb_pci_resume,
2642 #endif /* CONFIG_PCI */
2645 static int cirrusfb_zorro_register(struct zorro_dev *z,
2646 const struct zorro_device_id *ent)
2648 struct cirrusfb_info *cinfo;
2649 struct fb_info *info;
2650 enum cirrus_board btype;
2651 struct zorro_dev *z2 = NULL;
2652 unsigned long board_addr, board_size, size;
2655 btype = ent->driver_data;
2656 if (cirrusfb_zorro_table2[btype].id2)
2657 z2 = zorro_find_device(cirrusfb_zorro_table2[btype].id2, NULL);
2658 size = cirrusfb_zorro_table2[btype].size;
2659 printk(KERN_INFO "cirrusfb: %s board detected; ",
2660 cirrusfb_board_info[btype].name);
2662 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &z->dev);
2664 printk(KERN_ERR "cirrusfb: could not allocate memory\n");
2671 cinfo->btype = btype;
2675 assert(btype != BT_NONE);
2678 board_addr = zorro_resource_start(z);
2679 board_size = zorro_resource_len(z);
2682 if (!zorro_request_device(z, "cirrusfb")) {
2683 printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, "
2687 goto err_release_fb;
2690 printk(" RAM (%lu MB) at $%lx, ", board_size / MB_, board_addr);
2694 if (btype == BT_PICASSO4) {
2695 printk(KERN_INFO " REG at $%lx\n", board_addr + 0x600000);
2697 /* To be precise, for the P4 this is not the */
2698 /* begin of the board, but the begin of RAM. */
2699 /* for P4, map in its address space in 2 chunks (### TEST! ) */
2700 /* (note the ugly hardcoded 16M number) */
2701 cinfo->regbase = ioremap(board_addr, 16777216);
2702 if (!cinfo->regbase)
2703 goto err_release_region;
2705 DPRINTK("cirrusfb: Virtual address for board set to: $%p\n",
2707 cinfo->regbase += 0x600000;
2708 cinfo->fbregs_phys = board_addr + 0x600000;
2710 cinfo->fbmem_phys = board_addr + 16777216;
2711 cinfo->fbmem = ioremap(cinfo->fbmem_phys, 16777216);
2713 goto err_unmap_regbase;
2715 printk(KERN_INFO " REG at $%lx\n",
2716 (unsigned long) z2->resource.start);
2718 cinfo->fbmem_phys = board_addr;
2719 if (board_addr > 0x01000000)
2720 cinfo->fbmem = ioremap(board_addr, board_size);
2722 cinfo->fbmem = (caddr_t) ZTWO_VADDR(board_addr);
2724 goto err_release_region;
2726 /* set address for REG area of board */
2727 cinfo->regbase = (caddr_t) ZTWO_VADDR(z2->resource.start);
2728 cinfo->fbregs_phys = z2->resource.start;
2730 DPRINTK("cirrusfb: Virtual address for board set to: $%p\n",
2733 cinfo->unmap = cirrusfb_zorro_unmap;
2735 printk(KERN_INFO "Cirrus Logic chipset on Zorro bus\n");
2736 zorro_set_drvdata(z, info);
2738 ret = cirrusfb_register(cinfo);
2740 if (btype == BT_PICASSO4) {
2741 iounmap(cinfo->fbmem);
2742 iounmap(cinfo->regbase - 0x600000);
2743 } else if (board_addr > 0x01000000)
2744 iounmap(cinfo->fbmem);
2749 /* Parental advisory: explicit hack */
2750 iounmap(cinfo->regbase - 0x600000);
2752 release_region(board_addr, board_size);
2754 framebuffer_release(info);
2759 void __devexit cirrusfb_zorro_unregister(struct zorro_dev *z)
2761 struct fb_info *info = zorro_get_drvdata(z);
2764 cirrusfb_cleanup(info);
2769 static struct zorro_driver cirrusfb_zorro_driver = {
2771 .id_table = cirrusfb_zorro_table,
2772 .probe = cirrusfb_zorro_register,
2773 .remove = __devexit_p(cirrusfb_zorro_unregister),
2775 #endif /* CONFIG_ZORRO */
2777 static int __init cirrusfb_init(void)
2782 char *option = NULL;
2784 if (fb_get_options("cirrusfb", &option))
2786 cirrusfb_setup(option);
2790 error |= zorro_register_driver(&cirrusfb_zorro_driver);
2793 error |= pci_register_driver(&cirrusfb_pci_driver);
2799 static int __init cirrusfb_setup(char *options) {
2800 char *this_opt, s[32];
2805 if (!options || !*options)
2808 while ((this_opt = strsep(&options, ",")) != NULL) {
2809 if (!*this_opt) continue;
2811 DPRINTK("cirrusfb_setup: option '%s'\n", this_opt);
2813 for (i = 0; i < NUM_TOTAL_MODES; i++) {
2814 sprintf(s, "mode:%s", cirrusfb_predefined[i].name);
2815 if (strcmp(this_opt, s) == 0)
2816 cirrusfb_def_mode = i;
2818 if (!strcmp(this_opt, "noaccel"))
2829 MODULE_AUTHOR("Copyright 1999,2000 Jeff Garzik <jgarzik@pobox.com>");
2830 MODULE_DESCRIPTION("Accelerated FBDev driver for Cirrus Logic chips");
2831 MODULE_LICENSE("GPL");
2833 static void __exit cirrusfb_exit(void)
2836 pci_unregister_driver(&cirrusfb_pci_driver);
2839 zorro_unregister_driver(&cirrusfb_zorro_driver);
2843 module_init(cirrusfb_init);
2846 module_exit(cirrusfb_exit);
2849 /**********************************************************************/
2850 /* about the following functions - I have used the same names for the */
2851 /* functions as Markus Wild did in his Retina driver for NetBSD as */
2852 /* they just made sense for this purpose. Apart from that, I wrote */
2853 /* these functions myself. */
2854 /**********************************************************************/
2856 /*** WGen() - write into one of the external/general registers ***/
2857 static void WGen(const struct cirrusfb_info *cinfo,
2858 int regnum, unsigned char val)
2860 unsigned long regofs = 0;
2862 if (cinfo->btype == BT_PICASSO) {
2863 /* Picasso II specific hack */
2864 /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
2865 regnum == CL_VSSM2) */
2866 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
2870 vga_w(cinfo->regbase, regofs + regnum, val);
2873 /*** RGen() - read out one of the external/general registers ***/
2874 static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum)
2876 unsigned long regofs = 0;
2878 if (cinfo->btype == BT_PICASSO) {
2879 /* Picasso II specific hack */
2880 /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
2881 regnum == CL_VSSM2) */
2882 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
2886 return vga_r(cinfo->regbase, regofs + regnum);
2889 /*** AttrOn() - turn on VideoEnable for Attribute controller ***/
2890 static void AttrOn(const struct cirrusfb_info *cinfo)
2892 assert(cinfo != NULL);
2896 if (vga_rcrt(cinfo->regbase, CL_CRT24) & 0x80) {
2897 /* if we're just in "write value" mode, write back the */
2898 /* same value as before to not modify anything */
2899 vga_w(cinfo->regbase, VGA_ATT_IW,
2900 vga_r(cinfo->regbase, VGA_ATT_R));
2902 /* turn on video bit */
2903 /* vga_w(cinfo->regbase, VGA_ATT_IW, 0x20); */
2904 vga_w(cinfo->regbase, VGA_ATT_IW, 0x33);
2906 /* dummy write on Reg0 to be on "write index" mode next time */
2907 vga_w(cinfo->regbase, VGA_ATT_IW, 0x00);
2912 /*** WHDR() - write into the Hidden DAC register ***/
2913 /* as the HDR is the only extension register that requires special treatment
2914 * (the other extension registers are accessible just like the "ordinary"
2915 * registers of their functional group) here is a specialized routine for
2918 static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val)
2920 unsigned char dummy;
2922 if (cinfo->btype == BT_PICASSO) {
2923 /* Klaus' hint for correct access to HDR on some boards */
2924 /* first write 0 to pixel mask (3c6) */
2925 WGen(cinfo, VGA_PEL_MSK, 0x00);
2927 /* next read dummy from pixel address (3c8) */
2928 dummy = RGen(cinfo, VGA_PEL_IW);
2931 /* now do the usual stuff to access the HDR */
2933 dummy = RGen(cinfo, VGA_PEL_MSK);
2935 dummy = RGen(cinfo, VGA_PEL_MSK);
2937 dummy = RGen(cinfo, VGA_PEL_MSK);
2939 dummy = RGen(cinfo, VGA_PEL_MSK);
2942 WGen(cinfo, VGA_PEL_MSK, val);
2945 if (cinfo->btype == BT_PICASSO) {
2946 /* now first reset HDR access counter */
2947 dummy = RGen(cinfo, VGA_PEL_IW);
2950 /* and at the end, restore the mask value */
2951 /* ## is this mask always 0xff? */
2952 WGen(cinfo, VGA_PEL_MSK, 0xff);
2957 /*** WSFR() - write to the "special function register" (SFR) ***/
2958 static void WSFR(struct cirrusfb_info *cinfo, unsigned char val)
2961 assert(cinfo->regbase != NULL);
2963 z_writeb(val, cinfo->regbase + 0x8000);
2967 /* The Picasso has a second register for switching the monitor bit */
2968 static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val)
2971 /* writing an arbitrary value to this one causes the monitor switcher */
2972 /* to flip to Amiga display */
2973 assert(cinfo->regbase != NULL);
2975 z_writeb(val, cinfo->regbase + 0x9000);
2979 /*** WClut - set CLUT entry (range: 0..63) ***/
2980 static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red,
2981 unsigned char green, unsigned char blue)
2983 unsigned int data = VGA_PEL_D;
2985 /* address write mode register is not translated.. */
2986 vga_w(cinfo->regbase, VGA_PEL_IW, regnum);
2988 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2989 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
2990 /* but DAC data register IS, at least for Picasso II */
2991 if (cinfo->btype == BT_PICASSO)
2993 vga_w(cinfo->regbase, data, red);
2994 vga_w(cinfo->regbase, data, green);
2995 vga_w(cinfo->regbase, data, blue);
2997 vga_w(cinfo->regbase, data, blue);
2998 vga_w(cinfo->regbase, data, green);
2999 vga_w(cinfo->regbase, data, red);
3004 /*** RClut - read CLUT entry (range 0..63) ***/
3005 static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red,
3006 unsigned char *green, unsigned char *blue)
3008 unsigned int data = VGA_PEL_D;
3010 vga_w(cinfo->regbase, VGA_PEL_IR, regnum);
3012 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
3013 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
3014 if (cinfo->btype == BT_PICASSO)
3016 *red = vga_r(cinfo->regbase, data);
3017 *green = vga_r(cinfo->regbase, data);
3018 *blue = vga_r(cinfo->regbase, data);
3020 *blue = vga_r(cinfo->regbase, data);
3021 *green = vga_r(cinfo->regbase, data);
3022 *red = vga_r(cinfo->regbase, data);
3027 /*******************************************************************
3030 Wait for the BitBLT engine to complete a possible earlier job
3031 *********************************************************************/
3033 /* FIXME: use interrupts instead */
3034 static void cirrusfb_WaitBLT(u8 __iomem *regbase)
3036 /* now busy-wait until we're done */
3037 while (vga_rgfx(regbase, CL_GR31) & 0x08)
3041 /*******************************************************************
3044 perform accelerated "scrolling"
3045 ********************************************************************/
3047 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
3048 u_short curx, u_short cury,
3049 u_short destx, u_short desty,
3050 u_short width, u_short height,
3051 u_short line_length)
3053 u_short nwidth, nheight;
3060 nheight = height - 1;
3063 /* if source adr < dest addr, do the Blt backwards */
3064 if (cury <= desty) {
3065 if (cury == desty) {
3066 /* if src and dest are on the same line, check x */
3073 /* standard case: forward blitting */
3074 nsrc = (cury * line_length) + curx;
3075 ndest = (desty * line_length) + destx;
3077 /* this means start addresses are at the end,
3078 * counting backwards
3080 nsrc = cury * line_length + curx +
3081 nheight * line_length + nwidth;
3082 ndest = desty * line_length + destx +
3083 nheight * line_length + nwidth;
3087 run-down of registers to be programmed:
3095 VGA_GFX_SR_VALUE / VGA_GFX_SR_ENABLE: "fill color"
3099 cirrusfb_WaitBLT(regbase);
3101 /* pitch: set to line_length */
3102 /* dest pitch low */
3103 vga_wgfx(regbase, CL_GR24, line_length & 0xff);
3105 vga_wgfx(regbase, CL_GR25, line_length >> 8);
3106 /* source pitch low */
3107 vga_wgfx(regbase, CL_GR26, line_length & 0xff);
3108 /* source pitch hi */
3109 vga_wgfx(regbase, CL_GR27, line_length >> 8);
3111 /* BLT width: actual number of pixels - 1 */
3113 vga_wgfx(regbase, CL_GR20, nwidth & 0xff);
3115 vga_wgfx(regbase, CL_GR21, nwidth >> 8);
3117 /* BLT height: actual number of lines -1 */
3118 /* BLT height low */
3119 vga_wgfx(regbase, CL_GR22, nheight & 0xff);
3121 vga_wgfx(regbase, CL_GR23, nheight >> 8);
3123 /* BLT destination */
3125 vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
3127 vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
3129 vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
3133 vga_wgfx(regbase, CL_GR2C, (u_char) (nsrc & 0xff));
3135 vga_wgfx(regbase, CL_GR2D, (u_char) (nsrc >> 8));
3137 vga_wgfx(regbase, CL_GR2E, (u_char) (nsrc >> 16));
3140 vga_wgfx(regbase, CL_GR30, bltmode); /* BLT mode */
3142 /* BLT ROP: SrcCopy */
3143 vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */
3145 /* and finally: GO! */
3146 vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */
3151 /*******************************************************************
3154 perform accelerated rectangle fill
3155 ********************************************************************/
3157 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
3158 u_short x, u_short y, u_short width, u_short height,
3159 u_char color, u_short line_length)
3161 u_short nwidth, nheight;
3168 nheight = height - 1;
3170 ndest = (y * line_length) + x;
3172 cirrusfb_WaitBLT(regbase);
3174 /* pitch: set to line_length */
3175 vga_wgfx(regbase, CL_GR24, line_length & 0xff); /* dest pitch low */
3176 vga_wgfx(regbase, CL_GR25, line_length >> 8); /* dest pitch hi */
3177 vga_wgfx(regbase, CL_GR26, line_length & 0xff); /* source pitch low */
3178 vga_wgfx(regbase, CL_GR27, line_length >> 8); /* source pitch hi */
3180 /* BLT width: actual number of pixels - 1 */
3181 vga_wgfx(regbase, CL_GR20, nwidth & 0xff); /* BLT width low */
3182 vga_wgfx(regbase, CL_GR21, nwidth >> 8); /* BLT width hi */
3184 /* BLT height: actual number of lines -1 */
3185 vga_wgfx(regbase, CL_GR22, nheight & 0xff); /* BLT height low */
3186 vga_wgfx(regbase, CL_GR23, nheight >> 8); /* BLT width hi */
3188 /* BLT destination */
3190 vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
3192 vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
3194 vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
3196 /* BLT source: set to 0 (is a dummy here anyway) */
3197 vga_wgfx(regbase, CL_GR2C, 0x00); /* BLT src low */
3198 vga_wgfx(regbase, CL_GR2D, 0x00); /* BLT src mid */
3199 vga_wgfx(regbase, CL_GR2E, 0x00); /* BLT src hi */
3201 /* This is a ColorExpand Blt, using the */
3202 /* same color for foreground and background */
3203 vga_wgfx(regbase, VGA_GFX_SR_VALUE, color); /* foreground color */
3204 vga_wgfx(regbase, VGA_GFX_SR_ENABLE, color); /* background color */
3207 if (bits_per_pixel == 16) {
3208 vga_wgfx(regbase, CL_GR10, color); /* foreground color */
3209 vga_wgfx(regbase, CL_GR11, color); /* background color */
3212 } else if (bits_per_pixel == 32) {
3213 vga_wgfx(regbase, CL_GR10, color); /* foreground color */
3214 vga_wgfx(regbase, CL_GR11, color); /* background color */
3215 vga_wgfx(regbase, CL_GR12, color); /* foreground color */
3216 vga_wgfx(regbase, CL_GR13, color); /* background color */
3217 vga_wgfx(regbase, CL_GR14, 0); /* foreground color */
3218 vga_wgfx(regbase, CL_GR15, 0); /* background color */
3222 /* BLT mode: color expand, Enable 8x8 copy (faster?) */
3223 vga_wgfx(regbase, CL_GR30, op); /* BLT mode */
3225 /* BLT ROP: SrcCopy */
3226 vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */
3228 /* and finally: GO! */
3229 vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */
3234 /**************************************************************************
3235 * bestclock() - determine closest possible clock lower(?) than the
3236 * desired pixel clock
3237 **************************************************************************/
3238 static void bestclock(long freq, long *best, long *nom,
3239 long *den, long *div, long maxfreq)
3243 assert(best != NULL);
3244 assert(nom != NULL);
3245 assert(den != NULL);
3246 assert(div != NULL);
3247 assert(maxfreq > 0);
3264 for (n = 32; n < 128; n++) {
3265 d = (143181 * n) / f;
3266 if ((d >= 7) && (d <= 63)) {
3269 h = (14318 * n) / d;
3270 if (abs(h - freq) < abs(*best - freq)) {
3282 d = ((143181 * n) + f - 1) / f;
3283 if ((d >= 7) && (d <= 63)) {
3286 h = (14318 * n) / d;
3287 if (abs(h - freq) < abs(*best - freq)) {
3301 DPRINTK("Best possible values for given frequency:\n");
3302 DPRINTK(" best: %ld kHz nom: %ld den: %ld div: %ld\n",
3303 freq, *nom, *den, *div);
3308 /* -------------------------------------------------------------------------
3310 * debugging functions
3312 * -------------------------------------------------------------------------
3315 #ifdef CIRRUSFB_DEBUG
3318 * cirrusfb_dbg_print_byte
3319 * @name: name associated with byte value to be displayed
3320 * @val: byte value to be displayed
3323 * Display an indented string, along with a hexidecimal byte value, and
3324 * its decoded bits. Bits 7 through 0 are listed in left-to-right
3329 void cirrusfb_dbg_print_byte(const char *name, unsigned char val)
3331 DPRINTK("%8s = 0x%02X (bits 7-0: %c%c%c%c%c%c%c%c)\n",
3333 val & 0x80 ? '1' : '0',
3334 val & 0x40 ? '1' : '0',
3335 val & 0x20 ? '1' : '0',
3336 val & 0x10 ? '1' : '0',
3337 val & 0x08 ? '1' : '0',
3338 val & 0x04 ? '1' : '0',
3339 val & 0x02 ? '1' : '0',
3340 val & 0x01 ? '1' : '0');
3344 * cirrusfb_dbg_print_regs
3345 * @base: If using newmmio, the newmmio base address, otherwise %NULL
3346 * @reg_class: type of registers to read: %CRT, or %SEQ
3349 * Dumps the given list of VGA CRTC registers. If @base is %NULL,
3350 * old-style I/O ports are queried for information, otherwise MMIO is
3351 * used at the given @base address to query the information.
3355 void cirrusfb_dbg_print_regs(caddr_t regbase,
3356 enum cirrusfb_dbg_reg_class reg_class, ...)
3359 unsigned char val = 0;
3363 va_start(list, reg_class);
3365 name = va_arg(list, char *);
3366 while (name != NULL) {
3367 reg = va_arg(list, int);
3369 switch (reg_class) {
3371 val = vga_rcrt(regbase, (unsigned char) reg);
3374 val = vga_rseq(regbase, (unsigned char) reg);
3377 /* should never occur */
3382 cirrusfb_dbg_print_byte(name, val);
3384 name = va_arg(list, char *);
3397 static void cirrusfb_dump(void)
3399 cirrusfb_dbg_reg_dump(NULL);
3403 * cirrusfb_dbg_reg_dump
3404 * @base: If using newmmio, the newmmio base address, otherwise %NULL
3407 * Dumps a list of interesting VGA and CIRRUSFB registers. If @base is %NULL,
3408 * old-style I/O ports are queried for information, otherwise MMIO is
3409 * used at the given @base address to query the information.
3413 void cirrusfb_dbg_reg_dump(caddr_t regbase)
3415 DPRINTK("CIRRUSFB VGA CRTC register dump:\n");
3417 cirrusfb_dbg_print_regs(regbase, CRT,
3469 DPRINTK("CIRRUSFB VGA SEQ register dump:\n");
3471 cirrusfb_dbg_print_regs(regbase, SEQ,
3503 #endif /* CIRRUSFB_DEBUG */