2 * OHCI HCD (Host Controller Driver) for USB.
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
7 * This file is licenced under the GPL.
10 #include <linux/irq.h>
12 static void urb_free_priv (struct ohci_hcd *hc, urb_priv_t *urb_priv)
14 int last = urb_priv->length - 1;
20 for (i = 0; i <= last; i++) {
21 td = urb_priv->td [i];
27 list_del (&urb_priv->pending);
31 /*-------------------------------------------------------------------------*/
34 * URB goes back to driver, and isn't reissued.
35 * It's completely gone from HC data structures.
36 * PRECONDITION: ohci lock held, irqs blocked.
39 finish_urb (struct ohci_hcd *ohci, struct urb *urb)
40 __releases(ohci->lock)
41 __acquires(ohci->lock)
43 // ASSERT (urb->hcpriv != 0);
45 urb_free_priv (ohci, urb->hcpriv);
48 spin_lock (&urb->lock);
49 if (likely (urb->status == -EINPROGRESS))
51 /* report short control reads right even though the data TD always
52 * has TD_R set. (much simpler, but creates the 1-td limit.)
54 if (unlikely (urb->transfer_flags & URB_SHORT_NOT_OK)
55 && unlikely (usb_pipecontrol (urb->pipe))
56 && urb->actual_length < urb->transfer_buffer_length
57 && usb_pipein (urb->pipe)
58 && urb->status == 0) {
59 urb->status = -EREMOTEIO;
61 spin_unlock (&urb->lock);
63 switch (usb_pipetype (urb->pipe)) {
64 case PIPE_ISOCHRONOUS:
65 ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs--;
68 ohci_to_hcd(ohci)->self.bandwidth_int_reqs--;
72 #ifdef OHCI_VERBOSE_DEBUG
73 urb_print (urb, "RET", usb_pipeout (urb->pipe));
76 /* urb->complete() can reenter this HCD */
77 spin_unlock (&ohci->lock);
78 usb_hcd_giveback_urb (ohci_to_hcd(ohci), urb);
79 spin_lock (&ohci->lock);
81 /* stop periodic dma if it's not needed */
82 if (ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0
83 && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0) {
84 ohci->hc_control &= ~(OHCI_CTRL_PLE|OHCI_CTRL_IE);
85 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
90 /*-------------------------------------------------------------------------*
91 * ED handling functions
92 *-------------------------------------------------------------------------*/
94 /* search for the right schedule branch to use for a periodic ed.
95 * does some load balancing; returns the branch, or negative errno.
97 static int balance (struct ohci_hcd *ohci, int interval, int load)
99 int i, branch = -ENOSPC;
101 /* iso periods can be huge; iso tds specify frame numbers */
102 if (interval > NUM_INTS)
105 /* search for the least loaded schedule branch of that period
106 * that has enough bandwidth left unreserved.
108 for (i = 0; i < interval ; i++) {
109 if (branch < 0 || ohci->load [branch] > ohci->load [i]) {
110 #if 1 /* CONFIG_USB_BANDWIDTH */
113 /* usb 1.1 says 90% of one frame */
114 for (j = i; j < NUM_INTS; j += interval) {
115 if ((ohci->load [j] + load) > 900)
127 /*-------------------------------------------------------------------------*/
129 /* both iso and interrupt requests have periods; this routine puts them
130 * into the schedule tree in the apppropriate place. most iso devices use
131 * 1msec periods, but that's not required.
133 static void periodic_link (struct ohci_hcd *ohci, struct ed *ed)
137 ohci_vdbg (ohci, "link %sed %p branch %d [%dus.], interval %d\n",
138 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
139 ed, ed->branch, ed->load, ed->interval);
141 for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
142 struct ed **prev = &ohci->periodic [i];
143 __hc32 *prev_p = &ohci->hcca->int_table [i];
144 struct ed *here = *prev;
146 /* sorting each branch by period (slow before fast)
147 * lets us share the faster parts of the tree.
148 * (plus maybe: put interrupt eds before iso)
150 while (here && ed != here) {
151 if (ed->interval > here->interval)
153 prev = &here->ed_next;
154 prev_p = &here->hwNextED;
160 ed->hwNextED = *prev_p;
163 *prev_p = cpu_to_hc32(ohci, ed->dma);
166 ohci->load [i] += ed->load;
168 ohci_to_hcd(ohci)->self.bandwidth_allocated += ed->load / ed->interval;
171 /* link an ed into one of the HC chains */
173 static int ed_schedule (struct ohci_hcd *ohci, struct ed *ed)
177 if (ohci_to_hcd(ohci)->state == HC_STATE_QUIESCING)
186 /* we care about rm_list when setting CLE/BLE in case the HC was at
187 * work on some TD when CLE/BLE was turned off, and isn't quiesced
188 * yet. finish_unlinks() restarts as needed, some upcoming INTR_SF.
190 * control and bulk EDs are doubly linked (ed_next, ed_prev), but
191 * periodic ones are singly linked (ed_next). that's because the
192 * periodic schedule encodes a tree like figure 3-5 in the ohci
193 * spec: each qh can have several "previous" nodes, and the tree
194 * doesn't have unused/idle descriptors.
198 if (ohci->ed_controltail == NULL) {
199 WARN_ON (ohci->hc_control & OHCI_CTRL_CLE);
200 ohci_writel (ohci, ed->dma,
201 &ohci->regs->ed_controlhead);
203 ohci->ed_controltail->ed_next = ed;
204 ohci->ed_controltail->hwNextED = cpu_to_hc32 (ohci,
207 ed->ed_prev = ohci->ed_controltail;
208 if (!ohci->ed_controltail && !ohci->ed_rm_list) {
210 ohci->hc_control |= OHCI_CTRL_CLE;
211 ohci_writel (ohci, 0, &ohci->regs->ed_controlcurrent);
212 ohci_writel (ohci, ohci->hc_control,
213 &ohci->regs->control);
215 ohci->ed_controltail = ed;
219 if (ohci->ed_bulktail == NULL) {
220 WARN_ON (ohci->hc_control & OHCI_CTRL_BLE);
221 ohci_writel (ohci, ed->dma, &ohci->regs->ed_bulkhead);
223 ohci->ed_bulktail->ed_next = ed;
224 ohci->ed_bulktail->hwNextED = cpu_to_hc32 (ohci,
227 ed->ed_prev = ohci->ed_bulktail;
228 if (!ohci->ed_bulktail && !ohci->ed_rm_list) {
230 ohci->hc_control |= OHCI_CTRL_BLE;
231 ohci_writel (ohci, 0, &ohci->regs->ed_bulkcurrent);
232 ohci_writel (ohci, ohci->hc_control,
233 &ohci->regs->control);
235 ohci->ed_bulktail = ed;
238 // case PIPE_INTERRUPT:
239 // case PIPE_ISOCHRONOUS:
241 branch = balance (ohci, ed->interval, ed->load);
244 "ERR %d, interval %d msecs, load %d\n",
245 branch, ed->interval, ed->load);
246 // FIXME if there are TDs queued, fail them!
250 periodic_link (ohci, ed);
253 /* the HC may not see the schedule updates yet, but if it does
254 * then they'll be properly ordered.
259 /*-------------------------------------------------------------------------*/
261 /* scan the periodic table to find and unlink this ED */
262 static void periodic_unlink (struct ohci_hcd *ohci, struct ed *ed)
266 for (i = ed->branch; i < NUM_INTS; i += ed->interval) {
268 struct ed **prev = &ohci->periodic [i];
269 __hc32 *prev_p = &ohci->hcca->int_table [i];
271 while (*prev && (temp = *prev) != ed) {
272 prev_p = &temp->hwNextED;
273 prev = &temp->ed_next;
276 *prev_p = ed->hwNextED;
279 ohci->load [i] -= ed->load;
281 ohci_to_hcd(ohci)->self.bandwidth_allocated -= ed->load / ed->interval;
283 ohci_vdbg (ohci, "unlink %sed %p branch %d [%dus.], interval %d\n",
284 (ed->hwINFO & cpu_to_hc32 (ohci, ED_ISO)) ? "iso " : "",
285 ed, ed->branch, ed->load, ed->interval);
288 /* unlink an ed from one of the HC chains.
289 * just the link to the ed is unlinked.
290 * the link from the ed still points to another operational ed or 0
291 * so the HC can eventually finish the processing of the unlinked ed
292 * (assuming it already started that, which needn't be true).
294 * ED_UNLINK is a transient state: the HC may still see this ED, but soon
295 * it won't. ED_SKIP means the HC will finish its current transaction,
296 * but won't start anything new. The TD queue may still grow; device
297 * drivers don't know about this HCD-internal state.
299 * When the HC can't see the ED, something changes ED_UNLINK to one of:
301 * - ED_OPER: when there's any request queued, the ED gets rescheduled
302 * immediately. HC should be working on them.
304 * - ED_IDLE: when there's no TD queue. there's no reason for the HC
305 * to care about this ED; safe to disable the endpoint.
307 * When finish_unlinks() runs later, after SOF interrupt, it will often
308 * complete one or more URB unlinks before making that state change.
310 static void ed_deschedule (struct ohci_hcd *ohci, struct ed *ed)
312 ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
314 ed->state = ED_UNLINK;
316 /* To deschedule something from the control or bulk list, just
317 * clear CLE/BLE and wait. There's no safe way to scrub out list
318 * head/current registers until later, and "later" isn't very
319 * tightly specified. Figure 6-5 and Section 6.4.2.2 show how
320 * the HC is reading the ED queues (while we modify them).
322 * For now, ed_schedule() is "later". It might be good paranoia
323 * to scrub those registers in finish_unlinks(), in case of bugs
324 * that make the HC try to use them.
328 /* remove ED from the HC's list: */
329 if (ed->ed_prev == NULL) {
331 ohci->hc_control &= ~OHCI_CTRL_CLE;
332 ohci_writel (ohci, ohci->hc_control,
333 &ohci->regs->control);
334 // a ohci_readl() later syncs CLE with the HC
337 hc32_to_cpup (ohci, &ed->hwNextED),
338 &ohci->regs->ed_controlhead);
340 ed->ed_prev->ed_next = ed->ed_next;
341 ed->ed_prev->hwNextED = ed->hwNextED;
343 /* remove ED from the HCD's list: */
344 if (ohci->ed_controltail == ed) {
345 ohci->ed_controltail = ed->ed_prev;
346 if (ohci->ed_controltail)
347 ohci->ed_controltail->ed_next = NULL;
348 } else if (ed->ed_next) {
349 ed->ed_next->ed_prev = ed->ed_prev;
354 /* remove ED from the HC's list: */
355 if (ed->ed_prev == NULL) {
357 ohci->hc_control &= ~OHCI_CTRL_BLE;
358 ohci_writel (ohci, ohci->hc_control,
359 &ohci->regs->control);
360 // a ohci_readl() later syncs BLE with the HC
363 hc32_to_cpup (ohci, &ed->hwNextED),
364 &ohci->regs->ed_bulkhead);
366 ed->ed_prev->ed_next = ed->ed_next;
367 ed->ed_prev->hwNextED = ed->hwNextED;
369 /* remove ED from the HCD's list: */
370 if (ohci->ed_bulktail == ed) {
371 ohci->ed_bulktail = ed->ed_prev;
372 if (ohci->ed_bulktail)
373 ohci->ed_bulktail->ed_next = NULL;
374 } else if (ed->ed_next) {
375 ed->ed_next->ed_prev = ed->ed_prev;
379 // case PIPE_INTERRUPT:
380 // case PIPE_ISOCHRONOUS:
382 periodic_unlink (ohci, ed);
388 /*-------------------------------------------------------------------------*/
390 /* get and maybe (re)init an endpoint. init _should_ be done only as part
391 * of enumeration, usb_set_configuration() or usb_set_interface().
393 static struct ed *ed_get (
394 struct ohci_hcd *ohci,
395 struct usb_host_endpoint *ep,
396 struct usb_device *udev,
403 spin_lock_irqsave (&ohci->lock, flags);
405 if (!(ed = ep->hcpriv)) {
410 ed = ed_alloc (ohci, GFP_ATOMIC);
416 /* dummy td; end of td list for ed */
417 td = td_alloc (ohci, GFP_ATOMIC);
425 ed->hwTailP = cpu_to_hc32 (ohci, td->td_dma);
426 ed->hwHeadP = ed->hwTailP; /* ED_C, ED_H zeroed */
429 is_out = !(ep->desc.bEndpointAddress & USB_DIR_IN);
431 /* FIXME usbcore changes dev->devnum before SET_ADDRESS
432 * suceeds ... otherwise we wouldn't need "pipe".
434 info = usb_pipedevice (pipe);
435 ed->type = usb_pipetype(pipe);
437 info |= (ep->desc.bEndpointAddress & ~USB_DIR_IN) << 7;
438 info |= le16_to_cpu(ep->desc.wMaxPacketSize) << 16;
439 if (udev->speed == USB_SPEED_LOW)
441 /* only control transfers store pids in tds */
442 if (ed->type != PIPE_CONTROL) {
443 info |= is_out ? ED_OUT : ED_IN;
444 if (ed->type != PIPE_BULK) {
445 /* periodic transfers... */
446 if (ed->type == PIPE_ISOCHRONOUS)
448 else if (interval > 32) /* iso can be bigger */
450 ed->interval = interval;
451 ed->load = usb_calc_bus_time (
452 udev->speed, !is_out,
453 ed->type == PIPE_ISOCHRONOUS,
454 le16_to_cpu(ep->desc.wMaxPacketSize))
458 ed->hwINFO = cpu_to_hc32(ohci, info);
464 spin_unlock_irqrestore (&ohci->lock, flags);
468 /*-------------------------------------------------------------------------*/
470 /* request unlinking of an endpoint from an operational HC.
471 * put the ep on the rm_list
472 * real work is done at the next start frame (SF) hardware interrupt
473 * caller guarantees HCD is running, so hardware access is safe,
474 * and that ed->state is ED_OPER
476 static void start_ed_unlink (struct ohci_hcd *ohci, struct ed *ed)
478 ed->hwINFO |= cpu_to_hc32 (ohci, ED_DEQUEUE);
479 ed_deschedule (ohci, ed);
481 /* rm_list is just singly linked, for simplicity */
482 ed->ed_next = ohci->ed_rm_list;
484 ohci->ed_rm_list = ed;
486 /* enable SOF interrupt */
487 ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrstatus);
488 ohci_writel (ohci, OHCI_INTR_SF, &ohci->regs->intrenable);
489 // flush those writes, and get latest HCCA contents
490 (void) ohci_readl (ohci, &ohci->regs->control);
492 /* SF interrupt might get delayed; record the frame counter value that
493 * indicates when the HC isn't looking at it, so concurrent unlinks
494 * behave. frame_no wraps every 2^16 msec, and changes right before
497 ed->tick = ohci_frame_no(ohci) + 1;
501 /*-------------------------------------------------------------------------*
502 * TD handling functions
503 *-------------------------------------------------------------------------*/
505 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
508 td_fill (struct ohci_hcd *ohci, u32 info,
509 dma_addr_t data, int len,
510 struct urb *urb, int index)
512 struct td *td, *td_pt;
513 struct urb_priv *urb_priv = urb->hcpriv;
514 int is_iso = info & TD_ISO;
517 // ASSERT (index < urb_priv->length);
519 /* aim for only one interrupt per urb. mostly applies to control
520 * and iso; other urbs rarely need more than one TD per urb.
521 * this way, only final tds (or ones with an error) cause IRQs.
522 * at least immediately; use DI=6 in case any control request is
523 * tempted to die part way through. (and to force the hc to flush
524 * its donelist soonish, even on unlink paths.)
526 * NOTE: could delay interrupts even for the last TD, and get fewer
527 * interrupts ... increasing per-urb latency by sharing interrupts.
528 * Drivers that queue bulk urbs may request that behavior.
530 if (index != (urb_priv->length - 1)
531 || (urb->transfer_flags & URB_NO_INTERRUPT))
532 info |= TD_DI_SET (6);
534 /* use this td as the next dummy */
535 td_pt = urb_priv->td [index];
537 /* fill the old dummy TD */
538 td = urb_priv->td [index] = urb_priv->ed->dummy;
539 urb_priv->ed->dummy = td_pt;
541 td->ed = urb_priv->ed;
542 td->next_dl_td = NULL;
549 td->hwINFO = cpu_to_hc32 (ohci, info);
551 td->hwCBP = cpu_to_hc32 (ohci, data & 0xFFFFF000);
552 *ohci_hwPSWp(ohci, td, 0) = cpu_to_hc16 (ohci,
553 (data & 0x0FFF) | 0xE000);
554 td->ed->last_iso = info & 0xffff;
556 td->hwCBP = cpu_to_hc32 (ohci, data);
559 td->hwBE = cpu_to_hc32 (ohci, data + len - 1);
562 td->hwNextTD = cpu_to_hc32 (ohci, td_pt->td_dma);
564 /* append to queue */
565 list_add_tail (&td->td_list, &td->ed->td_list);
567 /* hash it for later reverse mapping */
568 hash = TD_HASH_FUNC (td->td_dma);
569 td->td_hash = ohci->td_hash [hash];
570 ohci->td_hash [hash] = td;
572 /* HC might read the TD (or cachelines) right away ... */
574 td->ed->hwTailP = td->hwNextTD;
577 /*-------------------------------------------------------------------------*/
579 /* Prepare all TDs of a transfer, and queue them onto the ED.
580 * Caller guarantees HC is active.
581 * Usually the ED is already on the schedule, so TDs might be
582 * processed as soon as they're queued.
584 static void td_submit_urb (
585 struct ohci_hcd *ohci,
588 struct urb_priv *urb_priv = urb->hcpriv;
590 int data_len = urb->transfer_buffer_length;
593 int is_out = usb_pipeout (urb->pipe);
596 /* OHCI handles the bulk/interrupt data toggles itself. We just
597 * use the device toggle bits for resetting, and rely on the fact
598 * that resetting toggle is meaningless if the endpoint is active.
600 if (!usb_gettoggle (urb->dev, usb_pipeendpoint (urb->pipe), is_out)) {
601 usb_settoggle (urb->dev, usb_pipeendpoint (urb->pipe),
603 urb_priv->ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_C);
606 urb_priv->td_cnt = 0;
607 list_add (&urb_priv->pending, &ohci->pending);
610 data = urb->transfer_dma;
614 /* NOTE: TD_CC is set so we can tell which TDs the HC processed by
615 * using TD_CC_GET, as well as by seeing them on the done list.
616 * (CC = NotAccessed ... 0x0F, or 0x0E in PSWs for ISO.)
618 switch (urb_priv->ed->type) {
620 /* Bulk and interrupt are identical except for where in the schedule
624 /* ... and periodic urbs have extra accounting */
625 periodic = ohci_to_hcd(ohci)->self.bandwidth_int_reqs++ == 0
626 && ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs == 0;
630 ? TD_T_TOGGLE | TD_CC | TD_DP_OUT
631 : TD_T_TOGGLE | TD_CC | TD_DP_IN;
632 /* TDs _could_ transfer up to 8K each */
633 while (data_len > 4096) {
634 td_fill (ohci, info, data, 4096, urb, cnt);
639 /* maybe avoid ED halt on final TD short read */
640 if (!(urb->transfer_flags & URB_SHORT_NOT_OK))
642 td_fill (ohci, info, data, data_len, urb, cnt);
644 if ((urb->transfer_flags & URB_ZERO_PACKET)
645 && cnt < urb_priv->length) {
646 td_fill (ohci, info, 0, 0, urb, cnt);
649 /* maybe kickstart bulk list */
650 if (urb_priv->ed->type == PIPE_BULK) {
652 ohci_writel (ohci, OHCI_BLF, &ohci->regs->cmdstatus);
656 /* control manages DATA0/DATA1 toggle per-request; SETUP resets it,
657 * any DATA phase works normally, and the STATUS ack is special.
660 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
661 td_fill (ohci, info, urb->setup_dma, 8, urb, cnt++);
663 info = TD_CC | TD_R | TD_T_DATA1;
664 info |= is_out ? TD_DP_OUT : TD_DP_IN;
665 /* NOTE: mishandles transfers >8K, some >4K */
666 td_fill (ohci, info, data, data_len, urb, cnt++);
668 info = (is_out || data_len == 0)
669 ? TD_CC | TD_DP_IN | TD_T_DATA1
670 : TD_CC | TD_DP_OUT | TD_T_DATA1;
671 td_fill (ohci, info, data, 0, urb, cnt++);
672 /* maybe kickstart control list */
674 ohci_writel (ohci, OHCI_CLF, &ohci->regs->cmdstatus);
677 /* ISO has no retransmit, so no toggle; and it uses special TDs.
678 * Each TD could handle multiple consecutive frames (interval 1);
679 * we could often reduce the number of TDs here.
681 case PIPE_ISOCHRONOUS:
682 for (cnt = 0; cnt < urb->number_of_packets; cnt++) {
683 int frame = urb->start_frame;
685 // FIXME scheduling should handle frame counter
686 // roll-around ... exotic case (and OHCI has
687 // a 2^16 iso range, vs other HCs max of 2^10)
688 frame += cnt * urb->interval;
690 td_fill (ohci, TD_CC | TD_ISO | frame,
691 data + urb->iso_frame_desc [cnt].offset,
692 urb->iso_frame_desc [cnt].length, urb, cnt);
694 periodic = ohci_to_hcd(ohci)->self.bandwidth_isoc_reqs++ == 0
695 && ohci_to_hcd(ohci)->self.bandwidth_int_reqs == 0;
699 /* start periodic dma if needed */
702 ohci->hc_control |= OHCI_CTRL_PLE|OHCI_CTRL_IE;
703 ohci_writel (ohci, ohci->hc_control, &ohci->regs->control);
706 // ASSERT (urb_priv->length == cnt);
709 /*-------------------------------------------------------------------------*
710 * Done List handling functions
711 *-------------------------------------------------------------------------*/
713 /* calculate transfer length/status and update the urb
714 * PRECONDITION: irqsafe (only for urb->status locking)
716 static void td_done (struct ohci_hcd *ohci, struct urb *urb, struct td *td)
718 u32 tdINFO = hc32_to_cpup (ohci, &td->hwINFO);
721 list_del (&td->td_list);
723 /* ISO ... drivers see per-TD length/status */
724 if (tdINFO & TD_ISO) {
725 u16 tdPSW = ohci_hwPSW (ohci, td, 0);
728 /* NOTE: assumes FC in tdINFO == 0, and that
729 * only the first of 0..MAXPSW psws is used.
732 cc = (tdPSW >> 12) & 0xF;
733 if (tdINFO & TD_CC) /* hc didn't touch? */
736 if (usb_pipeout (urb->pipe))
737 dlen = urb->iso_frame_desc [td->index].length;
739 /* short reads are always OK for ISO */
740 if (cc == TD_DATAUNDERRUN)
742 dlen = tdPSW & 0x3ff;
744 urb->actual_length += dlen;
745 urb->iso_frame_desc [td->index].actual_length = dlen;
746 urb->iso_frame_desc [td->index].status = cc_to_error [cc];
748 if (cc != TD_CC_NOERROR)
750 "urb %p iso td %p (%d) len %d cc %d\n",
751 urb, td, 1 + td->index, dlen, cc);
753 /* BULK, INT, CONTROL ... drivers see aggregate length/status,
754 * except that "setup" bytes aren't counted and "short" transfers
755 * might not be reported as errors.
758 int type = usb_pipetype (urb->pipe);
759 u32 tdBE = hc32_to_cpup (ohci, &td->hwBE);
761 cc = TD_CC_GET (tdINFO);
763 /* update packet status if needed (short is normally ok) */
764 if (cc == TD_DATAUNDERRUN
765 && !(urb->transfer_flags & URB_SHORT_NOT_OK))
767 if (cc != TD_CC_NOERROR && cc < 0x0E) {
768 spin_lock (&urb->lock);
769 if (urb->status == -EINPROGRESS)
770 urb->status = cc_to_error [cc];
771 spin_unlock (&urb->lock);
774 /* count all non-empty packets except control SETUP packet */
775 if ((type != PIPE_CONTROL || td->index != 0) && tdBE != 0) {
777 urb->actual_length += tdBE - td->data_dma + 1;
779 urb->actual_length +=
780 hc32_to_cpup (ohci, &td->hwCBP)
784 if (cc != TD_CC_NOERROR && cc < 0x0E)
786 "urb %p td %p (%d) cc %d, len=%d/%d\n",
787 urb, td, 1 + td->index, cc,
789 urb->transfer_buffer_length);
793 /*-------------------------------------------------------------------------*/
795 static inline struct td *
796 ed_halted (struct ohci_hcd *ohci, struct td *td, int cc, struct td *rev)
798 struct urb *urb = td->urb;
799 struct ed *ed = td->ed;
800 struct list_head *tmp = td->td_list.next;
801 __hc32 toggle = ed->hwHeadP & cpu_to_hc32 (ohci, ED_C);
803 /* clear ed halt; this is the td that caused it, but keep it inactive
804 * until its urb->complete() has a chance to clean up.
806 ed->hwINFO |= cpu_to_hc32 (ohci, ED_SKIP);
808 ed->hwHeadP &= ~cpu_to_hc32 (ohci, ED_H);
810 /* put any later tds from this urb onto the donelist, after 'td',
811 * order won't matter here: no errors, and nothing was transferred.
812 * also patch the ed so it looks as if those tds completed normally.
814 while (tmp != &ed->td_list) {
818 next = list_entry (tmp, struct td, td_list);
819 tmp = next->td_list.next;
821 if (next->urb != urb)
824 /* NOTE: if multi-td control DATA segments get supported,
825 * this urb had one of them, this td wasn't the last td
826 * in that segment (TD_R clear), this ed halted because
827 * of a short read, _and_ URB_SHORT_NOT_OK is clear ...
828 * then we need to leave the control STATUS packet queued
832 info |= cpu_to_hc32 (ohci, TD_DONE);
833 info &= ~cpu_to_hc32 (ohci, TD_CC);
836 next->next_dl_td = rev;
839 ed->hwHeadP = next->hwNextTD | toggle;
842 /* help for troubleshooting: report anything that
843 * looks odd ... that doesn't include protocol stalls
844 * (or maybe some other things)
847 case TD_DATAUNDERRUN:
848 if ((urb->transfer_flags & URB_SHORT_NOT_OK) == 0)
852 if (usb_pipecontrol (urb->pipe))
857 "urb %p path %s ep%d%s %08x cc %d --> status %d\n",
858 urb, urb->dev->devpath,
859 usb_pipeendpoint (urb->pipe),
860 usb_pipein (urb->pipe) ? "in" : "out",
861 hc32_to_cpu (ohci, td->hwINFO),
862 cc, cc_to_error [cc]);
868 /* replies to the request have to be on a FIFO basis so
869 * we unreverse the hc-reversed done-list
871 static struct td *dl_reverse_done_list (struct ohci_hcd *ohci)
874 struct td *td_rev = NULL;
875 struct td *td = NULL;
877 td_dma = hc32_to_cpup (ohci, &ohci->hcca->done_head);
878 ohci->hcca->done_head = 0;
881 /* get TD from hc's singly linked list, and
882 * prepend to ours. ed->td_list changes later.
887 td = dma_to_td (ohci, td_dma);
889 ohci_err (ohci, "bad entry %8x\n", td_dma);
893 td->hwINFO |= cpu_to_hc32 (ohci, TD_DONE);
894 cc = TD_CC_GET (hc32_to_cpup (ohci, &td->hwINFO));
896 /* Non-iso endpoints can halt on error; un-halt,
897 * and dequeue any other TDs from this urb.
898 * No other TD could have caused the halt.
900 if (cc != TD_CC_NOERROR
901 && (td->ed->hwHeadP & cpu_to_hc32 (ohci, ED_H)))
902 td_rev = ed_halted (ohci, td, cc, td_rev);
904 td->next_dl_td = td_rev;
906 td_dma = hc32_to_cpup (ohci, &td->hwNextTD);
911 /*-------------------------------------------------------------------------*/
913 /* there are some urbs/eds to unlink; called in_irq(), with HCD locked */
915 finish_unlinks (struct ohci_hcd *ohci, u16 tick)
917 struct ed *ed, **last;
920 for (last = &ohci->ed_rm_list, ed = *last; ed != NULL; ed = *last) {
921 struct list_head *entry, *tmp;
922 int completed, modified;
925 /* only take off EDs that the HC isn't using, accounting for
926 * frame counter wraps and EDs with partially retired TDs
928 if (likely (HC_IS_RUNNING(ohci_to_hcd(ohci)->state))) {
929 if (tick_before (tick, ed->tick)) {
935 if (!list_empty (&ed->td_list)) {
939 td = list_entry (ed->td_list.next, struct td,
941 head = hc32_to_cpu (ohci, ed->hwHeadP) &
944 /* INTR_WDH may need to clean up first */
945 if (td->td_dma != head)
950 /* reentrancy: if we drop the schedule lock, someone might
951 * have modified this list. normally it's just prepending
952 * entries (which we'd ignore), but paranoia won't hurt.
958 /* unlink urbs as requested, but rescan the list after
959 * we call a completion since it might have unlinked
960 * another (earlier) urb
962 * When we get here, the HC doesn't see this ed. But it
963 * must not be rescheduled until all completed URBs have
964 * been given back to the driver.
969 list_for_each_safe (entry, tmp, &ed->td_list) {
972 urb_priv_t *urb_priv;
975 td = list_entry (entry, struct td, td_list);
977 urb_priv = td->urb->hcpriv;
979 if (urb->status == -EINPROGRESS) {
980 prev = &td->hwNextTD;
984 /* patch pointer hc uses */
985 savebits = *prev & ~cpu_to_hc32 (ohci, TD_MASK);
986 *prev = td->hwNextTD | savebits;
988 /* HC may have partly processed this TD */
989 td_done (ohci, urb, td);
992 /* if URB is done, clean up */
993 if (urb_priv->td_cnt == urb_priv->length) {
994 modified = completed = 1;
995 finish_urb (ohci, urb);
998 if (completed && !list_empty (&ed->td_list))
1001 /* ED's now officially unlinked, hc doesn't see */
1002 ed->state = ED_IDLE;
1003 ed->hwHeadP &= ~cpu_to_hc32(ohci, ED_H);
1006 ed->hwINFO &= ~cpu_to_hc32 (ohci, ED_SKIP | ED_DEQUEUE);
1008 /* but if there's work queued, reschedule */
1009 if (!list_empty (&ed->td_list)) {
1010 if (HC_IS_RUNNING(ohci_to_hcd(ohci)->state))
1011 ed_schedule (ohci, ed);
1018 /* maybe reenable control and bulk lists */
1019 if (HC_IS_RUNNING(ohci_to_hcd(ohci)->state)
1020 && ohci_to_hcd(ohci)->state != HC_STATE_QUIESCING
1021 && !ohci->ed_rm_list) {
1022 u32 command = 0, control = 0;
1024 if (ohci->ed_controltail) {
1025 command |= OHCI_CLF;
1026 if (ohci->flags & OHCI_QUIRK_ZFMICRO)
1028 if (!(ohci->hc_control & OHCI_CTRL_CLE)) {
1029 control |= OHCI_CTRL_CLE;
1030 ohci_writel (ohci, 0,
1031 &ohci->regs->ed_controlcurrent);
1034 if (ohci->ed_bulktail) {
1035 command |= OHCI_BLF;
1036 if (ohci->flags & OHCI_QUIRK_ZFMICRO)
1038 if (!(ohci->hc_control & OHCI_CTRL_BLE)) {
1039 control |= OHCI_CTRL_BLE;
1040 ohci_writel (ohci, 0,
1041 &ohci->regs->ed_bulkcurrent);
1045 /* CLE/BLE to enable, CLF/BLF to (maybe) kickstart */
1047 ohci->hc_control |= control;
1048 if (ohci->flags & OHCI_QUIRK_ZFMICRO)
1050 ohci_writel (ohci, ohci->hc_control,
1051 &ohci->regs->control);
1054 if (ohci->flags & OHCI_QUIRK_ZFMICRO)
1056 ohci_writel (ohci, command, &ohci->regs->cmdstatus);
1063 /*-------------------------------------------------------------------------*/
1066 * Process normal completions (error or success) and clean the schedules.
1068 * This is the main path for handing urbs back to drivers. The only other
1069 * path is finish_unlinks(), which unlinks URBs using ed_rm_list, instead of
1070 * scanning the (re-reversed) donelist as this does.
1073 dl_done_list (struct ohci_hcd *ohci)
1075 struct td *td = dl_reverse_done_list (ohci);
1078 struct td *td_next = td->next_dl_td;
1079 struct urb *urb = td->urb;
1080 urb_priv_t *urb_priv = urb->hcpriv;
1081 struct ed *ed = td->ed;
1083 /* update URB's length and status from TD */
1084 td_done (ohci, urb, td);
1087 /* If all this urb's TDs are done, call complete() */
1088 if (urb_priv->td_cnt == urb_priv->length)
1089 finish_urb (ohci, urb);
1091 /* clean schedule: unlink EDs that are no longer busy */
1092 if (list_empty (&ed->td_list)) {
1093 if (ed->state == ED_OPER)
1094 start_ed_unlink (ohci, ed);
1096 /* ... reenabling halted EDs only after fault cleanup */
1097 } else if ((ed->hwINFO & cpu_to_hc32 (ohci, ED_SKIP | ED_DEQUEUE))
1098 == cpu_to_hc32 (ohci, ED_SKIP)) {
1099 td = list_entry (ed->td_list.next, struct td, td_list);
1100 if (!(td->hwINFO & cpu_to_hc32 (ohci, TD_DONE))) {
1101 ed->hwINFO &= ~cpu_to_hc32 (ohci, ED_SKIP);
1102 /* ... hc may need waking-up */
1105 ohci_writel (ohci, OHCI_CLF,
1106 &ohci->regs->cmdstatus);
1109 ohci_writel (ohci, OHCI_BLF,
1110 &ohci->regs->cmdstatus);