2 * Copyright (c) 2001-2002 by David Brownell
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software Foundation,
16 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19 #ifndef __LINUX_EHCI_HCD_H
20 #define __LINUX_EHCI_HCD_H
22 /* definitions used for the EHCI driver */
25 * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
26 * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
27 * the host controller implementation.
29 * To facilitate the strongest possible byte-order checking from "sparse"
30 * and so on, we use __leXX unless that's not practical.
32 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
33 typedef __u32 __bitwise __hc32;
34 typedef __u16 __bitwise __hc16;
40 /* statistics can be kept for for tuning/monitoring */
45 unsigned long reclaim;
46 unsigned long lost_iaa;
48 /* termination of urbs from core */
49 unsigned long complete;
53 /* ehci_hcd->lock guards shared data against other CPUs:
54 * ehci_hcd: async, reclaim, periodic (and shadow), ...
55 * usb_host_endpoint: hcpriv
56 * ehci_qh: qh_next, qtd_list
59 * Also, hold this lock when talking to HC registers or
60 * when updating hw_* fields in shared qh/qtd/... structures.
63 #define EHCI_MAX_ROOT_PORTS 15 /* see HCS_N_PORTS */
65 struct ehci_hcd { /* one per controller */
66 /* glue to PCI and HCD framework */
67 struct ehci_caps __iomem *caps;
68 struct ehci_regs __iomem *regs;
69 struct ehci_dbg_port __iomem *debug;
71 __u32 hcs_params; /* cached register copy */
74 #ifdef CONFIG_CPU_FREQ
75 struct notifier_block cpufreq_transition;
77 struct list_head split_intr_qhs;
80 /* async schedule support */
81 struct ehci_qh *async;
82 struct ehci_qh *reclaim;
83 unsigned reclaim_ready : 1;
84 unsigned scanning : 1;
86 /* periodic schedule support */
87 #define DEFAULT_I_TDPS 1024 /* some HCs can do less */
88 unsigned periodic_size;
89 __hc32 *periodic; /* hw periodic table */
90 dma_addr_t periodic_dma;
91 unsigned i_thresh; /* uframes HC might cache */
93 union ehci_shadow *pshadow; /* mirror hw periodic table */
94 int next_uframe; /* scan periodic, start here */
95 unsigned periodic_sched; /* periodic activity count */
97 /* per root hub port */
98 unsigned long reset_done [EHCI_MAX_ROOT_PORTS];
100 /* bit vectors (one bit per port) */
101 unsigned long bus_suspended; /* which ports were
102 already suspended at the start of a bus suspend */
103 unsigned long companion_ports; /* which ports are
104 dedicated to the companion controller */
105 unsigned long owned_ports; /* which ports are
106 owned by the companion during a bus suspend */
108 /* per-HC memory pools (could be per-bus, but ...) */
109 struct dma_pool *qh_pool; /* qh per active urb */
110 struct dma_pool *qtd_pool; /* one or more per qh */
111 struct dma_pool *itd_pool; /* itd per iso urb */
112 struct dma_pool *sitd_pool; /* sitd per split iso urb */
114 struct timer_list watchdog;
115 unsigned long actions;
117 unsigned long next_statechange;
121 unsigned is_tdi_rh_tt:1; /* TDI roothub with TT */
122 unsigned no_selective_suspend:1;
123 unsigned has_fsl_port_bug:1; /* FreeScale */
124 unsigned big_endian_mmio:1;
125 unsigned big_endian_desc:1;
127 u8 sbrn; /* packed release number */
131 struct ehci_stats stats;
132 # define COUNT(x) do { (x)++; } while (0)
134 # define COUNT(x) do {} while (0)
138 /* convert between an HCD pointer and the corresponding EHCI_HCD */
139 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
141 return (struct ehci_hcd *) (hcd->hcd_priv);
143 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
145 return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
149 enum ehci_timer_action {
157 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
159 clear_bit (action, &ehci->actions);
163 timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action)
165 if (!test_and_set_bit (action, &ehci->actions)) {
169 case TIMER_IAA_WATCHDOG:
170 t = EHCI_IAA_JIFFIES;
172 case TIMER_IO_WATCHDOG:
175 case TIMER_ASYNC_OFF:
176 t = EHCI_ASYNC_JIFFIES;
178 // case TIMER_ASYNC_SHRINK:
180 t = EHCI_SHRINK_JIFFIES;
184 // all timings except IAA watchdog can be overridden.
185 // async queue SHRINK often precedes IAA. while it's ready
186 // to go OFF neither can matter, and afterwards the IO
187 // watchdog stops unless there's still periodic traffic.
188 if (action != TIMER_IAA_WATCHDOG
189 && t > ehci->watchdog.expires
190 && timer_pending (&ehci->watchdog))
192 mod_timer (&ehci->watchdog, t);
196 /*-------------------------------------------------------------------------*/
198 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
200 /* Section 2.2 Host Controller Capability Registers */
202 /* these fields are specified as 8 and 16 bit registers,
203 * but some hosts can't perform 8 or 16 bit PCI accesses.
206 #define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
207 #define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
208 u32 hcs_params; /* HCSPARAMS - offset 0x4 */
209 #define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */
210 #define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
211 #define HCS_N_CC(p) (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
212 #define HCS_N_PCC(p) (((p)>>8)&0xf) /* bits 11:8, ports per CC */
213 #define HCS_PORTROUTED(p) ((p)&(1 << 7)) /* true: port routing */
214 #define HCS_PPC(p) ((p)&(1 << 4)) /* true: port power control */
215 #define HCS_N_PORTS(p) (((p)>>0)&0xf) /* bits 3:0, ports on HC */
217 u32 hcc_params; /* HCCPARAMS - offset 0x8 */
218 #define HCC_EXT_CAPS(p) (((p)>>8)&0xff) /* for pci extended caps */
219 #define HCC_ISOC_CACHE(p) ((p)&(1 << 7)) /* true: can cache isoc frame */
220 #define HCC_ISOC_THRES(p) (((p)>>4)&0x7) /* bits 6:4, uframes cached */
221 #define HCC_CANPARK(p) ((p)&(1 << 2)) /* true: can park on async qh */
222 #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
223 #define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */
224 u8 portroute [8]; /* nibbles for routing - offset 0xC */
225 } __attribute__ ((packed));
228 /* Section 2.3 Host Controller Operational Registers */
231 /* USBCMD: offset 0x00 */
233 /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
234 #define CMD_PARK (1<<11) /* enable "park" on async qh */
235 #define CMD_PARK_CNT(c) (((c)>>8)&3) /* how many transfers to park for */
236 #define CMD_LRESET (1<<7) /* partial reset (no ports, etc) */
237 #define CMD_IAAD (1<<6) /* "doorbell" interrupt async advance */
238 #define CMD_ASE (1<<5) /* async schedule enable */
239 #define CMD_PSE (1<<4) /* periodic schedule enable */
240 /* 3:2 is periodic frame list size */
241 #define CMD_RESET (1<<1) /* reset HC not bus */
242 #define CMD_RUN (1<<0) /* start/stop HC */
244 /* USBSTS: offset 0x04 */
246 #define STS_ASS (1<<15) /* Async Schedule Status */
247 #define STS_PSS (1<<14) /* Periodic Schedule Status */
248 #define STS_RECL (1<<13) /* Reclamation */
249 #define STS_HALT (1<<12) /* Not running (any reason) */
250 /* some bits reserved */
251 /* these STS_* flags are also intr_enable bits (USBINTR) */
252 #define STS_IAA (1<<5) /* Interrupted on async advance */
253 #define STS_FATAL (1<<4) /* such as some PCI access errors */
254 #define STS_FLR (1<<3) /* frame list rolled over */
255 #define STS_PCD (1<<2) /* port change detect */
256 #define STS_ERR (1<<1) /* "error" completion (overflow, ...) */
257 #define STS_INT (1<<0) /* "normal" completion (short, ...) */
259 /* USBINTR: offset 0x08 */
262 /* FRINDEX: offset 0x0C */
263 u32 frame_index; /* current microframe number */
264 /* CTRLDSSEGMENT: offset 0x10 */
265 u32 segment; /* address bits 63:32 if needed */
266 /* PERIODICLISTBASE: offset 0x14 */
267 u32 frame_list; /* points to periodic list */
268 /* ASYNCLISTADDR: offset 0x18 */
269 u32 async_next; /* address of next async queue head */
273 /* CONFIGFLAG: offset 0x40 */
275 #define FLAG_CF (1<<0) /* true: we'll support "high speed" */
277 /* PORTSC: offset 0x44 */
278 u32 port_status [0]; /* up to N_PORTS */
280 #define PORT_WKOC_E (1<<22) /* wake on overcurrent (enable) */
281 #define PORT_WKDISC_E (1<<21) /* wake on disconnect (enable) */
282 #define PORT_WKCONN_E (1<<20) /* wake on connect (enable) */
283 /* 19:16 for port testing */
284 #define PORT_LED_OFF (0<<14)
285 #define PORT_LED_AMBER (1<<14)
286 #define PORT_LED_GREEN (2<<14)
287 #define PORT_LED_MASK (3<<14)
288 #define PORT_OWNER (1<<13) /* true: companion hc owns this port */
289 #define PORT_POWER (1<<12) /* true: has power (see PPC) */
290 #define PORT_USB11(x) (((x)&(3<<10))==(1<<10)) /* USB 1.1 device */
291 /* 11:10 for detecting lowspeed devices (reset vs release ownership) */
293 #define PORT_RESET (1<<8) /* reset port */
294 #define PORT_SUSPEND (1<<7) /* suspend port */
295 #define PORT_RESUME (1<<6) /* resume it */
296 #define PORT_OCC (1<<5) /* over current change */
297 #define PORT_OC (1<<4) /* over current active */
298 #define PORT_PEC (1<<3) /* port enable change */
299 #define PORT_PE (1<<2) /* port enable */
300 #define PORT_CSC (1<<1) /* connect status change */
301 #define PORT_CONNECT (1<<0) /* device connected */
302 #define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
303 } __attribute__ ((packed));
305 /* Appendix C, Debug port ... intended for use with special "debug devices"
306 * that can help if there's no serial console. (nonstandard enumeration.)
308 struct ehci_dbg_port {
310 #define DBGP_OWNER (1<<30)
311 #define DBGP_ENABLED (1<<28)
312 #define DBGP_DONE (1<<16)
313 #define DBGP_INUSE (1<<10)
314 #define DBGP_ERRCODE(x) (((x)>>7)&0x07)
315 # define DBGP_ERR_BAD 1
316 # define DBGP_ERR_SIGNAL 2
317 #define DBGP_ERROR (1<<6)
318 #define DBGP_GO (1<<5)
319 #define DBGP_OUT (1<<4)
320 #define DBGP_LEN(x) (((x)>>0)&0x0f)
322 #define DBGP_PID_GET(x) (((x)>>16)&0xff)
323 #define DBGP_PID_SET(data,tok) (((data)<<8)|(tok))
327 #define DBGP_EPADDR(dev,ep) (((dev)<<8)|(ep))
328 } __attribute__ ((packed));
330 /*-------------------------------------------------------------------------*/
332 #define QTD_NEXT(ehci, dma) cpu_to_hc32(ehci, (u32)dma)
335 * EHCI Specification 0.95 Section 3.5
336 * QTD: describe data transfer components (buffer, direction, ...)
337 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
339 * These are associated only with "QH" (Queue Head) structures,
340 * used with control, bulk, and interrupt transfers.
343 /* first part defined by EHCI spec */
344 __hc32 hw_next; /* see EHCI 3.5.1 */
345 __hc32 hw_alt_next; /* see EHCI 3.5.2 */
346 __hc32 hw_token; /* see EHCI 3.5.3 */
347 #define QTD_TOGGLE (1 << 31) /* data toggle */
348 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
349 #define QTD_IOC (1 << 15) /* interrupt on complete */
350 #define QTD_CERR(tok) (((tok)>>10) & 0x3)
351 #define QTD_PID(tok) (((tok)>>8) & 0x3)
352 #define QTD_STS_ACTIVE (1 << 7) /* HC may execute this */
353 #define QTD_STS_HALT (1 << 6) /* halted on error */
354 #define QTD_STS_DBE (1 << 5) /* data buffer error (in HC) */
355 #define QTD_STS_BABBLE (1 << 4) /* device was babbling (qtd halted) */
356 #define QTD_STS_XACT (1 << 3) /* device gave illegal response */
357 #define QTD_STS_MMF (1 << 2) /* incomplete split transaction */
358 #define QTD_STS_STS (1 << 1) /* split transaction state */
359 #define QTD_STS_PING (1 << 0) /* issue PING? */
361 #define ACTIVE_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_ACTIVE)
362 #define HALT_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_HALT)
363 #define STATUS_BIT(ehci) cpu_to_hc32(ehci, QTD_STS_STS)
365 __hc32 hw_buf [5]; /* see EHCI 3.5.4 */
366 __hc32 hw_buf_hi [5]; /* Appendix B */
368 /* the rest is HCD-private */
369 dma_addr_t qtd_dma; /* qtd address */
370 struct list_head qtd_list; /* sw qtd list */
371 struct urb *urb; /* qtd's urb */
372 size_t length; /* length of buffer */
373 } __attribute__ ((aligned (32)));
375 /* mask NakCnt+T in qh->hw_alt_next */
376 #define QTD_MASK(ehci) cpu_to_hc32 (ehci, ~0x1f)
378 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
380 /*-------------------------------------------------------------------------*/
382 /* type tag from {qh,itd,sitd,fstn}->hw_next */
383 #define Q_NEXT_TYPE(ehci,dma) ((dma) & cpu_to_hc32(ehci, 3 << 1))
386 * Now the following defines are not converted using the
387 * __constant_cpu_to_le32() macro anymore, since we have to support
388 * "dynamic" switching between be and le support, so that the driver
389 * can be used on one system with SoC EHCI controller using big-endian
390 * descriptors as well as a normal little-endian PCI EHCI controller.
392 /* values for that type tag */
393 #define Q_TYPE_ITD (0 << 1)
394 #define Q_TYPE_QH (1 << 1)
395 #define Q_TYPE_SITD (2 << 1)
396 #define Q_TYPE_FSTN (3 << 1)
398 /* next async queue entry, or pointer to interrupt/periodic QH */
399 #define QH_NEXT(ehci,dma) (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
401 /* for periodic/async schedules and qtd lists, mark end of list */
402 #define EHCI_LIST_END(ehci) cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
405 * Entries in periodic shadow table are pointers to one of four kinds
406 * of data structure. That's dictated by the hardware; a type tag is
407 * encoded in the low bits of the hardware's periodic schedule. Use
408 * Q_NEXT_TYPE to get the tag.
410 * For entries in the async schedule, the type tag always says "qh".
413 struct ehci_qh *qh; /* Q_TYPE_QH */
414 struct ehci_itd *itd; /* Q_TYPE_ITD */
415 struct ehci_sitd *sitd; /* Q_TYPE_SITD */
416 struct ehci_fstn *fstn; /* Q_TYPE_FSTN */
417 __hc32 *hw_next; /* (all types) */
421 /*-------------------------------------------------------------------------*/
424 * EHCI Specification 0.95 Section 3.6
425 * QH: describes control/bulk/interrupt endpoints
426 * See Fig 3-7 "Queue Head Structure Layout".
428 * These appear in both the async and (for interrupt) periodic schedules.
432 /* first part defined by EHCI spec */
433 __hc32 hw_next; /* see EHCI 3.6.1 */
434 __hc32 hw_info1; /* see EHCI 3.6.2 */
435 #define QH_HEAD 0x00008000
436 #define QH_INACTIVATE 0x00000080
438 #define INACTIVATE_BIT(ehci) cpu_to_hc32(ehci, QH_INACTIVATE)
440 __hc32 hw_info2; /* see EHCI 3.6.2 */
441 #define QH_SMASK 0x000000ff
442 #define QH_CMASK 0x0000ff00
443 #define QH_HUBADDR 0x007f0000
444 #define QH_HUBPORT 0x3f800000
445 #define QH_MULT 0xc0000000
446 __hc32 hw_current; /* qtd list - see EHCI 3.6.4 */
448 /* qtd overlay (hardware parts of a struct ehci_qtd) */
453 __hc32 hw_buf_hi [5];
455 /* the rest is HCD-private */
456 dma_addr_t qh_dma; /* address of qh */
457 union ehci_shadow qh_next; /* ptr to qh; or periodic */
458 struct list_head qtd_list; /* sw qtd list */
459 struct ehci_qtd *dummy;
460 struct ehci_qh *reclaim; /* next to reclaim */
462 struct ehci_hcd *ehci;
465 * Do NOT use atomic operations for QH refcounting. On some CPUs
466 * (PPC7448 for example), atomic operations cannot be performed on
467 * memory that is cache-inhibited (i.e. being used for DMA).
468 * Spinlocks are used to protect all QH fields.
474 #define QH_STATE_LINKED 1 /* HC sees this */
475 #define QH_STATE_UNLINK 2 /* HC may still see this */
476 #define QH_STATE_IDLE 3 /* HC doesn't see this */
477 #define QH_STATE_UNLINK_WAIT 4 /* LINKED and on reclaim q */
478 #define QH_STATE_COMPLETING 5 /* don't touch token.HALT */
480 /* periodic schedule info */
481 u8 usecs; /* intr bandwidth */
482 u8 gap_uf; /* uframes split/csplit gap */
483 u8 c_usecs; /* ... split completion bw */
484 u16 tt_usecs; /* tt downstream bandwidth */
485 unsigned short period; /* polling interval */
486 unsigned short start; /* where polling starts */
487 #define NO_FRAME ((unsigned short)~0) /* pick new start */
488 struct usb_device *dev; /* access to TT */
489 #ifdef CONFIG_CPU_FREQ
490 struct list_head split_intr_qhs; /* list of split qhs */
491 __le32 was_active; /* active bit before "i" set */
493 } __attribute__ ((aligned (32)));
495 /*-------------------------------------------------------------------------*/
497 /* description of one iso transaction (up to 3 KB data if highspeed) */
498 struct ehci_iso_packet {
499 /* These will be copied to iTD when scheduling */
500 u64 bufp; /* itd->hw_bufp{,_hi}[pg] |= */
501 __hc32 transaction; /* itd->hw_transaction[i] |= */
502 u8 cross; /* buf crosses pages */
503 /* for full speed OUT splits */
507 /* temporary schedule data for packets from iso urbs (both speeds)
508 * each packet is one logical usb transaction to the device (not TT),
509 * beginning at stream->next_uframe
511 struct ehci_iso_sched {
512 struct list_head td_list;
514 struct ehci_iso_packet packet [0];
518 * ehci_iso_stream - groups all (s)itds for this endpoint.
519 * acts like a qh would, if EHCI had them for ISO.
521 struct ehci_iso_stream {
522 /* first two fields match QH, but info1 == 0 */
529 u16 depth; /* depth in uframes */
530 struct list_head td_list; /* queued itds/sitds */
531 struct list_head free_list; /* list of unused itds/sitds */
532 struct usb_device *udev;
533 struct usb_host_endpoint *ep;
535 /* output of (re)scheduling */
536 unsigned long start; /* jiffies */
537 unsigned long rescheduled;
541 /* the rest is derived from the endpoint descriptor,
542 * trusting urb->interval == f(epdesc->bInterval) and
543 * including the extra info for hw_bufp[0..2]
552 /* This is used to initialize iTD's hw_bufp fields */
557 /* this is used to initialize sITD's tt info */
561 /*-------------------------------------------------------------------------*/
564 * EHCI Specification 0.95 Section 3.3
565 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
567 * Schedule records for high speed iso xfers
570 /* first part defined by EHCI spec */
571 __hc32 hw_next; /* see EHCI 3.3.1 */
572 __hc32 hw_transaction [8]; /* see EHCI 3.3.2 */
573 #define EHCI_ISOC_ACTIVE (1<<31) /* activate transfer this slot */
574 #define EHCI_ISOC_BUF_ERR (1<<30) /* Data buffer error */
575 #define EHCI_ISOC_BABBLE (1<<29) /* babble detected */
576 #define EHCI_ISOC_XACTERR (1<<28) /* XactErr - transaction error */
577 #define EHCI_ITD_LENGTH(tok) (((tok)>>16) & 0x0fff)
578 #define EHCI_ITD_IOC (1 << 15) /* interrupt on complete */
580 #define ITD_ACTIVE(ehci) cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
582 __hc32 hw_bufp [7]; /* see EHCI 3.3.3 */
583 __hc32 hw_bufp_hi [7]; /* Appendix B */
585 /* the rest is HCD-private */
586 dma_addr_t itd_dma; /* for this itd */
587 union ehci_shadow itd_next; /* ptr to periodic q entry */
590 struct ehci_iso_stream *stream; /* endpoint's queue */
591 struct list_head itd_list; /* list of stream's itds */
593 /* any/all hw_transactions here may be used by that urb */
594 unsigned frame; /* where scheduled */
596 unsigned index[8]; /* in urb->iso_frame_desc */
598 } __attribute__ ((aligned (32)));
600 /*-------------------------------------------------------------------------*/
603 * EHCI Specification 0.95 Section 3.4
604 * siTD, aka split-transaction isochronous Transfer Descriptor
605 * ... describe full speed iso xfers through TT in hubs
606 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
609 /* first part defined by EHCI spec */
611 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
612 __hc32 hw_fullspeed_ep; /* EHCI table 3-9 */
613 __hc32 hw_uframe; /* EHCI table 3-10 */
614 __hc32 hw_results; /* EHCI table 3-11 */
615 #define SITD_IOC (1 << 31) /* interrupt on completion */
616 #define SITD_PAGE (1 << 30) /* buffer 0/1 */
617 #define SITD_LENGTH(x) (0x3ff & ((x)>>16))
618 #define SITD_STS_ACTIVE (1 << 7) /* HC may execute this */
619 #define SITD_STS_ERR (1 << 6) /* error from TT */
620 #define SITD_STS_DBE (1 << 5) /* data buffer error (in HC) */
621 #define SITD_STS_BABBLE (1 << 4) /* device was babbling */
622 #define SITD_STS_XACT (1 << 3) /* illegal IN response */
623 #define SITD_STS_MMF (1 << 2) /* incomplete split transaction */
624 #define SITD_STS_STS (1 << 1) /* split transaction state */
626 #define SITD_ACTIVE(ehci) cpu_to_hc32(ehci, SITD_STS_ACTIVE)
628 __hc32 hw_buf [2]; /* EHCI table 3-12 */
629 __hc32 hw_backpointer; /* EHCI table 3-13 */
630 __hc32 hw_buf_hi [2]; /* Appendix B */
632 /* the rest is HCD-private */
634 union ehci_shadow sitd_next; /* ptr to periodic q entry */
637 struct ehci_iso_stream *stream; /* endpoint's queue */
638 struct list_head sitd_list; /* list of stream's sitds */
641 } __attribute__ ((aligned (32)));
643 /*-------------------------------------------------------------------------*/
646 * EHCI Specification 0.96 Section 3.7
647 * Periodic Frame Span Traversal Node (FSTN)
649 * Manages split interrupt transactions (using TT) that span frame boundaries
650 * into uframes 0/1; see 4.12.2.2. In those uframes, a "save place" FSTN
651 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
652 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
655 __hc32 hw_next; /* any periodic q entry */
656 __hc32 hw_prev; /* qh or EHCI_LIST_END */
658 /* the rest is HCD-private */
660 union ehci_shadow fstn_next; /* ptr to periodic q entry */
661 } __attribute__ ((aligned (32)));
663 /*-------------------------------------------------------------------------*/
665 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
668 * Some EHCI controllers have a Transaction Translator built into the
669 * root hub. This is a non-standard feature. Each controller will need
670 * to add code to the following inline functions, and call them as
671 * needed (mostly in root hub code).
674 #define ehci_is_TDI(e) ((e)->is_tdi_rh_tt)
676 /* Returns the speed of a device attached to a port on the root hub. */
677 static inline unsigned int
678 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
680 if (ehci_is_TDI(ehci)) {
681 switch ((portsc>>26)&3) {
685 return (1<<USB_PORT_FEAT_LOWSPEED);
688 return (1<<USB_PORT_FEAT_HIGHSPEED);
691 return (1<<USB_PORT_FEAT_HIGHSPEED);
696 #define ehci_is_TDI(e) (0)
698 #define ehci_port_speed(ehci, portsc) (1<<USB_PORT_FEAT_HIGHSPEED)
701 /*-------------------------------------------------------------------------*/
703 #ifdef CONFIG_PPC_83xx
704 /* Some Freescale processors have an erratum in which the TT
705 * port number in the queue head was 0..N-1 instead of 1..N.
707 #define ehci_has_fsl_portno_bug(e) ((e)->has_fsl_port_bug)
709 #define ehci_has_fsl_portno_bug(e) (0)
713 * While most USB host controllers implement their registers in
714 * little-endian format, a minority (celleb companion chip) implement
715 * them in big endian format.
717 * This attempts to support either format at compile time without a
718 * runtime penalty, or both formats with the additional overhead
719 * of checking a flag bit.
722 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
723 #define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
725 #define ehci_big_endian_mmio(e) 0
729 * Big-endian read/write functions are arch-specific.
730 * Other arches can be added if/when they're needed.
732 * REVISIT: arch/powerpc now has readl/writel_be, so the
733 * definition below can die once the 4xx support is
734 * finally ported over.
736 #if defined(CONFIG_PPC)
737 #define readl_be(addr) in_be32((__force unsigned *)addr)
738 #define writel_be(val, addr) out_be32((__force unsigned *)addr, val)
741 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
742 __u32 __iomem * regs)
744 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
745 return ehci_big_endian_mmio(ehci) ?
753 static inline void ehci_writel(const struct ehci_hcd *ehci,
754 const unsigned int val, __u32 __iomem *regs)
756 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
757 ehci_big_endian_mmio(ehci) ?
758 writel_be(val, regs) :
765 /*-------------------------------------------------------------------------*/
768 * The AMCC 440EPx not only implements its EHCI registers in big-endian
769 * format, but also its DMA data structures (descriptors).
771 * EHCI controllers accessed through PCI work normally (little-endian
772 * everywhere), so we won't bother supporting a BE-only mode for now.
774 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
775 #define ehci_big_endian_desc(e) ((e)->big_endian_desc)
778 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
780 return ehci_big_endian_desc(ehci)
781 ? (__force __hc32)cpu_to_be32(x)
782 : (__force __hc32)cpu_to_le32(x);
786 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
788 return ehci_big_endian_desc(ehci)
789 ? be32_to_cpu((__force __be32)x)
790 : le32_to_cpu((__force __le32)x);
793 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
795 return ehci_big_endian_desc(ehci)
796 ? be32_to_cpup((__force __be32 *)x)
797 : le32_to_cpup((__force __le32 *)x);
803 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
805 return cpu_to_le32(x);
809 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
811 return le32_to_cpu(x);
814 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
816 return le32_to_cpup(x);
821 /*-------------------------------------------------------------------------*/
824 #define STUB_DEBUG_FILES
827 /*-------------------------------------------------------------------------*/
829 #endif /* __LINUX_EHCI_HCD_H */