2 * MPC83xx SPI controller driver.
4 * Maintainer: Kumar Gala
6 * Copyright (C) 2006 Polycom, Inc.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/types.h>
16 #include <linux/kernel.h>
17 #include <linux/completion.h>
18 #include <linux/interrupt.h>
19 #include <linux/delay.h>
20 #include <linux/irq.h>
21 #include <linux/device.h>
22 #include <linux/spi/spi.h>
23 #include <linux/spi/spi_bitbang.h>
24 #include <linux/platform_device.h>
25 #include <linux/fsl_devices.h>
30 /* SPI Controller registers */
31 struct mpc83xx_spi_reg {
41 /* SPI Controller mode register definitions */
42 #define SPMODE_CI_INACTIVEHIGH (1 << 29)
43 #define SPMODE_CP_BEGIN_EDGECLK (1 << 28)
44 #define SPMODE_DIV16 (1 << 27)
45 #define SPMODE_REV (1 << 26)
46 #define SPMODE_MS (1 << 25)
47 #define SPMODE_ENABLE (1 << 24)
48 #define SPMODE_LEN(x) ((x) << 20)
49 #define SPMODE_PM(x) ((x) << 16)
50 #define SPMODE_OP (1 << 14)
53 * Default for SPI Mode:
54 * SPI MODE 0 (inactive low, phase middle, MSB, 8-bit length, slow clk
56 #define SPMODE_INIT_VAL (SPMODE_CI_INACTIVEHIGH | SPMODE_DIV16 | SPMODE_REV | \
57 SPMODE_MS | SPMODE_LEN(7) | SPMODE_PM(0xf))
59 /* SPIE register values */
60 #define SPIE_NE 0x00000200 /* Not empty */
61 #define SPIE_NF 0x00000100 /* Not full */
63 /* SPIM register values */
64 #define SPIM_NE 0x00000200 /* Not empty */
65 #define SPIM_NF 0x00000100 /* Not full */
67 /* SPI Controller driver's private data. */
69 /* bitbang has to be first */
70 struct spi_bitbang bitbang;
71 struct completion done;
73 struct mpc83xx_spi_reg __iomem *base;
75 /* rx & tx bufs from the spi_transfer */
79 /* functions to deal with different sized buffers */
80 void (*get_rx) (u32 rx_data, struct mpc83xx_spi *);
81 u32(*get_tx) (struct mpc83xx_spi *);
86 unsigned nsecs; /* (clock cycle time)/2 */
89 u32 rx_shift; /* RX data reg shift when in qe mode */
90 u32 tx_shift; /* TX data reg shift when in qe mode */
94 void (*activate_cs) (u8 cs, u8 polarity);
95 void (*deactivate_cs) (u8 cs, u8 polarity);
98 static inline void mpc83xx_spi_write_reg(__be32 __iomem * reg, u32 val)
103 static inline u32 mpc83xx_spi_read_reg(__be32 __iomem * reg)
108 #define MPC83XX_SPI_RX_BUF(type) \
109 void mpc83xx_spi_rx_buf_##type(u32 data, struct mpc83xx_spi *mpc83xx_spi) \
111 type * rx = mpc83xx_spi->rx; \
112 *rx++ = (type)(data >> mpc83xx_spi->rx_shift); \
113 mpc83xx_spi->rx = rx; \
116 #define MPC83XX_SPI_TX_BUF(type) \
117 u32 mpc83xx_spi_tx_buf_##type(struct mpc83xx_spi *mpc83xx_spi) \
120 const type * tx = mpc83xx_spi->tx; \
123 data = *tx++ << mpc83xx_spi->tx_shift; \
124 mpc83xx_spi->tx = tx; \
128 MPC83XX_SPI_RX_BUF(u8)
129 MPC83XX_SPI_RX_BUF(u16)
130 MPC83XX_SPI_RX_BUF(u32)
131 MPC83XX_SPI_TX_BUF(u8)
132 MPC83XX_SPI_TX_BUF(u16)
133 MPC83XX_SPI_TX_BUF(u32)
135 static void mpc83xx_spi_chipselect(struct spi_device *spi, int value)
137 struct mpc83xx_spi *mpc83xx_spi;
138 u8 pol = spi->mode & SPI_CS_HIGH ? 1 : 0;
140 mpc83xx_spi = spi_master_get_devdata(spi->master);
142 if (value == BITBANG_CS_INACTIVE) {
143 if (mpc83xx_spi->deactivate_cs)
144 mpc83xx_spi->deactivate_cs(spi->chip_select, pol);
147 if (value == BITBANG_CS_ACTIVE) {
148 u32 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
149 u32 len = spi->bits_per_word;
155 /* mask out bits we are going to set */
156 regval &= ~(SPMODE_CP_BEGIN_EDGECLK | SPMODE_CI_INACTIVEHIGH
157 | SPMODE_LEN(0xF) | SPMODE_DIV16
158 | SPMODE_PM(0xF) | SPMODE_REV);
160 if (spi->mode & SPI_CPHA)
161 regval |= SPMODE_CP_BEGIN_EDGECLK;
162 if (spi->mode & SPI_CPOL)
163 regval |= SPMODE_CI_INACTIVEHIGH;
164 if (!(spi->mode & SPI_LSB_FIRST))
165 regval |= SPMODE_REV;
167 regval |= SPMODE_LEN(len);
169 if ((mpc83xx_spi->sysclk / spi->max_speed_hz) >= 64) {
170 u8 pm = mpc83xx_spi->sysclk / (spi->max_speed_hz * 64);
172 printk(KERN_WARNING "MPC83xx SPI: SPICLK can't be less then a SYSCLK/1024!\n"
173 "Requested SPICLK is %d Hz. Will use %d Hz instead.\n",
174 spi->max_speed_hz, mpc83xx_spi->sysclk / 1024);
177 regval |= SPMODE_PM(pm) | SPMODE_DIV16;
179 u8 pm = mpc83xx_spi->sysclk / (spi->max_speed_hz * 4);
180 regval |= SPMODE_PM(pm);
183 /* Turn off SPI unit prior changing mode */
184 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
185 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
186 if (mpc83xx_spi->activate_cs)
187 mpc83xx_spi->activate_cs(spi->chip_select, pol);
192 int mpc83xx_spi_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
194 struct mpc83xx_spi *mpc83xx_spi;
199 mpc83xx_spi = spi_master_get_devdata(spi->master);
202 bits_per_word = t->bits_per_word;
209 /* spi_transfer level calls that work per-word */
211 bits_per_word = spi->bits_per_word;
213 /* Make sure its a bit width we support [4..16, 32] */
214 if ((bits_per_word < 4)
215 || ((bits_per_word > 16) && (bits_per_word != 32)))
218 mpc83xx_spi->rx_shift = 0;
219 mpc83xx_spi->tx_shift = 0;
220 if (bits_per_word <= 8) {
221 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
222 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
223 if (mpc83xx_spi->qe_mode) {
224 mpc83xx_spi->rx_shift = 16;
225 mpc83xx_spi->tx_shift = 24;
227 } else if (bits_per_word <= 16) {
228 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u16;
229 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u16;
230 if (mpc83xx_spi->qe_mode) {
231 mpc83xx_spi->rx_shift = 16;
232 mpc83xx_spi->tx_shift = 16;
234 } else if (bits_per_word <= 32) {
235 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u32;
236 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u32;
240 if (mpc83xx_spi->qe_mode && spi->mode & SPI_LSB_FIRST) {
241 mpc83xx_spi->tx_shift = 0;
242 if (bits_per_word <= 8)
243 mpc83xx_spi->rx_shift = 8;
245 mpc83xx_spi->rx_shift = 0;
248 /* nsecs = (clock period)/2 */
250 hz = spi->max_speed_hz;
251 mpc83xx_spi->nsecs = (1000000000 / 2) / hz;
252 if (mpc83xx_spi->nsecs > MAX_UDELAY_MS * 1000)
255 if (bits_per_word == 32)
258 bits_per_word = bits_per_word - 1;
260 regval = mpc83xx_spi_read_reg(&mpc83xx_spi->base->mode);
262 /* mask out bits we are going to set */
263 regval &= ~(SPMODE_LEN(0xF) | SPMODE_REV);
264 regval |= SPMODE_LEN(bits_per_word);
265 if (!(spi->mode & SPI_LSB_FIRST))
266 regval |= SPMODE_REV;
268 /* Turn off SPI unit prior changing mode */
269 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
270 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
275 /* the spi->mode bits understood by this driver: */
276 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST)
278 static int mpc83xx_spi_setup(struct spi_device *spi)
280 struct spi_bitbang *bitbang;
281 struct mpc83xx_spi *mpc83xx_spi;
284 if (spi->mode & ~MODEBITS) {
285 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
286 spi->mode & ~MODEBITS);
290 if (!spi->max_speed_hz)
293 bitbang = spi_master_get_devdata(spi->master);
294 mpc83xx_spi = spi_master_get_devdata(spi->master);
296 if (!spi->bits_per_word)
297 spi->bits_per_word = 8;
299 retval = mpc83xx_spi_setup_transfer(spi, NULL);
303 dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec\n",
304 __FUNCTION__, spi->mode & (SPI_CPOL | SPI_CPHA),
305 spi->bits_per_word, 2 * mpc83xx_spi->nsecs);
307 /* NOTE we _need_ to call chipselect() early, ideally with adapter
308 * setup, unless the hardware defaults cooperate to avoid confusion
309 * between normal (active low) and inverted chipselects.
312 /* deselect chip (low or high) */
313 spin_lock(&bitbang->lock);
314 if (!bitbang->busy) {
315 bitbang->chipselect(spi, BITBANG_CS_INACTIVE);
316 ndelay(mpc83xx_spi->nsecs);
318 spin_unlock(&bitbang->lock);
323 static int mpc83xx_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
325 struct mpc83xx_spi *mpc83xx_spi;
328 mpc83xx_spi = spi_master_get_devdata(spi->master);
330 mpc83xx_spi->tx = t->tx_buf;
331 mpc83xx_spi->rx = t->rx_buf;
332 mpc83xx_spi->count = t->len;
333 INIT_COMPLETION(mpc83xx_spi->done);
336 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, SPIM_NE);
339 word = mpc83xx_spi->get_tx(mpc83xx_spi);
340 mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit, word);
342 wait_for_completion(&mpc83xx_spi->done);
344 /* disable rx ints */
345 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
347 return t->len - mpc83xx_spi->count;
350 irqreturn_t mpc83xx_spi_irq(s32 irq, void *context_data)
352 struct mpc83xx_spi *mpc83xx_spi = context_data;
354 irqreturn_t ret = IRQ_NONE;
356 /* Get interrupt events(tx/rx) */
357 event = mpc83xx_spi_read_reg(&mpc83xx_spi->base->event);
359 /* We need handle RX first */
360 if (event & SPIE_NE) {
361 u32 rx_data = mpc83xx_spi_read_reg(&mpc83xx_spi->base->receive);
364 mpc83xx_spi->get_rx(rx_data, mpc83xx_spi);
369 if ((event & SPIE_NF) == 0)
370 /* spin until TX is done */
372 mpc83xx_spi_read_reg(&mpc83xx_spi->base->event)) &
376 mpc83xx_spi->count -= 1;
377 if (mpc83xx_spi->count) {
378 if (mpc83xx_spi->tx) {
379 u32 word = mpc83xx_spi->get_tx(mpc83xx_spi);
380 mpc83xx_spi_write_reg(&mpc83xx_spi->base->transmit,
384 complete(&mpc83xx_spi->done);
387 /* Clear the events */
388 mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, event);
393 static int __init mpc83xx_spi_probe(struct platform_device *dev)
395 struct spi_master *master;
396 struct mpc83xx_spi *mpc83xx_spi;
397 struct fsl_spi_platform_data *pdata;
402 /* Get resources(memory, IRQ) associated with the device */
403 master = spi_alloc_master(&dev->dev, sizeof(struct mpc83xx_spi));
405 if (master == NULL) {
410 platform_set_drvdata(dev, master);
411 pdata = dev->dev.platform_data;
418 r = platform_get_resource(dev, IORESOURCE_MEM, 0);
423 mpc83xx_spi = spi_master_get_devdata(master);
424 mpc83xx_spi->bitbang.master = spi_master_get(master);
425 mpc83xx_spi->bitbang.chipselect = mpc83xx_spi_chipselect;
426 mpc83xx_spi->bitbang.setup_transfer = mpc83xx_spi_setup_transfer;
427 mpc83xx_spi->bitbang.txrx_bufs = mpc83xx_spi_bufs;
428 mpc83xx_spi->sysclk = pdata->sysclk;
429 mpc83xx_spi->activate_cs = pdata->activate_cs;
430 mpc83xx_spi->deactivate_cs = pdata->deactivate_cs;
431 mpc83xx_spi->qe_mode = pdata->qe_mode;
432 mpc83xx_spi->get_rx = mpc83xx_spi_rx_buf_u8;
433 mpc83xx_spi->get_tx = mpc83xx_spi_tx_buf_u8;
435 mpc83xx_spi->rx_shift = 0;
436 mpc83xx_spi->tx_shift = 0;
437 if (mpc83xx_spi->qe_mode) {
438 mpc83xx_spi->rx_shift = 16;
439 mpc83xx_spi->tx_shift = 24;
442 mpc83xx_spi->bitbang.master->setup = mpc83xx_spi_setup;
443 init_completion(&mpc83xx_spi->done);
445 mpc83xx_spi->base = ioremap(r->start, r->end - r->start + 1);
446 if (mpc83xx_spi->base == NULL) {
451 mpc83xx_spi->irq = platform_get_irq(dev, 0);
453 if (mpc83xx_spi->irq < 0) {
458 /* Register for SPI Interrupt */
459 ret = request_irq(mpc83xx_spi->irq, mpc83xx_spi_irq,
460 0, "mpc83xx_spi", mpc83xx_spi);
465 master->bus_num = pdata->bus_num;
466 master->num_chipselect = pdata->max_chipselect;
468 /* SPI controller initializations */
469 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, 0);
470 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mask, 0);
471 mpc83xx_spi_write_reg(&mpc83xx_spi->base->command, 0);
472 mpc83xx_spi_write_reg(&mpc83xx_spi->base->event, 0xffffffff);
474 /* Enable SPI interface */
475 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
479 mpc83xx_spi_write_reg(&mpc83xx_spi->base->mode, regval);
481 ret = spi_bitbang_start(&mpc83xx_spi->bitbang);
487 "%s: MPC83xx SPI Controller driver at 0x%p (irq = %d)\n",
488 dev->dev.bus_id, mpc83xx_spi->base, mpc83xx_spi->irq);
493 free_irq(mpc83xx_spi->irq, mpc83xx_spi);
495 iounmap(mpc83xx_spi->base);
497 spi_master_put(master);
504 static int __devexit mpc83xx_spi_remove(struct platform_device *dev)
506 struct mpc83xx_spi *mpc83xx_spi;
507 struct spi_master *master;
509 master = platform_get_drvdata(dev);
510 mpc83xx_spi = spi_master_get_devdata(master);
512 spi_bitbang_stop(&mpc83xx_spi->bitbang);
513 free_irq(mpc83xx_spi->irq, mpc83xx_spi);
514 iounmap(mpc83xx_spi->base);
515 spi_master_put(mpc83xx_spi->bitbang.master);
520 static struct platform_driver mpc83xx_spi_driver = {
521 .probe = mpc83xx_spi_probe,
522 .remove = __devexit_p(mpc83xx_spi_remove),
524 .name = "mpc83xx_spi",
528 static int __init mpc83xx_spi_init(void)
530 return platform_driver_register(&mpc83xx_spi_driver);
533 static void __exit mpc83xx_spi_exit(void)
535 platform_driver_unregister(&mpc83xx_spi_driver);
538 module_init(mpc83xx_spi_init);
539 module_exit(mpc83xx_spi_exit);
541 MODULE_AUTHOR("Kumar Gala");
542 MODULE_DESCRIPTION("Simple MPC83xx SPI Driver");
543 MODULE_LICENSE("GPL");