2 * File: drivers/spi/bfin5xx_spi.c
4 * Bryan Wu <bryan.wu@analog.com>
6 * Luke Yang (Analog Devices Inc.)
8 * Created: March. 10th 2006
9 * Description: SPI controller driver for Blackfin BF5xx
10 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 * March 10, 2006 bfin5xx_spi.c Created. (Luke Yang)
14 * August 7, 2006 added full duplex mode (Axel Weiss & Luke Yang)
15 * July 17, 2007 add support for BF54x SPI0 controller (Bryan Wu)
16 * July 30, 2007 add platfrom_resource interface to support multi-port
17 * SPI controller (Bryan Wu)
19 * Copyright 2004-2007 Analog Devices Inc.
21 * This program is free software ; you can redistribute it and/or modify
22 * it under the terms of the GNU General Public License as published by
23 * the Free Software Foundation ; either version 2, or (at your option)
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY ; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
31 * You should have received a copy of the GNU General Public License
32 * along with this program ; see the file COPYING.
33 * If not, write to the Free Software Foundation,
34 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
37 #include <linux/init.h>
38 #include <linux/module.h>
39 #include <linux/delay.h>
40 #include <linux/device.h>
42 #include <linux/ioport.h>
43 #include <linux/irq.h>
44 #include <linux/errno.h>
45 #include <linux/interrupt.h>
46 #include <linux/platform_device.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/spi/spi.h>
49 #include <linux/workqueue.h>
52 #include <asm/portmux.h>
53 #include <asm/bfin5xx_spi.h>
55 #define DRV_NAME "bfin-spi"
56 #define DRV_AUTHOR "Bryan Wu, Luke Yang"
57 #define DRV_DESC "Blackfin BF5xx on-chip SPI Controller Driver"
58 #define DRV_VERSION "1.0"
60 MODULE_AUTHOR(DRV_AUTHOR);
61 MODULE_DESCRIPTION(DRV_DESC);
62 MODULE_LICENSE("GPL");
64 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07) == 0)
66 #define START_STATE ((void *)0)
67 #define RUNNING_STATE ((void *)1)
68 #define DONE_STATE ((void *)2)
69 #define ERROR_STATE ((void *)-1)
70 #define QUEUE_RUNNING 0
71 #define QUEUE_STOPPED 1
74 /* Driver model hookup */
75 struct platform_device *pdev;
77 /* SPI framework hookup */
78 struct spi_master *master;
80 /* Regs base of SPI controller */
81 void __iomem *regs_base;
83 /* Pin request list */
87 struct bfin5xx_spi_master *master_info;
89 /* Driver message queue */
90 struct workqueue_struct *workqueue;
91 struct work_struct pump_messages;
93 struct list_head queue;
97 /* Message Transfer pump */
98 struct tasklet_struct pump_transfers;
100 /* Current message transfer state info */
101 struct spi_message *cur_msg;
102 struct spi_transfer *cur_transfer;
103 struct chip_data *cur_chip;
122 void (*write) (struct driver_data *);
123 void (*read) (struct driver_data *);
124 void (*duplex) (struct driver_data *);
134 u8 width; /* 0 or 1 */
136 u8 bits_per_word; /* 8 or 16 */
137 u8 cs_change_per_word;
138 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
139 void (*write) (struct driver_data *);
140 void (*read) (struct driver_data *);
141 void (*duplex) (struct driver_data *);
144 #define DEFINE_SPI_REG(reg, off) \
145 static inline u16 read_##reg(struct driver_data *drv_data) \
146 { return bfin_read16(drv_data->regs_base + off); } \
147 static inline void write_##reg(struct driver_data *drv_data, u16 v) \
148 { bfin_write16(drv_data->regs_base + off, v); }
150 DEFINE_SPI_REG(CTRL, 0x00)
151 DEFINE_SPI_REG(FLAG, 0x04)
152 DEFINE_SPI_REG(STAT, 0x08)
153 DEFINE_SPI_REG(TDBR, 0x0C)
154 DEFINE_SPI_REG(RDBR, 0x10)
155 DEFINE_SPI_REG(BAUD, 0x14)
156 DEFINE_SPI_REG(SHAW, 0x18)
158 static void bfin_spi_enable(struct driver_data *drv_data)
162 cr = read_CTRL(drv_data);
163 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
166 static void bfin_spi_disable(struct driver_data *drv_data)
170 cr = read_CTRL(drv_data);
171 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
174 /* Caculate the SPI_BAUD register value based on input HZ */
175 static u16 hz_to_spi_baud(u32 speed_hz)
177 u_long sclk = get_sclk();
178 u16 spi_baud = (sclk / (2 * speed_hz));
180 if ((sclk % (2 * speed_hz)) > 0)
186 static int flush(struct driver_data *drv_data)
188 unsigned long limit = loops_per_jiffy << 1;
190 /* wait for stop and clear stat */
191 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && limit--)
194 write_STAT(drv_data, BIT_STAT_CLR);
199 /* Chip select operation functions for cs_change flag */
200 static void cs_active(struct driver_data *drv_data, struct chip_data *chip)
202 u16 flag = read_FLAG(drv_data);
205 flag &= ~(chip->flag << 8);
207 write_FLAG(drv_data, flag);
210 static void cs_deactive(struct driver_data *drv_data, struct chip_data *chip)
212 u16 flag = read_FLAG(drv_data);
214 flag |= (chip->flag << 8);
216 write_FLAG(drv_data, flag);
218 /* Move delay here for consistency */
219 if (chip->cs_chg_udelay)
220 udelay(chip->cs_chg_udelay);
223 #define MAX_SPI_SSEL 7
225 /* stop controller and re-config current chip*/
226 static void restore_state(struct driver_data *drv_data)
228 struct chip_data *chip = drv_data->cur_chip;
230 /* Clear status and disable clock */
231 write_STAT(drv_data, BIT_STAT_CLR);
232 bfin_spi_disable(drv_data);
233 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
235 /* Load the registers */
236 write_CTRL(drv_data, chip->ctl_reg);
237 write_BAUD(drv_data, chip->baud);
239 bfin_spi_enable(drv_data);
240 cs_active(drv_data, chip);
243 /* used to kick off transfer in rx mode */
244 static unsigned short dummy_read(struct driver_data *drv_data)
247 tmp = read_RDBR(drv_data);
251 static void null_writer(struct driver_data *drv_data)
253 u8 n_bytes = drv_data->n_bytes;
255 while (drv_data->tx < drv_data->tx_end) {
256 write_TDBR(drv_data, 0);
257 while ((read_STAT(drv_data) & BIT_STAT_TXS))
259 drv_data->tx += n_bytes;
263 static void null_reader(struct driver_data *drv_data)
265 u8 n_bytes = drv_data->n_bytes;
266 dummy_read(drv_data);
268 while (drv_data->rx < drv_data->rx_end) {
269 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
271 dummy_read(drv_data);
272 drv_data->rx += n_bytes;
276 static void u8_writer(struct driver_data *drv_data)
278 dev_dbg(&drv_data->pdev->dev,
279 "cr8-s is 0x%x\n", read_STAT(drv_data));
281 while (drv_data->tx < drv_data->tx_end) {
282 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
283 while (read_STAT(drv_data) & BIT_STAT_TXS)
288 /* poll for SPI completion before return */
289 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
293 static void u8_cs_chg_writer(struct driver_data *drv_data)
295 struct chip_data *chip = drv_data->cur_chip;
297 while (drv_data->tx < drv_data->tx_end) {
298 cs_active(drv_data, chip);
300 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
301 while (read_STAT(drv_data) & BIT_STAT_TXS)
303 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
306 cs_deactive(drv_data, chip);
312 static void u8_reader(struct driver_data *drv_data)
314 dev_dbg(&drv_data->pdev->dev,
315 "cr-8 is 0x%x\n", read_STAT(drv_data));
317 /* poll for SPI completion before start */
318 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
321 /* clear TDBR buffer before read(else it will be shifted out) */
322 write_TDBR(drv_data, 0xFFFF);
324 dummy_read(drv_data);
326 while (drv_data->rx < drv_data->rx_end - 1) {
327 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
329 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
333 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
335 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
339 static void u8_cs_chg_reader(struct driver_data *drv_data)
341 struct chip_data *chip = drv_data->cur_chip;
343 while (drv_data->rx < drv_data->rx_end) {
344 cs_active(drv_data, chip);
345 read_RDBR(drv_data); /* kick off */
347 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
349 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
352 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
353 cs_deactive(drv_data, chip);
359 static void u8_duplex(struct driver_data *drv_data)
361 /* in duplex mode, clk is triggered by writing of TDBR */
362 while (drv_data->rx < drv_data->rx_end) {
363 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
364 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
366 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
368 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
374 static void u8_cs_chg_duplex(struct driver_data *drv_data)
376 struct chip_data *chip = drv_data->cur_chip;
378 while (drv_data->rx < drv_data->rx_end) {
379 cs_active(drv_data, chip);
381 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
383 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
385 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
387 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
389 cs_deactive(drv_data, chip);
396 static void u16_writer(struct driver_data *drv_data)
398 dev_dbg(&drv_data->pdev->dev,
399 "cr16 is 0x%x\n", read_STAT(drv_data));
401 while (drv_data->tx < drv_data->tx_end) {
402 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
403 while ((read_STAT(drv_data) & BIT_STAT_TXS))
408 /* poll for SPI completion before return */
409 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
413 static void u16_cs_chg_writer(struct driver_data *drv_data)
415 struct chip_data *chip = drv_data->cur_chip;
417 while (drv_data->tx < drv_data->tx_end) {
418 cs_active(drv_data, chip);
420 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
421 while ((read_STAT(drv_data) & BIT_STAT_TXS))
423 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
426 cs_deactive(drv_data, chip);
432 static void u16_reader(struct driver_data *drv_data)
434 dev_dbg(&drv_data->pdev->dev,
435 "cr-16 is 0x%x\n", read_STAT(drv_data));
437 /* poll for SPI completion before start */
438 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
441 /* clear TDBR buffer before read(else it will be shifted out) */
442 write_TDBR(drv_data, 0xFFFF);
444 dummy_read(drv_data);
446 while (drv_data->rx < (drv_data->rx_end - 2)) {
447 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
449 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
453 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
455 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
459 static void u16_cs_chg_reader(struct driver_data *drv_data)
461 struct chip_data *chip = drv_data->cur_chip;
463 /* poll for SPI completion before start */
464 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
467 /* clear TDBR buffer before read(else it will be shifted out) */
468 write_TDBR(drv_data, 0xFFFF);
470 cs_active(drv_data, chip);
471 dummy_read(drv_data);
473 while (drv_data->rx < drv_data->rx_end - 2) {
474 cs_deactive(drv_data, chip);
476 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
478 cs_active(drv_data, chip);
479 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
482 cs_deactive(drv_data, chip);
484 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
486 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
490 static void u16_duplex(struct driver_data *drv_data)
492 /* in duplex mode, clk is triggered by writing of TDBR */
493 while (drv_data->tx < drv_data->tx_end) {
494 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
495 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
497 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
499 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
505 static void u16_cs_chg_duplex(struct driver_data *drv_data)
507 struct chip_data *chip = drv_data->cur_chip;
509 while (drv_data->tx < drv_data->tx_end) {
510 cs_active(drv_data, chip);
512 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
513 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
515 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
517 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
519 cs_deactive(drv_data, chip);
526 /* test if ther is more transfer to be done */
527 static void *next_transfer(struct driver_data *drv_data)
529 struct spi_message *msg = drv_data->cur_msg;
530 struct spi_transfer *trans = drv_data->cur_transfer;
532 /* Move to next transfer */
533 if (trans->transfer_list.next != &msg->transfers) {
534 drv_data->cur_transfer =
535 list_entry(trans->transfer_list.next,
536 struct spi_transfer, transfer_list);
537 return RUNNING_STATE;
543 * caller already set message->status;
544 * dma and pio irqs are blocked give finished message back
546 static void giveback(struct driver_data *drv_data)
548 struct chip_data *chip = drv_data->cur_chip;
549 struct spi_transfer *last_transfer;
551 struct spi_message *msg;
553 spin_lock_irqsave(&drv_data->lock, flags);
554 msg = drv_data->cur_msg;
555 drv_data->cur_msg = NULL;
556 drv_data->cur_transfer = NULL;
557 drv_data->cur_chip = NULL;
558 queue_work(drv_data->workqueue, &drv_data->pump_messages);
559 spin_unlock_irqrestore(&drv_data->lock, flags);
561 last_transfer = list_entry(msg->transfers.prev,
562 struct spi_transfer, transfer_list);
566 /* disable chip select signal. And not stop spi in autobuffer mode */
567 if (drv_data->tx_dma != 0xFFFF) {
568 cs_deactive(drv_data, chip);
569 bfin_spi_disable(drv_data);
572 if (!drv_data->cs_change)
573 cs_deactive(drv_data, chip);
576 msg->complete(msg->context);
579 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
581 struct driver_data *drv_data = dev_id;
582 struct chip_data *chip = drv_data->cur_chip;
583 struct spi_message *msg = drv_data->cur_msg;
585 dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n");
586 clear_dma_irqstat(drv_data->dma_channel);
588 /* Wait for DMA to complete */
589 while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN)
593 * wait for the last transaction shifted out. HRM states:
594 * at this point there may still be data in the SPI DMA FIFO waiting
595 * to be transmitted ... software needs to poll TXS in the SPI_STAT
596 * register until it goes low for 2 successive reads
598 if (drv_data->tx != NULL) {
599 while ((read_STAT(drv_data) & TXS) ||
600 (read_STAT(drv_data) & TXS))
604 while (!(read_STAT(drv_data) & SPIF))
607 msg->actual_length += drv_data->len_in_bytes;
609 if (drv_data->cs_change)
610 cs_deactive(drv_data, chip);
612 /* Move to next transfer */
613 msg->state = next_transfer(drv_data);
615 /* Schedule transfer tasklet */
616 tasklet_schedule(&drv_data->pump_transfers);
618 /* free the irq handler before next transfer */
619 dev_dbg(&drv_data->pdev->dev,
620 "disable dma channel irq%d\n",
621 drv_data->dma_channel);
622 dma_disable_irq(drv_data->dma_channel);
627 static void pump_transfers(unsigned long data)
629 struct driver_data *drv_data = (struct driver_data *)data;
630 struct spi_message *message = NULL;
631 struct spi_transfer *transfer = NULL;
632 struct spi_transfer *previous = NULL;
633 struct chip_data *chip = NULL;
635 u16 cr, dma_width, dma_config;
636 u32 tranf_success = 1;
638 /* Get current state information */
639 message = drv_data->cur_msg;
640 transfer = drv_data->cur_transfer;
641 chip = drv_data->cur_chip;
644 * if msg is error or done, report it back using complete() callback
647 /* Handle for abort */
648 if (message->state == ERROR_STATE) {
649 message->status = -EIO;
654 /* Handle end of message */
655 if (message->state == DONE_STATE) {
661 /* Delay if requested at end of transfer */
662 if (message->state == RUNNING_STATE) {
663 previous = list_entry(transfer->transfer_list.prev,
664 struct spi_transfer, transfer_list);
665 if (previous->delay_usecs)
666 udelay(previous->delay_usecs);
669 /* Setup the transfer state based on the type of transfer */
670 if (flush(drv_data) == 0) {
671 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
672 message->status = -EIO;
677 if (transfer->tx_buf != NULL) {
678 drv_data->tx = (void *)transfer->tx_buf;
679 drv_data->tx_end = drv_data->tx + transfer->len;
680 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
681 transfer->tx_buf, drv_data->tx_end);
686 if (transfer->rx_buf != NULL) {
687 drv_data->rx = transfer->rx_buf;
688 drv_data->rx_end = drv_data->rx + transfer->len;
689 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
690 transfer->rx_buf, drv_data->rx_end);
695 drv_data->rx_dma = transfer->rx_dma;
696 drv_data->tx_dma = transfer->tx_dma;
697 drv_data->len_in_bytes = transfer->len;
698 drv_data->cs_change = transfer->cs_change;
700 /* Bits per word setup */
701 switch (transfer->bits_per_word) {
703 drv_data->n_bytes = 1;
704 width = CFG_SPI_WORDSIZE8;
705 drv_data->read = chip->cs_change_per_word ?
706 u8_cs_chg_reader : u8_reader;
707 drv_data->write = chip->cs_change_per_word ?
708 u8_cs_chg_writer : u8_writer;
709 drv_data->duplex = chip->cs_change_per_word ?
710 u8_cs_chg_duplex : u8_duplex;
714 drv_data->n_bytes = 2;
715 width = CFG_SPI_WORDSIZE16;
716 drv_data->read = chip->cs_change_per_word ?
717 u16_cs_chg_reader : u16_reader;
718 drv_data->write = chip->cs_change_per_word ?
719 u16_cs_chg_writer : u16_writer;
720 drv_data->duplex = chip->cs_change_per_word ?
721 u16_cs_chg_duplex : u16_duplex;
725 /* No change, the same as default setting */
726 drv_data->n_bytes = chip->n_bytes;
728 drv_data->write = drv_data->tx ? chip->write : null_writer;
729 drv_data->read = drv_data->rx ? chip->read : null_reader;
730 drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
733 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
735 write_CTRL(drv_data, cr);
737 if (width == CFG_SPI_WORDSIZE16) {
738 drv_data->len = (transfer->len) >> 1;
740 drv_data->len = transfer->len;
742 dev_dbg(&drv_data->pdev->dev, "transfer: ",
743 "drv_data->write is %p, chip->write is %p, null_wr is %p\n",
744 drv_data->write, chip->write, null_writer);
746 /* speed and width has been set on per message */
747 message->state = RUNNING_STATE;
750 /* Speed setup (surely valid because already checked) */
751 if (transfer->speed_hz)
752 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
754 write_BAUD(drv_data, chip->baud);
756 write_STAT(drv_data, BIT_STAT_CLR);
757 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
758 cs_active(drv_data, chip);
760 dev_dbg(&drv_data->pdev->dev,
761 "now pumping a transfer: width is %d, len is %d\n",
762 width, transfer->len);
765 * Try to map dma buffer and do a dma transfer if
766 * successful use different way to r/w according to
767 * drv_data->cur_chip->enable_dma
769 if (drv_data->cur_chip->enable_dma && drv_data->len > 6) {
771 disable_dma(drv_data->dma_channel);
772 clear_dma_irqstat(drv_data->dma_channel);
773 bfin_spi_disable(drv_data);
775 /* config dma channel */
776 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
777 if (width == CFG_SPI_WORDSIZE16) {
778 set_dma_x_count(drv_data->dma_channel, drv_data->len);
779 set_dma_x_modify(drv_data->dma_channel, 2);
780 dma_width = WDSIZE_16;
782 set_dma_x_count(drv_data->dma_channel, drv_data->len);
783 set_dma_x_modify(drv_data->dma_channel, 1);
784 dma_width = WDSIZE_8;
787 /* poll for SPI completion before start */
788 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
791 /* dirty hack for autobuffer DMA mode */
792 if (drv_data->tx_dma == 0xFFFF) {
793 dev_dbg(&drv_data->pdev->dev,
794 "doing autobuffer DMA out.\n");
796 /* no irq in autobuffer mode */
798 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
799 set_dma_config(drv_data->dma_channel, dma_config);
800 set_dma_start_addr(drv_data->dma_channel,
801 (unsigned long)drv_data->tx);
802 enable_dma(drv_data->dma_channel);
804 /* start SPI transfer */
806 (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE));
808 /* just return here, there can only be one transfer
816 /* In dma mode, rx or tx must be NULL in one transfer */
817 if (drv_data->rx != NULL) {
818 /* set transfer mode, and enable SPI */
819 dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n");
821 /* clear tx reg soformer data is not shifted out */
822 write_TDBR(drv_data, 0xFFFF);
824 set_dma_x_count(drv_data->dma_channel, drv_data->len);
827 dma_enable_irq(drv_data->dma_channel);
828 dma_config = (WNR | RESTART | dma_width | DI_EN);
829 set_dma_config(drv_data->dma_channel, dma_config);
830 set_dma_start_addr(drv_data->dma_channel,
831 (unsigned long)drv_data->rx);
832 enable_dma(drv_data->dma_channel);
834 /* start SPI transfer */
836 (cr | CFG_SPI_DMAREAD | BIT_CTL_ENABLE));
838 } else if (drv_data->tx != NULL) {
839 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
842 dma_enable_irq(drv_data->dma_channel);
843 dma_config = (RESTART | dma_width | DI_EN);
844 set_dma_config(drv_data->dma_channel, dma_config);
845 set_dma_start_addr(drv_data->dma_channel,
846 (unsigned long)drv_data->tx);
847 enable_dma(drv_data->dma_channel);
849 /* start SPI transfer */
851 (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE));
854 /* IO mode write then read */
855 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
857 if (drv_data->tx != NULL && drv_data->rx != NULL) {
858 /* full duplex mode */
859 BUG_ON((drv_data->tx_end - drv_data->tx) !=
860 (drv_data->rx_end - drv_data->rx));
861 dev_dbg(&drv_data->pdev->dev,
862 "IO duplex: cr is 0x%x\n", cr);
864 /* set SPI transfer mode */
865 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
867 drv_data->duplex(drv_data);
869 if (drv_data->tx != drv_data->tx_end)
871 } else if (drv_data->tx != NULL) {
872 /* write only half duplex */
873 dev_dbg(&drv_data->pdev->dev,
874 "IO write: cr is 0x%x\n", cr);
876 /* set SPI transfer mode */
877 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
879 drv_data->write(drv_data);
881 if (drv_data->tx != drv_data->tx_end)
883 } else if (drv_data->rx != NULL) {
884 /* read only half duplex */
885 dev_dbg(&drv_data->pdev->dev,
886 "IO read: cr is 0x%x\n", cr);
888 /* set SPI transfer mode */
889 write_CTRL(drv_data, (cr | CFG_SPI_READ));
891 drv_data->read(drv_data);
892 if (drv_data->rx != drv_data->rx_end)
896 if (!tranf_success) {
897 dev_dbg(&drv_data->pdev->dev,
898 "IO write error!\n");
899 message->state = ERROR_STATE;
901 /* Update total byte transfered */
902 message->actual_length += drv_data->len;
904 /* Move to next transfer of this msg */
905 message->state = next_transfer(drv_data);
908 /* Schedule next transfer tasklet */
909 tasklet_schedule(&drv_data->pump_transfers);
914 /* pop a msg from queue and kick off real transfer */
915 static void pump_messages(struct work_struct *work)
917 struct driver_data *drv_data;
920 drv_data = container_of(work, struct driver_data, pump_messages);
922 /* Lock queue and check for queue work */
923 spin_lock_irqsave(&drv_data->lock, flags);
924 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
925 /* pumper kicked off but no work to do */
927 spin_unlock_irqrestore(&drv_data->lock, flags);
931 /* Make sure we are not already running a message */
932 if (drv_data->cur_msg) {
933 spin_unlock_irqrestore(&drv_data->lock, flags);
937 /* Extract head of queue */
938 drv_data->cur_msg = list_entry(drv_data->queue.next,
939 struct spi_message, queue);
941 /* Setup the SSP using the per chip configuration */
942 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
943 restore_state(drv_data);
945 list_del_init(&drv_data->cur_msg->queue);
947 /* Initial message state */
948 drv_data->cur_msg->state = START_STATE;
949 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
950 struct spi_transfer, transfer_list);
952 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
953 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
954 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
955 drv_data->cur_chip->ctl_reg);
957 dev_dbg(&drv_data->pdev->dev,
958 "the first transfer len is %d\n",
959 drv_data->cur_transfer->len);
961 /* Mark as busy and launch transfers */
962 tasklet_schedule(&drv_data->pump_transfers);
965 spin_unlock_irqrestore(&drv_data->lock, flags);
969 * got a msg to transfer, queue it in drv_data->queue.
970 * And kick off message pumper
972 static int transfer(struct spi_device *spi, struct spi_message *msg)
974 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
977 spin_lock_irqsave(&drv_data->lock, flags);
979 if (drv_data->run == QUEUE_STOPPED) {
980 spin_unlock_irqrestore(&drv_data->lock, flags);
984 msg->actual_length = 0;
985 msg->status = -EINPROGRESS;
986 msg->state = START_STATE;
988 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
989 list_add_tail(&msg->queue, &drv_data->queue);
991 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
992 queue_work(drv_data->workqueue, &drv_data->pump_messages);
994 spin_unlock_irqrestore(&drv_data->lock, flags);
999 #define MAX_SPI_SSEL 7
1001 static u16 ssel[3][MAX_SPI_SSEL] = {
1002 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
1003 P_SPI0_SSEL4, P_SPI0_SSEL5,
1004 P_SPI0_SSEL6, P_SPI0_SSEL7},
1006 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
1007 P_SPI1_SSEL4, P_SPI1_SSEL5,
1008 P_SPI1_SSEL6, P_SPI1_SSEL7},
1010 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
1011 P_SPI2_SSEL4, P_SPI2_SSEL5,
1012 P_SPI2_SSEL6, P_SPI2_SSEL7},
1015 /* first setup for new devices */
1016 static int setup(struct spi_device *spi)
1018 struct bfin5xx_spi_chip *chip_info = NULL;
1019 struct chip_data *chip;
1020 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1023 /* Abort device setup if requested features are not supported */
1024 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1025 dev_err(&spi->dev, "requested mode not fully supported\n");
1029 /* Zero (the default) here means 8 bits */
1030 if (!spi->bits_per_word)
1031 spi->bits_per_word = 8;
1033 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
1036 /* Only alloc (or use chip_info) on first setup */
1037 chip = spi_get_ctldata(spi);
1039 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1043 chip->enable_dma = 0;
1044 chip_info = spi->controller_data;
1047 /* chip_info isn't always needed */
1049 /* Make sure people stop trying to set fields via ctl_reg
1050 * when they should actually be using common SPI framework.
1051 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1052 * Not sure if a user actually needs/uses any of these,
1053 * but let's assume (for now) they do.
1055 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1056 dev_err(&spi->dev, "do not set bits in ctl_reg "
1057 "that the SPI framework manages\n");
1061 chip->enable_dma = chip_info->enable_dma != 0
1062 && drv_data->master_info->enable_dma;
1063 chip->ctl_reg = chip_info->ctl_reg;
1064 chip->bits_per_word = chip_info->bits_per_word;
1065 chip->cs_change_per_word = chip_info->cs_change_per_word;
1066 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1069 /* translate common spi framework into our register */
1070 if (spi->mode & SPI_CPOL)
1071 chip->ctl_reg |= CPOL;
1072 if (spi->mode & SPI_CPHA)
1073 chip->ctl_reg |= CPHA;
1074 if (spi->mode & SPI_LSB_FIRST)
1075 chip->ctl_reg |= LSBF;
1076 /* we dont support running in slave mode (yet?) */
1077 chip->ctl_reg |= MSTR;
1080 * if any one SPI chip is registered and wants DMA, request the
1081 * DMA channel for it
1083 if (chip->enable_dma && !drv_data->dma_requested) {
1084 /* register dma irq handler */
1085 if (request_dma(drv_data->dma_channel, "BF53x_SPI_DMA") < 0) {
1087 "Unable to request BlackFin SPI DMA channel\n");
1090 if (set_dma_callback(drv_data->dma_channel,
1091 (void *)dma_irq_handler, drv_data) < 0) {
1092 dev_dbg(&spi->dev, "Unable to set dma callback\n");
1095 dma_disable_irq(drv_data->dma_channel);
1096 drv_data->dma_requested = 1;
1100 * Notice: for blackfin, the speed_hz is the value of register
1101 * SPI_BAUD, not the real baudrate
1103 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1104 spi_flg = ~(1 << (spi->chip_select));
1105 chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select));
1106 chip->chip_select_num = spi->chip_select;
1108 switch (chip->bits_per_word) {
1111 chip->width = CFG_SPI_WORDSIZE8;
1112 chip->read = chip->cs_change_per_word ?
1113 u8_cs_chg_reader : u8_reader;
1114 chip->write = chip->cs_change_per_word ?
1115 u8_cs_chg_writer : u8_writer;
1116 chip->duplex = chip->cs_change_per_word ?
1117 u8_cs_chg_duplex : u8_duplex;
1122 chip->width = CFG_SPI_WORDSIZE16;
1123 chip->read = chip->cs_change_per_word ?
1124 u16_cs_chg_reader : u16_reader;
1125 chip->write = chip->cs_change_per_word ?
1126 u16_cs_chg_writer : u16_writer;
1127 chip->duplex = chip->cs_change_per_word ?
1128 u16_cs_chg_duplex : u16_duplex;
1132 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1133 chip->bits_per_word);
1138 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1139 spi->modalias, chip->width, chip->enable_dma);
1140 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1141 chip->ctl_reg, chip->flag);
1143 spi_set_ctldata(spi, chip);
1145 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1146 if ((chip->chip_select_num > 0)
1147 && (chip->chip_select_num <= spi->master->num_chipselect))
1148 peripheral_request(ssel[spi->master->bus_num]
1149 [chip->chip_select_num-1], spi->modalias);
1151 cs_deactive(drv_data, chip);
1157 * callback for spi framework.
1158 * clean driver specific data
1160 static void cleanup(struct spi_device *spi)
1162 struct chip_data *chip = spi_get_ctldata(spi);
1164 if ((chip->chip_select_num > 0)
1165 && (chip->chip_select_num <= spi->master->num_chipselect))
1166 peripheral_free(ssel[spi->master->bus_num]
1167 [chip->chip_select_num-1]);
1172 static inline int init_queue(struct driver_data *drv_data)
1174 INIT_LIST_HEAD(&drv_data->queue);
1175 spin_lock_init(&drv_data->lock);
1177 drv_data->run = QUEUE_STOPPED;
1180 /* init transfer tasklet */
1181 tasklet_init(&drv_data->pump_transfers,
1182 pump_transfers, (unsigned long)drv_data);
1184 /* init messages workqueue */
1185 INIT_WORK(&drv_data->pump_messages, pump_messages);
1186 drv_data->workqueue =
1187 create_singlethread_workqueue(drv_data->master->dev.parent->bus_id);
1188 if (drv_data->workqueue == NULL)
1194 static inline int start_queue(struct driver_data *drv_data)
1196 unsigned long flags;
1198 spin_lock_irqsave(&drv_data->lock, flags);
1200 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1201 spin_unlock_irqrestore(&drv_data->lock, flags);
1205 drv_data->run = QUEUE_RUNNING;
1206 drv_data->cur_msg = NULL;
1207 drv_data->cur_transfer = NULL;
1208 drv_data->cur_chip = NULL;
1209 spin_unlock_irqrestore(&drv_data->lock, flags);
1211 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1216 static inline int stop_queue(struct driver_data *drv_data)
1218 unsigned long flags;
1219 unsigned limit = 500;
1222 spin_lock_irqsave(&drv_data->lock, flags);
1225 * This is a bit lame, but is optimized for the common execution path.
1226 * A wait_queue on the drv_data->busy could be used, but then the common
1227 * execution path (pump_messages) would be required to call wake_up or
1228 * friends on every SPI message. Do this instead
1230 drv_data->run = QUEUE_STOPPED;
1231 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1232 spin_unlock_irqrestore(&drv_data->lock, flags);
1234 spin_lock_irqsave(&drv_data->lock, flags);
1237 if (!list_empty(&drv_data->queue) || drv_data->busy)
1240 spin_unlock_irqrestore(&drv_data->lock, flags);
1245 static inline int destroy_queue(struct driver_data *drv_data)
1249 status = stop_queue(drv_data);
1253 destroy_workqueue(drv_data->workqueue);
1258 static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1260 struct device *dev = &pdev->dev;
1261 struct bfin5xx_spi_master *platform_info;
1262 struct spi_master *master;
1263 struct driver_data *drv_data = 0;
1264 struct resource *res;
1267 platform_info = dev->platform_data;
1269 /* Allocate master with space for drv_data */
1270 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1272 dev_err(&pdev->dev, "can not alloc spi_master\n");
1276 drv_data = spi_master_get_devdata(master);
1277 drv_data->master = master;
1278 drv_data->master_info = platform_info;
1279 drv_data->pdev = pdev;
1280 drv_data->pin_req = platform_info->pin_req;
1282 master->bus_num = pdev->id;
1283 master->num_chipselect = platform_info->num_chipselect;
1284 master->cleanup = cleanup;
1285 master->setup = setup;
1286 master->transfer = transfer;
1288 /* Find and map our resources */
1289 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1291 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1293 goto out_error_get_res;
1296 drv_data->regs_base = ioremap(res->start, (res->end - res->start + 1));
1297 if (drv_data->regs_base == NULL) {
1298 dev_err(dev, "Cannot map IO\n");
1300 goto out_error_ioremap;
1303 drv_data->dma_channel = platform_get_irq(pdev, 0);
1304 if (drv_data->dma_channel < 0) {
1305 dev_err(dev, "No DMA channel specified\n");
1307 goto out_error_no_dma_ch;
1310 /* Initial and start queue */
1311 status = init_queue(drv_data);
1313 dev_err(dev, "problem initializing queue\n");
1314 goto out_error_queue_alloc;
1317 status = start_queue(drv_data);
1319 dev_err(dev, "problem starting queue\n");
1320 goto out_error_queue_alloc;
1323 /* Register with the SPI framework */
1324 platform_set_drvdata(pdev, drv_data);
1325 status = spi_register_master(master);
1327 dev_err(dev, "problem registering spi master\n");
1328 goto out_error_queue_alloc;
1331 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1333 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1337 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
1338 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1339 drv_data->dma_channel);
1342 out_error_queue_alloc:
1343 destroy_queue(drv_data);
1344 out_error_no_dma_ch:
1345 iounmap((void *) drv_data->regs_base);
1349 spi_master_put(master);
1354 /* stop hardware and remove the driver */
1355 static int __devexit bfin5xx_spi_remove(struct platform_device *pdev)
1357 struct driver_data *drv_data = platform_get_drvdata(pdev);
1363 /* Remove the queue */
1364 status = destroy_queue(drv_data);
1368 /* Disable the SSP at the peripheral and SOC level */
1369 bfin_spi_disable(drv_data);
1372 if (drv_data->master_info->enable_dma) {
1373 if (dma_channel_active(drv_data->dma_channel))
1374 free_dma(drv_data->dma_channel);
1377 /* Disconnect from the SPI framework */
1378 spi_unregister_master(drv_data->master);
1380 peripheral_free_list(drv_data->pin_req);
1382 /* Prevent double remove */
1383 platform_set_drvdata(pdev, NULL);
1389 static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1391 struct driver_data *drv_data = platform_get_drvdata(pdev);
1394 status = stop_queue(drv_data);
1399 bfin_spi_disable(drv_data);
1404 static int bfin5xx_spi_resume(struct platform_device *pdev)
1406 struct driver_data *drv_data = platform_get_drvdata(pdev);
1409 /* Enable the SPI interface */
1410 bfin_spi_enable(drv_data);
1412 /* Start the queue running */
1413 status = start_queue(drv_data);
1415 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1422 #define bfin5xx_spi_suspend NULL
1423 #define bfin5xx_spi_resume NULL
1424 #endif /* CONFIG_PM */
1426 MODULE_ALIAS("bfin-spi-master"); /* for platform bus hotplug */
1427 static struct platform_driver bfin5xx_spi_driver = {
1430 .owner = THIS_MODULE,
1432 .suspend = bfin5xx_spi_suspend,
1433 .resume = bfin5xx_spi_resume,
1434 .remove = __devexit_p(bfin5xx_spi_remove),
1437 static int __init bfin5xx_spi_init(void)
1439 return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe);
1441 module_init(bfin5xx_spi_init);
1443 static void __exit bfin5xx_spi_exit(void)
1445 platform_driver_unregister(&bfin5xx_spi_driver);
1447 module_exit(bfin5xx_spi_exit);