2 * File: drivers/spi/bfin5xx_spi.c
4 * Bryan Wu <bryan.wu@analog.com>
6 * Luke Yang (Analog Devices Inc.)
8 * Created: March. 10th 2006
9 * Description: SPI controller driver for Blackfin BF5xx
10 * Bugs: Enter bugs at http://blackfin.uclinux.org/
13 * March 10, 2006 bfin5xx_spi.c Created. (Luke Yang)
14 * August 7, 2006 added full duplex mode (Axel Weiss & Luke Yang)
15 * July 17, 2007 add support for BF54x SPI0 controller (Bryan Wu)
16 * July 30, 2007 add platfrom_resource interface to support multi-port
17 * SPI controller (Bryan Wu)
19 * Copyright 2004-2007 Analog Devices Inc.
21 * This program is free software ; you can redistribute it and/or modify
22 * it under the terms of the GNU General Public License as published by
23 * the Free Software Foundation ; either version 2, or (at your option)
26 * This program is distributed in the hope that it will be useful,
27 * but WITHOUT ANY WARRANTY ; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
29 * GNU General Public License for more details.
31 * You should have received a copy of the GNU General Public License
32 * along with this program ; see the file COPYING.
33 * If not, write to the Free Software Foundation,
34 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
37 #include <linux/init.h>
38 #include <linux/module.h>
39 #include <linux/delay.h>
40 #include <linux/device.h>
42 #include <linux/ioport.h>
43 #include <linux/irq.h>
44 #include <linux/errno.h>
45 #include <linux/interrupt.h>
46 #include <linux/platform_device.h>
47 #include <linux/dma-mapping.h>
48 #include <linux/spi/spi.h>
49 #include <linux/workqueue.h>
52 #include <asm/portmux.h>
53 #include <asm/bfin5xx_spi.h>
55 #define DRV_NAME "bfin-spi"
56 #define DRV_AUTHOR "Bryan Wu, Luke Yang"
57 #define DRV_DESC "Blackfin BF5xx on-chip SPI Controller Driver"
58 #define DRV_VERSION "1.0"
60 MODULE_AUTHOR(DRV_AUTHOR);
61 MODULE_DESCRIPTION(DRV_DESC);
62 MODULE_LICENSE("GPL");
64 #define IS_DMA_ALIGNED(x) (((u32)(x)&0x07) == 0)
66 #define START_STATE ((void *)0)
67 #define RUNNING_STATE ((void *)1)
68 #define DONE_STATE ((void *)2)
69 #define ERROR_STATE ((void *)-1)
70 #define QUEUE_RUNNING 0
71 #define QUEUE_STOPPED 1
74 /* Driver model hookup */
75 struct platform_device *pdev;
77 /* SPI framework hookup */
78 struct spi_master *master;
80 /* Regs base of SPI controller */
81 void __iomem *regs_base;
83 /* Pin request list */
87 struct bfin5xx_spi_master *master_info;
89 /* Driver message queue */
90 struct workqueue_struct *workqueue;
91 struct work_struct pump_messages;
93 struct list_head queue;
97 /* Message Transfer pump */
98 struct tasklet_struct pump_transfers;
100 /* Current message transfer state info */
101 struct spi_message *cur_msg;
102 struct spi_transfer *cur_transfer;
103 struct chip_data *cur_chip;
122 void (*write) (struct driver_data *);
123 void (*read) (struct driver_data *);
124 void (*duplex) (struct driver_data *);
134 u8 width; /* 0 or 1 */
136 u8 bits_per_word; /* 8 or 16 */
137 u8 cs_change_per_word;
138 u16 cs_chg_udelay; /* Some devices require > 255usec delay */
139 void (*write) (struct driver_data *);
140 void (*read) (struct driver_data *);
141 void (*duplex) (struct driver_data *);
144 #define DEFINE_SPI_REG(reg, off) \
145 static inline u16 read_##reg(struct driver_data *drv_data) \
146 { return bfin_read16(drv_data->regs_base + off); } \
147 static inline void write_##reg(struct driver_data *drv_data, u16 v) \
148 { bfin_write16(drv_data->regs_base + off, v); }
150 DEFINE_SPI_REG(CTRL, 0x00)
151 DEFINE_SPI_REG(FLAG, 0x04)
152 DEFINE_SPI_REG(STAT, 0x08)
153 DEFINE_SPI_REG(TDBR, 0x0C)
154 DEFINE_SPI_REG(RDBR, 0x10)
155 DEFINE_SPI_REG(BAUD, 0x14)
156 DEFINE_SPI_REG(SHAW, 0x18)
158 static void bfin_spi_enable(struct driver_data *drv_data)
162 cr = read_CTRL(drv_data);
163 write_CTRL(drv_data, (cr | BIT_CTL_ENABLE));
166 static void bfin_spi_disable(struct driver_data *drv_data)
170 cr = read_CTRL(drv_data);
171 write_CTRL(drv_data, (cr & (~BIT_CTL_ENABLE)));
174 /* Caculate the SPI_BAUD register value based on input HZ */
175 static u16 hz_to_spi_baud(u32 speed_hz)
177 u_long sclk = get_sclk();
178 u16 spi_baud = (sclk / (2 * speed_hz));
180 if ((sclk % (2 * speed_hz)) > 0)
186 static int flush(struct driver_data *drv_data)
188 unsigned long limit = loops_per_jiffy << 1;
190 /* wait for stop and clear stat */
191 while (!(read_STAT(drv_data) & BIT_STAT_SPIF) && limit--)
194 write_STAT(drv_data, BIT_STAT_CLR);
199 /* Chip select operation functions for cs_change flag */
200 static void cs_active(struct driver_data *drv_data, struct chip_data *chip)
202 u16 flag = read_FLAG(drv_data);
205 flag &= ~(chip->flag << 8);
207 write_FLAG(drv_data, flag);
210 static void cs_deactive(struct driver_data *drv_data, struct chip_data *chip)
212 u16 flag = read_FLAG(drv_data);
214 flag |= (chip->flag << 8);
216 write_FLAG(drv_data, flag);
218 /* Move delay here for consistency */
219 if (chip->cs_chg_udelay)
220 udelay(chip->cs_chg_udelay);
223 #define MAX_SPI_SSEL 7
225 /* stop controller and re-config current chip*/
226 static void restore_state(struct driver_data *drv_data)
228 struct chip_data *chip = drv_data->cur_chip;
230 /* Clear status and disable clock */
231 write_STAT(drv_data, BIT_STAT_CLR);
232 bfin_spi_disable(drv_data);
233 dev_dbg(&drv_data->pdev->dev, "restoring spi ctl state\n");
235 /* Load the registers */
236 write_CTRL(drv_data, chip->ctl_reg);
237 write_BAUD(drv_data, chip->baud);
239 bfin_spi_enable(drv_data);
240 cs_active(drv_data, chip);
243 /* used to kick off transfer in rx mode */
244 static unsigned short dummy_read(struct driver_data *drv_data)
247 tmp = read_RDBR(drv_data);
251 static void null_writer(struct driver_data *drv_data)
253 u8 n_bytes = drv_data->n_bytes;
255 while (drv_data->tx < drv_data->tx_end) {
256 write_TDBR(drv_data, 0);
257 while ((read_STAT(drv_data) & BIT_STAT_TXS))
259 drv_data->tx += n_bytes;
263 static void null_reader(struct driver_data *drv_data)
265 u8 n_bytes = drv_data->n_bytes;
266 dummy_read(drv_data);
268 while (drv_data->rx < drv_data->rx_end) {
269 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
271 dummy_read(drv_data);
272 drv_data->rx += n_bytes;
276 static void u8_writer(struct driver_data *drv_data)
278 dev_dbg(&drv_data->pdev->dev,
279 "cr8-s is 0x%x\n", read_STAT(drv_data));
281 /* poll for SPI completion before start */
282 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
285 while (drv_data->tx < drv_data->tx_end) {
286 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
287 while (read_STAT(drv_data) & BIT_STAT_TXS)
293 static void u8_cs_chg_writer(struct driver_data *drv_data)
295 struct chip_data *chip = drv_data->cur_chip;
297 /* poll for SPI completion before start */
298 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
301 while (drv_data->tx < drv_data->tx_end) {
302 cs_active(drv_data, chip);
304 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
305 while (read_STAT(drv_data) & BIT_STAT_TXS)
308 cs_deactive(drv_data, chip);
314 static void u8_reader(struct driver_data *drv_data)
316 dev_dbg(&drv_data->pdev->dev,
317 "cr-8 is 0x%x\n", read_STAT(drv_data));
319 /* poll for SPI completion before start */
320 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
323 /* clear TDBR buffer before read(else it will be shifted out) */
324 write_TDBR(drv_data, 0xFFFF);
326 dummy_read(drv_data);
328 while (drv_data->rx < drv_data->rx_end - 1) {
329 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
331 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
335 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
337 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
341 static void u8_cs_chg_reader(struct driver_data *drv_data)
343 struct chip_data *chip = drv_data->cur_chip;
345 /* poll for SPI completion before start */
346 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
349 /* clear TDBR buffer before read(else it will be shifted out) */
350 write_TDBR(drv_data, 0xFFFF);
352 cs_active(drv_data, chip);
353 dummy_read(drv_data);
355 while (drv_data->rx < drv_data->rx_end - 1) {
356 cs_deactive(drv_data, chip);
358 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
360 cs_active(drv_data, chip);
361 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
364 cs_deactive(drv_data, chip);
366 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
368 *(u8 *) (drv_data->rx) = read_SHAW(drv_data);
372 static void u8_duplex(struct driver_data *drv_data)
374 /* poll for SPI completion before start */
375 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
378 /* in duplex mode, clk is triggered by writing of TDBR */
379 while (drv_data->rx < drv_data->rx_end) {
380 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
381 while (read_STAT(drv_data) & BIT_STAT_TXS)
383 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
385 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
391 static void u8_cs_chg_duplex(struct driver_data *drv_data)
393 struct chip_data *chip = drv_data->cur_chip;
395 /* poll for SPI completion before start */
396 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
399 while (drv_data->rx < drv_data->rx_end) {
400 cs_active(drv_data, chip);
402 write_TDBR(drv_data, (*(u8 *) (drv_data->tx)));
403 while (read_STAT(drv_data) & BIT_STAT_TXS)
405 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
407 *(u8 *) (drv_data->rx) = read_RDBR(drv_data);
409 cs_deactive(drv_data, chip);
416 static void u16_writer(struct driver_data *drv_data)
418 dev_dbg(&drv_data->pdev->dev,
419 "cr16 is 0x%x\n", read_STAT(drv_data));
421 /* poll for SPI completion before start */
422 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
425 while (drv_data->tx < drv_data->tx_end) {
426 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
427 while ((read_STAT(drv_data) & BIT_STAT_TXS))
433 static void u16_cs_chg_writer(struct driver_data *drv_data)
435 struct chip_data *chip = drv_data->cur_chip;
437 /* poll for SPI completion before start */
438 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
441 while (drv_data->tx < drv_data->tx_end) {
442 cs_active(drv_data, chip);
444 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
445 while ((read_STAT(drv_data) & BIT_STAT_TXS))
448 cs_deactive(drv_data, chip);
454 static void u16_reader(struct driver_data *drv_data)
456 dev_dbg(&drv_data->pdev->dev,
457 "cr-16 is 0x%x\n", read_STAT(drv_data));
459 /* poll for SPI completion before start */
460 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
463 /* clear TDBR buffer before read(else it will be shifted out) */
464 write_TDBR(drv_data, 0xFFFF);
466 dummy_read(drv_data);
468 while (drv_data->rx < (drv_data->rx_end - 2)) {
469 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
471 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
475 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
477 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
481 static void u16_cs_chg_reader(struct driver_data *drv_data)
483 struct chip_data *chip = drv_data->cur_chip;
485 /* poll for SPI completion before start */
486 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
489 /* clear TDBR buffer before read(else it will be shifted out) */
490 write_TDBR(drv_data, 0xFFFF);
492 cs_active(drv_data, chip);
493 dummy_read(drv_data);
495 while (drv_data->rx < drv_data->rx_end - 2) {
496 cs_deactive(drv_data, chip);
498 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
500 cs_active(drv_data, chip);
501 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
504 cs_deactive(drv_data, chip);
506 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
508 *(u16 *) (drv_data->rx) = read_SHAW(drv_data);
512 static void u16_duplex(struct driver_data *drv_data)
514 /* poll for SPI completion before start */
515 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
518 /* in duplex mode, clk is triggered by writing of TDBR */
519 while (drv_data->tx < drv_data->tx_end) {
520 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
521 while (read_STAT(drv_data) & BIT_STAT_TXS)
523 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
525 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
531 static void u16_cs_chg_duplex(struct driver_data *drv_data)
533 struct chip_data *chip = drv_data->cur_chip;
535 /* poll for SPI completion before start */
536 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
539 while (drv_data->tx < drv_data->tx_end) {
540 cs_active(drv_data, chip);
542 write_TDBR(drv_data, (*(u16 *) (drv_data->tx)));
543 while (read_STAT(drv_data) & BIT_STAT_TXS)
545 while (!(read_STAT(drv_data) & BIT_STAT_RXS))
547 *(u16 *) (drv_data->rx) = read_RDBR(drv_data);
549 cs_deactive(drv_data, chip);
556 /* test if ther is more transfer to be done */
557 static void *next_transfer(struct driver_data *drv_data)
559 struct spi_message *msg = drv_data->cur_msg;
560 struct spi_transfer *trans = drv_data->cur_transfer;
562 /* Move to next transfer */
563 if (trans->transfer_list.next != &msg->transfers) {
564 drv_data->cur_transfer =
565 list_entry(trans->transfer_list.next,
566 struct spi_transfer, transfer_list);
567 return RUNNING_STATE;
573 * caller already set message->status;
574 * dma and pio irqs are blocked give finished message back
576 static void giveback(struct driver_data *drv_data)
578 struct chip_data *chip = drv_data->cur_chip;
579 struct spi_transfer *last_transfer;
581 struct spi_message *msg;
583 spin_lock_irqsave(&drv_data->lock, flags);
584 msg = drv_data->cur_msg;
585 drv_data->cur_msg = NULL;
586 drv_data->cur_transfer = NULL;
587 drv_data->cur_chip = NULL;
588 queue_work(drv_data->workqueue, &drv_data->pump_messages);
589 spin_unlock_irqrestore(&drv_data->lock, flags);
591 last_transfer = list_entry(msg->transfers.prev,
592 struct spi_transfer, transfer_list);
596 /* disable chip select signal. And not stop spi in autobuffer mode */
597 if (drv_data->tx_dma != 0xFFFF) {
598 cs_deactive(drv_data, chip);
599 bfin_spi_disable(drv_data);
602 if (!drv_data->cs_change)
603 cs_deactive(drv_data, chip);
606 msg->complete(msg->context);
609 static irqreturn_t dma_irq_handler(int irq, void *dev_id)
611 struct driver_data *drv_data = dev_id;
612 struct chip_data *chip = drv_data->cur_chip;
613 struct spi_message *msg = drv_data->cur_msg;
615 dev_dbg(&drv_data->pdev->dev, "in dma_irq_handler\n");
616 clear_dma_irqstat(drv_data->dma_channel);
618 /* Wait for DMA to complete */
619 while (get_dma_curr_irqstat(drv_data->dma_channel) & DMA_RUN)
623 * wait for the last transaction shifted out. HRM states:
624 * at this point there may still be data in the SPI DMA FIFO waiting
625 * to be transmitted ... software needs to poll TXS in the SPI_STAT
626 * register until it goes low for 2 successive reads
628 if (drv_data->tx != NULL) {
629 while ((read_STAT(drv_data) & TXS) ||
630 (read_STAT(drv_data) & TXS))
634 while (!(read_STAT(drv_data) & SPIF))
637 msg->actual_length += drv_data->len_in_bytes;
639 if (drv_data->cs_change)
640 cs_deactive(drv_data, chip);
642 /* Move to next transfer */
643 msg->state = next_transfer(drv_data);
645 /* Schedule transfer tasklet */
646 tasklet_schedule(&drv_data->pump_transfers);
648 /* free the irq handler before next transfer */
649 dev_dbg(&drv_data->pdev->dev,
650 "disable dma channel irq%d\n",
651 drv_data->dma_channel);
652 dma_disable_irq(drv_data->dma_channel);
657 static void pump_transfers(unsigned long data)
659 struct driver_data *drv_data = (struct driver_data *)data;
660 struct spi_message *message = NULL;
661 struct spi_transfer *transfer = NULL;
662 struct spi_transfer *previous = NULL;
663 struct chip_data *chip = NULL;
665 u16 cr, dma_width, dma_config;
666 u32 tranf_success = 1;
668 /* Get current state information */
669 message = drv_data->cur_msg;
670 transfer = drv_data->cur_transfer;
671 chip = drv_data->cur_chip;
674 * if msg is error or done, report it back using complete() callback
677 /* Handle for abort */
678 if (message->state == ERROR_STATE) {
679 message->status = -EIO;
684 /* Handle end of message */
685 if (message->state == DONE_STATE) {
691 /* Delay if requested at end of transfer */
692 if (message->state == RUNNING_STATE) {
693 previous = list_entry(transfer->transfer_list.prev,
694 struct spi_transfer, transfer_list);
695 if (previous->delay_usecs)
696 udelay(previous->delay_usecs);
699 /* Setup the transfer state based on the type of transfer */
700 if (flush(drv_data) == 0) {
701 dev_err(&drv_data->pdev->dev, "pump_transfers: flush failed\n");
702 message->status = -EIO;
707 if (transfer->tx_buf != NULL) {
708 drv_data->tx = (void *)transfer->tx_buf;
709 drv_data->tx_end = drv_data->tx + transfer->len;
710 dev_dbg(&drv_data->pdev->dev, "tx_buf is %p, tx_end is %p\n",
711 transfer->tx_buf, drv_data->tx_end);
716 if (transfer->rx_buf != NULL) {
717 drv_data->rx = transfer->rx_buf;
718 drv_data->rx_end = drv_data->rx + transfer->len;
719 dev_dbg(&drv_data->pdev->dev, "rx_buf is %p, rx_end is %p\n",
720 transfer->rx_buf, drv_data->rx_end);
725 drv_data->rx_dma = transfer->rx_dma;
726 drv_data->tx_dma = transfer->tx_dma;
727 drv_data->len_in_bytes = transfer->len;
728 drv_data->cs_change = transfer->cs_change;
730 /* Bits per word setup */
731 switch (transfer->bits_per_word) {
733 drv_data->n_bytes = 1;
734 width = CFG_SPI_WORDSIZE8;
735 drv_data->read = chip->cs_change_per_word ?
736 u8_cs_chg_reader : u8_reader;
737 drv_data->write = chip->cs_change_per_word ?
738 u8_cs_chg_writer : u8_writer;
739 drv_data->duplex = chip->cs_change_per_word ?
740 u8_cs_chg_duplex : u8_duplex;
744 drv_data->n_bytes = 2;
745 width = CFG_SPI_WORDSIZE16;
746 drv_data->read = chip->cs_change_per_word ?
747 u16_cs_chg_reader : u16_reader;
748 drv_data->write = chip->cs_change_per_word ?
749 u16_cs_chg_writer : u16_writer;
750 drv_data->duplex = chip->cs_change_per_word ?
751 u16_cs_chg_duplex : u16_duplex;
755 /* No change, the same as default setting */
756 drv_data->n_bytes = chip->n_bytes;
758 drv_data->write = drv_data->tx ? chip->write : null_writer;
759 drv_data->read = drv_data->rx ? chip->read : null_reader;
760 drv_data->duplex = chip->duplex ? chip->duplex : null_writer;
763 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
765 write_CTRL(drv_data, cr);
767 if (width == CFG_SPI_WORDSIZE16) {
768 drv_data->len = (transfer->len) >> 1;
770 drv_data->len = transfer->len;
772 dev_dbg(&drv_data->pdev->dev, "transfer: ",
773 "drv_data->write is %p, chip->write is %p, null_wr is %p\n",
774 drv_data->write, chip->write, null_writer);
776 /* speed and width has been set on per message */
777 message->state = RUNNING_STATE;
780 /* Speed setup (surely valid because already checked) */
781 if (transfer->speed_hz)
782 write_BAUD(drv_data, hz_to_spi_baud(transfer->speed_hz));
784 write_BAUD(drv_data, chip->baud);
786 write_STAT(drv_data, BIT_STAT_CLR);
787 cr = (read_CTRL(drv_data) & (~BIT_CTL_TIMOD));
788 cs_active(drv_data, chip);
790 dev_dbg(&drv_data->pdev->dev,
791 "now pumping a transfer: width is %d, len is %d\n",
792 width, transfer->len);
795 * Try to map dma buffer and do a dma transfer if
796 * successful use different way to r/w according to
797 * drv_data->cur_chip->enable_dma
799 if (drv_data->cur_chip->enable_dma && drv_data->len > 6) {
801 disable_dma(drv_data->dma_channel);
802 clear_dma_irqstat(drv_data->dma_channel);
803 bfin_spi_disable(drv_data);
805 /* config dma channel */
806 dev_dbg(&drv_data->pdev->dev, "doing dma transfer\n");
807 if (width == CFG_SPI_WORDSIZE16) {
808 set_dma_x_count(drv_data->dma_channel, drv_data->len);
809 set_dma_x_modify(drv_data->dma_channel, 2);
810 dma_width = WDSIZE_16;
812 set_dma_x_count(drv_data->dma_channel, drv_data->len);
813 set_dma_x_modify(drv_data->dma_channel, 1);
814 dma_width = WDSIZE_8;
817 /* poll for SPI completion before start */
818 while (!(read_STAT(drv_data) & BIT_STAT_SPIF))
821 /* dirty hack for autobuffer DMA mode */
822 if (drv_data->tx_dma == 0xFFFF) {
823 dev_dbg(&drv_data->pdev->dev,
824 "doing autobuffer DMA out.\n");
826 /* no irq in autobuffer mode */
828 (DMAFLOW_AUTO | RESTART | dma_width | DI_EN);
829 set_dma_config(drv_data->dma_channel, dma_config);
830 set_dma_start_addr(drv_data->dma_channel,
831 (unsigned long)drv_data->tx);
832 enable_dma(drv_data->dma_channel);
834 /* start SPI transfer */
836 (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE));
838 /* just return here, there can only be one transfer
846 /* In dma mode, rx or tx must be NULL in one transfer */
847 if (drv_data->rx != NULL) {
848 /* set transfer mode, and enable SPI */
849 dev_dbg(&drv_data->pdev->dev, "doing DMA in.\n");
851 /* clear tx reg soformer data is not shifted out */
852 write_TDBR(drv_data, 0xFFFF);
854 set_dma_x_count(drv_data->dma_channel, drv_data->len);
857 dma_enable_irq(drv_data->dma_channel);
858 dma_config = (WNR | RESTART | dma_width | DI_EN);
859 set_dma_config(drv_data->dma_channel, dma_config);
860 set_dma_start_addr(drv_data->dma_channel,
861 (unsigned long)drv_data->rx);
862 enable_dma(drv_data->dma_channel);
864 /* start SPI transfer */
866 (cr | CFG_SPI_DMAREAD | BIT_CTL_ENABLE));
868 } else if (drv_data->tx != NULL) {
869 dev_dbg(&drv_data->pdev->dev, "doing DMA out.\n");
872 dma_enable_irq(drv_data->dma_channel);
873 dma_config = (RESTART | dma_width | DI_EN);
874 set_dma_config(drv_data->dma_channel, dma_config);
875 set_dma_start_addr(drv_data->dma_channel,
876 (unsigned long)drv_data->tx);
877 enable_dma(drv_data->dma_channel);
879 /* start SPI transfer */
881 (cr | CFG_SPI_DMAWRITE | BIT_CTL_ENABLE));
884 /* IO mode write then read */
885 dev_dbg(&drv_data->pdev->dev, "doing IO transfer\n");
887 if (drv_data->tx != NULL && drv_data->rx != NULL) {
888 /* full duplex mode */
889 BUG_ON((drv_data->tx_end - drv_data->tx) !=
890 (drv_data->rx_end - drv_data->rx));
891 dev_dbg(&drv_data->pdev->dev,
892 "IO duplex: cr is 0x%x\n", cr);
894 /* set SPI transfer mode */
895 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
897 drv_data->duplex(drv_data);
899 if (drv_data->tx != drv_data->tx_end)
901 } else if (drv_data->tx != NULL) {
902 /* write only half duplex */
903 dev_dbg(&drv_data->pdev->dev,
904 "IO write: cr is 0x%x\n", cr);
906 /* set SPI transfer mode */
907 write_CTRL(drv_data, (cr | CFG_SPI_WRITE));
909 drv_data->write(drv_data);
911 if (drv_data->tx != drv_data->tx_end)
913 } else if (drv_data->rx != NULL) {
914 /* read only half duplex */
915 dev_dbg(&drv_data->pdev->dev,
916 "IO read: cr is 0x%x\n", cr);
918 /* set SPI transfer mode */
919 write_CTRL(drv_data, (cr | CFG_SPI_READ));
921 drv_data->read(drv_data);
922 if (drv_data->rx != drv_data->rx_end)
926 if (!tranf_success) {
927 dev_dbg(&drv_data->pdev->dev,
928 "IO write error!\n");
929 message->state = ERROR_STATE;
931 /* Update total byte transfered */
932 message->actual_length += drv_data->len;
934 /* Move to next transfer of this msg */
935 message->state = next_transfer(drv_data);
938 /* Schedule next transfer tasklet */
939 tasklet_schedule(&drv_data->pump_transfers);
944 /* pop a msg from queue and kick off real transfer */
945 static void pump_messages(struct work_struct *work)
947 struct driver_data *drv_data;
950 drv_data = container_of(work, struct driver_data, pump_messages);
952 /* Lock queue and check for queue work */
953 spin_lock_irqsave(&drv_data->lock, flags);
954 if (list_empty(&drv_data->queue) || drv_data->run == QUEUE_STOPPED) {
955 /* pumper kicked off but no work to do */
957 spin_unlock_irqrestore(&drv_data->lock, flags);
961 /* Make sure we are not already running a message */
962 if (drv_data->cur_msg) {
963 spin_unlock_irqrestore(&drv_data->lock, flags);
967 /* Extract head of queue */
968 drv_data->cur_msg = list_entry(drv_data->queue.next,
969 struct spi_message, queue);
971 /* Setup the SSP using the per chip configuration */
972 drv_data->cur_chip = spi_get_ctldata(drv_data->cur_msg->spi);
973 restore_state(drv_data);
975 list_del_init(&drv_data->cur_msg->queue);
977 /* Initial message state */
978 drv_data->cur_msg->state = START_STATE;
979 drv_data->cur_transfer = list_entry(drv_data->cur_msg->transfers.next,
980 struct spi_transfer, transfer_list);
982 dev_dbg(&drv_data->pdev->dev, "got a message to pump, "
983 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
984 drv_data->cur_chip->baud, drv_data->cur_chip->flag,
985 drv_data->cur_chip->ctl_reg);
987 dev_dbg(&drv_data->pdev->dev,
988 "the first transfer len is %d\n",
989 drv_data->cur_transfer->len);
991 /* Mark as busy and launch transfers */
992 tasklet_schedule(&drv_data->pump_transfers);
995 spin_unlock_irqrestore(&drv_data->lock, flags);
999 * got a msg to transfer, queue it in drv_data->queue.
1000 * And kick off message pumper
1002 static int transfer(struct spi_device *spi, struct spi_message *msg)
1004 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1005 unsigned long flags;
1007 spin_lock_irqsave(&drv_data->lock, flags);
1009 if (drv_data->run == QUEUE_STOPPED) {
1010 spin_unlock_irqrestore(&drv_data->lock, flags);
1014 msg->actual_length = 0;
1015 msg->status = -EINPROGRESS;
1016 msg->state = START_STATE;
1018 dev_dbg(&spi->dev, "adding an msg in transfer() \n");
1019 list_add_tail(&msg->queue, &drv_data->queue);
1021 if (drv_data->run == QUEUE_RUNNING && !drv_data->busy)
1022 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1024 spin_unlock_irqrestore(&drv_data->lock, flags);
1029 #define MAX_SPI_SSEL 7
1031 static u16 ssel[3][MAX_SPI_SSEL] = {
1032 {P_SPI0_SSEL1, P_SPI0_SSEL2, P_SPI0_SSEL3,
1033 P_SPI0_SSEL4, P_SPI0_SSEL5,
1034 P_SPI0_SSEL6, P_SPI0_SSEL7},
1036 {P_SPI1_SSEL1, P_SPI1_SSEL2, P_SPI1_SSEL3,
1037 P_SPI1_SSEL4, P_SPI1_SSEL5,
1038 P_SPI1_SSEL6, P_SPI1_SSEL7},
1040 {P_SPI2_SSEL1, P_SPI2_SSEL2, P_SPI2_SSEL3,
1041 P_SPI2_SSEL4, P_SPI2_SSEL5,
1042 P_SPI2_SSEL6, P_SPI2_SSEL7},
1045 /* first setup for new devices */
1046 static int setup(struct spi_device *spi)
1048 struct bfin5xx_spi_chip *chip_info = NULL;
1049 struct chip_data *chip;
1050 struct driver_data *drv_data = spi_master_get_devdata(spi->master);
1053 /* Abort device setup if requested features are not supported */
1054 if (spi->mode & ~(SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST)) {
1055 dev_err(&spi->dev, "requested mode not fully supported\n");
1059 /* Zero (the default) here means 8 bits */
1060 if (!spi->bits_per_word)
1061 spi->bits_per_word = 8;
1063 if (spi->bits_per_word != 8 && spi->bits_per_word != 16)
1066 /* Only alloc (or use chip_info) on first setup */
1067 chip = spi_get_ctldata(spi);
1069 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
1073 chip->enable_dma = 0;
1074 chip_info = spi->controller_data;
1077 /* chip_info isn't always needed */
1079 /* Make sure people stop trying to set fields via ctl_reg
1080 * when they should actually be using common SPI framework.
1081 * Currently we let through: WOM EMISO PSSE GM SZ TIMOD.
1082 * Not sure if a user actually needs/uses any of these,
1083 * but let's assume (for now) they do.
1085 if (chip_info->ctl_reg & (SPE|MSTR|CPOL|CPHA|LSBF|SIZE)) {
1086 dev_err(&spi->dev, "do not set bits in ctl_reg "
1087 "that the SPI framework manages\n");
1091 chip->enable_dma = chip_info->enable_dma != 0
1092 && drv_data->master_info->enable_dma;
1093 chip->ctl_reg = chip_info->ctl_reg;
1094 chip->bits_per_word = chip_info->bits_per_word;
1095 chip->cs_change_per_word = chip_info->cs_change_per_word;
1096 chip->cs_chg_udelay = chip_info->cs_chg_udelay;
1099 /* translate common spi framework into our register */
1100 if (spi->mode & SPI_CPOL)
1101 chip->ctl_reg |= CPOL;
1102 if (spi->mode & SPI_CPHA)
1103 chip->ctl_reg |= CPHA;
1104 if (spi->mode & SPI_LSB_FIRST)
1105 chip->ctl_reg |= LSBF;
1106 /* we dont support running in slave mode (yet?) */
1107 chip->ctl_reg |= MSTR;
1110 * if any one SPI chip is registered and wants DMA, request the
1111 * DMA channel for it
1113 if (chip->enable_dma && !drv_data->dma_requested) {
1114 /* register dma irq handler */
1115 if (request_dma(drv_data->dma_channel, "BF53x_SPI_DMA") < 0) {
1117 "Unable to request BlackFin SPI DMA channel\n");
1120 if (set_dma_callback(drv_data->dma_channel,
1121 (void *)dma_irq_handler, drv_data) < 0) {
1122 dev_dbg(&spi->dev, "Unable to set dma callback\n");
1125 dma_disable_irq(drv_data->dma_channel);
1126 drv_data->dma_requested = 1;
1130 * Notice: for blackfin, the speed_hz is the value of register
1131 * SPI_BAUD, not the real baudrate
1133 chip->baud = hz_to_spi_baud(spi->max_speed_hz);
1134 spi_flg = ~(1 << (spi->chip_select));
1135 chip->flag = ((u16) spi_flg << 8) | (1 << (spi->chip_select));
1136 chip->chip_select_num = spi->chip_select;
1138 switch (chip->bits_per_word) {
1141 chip->width = CFG_SPI_WORDSIZE8;
1142 chip->read = chip->cs_change_per_word ?
1143 u8_cs_chg_reader : u8_reader;
1144 chip->write = chip->cs_change_per_word ?
1145 u8_cs_chg_writer : u8_writer;
1146 chip->duplex = chip->cs_change_per_word ?
1147 u8_cs_chg_duplex : u8_duplex;
1152 chip->width = CFG_SPI_WORDSIZE16;
1153 chip->read = chip->cs_change_per_word ?
1154 u16_cs_chg_reader : u16_reader;
1155 chip->write = chip->cs_change_per_word ?
1156 u16_cs_chg_writer : u16_writer;
1157 chip->duplex = chip->cs_change_per_word ?
1158 u16_cs_chg_duplex : u16_duplex;
1162 dev_err(&spi->dev, "%d bits_per_word is not supported\n",
1163 chip->bits_per_word);
1168 dev_dbg(&spi->dev, "setup spi chip %s, width is %d, dma is %d\n",
1169 spi->modalias, chip->width, chip->enable_dma);
1170 dev_dbg(&spi->dev, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1171 chip->ctl_reg, chip->flag);
1173 spi_set_ctldata(spi, chip);
1175 dev_dbg(&spi->dev, "chip select number is %d\n", chip->chip_select_num);
1176 if ((chip->chip_select_num > 0)
1177 && (chip->chip_select_num <= spi->master->num_chipselect))
1178 peripheral_request(ssel[spi->master->bus_num]
1179 [chip->chip_select_num-1], spi->modalias);
1181 cs_deactive(drv_data, chip);
1187 * callback for spi framework.
1188 * clean driver specific data
1190 static void cleanup(struct spi_device *spi)
1192 struct chip_data *chip = spi_get_ctldata(spi);
1194 if ((chip->chip_select_num > 0)
1195 && (chip->chip_select_num <= spi->master->num_chipselect))
1196 peripheral_free(ssel[spi->master->bus_num]
1197 [chip->chip_select_num-1]);
1202 static inline int init_queue(struct driver_data *drv_data)
1204 INIT_LIST_HEAD(&drv_data->queue);
1205 spin_lock_init(&drv_data->lock);
1207 drv_data->run = QUEUE_STOPPED;
1210 /* init transfer tasklet */
1211 tasklet_init(&drv_data->pump_transfers,
1212 pump_transfers, (unsigned long)drv_data);
1214 /* init messages workqueue */
1215 INIT_WORK(&drv_data->pump_messages, pump_messages);
1216 drv_data->workqueue =
1217 create_singlethread_workqueue(drv_data->master->dev.parent->bus_id);
1218 if (drv_data->workqueue == NULL)
1224 static inline int start_queue(struct driver_data *drv_data)
1226 unsigned long flags;
1228 spin_lock_irqsave(&drv_data->lock, flags);
1230 if (drv_data->run == QUEUE_RUNNING || drv_data->busy) {
1231 spin_unlock_irqrestore(&drv_data->lock, flags);
1235 drv_data->run = QUEUE_RUNNING;
1236 drv_data->cur_msg = NULL;
1237 drv_data->cur_transfer = NULL;
1238 drv_data->cur_chip = NULL;
1239 spin_unlock_irqrestore(&drv_data->lock, flags);
1241 queue_work(drv_data->workqueue, &drv_data->pump_messages);
1246 static inline int stop_queue(struct driver_data *drv_data)
1248 unsigned long flags;
1249 unsigned limit = 500;
1252 spin_lock_irqsave(&drv_data->lock, flags);
1255 * This is a bit lame, but is optimized for the common execution path.
1256 * A wait_queue on the drv_data->busy could be used, but then the common
1257 * execution path (pump_messages) would be required to call wake_up or
1258 * friends on every SPI message. Do this instead
1260 drv_data->run = QUEUE_STOPPED;
1261 while (!list_empty(&drv_data->queue) && drv_data->busy && limit--) {
1262 spin_unlock_irqrestore(&drv_data->lock, flags);
1264 spin_lock_irqsave(&drv_data->lock, flags);
1267 if (!list_empty(&drv_data->queue) || drv_data->busy)
1270 spin_unlock_irqrestore(&drv_data->lock, flags);
1275 static inline int destroy_queue(struct driver_data *drv_data)
1279 status = stop_queue(drv_data);
1283 destroy_workqueue(drv_data->workqueue);
1288 static int __init bfin5xx_spi_probe(struct platform_device *pdev)
1290 struct device *dev = &pdev->dev;
1291 struct bfin5xx_spi_master *platform_info;
1292 struct spi_master *master;
1293 struct driver_data *drv_data = 0;
1294 struct resource *res;
1297 platform_info = dev->platform_data;
1299 /* Allocate master with space for drv_data */
1300 master = spi_alloc_master(dev, sizeof(struct driver_data) + 16);
1302 dev_err(&pdev->dev, "can not alloc spi_master\n");
1306 drv_data = spi_master_get_devdata(master);
1307 drv_data->master = master;
1308 drv_data->master_info = platform_info;
1309 drv_data->pdev = pdev;
1310 drv_data->pin_req = platform_info->pin_req;
1312 master->bus_num = pdev->id;
1313 master->num_chipselect = platform_info->num_chipselect;
1314 master->cleanup = cleanup;
1315 master->setup = setup;
1316 master->transfer = transfer;
1318 /* Find and map our resources */
1319 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1321 dev_err(dev, "Cannot get IORESOURCE_MEM\n");
1323 goto out_error_get_res;
1326 drv_data->regs_base = ioremap(res->start, (res->end - res->start + 1));
1327 if (drv_data->regs_base == NULL) {
1328 dev_err(dev, "Cannot map IO\n");
1330 goto out_error_ioremap;
1333 drv_data->dma_channel = platform_get_irq(pdev, 0);
1334 if (drv_data->dma_channel < 0) {
1335 dev_err(dev, "No DMA channel specified\n");
1337 goto out_error_no_dma_ch;
1340 /* Initial and start queue */
1341 status = init_queue(drv_data);
1343 dev_err(dev, "problem initializing queue\n");
1344 goto out_error_queue_alloc;
1347 status = start_queue(drv_data);
1349 dev_err(dev, "problem starting queue\n");
1350 goto out_error_queue_alloc;
1353 /* Register with the SPI framework */
1354 platform_set_drvdata(pdev, drv_data);
1355 status = spi_register_master(master);
1357 dev_err(dev, "problem registering spi master\n");
1358 goto out_error_queue_alloc;
1361 status = peripheral_request_list(drv_data->pin_req, DRV_NAME);
1363 dev_err(&pdev->dev, ": Requesting Peripherals failed\n");
1367 dev_info(dev, "%s, Version %s, regs_base@%p, dma channel@%d\n",
1368 DRV_DESC, DRV_VERSION, drv_data->regs_base,
1369 drv_data->dma_channel);
1372 out_error_queue_alloc:
1373 destroy_queue(drv_data);
1374 out_error_no_dma_ch:
1375 iounmap((void *) drv_data->regs_base);
1379 spi_master_put(master);
1384 /* stop hardware and remove the driver */
1385 static int __devexit bfin5xx_spi_remove(struct platform_device *pdev)
1387 struct driver_data *drv_data = platform_get_drvdata(pdev);
1393 /* Remove the queue */
1394 status = destroy_queue(drv_data);
1398 /* Disable the SSP at the peripheral and SOC level */
1399 bfin_spi_disable(drv_data);
1402 if (drv_data->master_info->enable_dma) {
1403 if (dma_channel_active(drv_data->dma_channel))
1404 free_dma(drv_data->dma_channel);
1407 /* Disconnect from the SPI framework */
1408 spi_unregister_master(drv_data->master);
1410 peripheral_free_list(drv_data->pin_req);
1412 /* Prevent double remove */
1413 platform_set_drvdata(pdev, NULL);
1419 static int bfin5xx_spi_suspend(struct platform_device *pdev, pm_message_t state)
1421 struct driver_data *drv_data = platform_get_drvdata(pdev);
1424 status = stop_queue(drv_data);
1429 bfin_spi_disable(drv_data);
1434 static int bfin5xx_spi_resume(struct platform_device *pdev)
1436 struct driver_data *drv_data = platform_get_drvdata(pdev);
1439 /* Enable the SPI interface */
1440 bfin_spi_enable(drv_data);
1442 /* Start the queue running */
1443 status = start_queue(drv_data);
1445 dev_err(&pdev->dev, "problem starting queue (%d)\n", status);
1452 #define bfin5xx_spi_suspend NULL
1453 #define bfin5xx_spi_resume NULL
1454 #endif /* CONFIG_PM */
1456 MODULE_ALIAS("bfin-spi-master"); /* for platform bus hotplug */
1457 static struct platform_driver bfin5xx_spi_driver = {
1460 .owner = THIS_MODULE,
1462 .suspend = bfin5xx_spi_suspend,
1463 .resume = bfin5xx_spi_resume,
1464 .remove = __devexit_p(bfin5xx_spi_remove),
1467 static int __init bfin5xx_spi_init(void)
1469 return platform_driver_probe(&bfin5xx_spi_driver, bfin5xx_spi_probe);
1471 module_init(bfin5xx_spi_init);
1473 static void __exit bfin5xx_spi_exit(void)
1475 platform_driver_unregister(&bfin5xx_spi_driver);
1477 module_exit(bfin5xx_spi_exit);