err.no Git - linux-2.6/blob - drivers/spi/omap2_mcspi.c

   1 /*
   2  * OMAP2 McSPI controller driver
   3  *
   4  * Copyright (C) 2005, 2006 Nokia Corporation
   5  * Author:      Samuel Ortiz <samuel.ortiz@nokia.com> and
   6  *              Juha Yrjölä <juha.yrjola@nokia.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21  *
  22  */
  23
  24 #include <linux/kernel.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/module.h>
  28 #include <linux/device.h>
  29 #include <linux/delay.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/platform_device.h>
  32 #include <linux/err.h>
  33 #include <linux/clk.h>
  34 #include <linux/io.h>
  35
  36 #include <linux/spi/spi.h>
  37
  38 #include <asm/arch/dma.h>
  39 #include <asm/arch/clock.h>
  40
  41
  42 #define OMAP2_MCSPI_MAX_FREQ            48000000
  43
  44 #define OMAP2_MCSPI_REVISION            0x00
  45 #define OMAP2_MCSPI_SYSCONFIG           0x10
  46 #define OMAP2_MCSPI_SYSSTATUS           0x14
  47 #define OMAP2_MCSPI_IRQSTATUS           0x18
  48 #define OMAP2_MCSPI_IRQENABLE           0x1c
  49 #define OMAP2_MCSPI_WAKEUPENABLE        0x20
  50 #define OMAP2_MCSPI_SYST                0x24
  51 #define OMAP2_MCSPI_MODULCTRL           0x28
  52
  53 /* per-channel banks, 0x14 bytes each, first is: */
  54 #define OMAP2_MCSPI_CHCONF0             0x2c
  55 #define OMAP2_MCSPI_CHSTAT0             0x30
  56 #define OMAP2_MCSPI_CHCTRL0             0x34
  57 #define OMAP2_MCSPI_TX0                 0x38
  58 #define OMAP2_MCSPI_RX0                 0x3c
  59
  60 /* per-register bitmasks: */
  61
  62 #define OMAP2_MCSPI_SYSCONFIG_AUTOIDLE  (1 << 0)
  63 #define OMAP2_MCSPI_SYSCONFIG_SOFTRESET (1 << 1)
  64
  65 #define OMAP2_MCSPI_SYSSTATUS_RESETDONE (1 << 0)
  66
  67 #define OMAP2_MCSPI_MODULCTRL_SINGLE    (1 << 0)
  68 #define OMAP2_MCSPI_MODULCTRL_MS        (1 << 2)
  69 #define OMAP2_MCSPI_MODULCTRL_STEST     (1 << 3)
  70
  71 #define OMAP2_MCSPI_CHCONF_PHA          (1 << 0)
  72 #define OMAP2_MCSPI_CHCONF_POL          (1 << 1)
  73 #define OMAP2_MCSPI_CHCONF_CLKD_MASK    (0x0f << 2)
  74 #define OMAP2_MCSPI_CHCONF_EPOL         (1 << 6)
  75 #define OMAP2_MCSPI_CHCONF_WL_MASK      (0x1f << 7)
  76 #define OMAP2_MCSPI_CHCONF_TRM_RX_ONLY  (0x01 << 12)
  77 #define OMAP2_MCSPI_CHCONF_TRM_TX_ONLY  (0x02 << 12)
  78 #define OMAP2_MCSPI_CHCONF_TRM_MASK     (0x03 << 12)
  79 #define OMAP2_MCSPI_CHCONF_DMAW         (1 << 14)
  80 #define OMAP2_MCSPI_CHCONF_DMAR         (1 << 15)
  81 #define OMAP2_MCSPI_CHCONF_DPE0         (1 << 16)
  82 #define OMAP2_MCSPI_CHCONF_DPE1         (1 << 17)
  83 #define OMAP2_MCSPI_CHCONF_IS           (1 << 18)
  84 #define OMAP2_MCSPI_CHCONF_TURBO        (1 << 19)
  85 #define OMAP2_MCSPI_CHCONF_FORCE        (1 << 20)
  86
  87 #define OMAP2_MCSPI_CHSTAT_RXS          (1 << 0)
  88 #define OMAP2_MCSPI_CHSTAT_TXS          (1 << 1)
  89 #define OMAP2_MCSPI_CHSTAT_EOT          (1 << 2)
  90
  91 #define OMAP2_MCSPI_CHCTRL_EN           (1 << 0)
  92
  93
  94 /* We have 2 DMA channels per CS, one for RX and one for TX */
  95 struct omap2_mcspi_dma {
  96         int dma_tx_channel;
  97         int dma_rx_channel;
  98
  99         int dma_tx_sync_dev;
 100         int dma_rx_sync_dev;
 101
 102         struct completion dma_tx_completion;
 103         struct completion dma_rx_completion;
 104 };
 105
 106 /* use PIO for small transfers, avoiding DMA setup/teardown overhead and
 107  * cache operations; better heuristics consider wordsize and bitrate.
 108  */
 109 #define DMA_MIN_BYTES                   8
 110
 111
 112 struct omap2_mcspi {
 113         struct work_struct      work;
 114         /* lock protects queue and registers */
 115         spinlock_t              lock;
 116         struct list_head        msg_queue;
 117         struct spi_master       *master;
 118         struct clk              *ick;
 119         struct clk              *fck;
 120         /* Virtual base address of the controller */
 121         void __iomem            *base;
 122         /* SPI1 has 4 channels, while SPI2 has 2 */
 123         struct omap2_mcspi_dma  *dma_channels;
 124 };
 125
 126 struct omap2_mcspi_cs {
 127         void __iomem            *base;
 128         int                     word_len;
 129 };
 130
 131 static struct workqueue_struct *omap2_mcspi_wq;
 132
 133 #define MOD_REG_BIT(val, mask, set) do { \
 134         if (set) \
 135                 val |= mask; \
 136         else \
 137                 val &= ~mask; \
 138 } while (0)
 139
 140 static inline void mcspi_write_reg(struct spi_master *master,
 141                 int idx, u32 val)
 142 {
 143         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 144
 145         __raw_writel(val, mcspi->base + idx);
 146 }
 147
 148 static inline u32 mcspi_read_reg(struct spi_master *master, int idx)
 149 {
 150         struct omap2_mcspi *mcspi = spi_master_get_devdata(master);
 151
 152         return __raw_readl(mcspi->base + idx);
 153 }
 154
 155 static inline void mcspi_write_cs_reg(const struct spi_device *spi,
 156                 int idx, u32 val)
 157 {
 158         struct omap2_mcspi_cs   *cs = spi->controller_state;
 159
 160         __raw_writel(val, cs->base +  idx);
 161 }
 162
 163 static inline u32 mcspi_read_cs_reg(const struct spi_device *spi, int idx)
 164 {
 165         struct omap2_mcspi_cs   *cs = spi->controller_state;
 166
 167         return __raw_readl(cs->base + idx);
 168 }
 169
 170 static void omap2_mcspi_set_dma_req(const struct spi_device *spi,
 171                 int is_read, int enable)
 172 {
 173         u32 l, rw;
 174
 175         l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 176
 177         if (is_read) /* 1 is read, 0 write */
 178                 rw = OMAP2_MCSPI_CHCONF_DMAR;
 179         else
 180                 rw = OMAP2_MCSPI_CHCONF_DMAW;
 181
 182         MOD_REG_BIT(l, rw, enable);
 183         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
 184 }
 185
 186 static void omap2_mcspi_set_enable(const struct spi_device *spi, int enable)
 187 {
 188         u32 l;
 189
 190         l = enable ? OMAP2_MCSPI_CHCTRL_EN : 0;
 191         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCTRL0, l);
 192 }
 193
 194 static void omap2_mcspi_force_cs(struct spi_device *spi, int cs_active)
 195 {
 196         u32 l;
 197
 198         l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 199         MOD_REG_BIT(l, OMAP2_MCSPI_CHCONF_FORCE, cs_active);
 200         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
 201 }
 202
 203 static void omap2_mcspi_set_master_mode(struct spi_master *master)
 204 {
 205         u32 l;
 206
 207         /* setup when switching from (reset default) slave mode
 208          * to single-channel master mode
 209          */
 210         l = mcspi_read_reg(master, OMAP2_MCSPI_MODULCTRL);
 211         MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_STEST, 0);
 212         MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_MS, 0);
 213         MOD_REG_BIT(l, OMAP2_MCSPI_MODULCTRL_SINGLE, 1);
 214         mcspi_write_reg(master, OMAP2_MCSPI_MODULCTRL, l);
 215 }
 216
 217 static unsigned
 218 omap2_mcspi_txrx_dma(struct spi_device *spi, struct spi_transfer *xfer)
 219 {
 220         struct omap2_mcspi      *mcspi;
 221         struct omap2_mcspi_cs   *cs = spi->controller_state;
 222         struct omap2_mcspi_dma  *mcspi_dma;
 223         unsigned int            count, c;
 224         unsigned long           base, tx_reg, rx_reg;
 225         int                     word_len, data_type, element_count;
 226         u8                      * rx;
 227         const u8                * tx;
 228
 229         mcspi = spi_master_get_devdata(spi->master);
 230         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 231
 232         count = xfer->len;
 233         c = count;
 234         word_len = cs->word_len;
 235
 236         base = (unsigned long) io_v2p(cs->base);
 237         tx_reg = base + OMAP2_MCSPI_TX0;
 238         rx_reg = base + OMAP2_MCSPI_RX0;
 239         rx = xfer->rx_buf;
 240         tx = xfer->tx_buf;
 241
 242         if (word_len <= 8) {
 243                 data_type = OMAP_DMA_DATA_TYPE_S8;
 244                 element_count = count;
 245         } else if (word_len <= 16) {
 246                 data_type = OMAP_DMA_DATA_TYPE_S16;
 247                 element_count = count >> 1;
 248         } else /* word_len <= 32 */ {
 249                 data_type = OMAP_DMA_DATA_TYPE_S32;
 250                 element_count = count >> 2;
 251         }
 252
 253         if (tx != NULL) {
 254                 omap_set_dma_transfer_params(mcspi_dma->dma_tx_channel,
 255                                 data_type, element_count, 1,
 256                                 OMAP_DMA_SYNC_ELEMENT,
 257                                 mcspi_dma->dma_tx_sync_dev, 0);
 258
 259                 omap_set_dma_dest_params(mcspi_dma->dma_tx_channel, 0,
 260                                 OMAP_DMA_AMODE_CONSTANT,
 261                                 tx_reg, 0, 0);
 262
 263                 omap_set_dma_src_params(mcspi_dma->dma_tx_channel, 0,
 264                                 OMAP_DMA_AMODE_POST_INC,
 265                                 xfer->tx_dma, 0, 0);
 266         }
 267
 268         if (rx != NULL) {
 269                 omap_set_dma_transfer_params(mcspi_dma->dma_rx_channel,
 270                                 data_type, element_count, 1,
 271                                 OMAP_DMA_SYNC_ELEMENT,
 272                                 mcspi_dma->dma_rx_sync_dev, 1);
 273
 274                 omap_set_dma_src_params(mcspi_dma->dma_rx_channel, 0,
 275                                 OMAP_DMA_AMODE_CONSTANT,
 276                                 rx_reg, 0, 0);
 277
 278                 omap_set_dma_dest_params(mcspi_dma->dma_rx_channel, 0,
 279                                 OMAP_DMA_AMODE_POST_INC,
 280                                 xfer->rx_dma, 0, 0);
 281         }
 282
 283         if (tx != NULL) {
 284                 omap_start_dma(mcspi_dma->dma_tx_channel);
 285                 omap2_mcspi_set_dma_req(spi, 0, 1);
 286         }
 287
 288         if (rx != NULL) {
 289                 omap_start_dma(mcspi_dma->dma_rx_channel);
 290                 omap2_mcspi_set_dma_req(spi, 1, 1);
 291         }
 292
 293         if (tx != NULL) {
 294                 wait_for_completion(&mcspi_dma->dma_tx_completion);
 295                 dma_unmap_single(NULL, xfer->tx_dma, count, DMA_TO_DEVICE);
 296         }
 297
 298         if (rx != NULL) {
 299                 wait_for_completion(&mcspi_dma->dma_rx_completion);
 300                 dma_unmap_single(NULL, xfer->rx_dma, count, DMA_FROM_DEVICE);
 301         }
 302         return count;
 303 }
 304
 305 static int mcspi_wait_for_reg_bit(void __iomem *reg, unsigned long bit)
 306 {
 307         unsigned long timeout;
 308
 309         timeout = jiffies + msecs_to_jiffies(1000);
 310         while (!(__raw_readl(reg) & bit)) {
 311                 if (time_after(jiffies, timeout))
 312                         return -1;
 313                 cpu_relax();
 314         }
 315         return 0;
 316 }
 317
 318 static unsigned
 319 omap2_mcspi_txrx_pio(struct spi_device *spi, struct spi_transfer *xfer)
 320 {
 321         struct omap2_mcspi      *mcspi;
 322         struct omap2_mcspi_cs   *cs = spi->controller_state;
 323         unsigned int            count, c;
 324         u32                     l;
 325         void __iomem            *base = cs->base;
 326         void __iomem            *tx_reg;
 327         void __iomem            *rx_reg;
 328         void __iomem            *chstat_reg;
 329         int                     word_len;
 330
 331         mcspi = spi_master_get_devdata(spi->master);
 332         count = xfer->len;
 333         c = count;
 334         word_len = cs->word_len;
 335
 336         l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 337         l &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
 338
 339         /* We store the pre-calculated register addresses on stack to speed
 340          * up the transfer loop. */
 341         tx_reg          = base + OMAP2_MCSPI_TX0;
 342         rx_reg          = base + OMAP2_MCSPI_RX0;
 343         chstat_reg      = base + OMAP2_MCSPI_CHSTAT0;
 344
 345         if (word_len <= 8) {
 346                 u8              *rx;
 347                 const u8        *tx;
 348
 349                 rx = xfer->rx_buf;
 350                 tx = xfer->tx_buf;
 351
 352                 do {
 353                         c -= 1;
 354                         if (tx != NULL) {
 355                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 356                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 357                                         dev_err(&spi->dev, "TXS timed out\n");
 358                                         goto out;
 359                                 }
 360 #ifdef VERBOSE
 361                                 dev_dbg(&spi->dev, "write-%d %02x\n",
 362                                                 word_len, *tx);
 363 #endif
 364                                 __raw_writel(*tx++, tx_reg);
 365                         }
 366                         if (rx != NULL) {
 367                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 368                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 369                                         dev_err(&spi->dev, "RXS timed out\n");
 370                                         goto out;
 371                                 }
 372                                 /* prevent last RX_ONLY read from triggering
 373                                  * more word i/o: switch to rx+tx
 374                                  */
 375                                 if (c == 0 && tx == NULL)
 376                                         mcspi_write_cs_reg(spi,
 377                                                         OMAP2_MCSPI_CHCONF0, l);
 378                                 *rx++ = __raw_readl(rx_reg);
 379 #ifdef VERBOSE
 380                                 dev_dbg(&spi->dev, "read-%d %02x\n",
 381                                                 word_len, *(rx - 1));
 382 #endif
 383                         }
 384                 } while (c);
 385         } else if (word_len <= 16) {
 386                 u16             *rx;
 387                 const u16       *tx;
 388
 389                 rx = xfer->rx_buf;
 390                 tx = xfer->tx_buf;
 391                 do {
 392                         c -= 2;
 393                         if (tx != NULL) {
 394                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 395                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 396                                         dev_err(&spi->dev, "TXS timed out\n");
 397                                         goto out;
 398                                 }
 399 #ifdef VERBOSE
 400                                 dev_dbg(&spi->dev, "write-%d %04x\n",
 401                                                 word_len, *tx);
 402 #endif
 403                                 __raw_writel(*tx++, tx_reg);
 404                         }
 405                         if (rx != NULL) {
 406                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 407                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 408                                         dev_err(&spi->dev, "RXS timed out\n");
 409                                         goto out;
 410                                 }
 411                                 /* prevent last RX_ONLY read from triggering
 412                                  * more word i/o: switch to rx+tx
 413                                  */
 414                                 if (c == 0 && tx == NULL)
 415                                         mcspi_write_cs_reg(spi,
 416                                                         OMAP2_MCSPI_CHCONF0, l);
 417                                 *rx++ = __raw_readl(rx_reg);
 418 #ifdef VERBOSE
 419                                 dev_dbg(&spi->dev, "read-%d %04x\n",
 420                                                 word_len, *(rx - 1));
 421 #endif
 422                         }
 423                 } while (c);
 424         } else if (word_len <= 32) {
 425                 u32             *rx;
 426                 const u32       *tx;
 427
 428                 rx = xfer->rx_buf;
 429                 tx = xfer->tx_buf;
 430                 do {
 431                         c -= 4;
 432                         if (tx != NULL) {
 433                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 434                                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 435                                         dev_err(&spi->dev, "TXS timed out\n");
 436                                         goto out;
 437                                 }
 438 #ifdef VERBOSE
 439                                 dev_dbg(&spi->dev, "write-%d %04x\n",
 440                                                 word_len, *tx);
 441 #endif
 442                                 __raw_writel(*tx++, tx_reg);
 443                         }
 444                         if (rx != NULL) {
 445                                 if (mcspi_wait_for_reg_bit(chstat_reg,
 446                                                 OMAP2_MCSPI_CHSTAT_RXS) < 0) {
 447                                         dev_err(&spi->dev, "RXS timed out\n");
 448                                         goto out;
 449                                 }
 450                                 /* prevent last RX_ONLY read from triggering
 451                                  * more word i/o: switch to rx+tx
 452                                  */
 453                                 if (c == 0 && tx == NULL)
 454                                         mcspi_write_cs_reg(spi,
 455                                                         OMAP2_MCSPI_CHCONF0, l);
 456                                 *rx++ = __raw_readl(rx_reg);
 457 #ifdef VERBOSE
 458                                 dev_dbg(&spi->dev, "read-%d %04x\n",
 459                                                 word_len, *(rx - 1));
 460 #endif
 461                         }
 462                 } while (c);
 463         }
 464
 465         /* for TX_ONLY mode, be sure all words have shifted out */
 466         if (xfer->rx_buf == NULL) {
 467                 if (mcspi_wait_for_reg_bit(chstat_reg,
 468                                 OMAP2_MCSPI_CHSTAT_TXS) < 0) {
 469                         dev_err(&spi->dev, "TXS timed out\n");
 470                 } else if (mcspi_wait_for_reg_bit(chstat_reg,
 471                                 OMAP2_MCSPI_CHSTAT_EOT) < 0)
 472                         dev_err(&spi->dev, "EOT timed out\n");
 473         }
 474 out:
 475         return count - c;
 476 }
 477
 478 /* called only when no transfer is active to this device */
 479 static int omap2_mcspi_setup_transfer(struct spi_device *spi,
 480                 struct spi_transfer *t)
 481 {
 482         struct omap2_mcspi_cs *cs = spi->controller_state;
 483         struct omap2_mcspi *mcspi;
 484         u32 l = 0, div = 0;
 485         u8 word_len = spi->bits_per_word;
 486
 487         mcspi = spi_master_get_devdata(spi->master);
 488
 489         if (t != NULL && t->bits_per_word)
 490                 word_len = t->bits_per_word;
 491
 492         cs->word_len = word_len;
 493
 494         if (spi->max_speed_hz) {
 495                 while (div <= 15 && (OMAP2_MCSPI_MAX_FREQ / (1 << div))
 496                                         > spi->max_speed_hz)
 497                         div++;
 498         } else
 499                 div = 15;
 500
 501         l = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 502
 503         /* standard 4-wire master mode:  SCK, MOSI/out, MISO/in, nCS
 504          * REVISIT: this controller could support SPI_3WIRE mode.
 505          */
 506         l &= ~(OMAP2_MCSPI_CHCONF_IS|OMAP2_MCSPI_CHCONF_DPE1);
 507         l |= OMAP2_MCSPI_CHCONF_DPE0;
 508
 509         /* wordlength */
 510         l &= ~OMAP2_MCSPI_CHCONF_WL_MASK;
 511         l |= (word_len - 1) << 7;
 512
 513         /* set chipselect polarity; manage with FORCE */
 514         if (!(spi->mode & SPI_CS_HIGH))
 515                 l |= OMAP2_MCSPI_CHCONF_EPOL;   /* active-low; normal */
 516         else
 517                 l &= ~OMAP2_MCSPI_CHCONF_EPOL;
 518
 519         /* set clock divisor */
 520         l &= ~OMAP2_MCSPI_CHCONF_CLKD_MASK;
 521         l |= div << 2;
 522
 523         /* set SPI mode 0..3 */
 524         if (spi->mode & SPI_CPOL)
 525                 l |= OMAP2_MCSPI_CHCONF_POL;
 526         else
 527                 l &= ~OMAP2_MCSPI_CHCONF_POL;
 528         if (spi->mode & SPI_CPHA)
 529                 l |= OMAP2_MCSPI_CHCONF_PHA;
 530         else
 531                 l &= ~OMAP2_MCSPI_CHCONF_PHA;
 532
 533         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, l);
 534
 535         dev_dbg(&spi->dev, "setup: speed %d, sample %s edge, clk %s\n",
 536                         OMAP2_MCSPI_MAX_FREQ / (1 << div),
 537                         (spi->mode & SPI_CPHA) ? "trailing" : "leading",
 538                         (spi->mode & SPI_CPOL) ? "inverted" : "normal");
 539
 540         return 0;
 541 }
 542
 543 static void omap2_mcspi_dma_rx_callback(int lch, u16 ch_status, void *data)
 544 {
 545         struct spi_device       *spi = data;
 546         struct omap2_mcspi      *mcspi;
 547         struct omap2_mcspi_dma  *mcspi_dma;
 548
 549         mcspi = spi_master_get_devdata(spi->master);
 550         mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
 551
 552         complete(&mcspi_dma->dma_rx_completion);
 553
 554         /* We must disable the DMA RX request */
 555         omap2_mcspi_set_dma_req(spi, 1, 0);
 556 }
 557
 558 static void omap2_mcspi_dma_tx_callback(int lch, u16 ch_status, void *data)
 559 {
 560         struct spi_device       *spi = data;
 561         struct omap2_mcspi      *mcspi;
 562         struct omap2_mcspi_dma  *mcspi_dma;
 563
 564         mcspi = spi_master_get_devdata(spi->master);
 565         mcspi_dma = &(mcspi->dma_channels[spi->chip_select]);
 566
 567         complete(&mcspi_dma->dma_tx_completion);
 568
 569         /* We must disable the DMA TX request */
 570         omap2_mcspi_set_dma_req(spi, 0, 0);
 571 }
 572
 573 static int omap2_mcspi_request_dma(struct spi_device *spi)
 574 {
 575         struct spi_master       *master = spi->master;
 576         struct omap2_mcspi      *mcspi;
 577         struct omap2_mcspi_dma  *mcspi_dma;
 578
 579         mcspi = spi_master_get_devdata(master);
 580         mcspi_dma = mcspi->dma_channels + spi->chip_select;
 581
 582         if (omap_request_dma(mcspi_dma->dma_rx_sync_dev, "McSPI RX",
 583                         omap2_mcspi_dma_rx_callback, spi,
 584                         &mcspi_dma->dma_rx_channel)) {
 585                 dev_err(&spi->dev, "no RX DMA channel for McSPI\n");
 586                 return -EAGAIN;
 587         }
 588
 589         if (omap_request_dma(mcspi_dma->dma_tx_sync_dev, "McSPI TX",
 590                         omap2_mcspi_dma_tx_callback, spi,
 591                         &mcspi_dma->dma_tx_channel)) {
 592                 omap_free_dma(mcspi_dma->dma_rx_channel);
 593                 mcspi_dma->dma_rx_channel = -1;
 594                 dev_err(&spi->dev, "no TX DMA channel for McSPI\n");
 595                 return -EAGAIN;
 596         }
 597
 598         init_completion(&mcspi_dma->dma_rx_completion);
 599         init_completion(&mcspi_dma->dma_tx_completion);
 600
 601         return 0;
 602 }
 603
 604 /* the spi->mode bits understood by this driver: */
 605 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH)
 606
 607 static int omap2_mcspi_setup(struct spi_device *spi)
 608 {
 609         int                     ret;
 610         struct omap2_mcspi      *mcspi;
 611         struct omap2_mcspi_dma  *mcspi_dma;
 612         struct omap2_mcspi_cs   *cs = spi->controller_state;
 613
 614         if (spi->mode & ~MODEBITS) {
 615                 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
 616                         spi->mode & ~MODEBITS);
 617                 return -EINVAL;
 618         }
 619
 620         if (spi->bits_per_word == 0)
 621                 spi->bits_per_word = 8;
 622         else if (spi->bits_per_word < 4 || spi->bits_per_word > 32) {
 623                 dev_dbg(&spi->dev, "setup: unsupported %d bit words\n",
 624                         spi->bits_per_word);
 625                 return -EINVAL;
 626         }
 627
 628         mcspi = spi_master_get_devdata(spi->master);
 629         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 630
 631         if (!cs) {
 632                 cs = kzalloc(sizeof *cs, GFP_KERNEL);
 633                 if (!cs)
 634                         return -ENOMEM;
 635                 cs->base = mcspi->base + spi->chip_select * 0x14;
 636                 spi->controller_state = cs;
 637         }
 638
 639         if (mcspi_dma->dma_rx_channel == -1
 640                         || mcspi_dma->dma_tx_channel == -1) {
 641                 ret = omap2_mcspi_request_dma(spi);
 642                 if (ret < 0)
 643                         return ret;
 644         }
 645
 646         clk_enable(mcspi->ick);
 647         clk_enable(mcspi->fck);
 648         ret = omap2_mcspi_setup_transfer(spi, NULL);
 649         clk_disable(mcspi->fck);
 650         clk_disable(mcspi->ick);
 651
 652         return ret;
 653 }
 654
 655 static void omap2_mcspi_cleanup(struct spi_device *spi)
 656 {
 657         struct omap2_mcspi      *mcspi;
 658         struct omap2_mcspi_dma  *mcspi_dma;
 659
 660         mcspi = spi_master_get_devdata(spi->master);
 661         mcspi_dma = &mcspi->dma_channels[spi->chip_select];
 662
 663         kfree(spi->controller_state);
 664
 665         if (mcspi_dma->dma_rx_channel != -1) {
 666                 omap_free_dma(mcspi_dma->dma_rx_channel);
 667                 mcspi_dma->dma_rx_channel = -1;
 668         }
 669         if (mcspi_dma->dma_tx_channel != -1) {
 670                 omap_free_dma(mcspi_dma->dma_tx_channel);
 671                 mcspi_dma->dma_tx_channel = -1;
 672         }
 673 }
 674
 675 static void omap2_mcspi_work(struct work_struct *work)
 676 {
 677         struct omap2_mcspi      *mcspi;
 678
 679         mcspi = container_of(work, struct omap2_mcspi, work);
 680         spin_lock_irq(&mcspi->lock);
 681
 682         clk_enable(mcspi->ick);
 683         clk_enable(mcspi->fck);
 684
 685         /* We only enable one channel at a time -- the one whose message is
 686          * at the head of the queue -- although this controller would gladly
 687          * arbitrate among multiple channels.  This corresponds to "single
 688          * channel" master mode.  As a side effect, we need to manage the
 689          * chipselect with the FORCE bit ... CS != channel enable.
 690          */
 691         while (!list_empty(&mcspi->msg_queue)) {
 692                 struct spi_message              *m;
 693                 struct spi_device               *spi;
 694                 struct spi_transfer             *t = NULL;
 695                 int                             cs_active = 0;
 696                 struct omap2_mcspi_cs           *cs;
 697                 int                             par_override = 0;
 698                 int                             status = 0;
 699                 u32                             chconf;
 700
 701                 m = container_of(mcspi->msg_queue.next, struct spi_message,
 702                                  queue);
 703
 704                 list_del_init(&m->queue);
 705                 spin_unlock_irq(&mcspi->lock);
 706
 707                 spi = m->spi;
 708                 cs = spi->controller_state;
 709
 710                 omap2_mcspi_set_enable(spi, 1);
 711                 list_for_each_entry(t, &m->transfers, transfer_list) {
 712                         if (t->tx_buf == NULL && t->rx_buf == NULL && t->len) {
 713                                 status = -EINVAL;
 714                                 break;
 715                         }
 716                         if (par_override || t->speed_hz || t->bits_per_word) {
 717                                 par_override = 1;
 718                                 status = omap2_mcspi_setup_transfer(spi, t);
 719                                 if (status < 0)
 720                                         break;
 721                                 if (!t->speed_hz && !t->bits_per_word)
 722                                         par_override = 0;
 723                         }
 724
 725                         if (!cs_active) {
 726                                 omap2_mcspi_force_cs(spi, 1);
 727                                 cs_active = 1;
 728                         }
 729
 730                         chconf = mcspi_read_cs_reg(spi, OMAP2_MCSPI_CHCONF0);
 731                         chconf &= ~OMAP2_MCSPI_CHCONF_TRM_MASK;
 732                         if (t->tx_buf == NULL)
 733                                 chconf |= OMAP2_MCSPI_CHCONF_TRM_RX_ONLY;
 734                         else if (t->rx_buf == NULL)
 735                                 chconf |= OMAP2_MCSPI_CHCONF_TRM_TX_ONLY;
 736                         mcspi_write_cs_reg(spi, OMAP2_MCSPI_CHCONF0, chconf);
 737
 738                         if (t->len) {
 739                                 unsigned        count;
 740
 741                                 /* RX_ONLY mode needs dummy data in TX reg */
 742                                 if (t->tx_buf == NULL)
 743                                         __raw_writel(0, cs->base
 744                                                         + OMAP2_MCSPI_TX0);
 745
 746                                 if (m->is_dma_mapped || t->len >= DMA_MIN_BYTES)
 747                                         count = omap2_mcspi_txrx_dma(spi, t);
 748                                 else
 749                                         count = omap2_mcspi_txrx_pio(spi, t);
 750                                 m->actual_length += count;
 751
 752                                 if (count != t->len) {
 753                                         status = -EIO;
 754                                         break;
 755                                 }
 756                         }
 757
 758                         if (t->delay_usecs)
 759                                 udelay(t->delay_usecs);
 760
 761                         /* ignore the "leave it on after last xfer" hint */
 762                         if (t->cs_change) {
 763                                 omap2_mcspi_force_cs(spi, 0);
 764                                 cs_active = 0;
 765                         }
 766                 }
 767
 768                 /* Restore defaults if they were overriden */
 769                 if (par_override) {
 770                         par_override = 0;
 771                         status = omap2_mcspi_setup_transfer(spi, NULL);
 772                 }
 773
 774                 if (cs_active)
 775                         omap2_mcspi_force_cs(spi, 0);
 776
 777                 omap2_mcspi_set_enable(spi, 0);
 778
 779                 m->status = status;
 780                 m->complete(m->context);
 781
 782                 spin_lock_irq(&mcspi->lock);
 783         }
 784
 785         clk_disable(mcspi->fck);
 786         clk_disable(mcspi->ick);
 787
 788         spin_unlock_irq(&mcspi->lock);
 789 }
 790
 791 static int omap2_mcspi_transfer(struct spi_device *spi, struct spi_message *m)
 792 {
 793         struct omap2_mcspi      *mcspi;
 794         unsigned long           flags;
 795         struct spi_transfer     *t;
 796
 797         m->actual_length = 0;
 798         m->status = 0;
 799
 800         /* reject invalid messages and transfers */
 801         if (list_empty(&m->transfers) || !m->complete)
 802                 return -EINVAL;
 803         list_for_each_entry(t, &m->transfers, transfer_list) {
 804                 const void      *tx_buf = t->tx_buf;
 805                 void            *rx_buf = t->rx_buf;
 806                 unsigned        len = t->len;
 807
 808                 if (t->speed_hz > OMAP2_MCSPI_MAX_FREQ
 809                                 || (len && !(rx_buf || tx_buf))
 810                                 || (t->bits_per_word &&
 811                                         (  t->bits_per_word < 4
 812                                         || t->bits_per_word > 32))) {
 813                         dev_dbg(&spi->dev, "transfer: %d Hz, %d %s%s, %d bpw\n",
 814                                         t->speed_hz,
 815                                         len,
 816                                         tx_buf ? "tx" : "",
 817                                         rx_buf ? "rx" : "",
 818                                         t->bits_per_word);
 819                         return -EINVAL;
 820                 }
 821                 if (t->speed_hz && t->speed_hz < OMAP2_MCSPI_MAX_FREQ/(1<<16)) {
 822                         dev_dbg(&spi->dev, "%d Hz max exceeds %d\n",
 823                                         t->speed_hz,
 824                                         OMAP2_MCSPI_MAX_FREQ/(1<<16));
 825                         return -EINVAL;
 826                 }
 827
 828                 if (m->is_dma_mapped || len < DMA_MIN_BYTES)
 829                         continue;
 830
 831                 /* Do DMA mapping "early" for better error reporting and
 832                  * dcache use.  Note that if dma_unmap_single() ever starts
 833                  * to do real work on ARM, we'd need to clean up mappings
 834                  * for previous transfers on *ALL* exits of this loop...
 835                  */
 836                 if (tx_buf != NULL) {
 837                         t->tx_dma = dma_map_single(&spi->dev, (void *) tx_buf,
 838                                         len, DMA_TO_DEVICE);
 839                         if (dma_mapping_error(&spi->dev, t->tx_dma)) {
 840                                 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
 841                                                 'T', len);
 842                                 return -EINVAL;
 843                         }
 844                 }
 845                 if (rx_buf != NULL) {
 846                         t->rx_dma = dma_map_single(&spi->dev, rx_buf, t->len,
 847                                         DMA_FROM_DEVICE);
 848                         if (dma_mapping_error(&spi->dev, t->rx_dma)) {
 849                                 dev_dbg(&spi->dev, "dma %cX %d bytes error\n",
 850                                                 'R', len);
 851                                 if (tx_buf != NULL)
 852                                         dma_unmap_single(NULL, t->tx_dma,
 853                                                         len, DMA_TO_DEVICE);
 854                                 return -EINVAL;
 855                         }
 856                 }
 857         }
 858
 859         mcspi = spi_master_get_devdata(spi->master);
 860
 861         spin_lock_irqsave(&mcspi->lock, flags);
 862         list_add_tail(&m->queue, &mcspi->msg_queue);
 863         queue_work(omap2_mcspi_wq, &mcspi->work);
 864         spin_unlock_irqrestore(&mcspi->lock, flags);
 865
 866         return 0;
 867 }
 868
 869 static int __init omap2_mcspi_reset(struct omap2_mcspi *mcspi)
 870 {
 871         struct spi_master       *master = mcspi->master;
 872         u32                     tmp;
 873
 874         clk_enable(mcspi->ick);
 875         clk_enable(mcspi->fck);
 876
 877         mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
 878                         OMAP2_MCSPI_SYSCONFIG_SOFTRESET);
 879         do {
 880                 tmp = mcspi_read_reg(master, OMAP2_MCSPI_SYSSTATUS);
 881         } while (!(tmp & OMAP2_MCSPI_SYSSTATUS_RESETDONE));
 882
 883         mcspi_write_reg(master, OMAP2_MCSPI_SYSCONFIG,
 884                         /* (3 << 8) | (2 << 3) | */
 885                         OMAP2_MCSPI_SYSCONFIG_AUTOIDLE);
 886
 887         omap2_mcspi_set_master_mode(master);
 888
 889         clk_disable(mcspi->fck);
 890         clk_disable(mcspi->ick);
 891         return 0;
 892 }
 893
 894 static u8 __initdata spi1_rxdma_id [] = {
 895         OMAP24XX_DMA_SPI1_RX0,
 896         OMAP24XX_DMA_SPI1_RX1,
 897         OMAP24XX_DMA_SPI1_RX2,
 898         OMAP24XX_DMA_SPI1_RX3,
 899 };
 900
 901 static u8 __initdata spi1_txdma_id [] = {
 902         OMAP24XX_DMA_SPI1_TX0,
 903         OMAP24XX_DMA_SPI1_TX1,
 904         OMAP24XX_DMA_SPI1_TX2,
 905         OMAP24XX_DMA_SPI1_TX3,
 906 };
 907
 908 static u8 __initdata spi2_rxdma_id[] = {
 909         OMAP24XX_DMA_SPI2_RX0,
 910         OMAP24XX_DMA_SPI2_RX1,
 911 };
 912
 913 static u8 __initdata spi2_txdma_id[] = {
 914         OMAP24XX_DMA_SPI2_TX0,
 915         OMAP24XX_DMA_SPI2_TX1,
 916 };
 917
 918 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP34XX)
 919 static u8 __initdata spi3_rxdma_id[] = {
 920         OMAP24XX_DMA_SPI3_RX0,
 921         OMAP24XX_DMA_SPI3_RX1,
 922 };
 923
 924 static u8 __initdata spi3_txdma_id[] = {
 925         OMAP24XX_DMA_SPI3_TX0,
 926         OMAP24XX_DMA_SPI3_TX1,
 927 };
 928 #endif
 929
 930 #ifdef CONFIG_ARCH_OMAP3
 931 static u8 __initdata spi4_rxdma_id[] = {
 932         OMAP34XX_DMA_SPI4_RX0,
 933 };
 934
 935 static u8 __initdata spi4_txdma_id[] = {
 936         OMAP34XX_DMA_SPI4_TX0,
 937 };
 938 #endif
 939
 940 static int __init omap2_mcspi_probe(struct platform_device *pdev)
 941 {
 942         struct spi_master       *master;
 943         struct omap2_mcspi      *mcspi;
 944         struct resource         *r;
 945         int                     status = 0, i;
 946         const u8                *rxdma_id, *txdma_id;
 947         unsigned                num_chipselect;
 948
 949         switch (pdev->id) {
 950         case 1:
 951                 rxdma_id = spi1_rxdma_id;
 952                 txdma_id = spi1_txdma_id;
 953                 num_chipselect = 4;
 954                 break;
 955         case 2:
 956                 rxdma_id = spi2_rxdma_id;
 957                 txdma_id = spi2_txdma_id;
 958                 num_chipselect = 2;
 959                 break;
 960 #if defined(CONFIG_ARCH_OMAP2430) || defined(CONFIG_ARCH_OMAP3)
 961         case 3:
 962                 rxdma_id = spi3_rxdma_id;
 963                 txdma_id = spi3_txdma_id;
 964                 num_chipselect = 2;
 965                 break;
 966 #endif
 967 #ifdef CONFIG_ARCH_OMAP3
 968         case 4:
 969                 rxdma_id = spi4_rxdma_id;
 970                 txdma_id = spi4_txdma_id;
 971                 num_chipselect = 1;
 972                 break;
 973 #endif
 974         default:
 975                 return -EINVAL;
 976         }
 977
 978         master = spi_alloc_master(&pdev->dev, sizeof *mcspi);
 979         if (master == NULL) {
 980                 dev_dbg(&pdev->dev, "master allocation failed\n");
 981                 return -ENOMEM;
 982         }
 983
 984         if (pdev->id != -1)
 985                 master->bus_num = pdev->id;
 986
 987         master->setup = omap2_mcspi_setup;
 988         master->transfer = omap2_mcspi_transfer;
 989         master->cleanup = omap2_mcspi_cleanup;
 990         master->num_chipselect = num_chipselect;
 991
 992         dev_set_drvdata(&pdev->dev, master);
 993
 994         mcspi = spi_master_get_devdata(master);
 995         mcspi->master = master;
 996
 997         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 998         if (r == NULL) {
 999                 status = -ENODEV;
1000                 goto err1;
1001         }
1002         if (!request_mem_region(r->start, (r->end - r->start) + 1,
1003                         pdev->dev.bus_id)) {
1004                 status = -EBUSY;
1005                 goto err1;
1006         }
1007
1008         mcspi->base = (void __iomem *) io_p2v(r->start);
1009
1010         INIT_WORK(&mcspi->work, omap2_mcspi_work);
1011
1012         spin_lock_init(&mcspi->lock);
1013         INIT_LIST_HEAD(&mcspi->msg_queue);
1014
1015         mcspi->ick = clk_get(&pdev->dev, "mcspi_ick");
1016         if (IS_ERR(mcspi->ick)) {
1017                 dev_dbg(&pdev->dev, "can't get mcspi_ick\n");
1018                 status = PTR_ERR(mcspi->ick);
1019                 goto err1a;
1020         }
1021         mcspi->fck = clk_get(&pdev->dev, "mcspi_fck");
1022         if (IS_ERR(mcspi->fck)) {
1023                 dev_dbg(&pdev->dev, "can't get mcspi_fck\n");
1024                 status = PTR_ERR(mcspi->fck);
1025                 goto err2;
1026         }
1027
1028         mcspi->dma_channels = kcalloc(master->num_chipselect,
1029                         sizeof(struct omap2_mcspi_dma),
1030                         GFP_KERNEL);
1031
1032         if (mcspi->dma_channels == NULL)
1033                 goto err3;
1034
1035         for (i = 0; i < num_chipselect; i++) {
1036                 mcspi->dma_channels[i].dma_rx_channel = -1;
1037                 mcspi->dma_channels[i].dma_rx_sync_dev = rxdma_id[i];
1038                 mcspi->dma_channels[i].dma_tx_channel = -1;
1039                 mcspi->dma_channels[i].dma_tx_sync_dev = txdma_id[i];
1040         }
1041
1042         if (omap2_mcspi_reset(mcspi) < 0)
1043                 goto err4;
1044
1045         status = spi_register_master(master);
1046         if (status < 0)
1047                 goto err4;
1048
1049         return status;
1050
1051 err4:
1052         kfree(mcspi->dma_channels);
1053 err3:
1054         clk_put(mcspi->fck);
1055 err2:
1056         clk_put(mcspi->ick);
1057 err1a:
1058         release_mem_region(r->start, (r->end - r->start) + 1);
1059 err1:
1060         spi_master_put(master);
1061         return status;
1062 }
1063
1064 static int __exit omap2_mcspi_remove(struct platform_device *pdev)
1065 {
1066         struct spi_master       *master;
1067         struct omap2_mcspi      *mcspi;
1068         struct omap2_mcspi_dma  *dma_channels;
1069         struct resource         *r;
1070
1071         master = dev_get_drvdata(&pdev->dev);
1072         mcspi = spi_master_get_devdata(master);
1073         dma_channels = mcspi->dma_channels;
1074
1075         clk_put(mcspi->fck);
1076         clk_put(mcspi->ick);
1077
1078         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1079         release_mem_region(r->start, (r->end - r->start) + 1);
1080
1081         spi_unregister_master(master);
1082         kfree(dma_channels);
1083
1084         return 0;
1085 }
1086
1087 /* work with hotplug and coldplug */
1088 MODULE_ALIAS("platform:omap2_mcspi");
1089
1090 static struct platform_driver omap2_mcspi_driver = {
1091         .driver = {
1092                 .name =         "omap2_mcspi",
1093                 .owner =        THIS_MODULE,
1094         },
1095         .remove =       __exit_p(omap2_mcspi_remove),
1096 };
1097
1098
1099 static int __init omap2_mcspi_init(void)
1100 {
1101         omap2_mcspi_wq = create_singlethread_workqueue(
1102                                 omap2_mcspi_driver.driver.name);
1103         if (omap2_mcspi_wq == NULL)
1104                 return -1;
1105         return platform_driver_probe(&omap2_mcspi_driver, omap2_mcspi_probe);
1106 }
1107 subsys_initcall(omap2_mcspi_init);
1108
1109 static void __exit omap2_mcspi_exit(void)
1110 {
1111         platform_driver_unregister(&omap2_mcspi_driver);
1112
1113         destroy_workqueue(omap2_mcspi_wq);
1114 }
1115 module_exit(omap2_mcspi_exit);
1116
1117 MODULE_LICENSE("GPL");