err.no Git - linux-2.6/blob - drivers/spi/au1550_spi.c

   1 /*
   2  * au1550_spi.c - au1550 psc spi controller driver
   3  * may work also with au1200, au1210, au1250
   4  * will not work on au1000, au1100 and au1500 (no full spi controller there)
   5  *
   6  * Copyright (c) 2006 ATRON electronic GmbH
   7  * Author: Jan Nikitenko <jan.nikitenko@gmail.com>
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License as published by
  11  * the Free Software Foundation; either version 2 of the License, or
  12  * (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  22  */
  23
  24 #include <linux/init.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/errno.h>
  27 #include <linux/device.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/resource.h>
  30 #include <linux/spi/spi.h>
  31 #include <linux/spi/spi_bitbang.h>
  32 #include <linux/dma-mapping.h>
  33 #include <linux/completion.h>
  34 #include <asm/mach-au1x00/au1000.h>
  35 #include <asm/mach-au1x00/au1xxx_psc.h>
  36 #include <asm/mach-au1x00/au1xxx_dbdma.h>
  37
  38 #include <asm/mach-au1x00/au1550_spi.h>
  39
  40 static unsigned usedma = 1;
  41 module_param(usedma, uint, 0644);
  42
  43 /*
  44 #define AU1550_SPI_DEBUG_LOOPBACK
  45 */
  46
  47
  48 #define AU1550_SPI_DBDMA_DESCRIPTORS 1
  49 #define AU1550_SPI_DMA_RXTMP_MINSIZE 2048U
  50
  51 struct au1550_spi {
  52         struct spi_bitbang bitbang;
  53
  54         volatile psc_spi_t __iomem *regs;
  55         int irq;
  56         unsigned freq_max;
  57         unsigned freq_min;
  58
  59         unsigned len;
  60         unsigned tx_count;
  61         unsigned rx_count;
  62         const u8 *tx;
  63         u8 *rx;
  64
  65         void (*rx_word)(struct au1550_spi *hw);
  66         void (*tx_word)(struct au1550_spi *hw);
  67         int (*txrx_bufs)(struct spi_device *spi, struct spi_transfer *t);
  68         irqreturn_t (*irq_callback)(struct au1550_spi *hw);
  69
  70         struct completion master_done;
  71
  72         unsigned usedma;
  73         u32 dma_tx_id;
  74         u32 dma_rx_id;
  75         u32 dma_tx_ch;
  76         u32 dma_rx_ch;
  77
  78         u8 *dma_rx_tmpbuf;
  79         unsigned dma_rx_tmpbuf_size;
  80         u32 dma_rx_tmpbuf_addr;
  81
  82         struct spi_master *master;
  83         struct device *dev;
  84         struct au1550_spi_info *pdata;
  85         struct resource *ioarea;
  86 };
  87
  88
  89 /* we use an 8-bit memory device for dma transfers to/from spi fifo */
  90 static dbdev_tab_t au1550_spi_mem_dbdev =
  91 {
  92         .dev_id                 = DBDMA_MEM_CHAN,
  93         .dev_flags              = DEV_FLAGS_ANYUSE|DEV_FLAGS_SYNC,
  94         .dev_tsize              = 0,
  95         .dev_devwidth           = 8,
  96         .dev_physaddr           = 0x00000000,
  97         .dev_intlevel           = 0,
  98         .dev_intpolarity        = 0
  99 };
 100
 101 static int ddma_memid;  /* id to above mem dma device */
 102
 103 static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw);
 104
 105
 106 /*
 107  *  compute BRG and DIV bits to setup spi clock based on main input clock rate
 108  *  that was specified in platform data structure
 109  *  according to au1550 datasheet:
 110  *    psc_tempclk = psc_mainclk / (2 << DIV)
 111  *    spiclk = psc_tempclk / (2 * (BRG + 1))
 112  *    BRG valid range is 4..63
 113  *    DIV valid range is 0..3
 114  */
 115 static u32 au1550_spi_baudcfg(struct au1550_spi *hw, unsigned speed_hz)
 116 {
 117         u32 mainclk_hz = hw->pdata->mainclk_hz;
 118         u32 div, brg;
 119
 120         for (div = 0; div < 4; div++) {
 121                 brg = mainclk_hz / speed_hz / (4 << div);
 122                 /* now we have BRG+1 in brg, so count with that */
 123                 if (brg < (4 + 1)) {
 124                         brg = (4 + 1);  /* speed_hz too big */
 125                         break;          /* set lowest brg (div is == 0) */
 126                 }
 127                 if (brg <= (63 + 1))
 128                         break;          /* we have valid brg and div */
 129         }
 130         if (div == 4) {
 131                 div = 3;                /* speed_hz too small */
 132                 brg = (63 + 1);         /* set highest brg and div */
 133         }
 134         brg--;
 135         return PSC_SPICFG_SET_BAUD(brg) | PSC_SPICFG_SET_DIV(div);
 136 }
 137
 138 static inline void au1550_spi_mask_ack_all(struct au1550_spi *hw)
 139 {
 140         hw->regs->psc_spimsk =
 141                   PSC_SPIMSK_MM | PSC_SPIMSK_RR | PSC_SPIMSK_RO
 142                 | PSC_SPIMSK_RU | PSC_SPIMSK_TR | PSC_SPIMSK_TO
 143                 | PSC_SPIMSK_TU | PSC_SPIMSK_SD | PSC_SPIMSK_MD;
 144         au_sync();
 145
 146         hw->regs->psc_spievent =
 147                   PSC_SPIEVNT_MM | PSC_SPIEVNT_RR | PSC_SPIEVNT_RO
 148                 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TR | PSC_SPIEVNT_TO
 149                 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD | PSC_SPIEVNT_MD;
 150         au_sync();
 151 }
 152
 153 static void au1550_spi_reset_fifos(struct au1550_spi *hw)
 154 {
 155         u32 pcr;
 156
 157         hw->regs->psc_spipcr = PSC_SPIPCR_RC | PSC_SPIPCR_TC;
 158         au_sync();
 159         do {
 160                 pcr = hw->regs->psc_spipcr;
 161                 au_sync();
 162         } while (pcr != 0);
 163 }
 164
 165 /*
 166  * dma transfers are used for the most common spi word size of 8-bits
 167  * we cannot easily change already set up dma channels' width, so if we wanted
 168  * dma support for more than 8-bit words (up to 24 bits), we would need to
 169  * setup dma channels from scratch on each spi transfer, based on bits_per_word
 170  * instead we have pre set up 8 bit dma channels supporting spi 4 to 8 bits
 171  * transfers, and 9 to 24 bits spi transfers will be done in pio irq based mode
 172  * callbacks to handle dma or pio are set up in au1550_spi_bits_handlers_set()
 173  */
 174 static void au1550_spi_chipsel(struct spi_device *spi, int value)
 175 {
 176         struct au1550_spi *hw = spi_master_get_devdata(spi->master);
 177         unsigned cspol = spi->mode & SPI_CS_HIGH ? 1 : 0;
 178         u32 cfg, stat;
 179
 180         switch (value) {
 181         case BITBANG_CS_INACTIVE:
 182                 if (hw->pdata->deactivate_cs)
 183                         hw->pdata->deactivate_cs(hw->pdata, spi->chip_select,
 184                                         cspol);
 185                 break;
 186
 187         case BITBANG_CS_ACTIVE:
 188                 au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
 189
 190                 cfg = hw->regs->psc_spicfg;
 191                 au_sync();
 192                 hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
 193                 au_sync();
 194
 195                 if (spi->mode & SPI_CPOL)
 196                         cfg |= PSC_SPICFG_BI;
 197                 else
 198                         cfg &= ~PSC_SPICFG_BI;
 199                 if (spi->mode & SPI_CPHA)
 200                         cfg &= ~PSC_SPICFG_CDE;
 201                 else
 202                         cfg |= PSC_SPICFG_CDE;
 203
 204                 if (spi->mode & SPI_LSB_FIRST)
 205                         cfg |= PSC_SPICFG_MLF;
 206                 else
 207                         cfg &= ~PSC_SPICFG_MLF;
 208
 209                 if (hw->usedma && spi->bits_per_word <= 8)
 210                         cfg &= ~PSC_SPICFG_DD_DISABLE;
 211                 else
 212                         cfg |= PSC_SPICFG_DD_DISABLE;
 213                 cfg = PSC_SPICFG_CLR_LEN(cfg);
 214                 cfg |= PSC_SPICFG_SET_LEN(spi->bits_per_word);
 215
 216                 cfg = PSC_SPICFG_CLR_BAUD(cfg);
 217                 cfg &= ~PSC_SPICFG_SET_DIV(3);
 218                 cfg |= au1550_spi_baudcfg(hw, spi->max_speed_hz);
 219
 220                 hw->regs->psc_spicfg = cfg | PSC_SPICFG_DE_ENABLE;
 221                 au_sync();
 222                 do {
 223                         stat = hw->regs->psc_spistat;
 224                         au_sync();
 225                 } while ((stat & PSC_SPISTAT_DR) == 0);
 226
 227                 if (hw->pdata->activate_cs)
 228                         hw->pdata->activate_cs(hw->pdata, spi->chip_select,
 229                                         cspol);
 230                 break;
 231         }
 232 }
 233
 234 static int au1550_spi_setupxfer(struct spi_device *spi, struct spi_transfer *t)
 235 {
 236         struct au1550_spi *hw = spi_master_get_devdata(spi->master);
 237         unsigned bpw, hz;
 238         u32 cfg, stat;
 239
 240         bpw = t ? t->bits_per_word : spi->bits_per_word;
 241         hz = t ? t->speed_hz : spi->max_speed_hz;
 242
 243         if (bpw < 4 || bpw > 24) {
 244                 dev_err(&spi->dev, "setupxfer: invalid bits_per_word=%d\n",
 245                         bpw);
 246                 return -EINVAL;
 247         }
 248         if (hz > spi->max_speed_hz || hz > hw->freq_max || hz < hw->freq_min) {
 249                 dev_err(&spi->dev, "setupxfer: clock rate=%d out of range\n",
 250                         hz);
 251                 return -EINVAL;
 252         }
 253
 254         au1550_spi_bits_handlers_set(hw, spi->bits_per_word);
 255
 256         cfg = hw->regs->psc_spicfg;
 257         au_sync();
 258         hw->regs->psc_spicfg = cfg & ~PSC_SPICFG_DE_ENABLE;
 259         au_sync();
 260
 261         if (hw->usedma && bpw <= 8)
 262                 cfg &= ~PSC_SPICFG_DD_DISABLE;
 263         else
 264                 cfg |= PSC_SPICFG_DD_DISABLE;
 265         cfg = PSC_SPICFG_CLR_LEN(cfg);
 266         cfg |= PSC_SPICFG_SET_LEN(bpw);
 267
 268         cfg = PSC_SPICFG_CLR_BAUD(cfg);
 269         cfg &= ~PSC_SPICFG_SET_DIV(3);
 270         cfg |= au1550_spi_baudcfg(hw, hz);
 271
 272         hw->regs->psc_spicfg = cfg;
 273         au_sync();
 274
 275         if (cfg & PSC_SPICFG_DE_ENABLE) {
 276                 do {
 277                         stat = hw->regs->psc_spistat;
 278                         au_sync();
 279                 } while ((stat & PSC_SPISTAT_DR) == 0);
 280         }
 281
 282         au1550_spi_reset_fifos(hw);
 283         au1550_spi_mask_ack_all(hw);
 284         return 0;
 285 }
 286
 287 /* the spi->mode bits understood by this driver: */
 288 #define MODEBITS (SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST)
 289
 290 static int au1550_spi_setup(struct spi_device *spi)
 291 {
 292         struct au1550_spi *hw = spi_master_get_devdata(spi->master);
 293
 294         if (spi->bits_per_word == 0)
 295                 spi->bits_per_word = 8;
 296         if (spi->bits_per_word < 4 || spi->bits_per_word > 24) {
 297                 dev_err(&spi->dev, "setup: invalid bits_per_word=%d\n",
 298                         spi->bits_per_word);
 299                 return -EINVAL;
 300         }
 301
 302         if (spi->mode & ~MODEBITS) {
 303                 dev_dbg(&spi->dev, "setup: unsupported mode bits %x\n",
 304                         spi->mode & ~MODEBITS);
 305                 return -EINVAL;
 306         }
 307
 308         if (spi->max_speed_hz == 0)
 309                 spi->max_speed_hz = hw->freq_max;
 310         if (spi->max_speed_hz > hw->freq_max
 311                         || spi->max_speed_hz < hw->freq_min)
 312                 return -EINVAL;
 313         /*
 314          * NOTE: cannot change speed and other hw settings immediately,
 315          *       otherwise sharing of spi bus is not possible,
 316          *       so do not call setupxfer(spi, NULL) here
 317          */
 318         return 0;
 319 }
 320
 321 /*
 322  * for dma spi transfers, we have to setup rx channel, otherwise there is
 323  * no reliable way how to recognize that spi transfer is done
 324  * dma complete callbacks are called before real spi transfer is finished
 325  * and if only tx dma channel is set up (and rx fifo overflow event masked)
 326  * spi master done event irq is not generated unless rx fifo is empty (emptied)
 327  * so we need rx tmp buffer to use for rx dma if user does not provide one
 328  */
 329 static int au1550_spi_dma_rxtmp_alloc(struct au1550_spi *hw, unsigned size)
 330 {
 331         hw->dma_rx_tmpbuf = kmalloc(size, GFP_KERNEL);
 332         if (!hw->dma_rx_tmpbuf)
 333                 return -ENOMEM;
 334         hw->dma_rx_tmpbuf_size = size;
 335         hw->dma_rx_tmpbuf_addr = dma_map_single(hw->dev, hw->dma_rx_tmpbuf,
 336                         size, DMA_FROM_DEVICE);
 337         if (dma_mapping_error(hw->dma_rx_tmpbuf_addr)) {
 338                 kfree(hw->dma_rx_tmpbuf);
 339                 hw->dma_rx_tmpbuf = 0;
 340                 hw->dma_rx_tmpbuf_size = 0;
 341                 return -EFAULT;
 342         }
 343         return 0;
 344 }
 345
 346 static void au1550_spi_dma_rxtmp_free(struct au1550_spi *hw)
 347 {
 348         dma_unmap_single(hw->dev, hw->dma_rx_tmpbuf_addr,
 349                         hw->dma_rx_tmpbuf_size, DMA_FROM_DEVICE);
 350         kfree(hw->dma_rx_tmpbuf);
 351         hw->dma_rx_tmpbuf = 0;
 352         hw->dma_rx_tmpbuf_size = 0;
 353 }
 354
 355 static int au1550_spi_dma_txrxb(struct spi_device *spi, struct spi_transfer *t)
 356 {
 357         struct au1550_spi *hw = spi_master_get_devdata(spi->master);
 358         dma_addr_t dma_tx_addr;
 359         dma_addr_t dma_rx_addr;
 360         u32 res;
 361
 362         hw->len = t->len;
 363         hw->tx_count = 0;
 364         hw->rx_count = 0;
 365
 366         hw->tx = t->tx_buf;
 367         hw->rx = t->rx_buf;
 368         dma_tx_addr = t->tx_dma;
 369         dma_rx_addr = t->rx_dma;
 370
 371         /*
 372          * check if buffers are already dma mapped, map them otherwise
 373          * use rx buffer in place of tx if tx buffer was not provided
 374          * use temp rx buffer (preallocated or realloc to fit) for rx dma
 375          */
 376         if (t->rx_buf) {
 377                 if (t->rx_dma == 0) {   /* if DMA_ADDR_INVALID, map it */
 378                         dma_rx_addr = dma_map_single(hw->dev,
 379                                         (void *)t->rx_buf,
 380                                         t->len, DMA_FROM_DEVICE);
 381                         if (dma_mapping_error(dma_rx_addr))
 382                                 dev_err(hw->dev, "rx dma map error\n");
 383                 }
 384         } else {
 385                 if (t->len > hw->dma_rx_tmpbuf_size) {
 386                         int ret;
 387
 388                         au1550_spi_dma_rxtmp_free(hw);
 389                         ret = au1550_spi_dma_rxtmp_alloc(hw, max(t->len,
 390                                         AU1550_SPI_DMA_RXTMP_MINSIZE));
 391                         if (ret < 0)
 392                                 return ret;
 393                 }
 394                 hw->rx = hw->dma_rx_tmpbuf;
 395                 dma_rx_addr = hw->dma_rx_tmpbuf_addr;
 396                 dma_sync_single_for_device(hw->dev, dma_rx_addr,
 397                         t->len, DMA_FROM_DEVICE);
 398         }
 399         if (t->tx_buf) {
 400                 if (t->tx_dma == 0) {   /* if DMA_ADDR_INVALID, map it */
 401                         dma_tx_addr = dma_map_single(hw->dev,
 402                                         (void *)t->tx_buf,
 403                                         t->len, DMA_TO_DEVICE);
 404                         if (dma_mapping_error(dma_tx_addr))
 405                                 dev_err(hw->dev, "tx dma map error\n");
 406                 }
 407         } else {
 408                 dma_sync_single_for_device(hw->dev, dma_rx_addr,
 409                                 t->len, DMA_BIDIRECTIONAL);
 410                 hw->tx = hw->rx;
 411         }
 412
 413         /* put buffers on the ring */
 414         res = au1xxx_dbdma_put_dest(hw->dma_rx_ch, hw->rx, t->len);
 415         if (!res)
 416                 dev_err(hw->dev, "rx dma put dest error\n");
 417
 418         res = au1xxx_dbdma_put_source(hw->dma_tx_ch, (void *)hw->tx, t->len);
 419         if (!res)
 420                 dev_err(hw->dev, "tx dma put source error\n");
 421
 422         au1xxx_dbdma_start(hw->dma_rx_ch);
 423         au1xxx_dbdma_start(hw->dma_tx_ch);
 424
 425         /* by default enable nearly all events interrupt */
 426         hw->regs->psc_spimsk = PSC_SPIMSK_SD;
 427         au_sync();
 428
 429         /* start the transfer */
 430         hw->regs->psc_spipcr = PSC_SPIPCR_MS;
 431         au_sync();
 432
 433         wait_for_completion(&hw->master_done);
 434
 435         au1xxx_dbdma_stop(hw->dma_tx_ch);
 436         au1xxx_dbdma_stop(hw->dma_rx_ch);
 437
 438         if (!t->rx_buf) {
 439                 /* using the temporal preallocated and premapped buffer */
 440                 dma_sync_single_for_cpu(hw->dev, dma_rx_addr, t->len,
 441                         DMA_FROM_DEVICE);
 442         }
 443         /* unmap buffers if mapped above */
 444         if (t->rx_buf && t->rx_dma == 0 )
 445                 dma_unmap_single(hw->dev, dma_rx_addr, t->len,
 446                         DMA_FROM_DEVICE);
 447         if (t->tx_buf && t->tx_dma == 0 )
 448                 dma_unmap_single(hw->dev, dma_tx_addr, t->len,
 449                         DMA_TO_DEVICE);
 450
 451         return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
 452 }
 453
 454 static irqreturn_t au1550_spi_dma_irq_callback(struct au1550_spi *hw)
 455 {
 456         u32 stat, evnt;
 457
 458         stat = hw->regs->psc_spistat;
 459         evnt = hw->regs->psc_spievent;
 460         au_sync();
 461         if ((stat & PSC_SPISTAT_DI) == 0) {
 462                 dev_err(hw->dev, "Unexpected IRQ!\n");
 463                 return IRQ_NONE;
 464         }
 465
 466         if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
 467                                 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
 468                                 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD))
 469                         != 0) {
 470                 /*
 471                  * due to an spi error we consider transfer as done,
 472                  * so mask all events until before next transfer start
 473                  * and stop the possibly running dma immediatelly
 474                  */
 475                 au1550_spi_mask_ack_all(hw);
 476                 au1xxx_dbdma_stop(hw->dma_rx_ch);
 477                 au1xxx_dbdma_stop(hw->dma_tx_ch);
 478
 479                 /* get number of transfered bytes */
 480                 hw->rx_count = hw->len - au1xxx_get_dma_residue(hw->dma_rx_ch);
 481                 hw->tx_count = hw->len - au1xxx_get_dma_residue(hw->dma_tx_ch);
 482
 483                 au1xxx_dbdma_reset(hw->dma_rx_ch);
 484                 au1xxx_dbdma_reset(hw->dma_tx_ch);
 485                 au1550_spi_reset_fifos(hw);
 486
 487                 dev_err(hw->dev,
 488                         "Unexpected SPI error: event=0x%x stat=0x%x!\n",
 489                         evnt, stat);
 490
 491                 complete(&hw->master_done);
 492                 return IRQ_HANDLED;
 493         }
 494
 495         if ((evnt & PSC_SPIEVNT_MD) != 0) {
 496                 /* transfer completed successfully */
 497                 au1550_spi_mask_ack_all(hw);
 498                 hw->rx_count = hw->len;
 499                 hw->tx_count = hw->len;
 500                 complete(&hw->master_done);
 501         }
 502         return IRQ_HANDLED;
 503 }
 504
 505
 506 /* routines to handle different word sizes in pio mode */
 507 #define AU1550_SPI_RX_WORD(size, mask)                                  \
 508 static void au1550_spi_rx_word_##size(struct au1550_spi *hw)            \
 509 {                                                                       \
 510         u32 fifoword = hw->regs->psc_spitxrx & (u32)(mask);             \
 511         au_sync();                                                      \
 512         if (hw->rx) {                                                   \
 513                 *(u##size *)hw->rx = (u##size)fifoword;                 \
 514                 hw->rx += (size) / 8;                                   \
 515         }                                                               \
 516         hw->rx_count += (size) / 8;                                     \
 517 }
 518
 519 #define AU1550_SPI_TX_WORD(size, mask)                                  \
 520 static void au1550_spi_tx_word_##size(struct au1550_spi *hw)            \
 521 {                                                                       \
 522         u32 fifoword = 0;                                               \
 523         if (hw->tx) {                                                   \
 524                 fifoword = *(u##size *)hw->tx & (u32)(mask);            \
 525                 hw->tx += (size) / 8;                                   \
 526         }                                                               \
 527         hw->tx_count += (size) / 8;                                     \
 528         if (hw->tx_count >= hw->len)                                    \
 529                 fifoword |= PSC_SPITXRX_LC;                             \
 530         hw->regs->psc_spitxrx = fifoword;                               \
 531         au_sync();                                                      \
 532 }
 533
 534 AU1550_SPI_RX_WORD(8,0xff)
 535 AU1550_SPI_RX_WORD(16,0xffff)
 536 AU1550_SPI_RX_WORD(32,0xffffff)
 537 AU1550_SPI_TX_WORD(8,0xff)
 538 AU1550_SPI_TX_WORD(16,0xffff)
 539 AU1550_SPI_TX_WORD(32,0xffffff)
 540
 541 static int au1550_spi_pio_txrxb(struct spi_device *spi, struct spi_transfer *t)
 542 {
 543         u32 stat, mask;
 544         struct au1550_spi *hw = spi_master_get_devdata(spi->master);
 545
 546         hw->tx = t->tx_buf;
 547         hw->rx = t->rx_buf;
 548         hw->len = t->len;
 549         hw->tx_count = 0;
 550         hw->rx_count = 0;
 551
 552         /* by default enable nearly all events after filling tx fifo */
 553         mask = PSC_SPIMSK_SD;
 554
 555         /* fill the transmit FIFO */
 556         while (hw->tx_count < hw->len) {
 557
 558                 hw->tx_word(hw);
 559
 560                 if (hw->tx_count >= hw->len) {
 561                         /* mask tx fifo request interrupt as we are done */
 562                         mask |= PSC_SPIMSK_TR;
 563                 }
 564
 565                 stat = hw->regs->psc_spistat;
 566                 au_sync();
 567                 if (stat & PSC_SPISTAT_TF)
 568                         break;
 569         }
 570
 571         /* enable event interrupts */
 572         hw->regs->psc_spimsk = mask;
 573         au_sync();
 574
 575         /* start the transfer */
 576         hw->regs->psc_spipcr = PSC_SPIPCR_MS;
 577         au_sync();
 578
 579         wait_for_completion(&hw->master_done);
 580
 581         return hw->rx_count < hw->tx_count ? hw->rx_count : hw->tx_count;
 582 }
 583
 584 static irqreturn_t au1550_spi_pio_irq_callback(struct au1550_spi *hw)
 585 {
 586         int busy;
 587         u32 stat, evnt;
 588
 589         stat = hw->regs->psc_spistat;
 590         evnt = hw->regs->psc_spievent;
 591         au_sync();
 592         if ((stat & PSC_SPISTAT_DI) == 0) {
 593                 dev_err(hw->dev, "Unexpected IRQ!\n");
 594                 return IRQ_NONE;
 595         }
 596
 597         if ((evnt & (PSC_SPIEVNT_MM | PSC_SPIEVNT_RO
 598                                 | PSC_SPIEVNT_RU | PSC_SPIEVNT_TO
 599                                 | PSC_SPIEVNT_TU | PSC_SPIEVNT_SD))
 600                         != 0) {
 601                 dev_err(hw->dev,
 602                         "Unexpected SPI error: event=0x%x stat=0x%x!\n",
 603                         evnt, stat);
 604                 /*
 605                  * due to an error we consider transfer as done,
 606                  * so mask all events until before next transfer start
 607                  */
 608                 au1550_spi_mask_ack_all(hw);
 609                 au1550_spi_reset_fifos(hw);
 610                 complete(&hw->master_done);
 611                 return IRQ_HANDLED;
 612         }
 613
 614         /*
 615          * while there is something to read from rx fifo
 616          * or there is a space to write to tx fifo:
 617          */
 618         do {
 619                 busy = 0;
 620                 stat = hw->regs->psc_spistat;
 621                 au_sync();
 622
 623                 if ((stat & PSC_SPISTAT_RE) == 0 && hw->rx_count < hw->len) {
 624                         hw->rx_word(hw);
 625                         /* ack the receive request event */
 626                         hw->regs->psc_spievent = PSC_SPIEVNT_RR;
 627                         au_sync();
 628                         busy = 1;
 629                 }
 630
 631                 if ((stat & PSC_SPISTAT_TF) == 0 && hw->tx_count < hw->len) {
 632                         hw->tx_word(hw);
 633                         /* ack the transmit request event */
 634                         hw->regs->psc_spievent = PSC_SPIEVNT_TR;
 635                         au_sync();
 636                         busy = 1;
 637                 }
 638         } while (busy);
 639
 640         evnt = hw->regs->psc_spievent;
 641         au_sync();
 642
 643         if (hw->rx_count >= hw->len || (evnt & PSC_SPIEVNT_MD) != 0) {
 644                 /* transfer completed successfully */
 645                 au1550_spi_mask_ack_all(hw);
 646                 complete(&hw->master_done);
 647         }
 648         return IRQ_HANDLED;
 649 }
 650
 651 static int au1550_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
 652 {
 653         struct au1550_spi *hw = spi_master_get_devdata(spi->master);
 654         return hw->txrx_bufs(spi, t);
 655 }
 656
 657 static irqreturn_t au1550_spi_irq(int irq, void *dev)
 658 {
 659         struct au1550_spi *hw = dev;
 660         return hw->irq_callback(hw);
 661 }
 662
 663 static void au1550_spi_bits_handlers_set(struct au1550_spi *hw, int bpw)
 664 {
 665         if (bpw <= 8) {
 666                 if (hw->usedma) {
 667                         hw->txrx_bufs = &au1550_spi_dma_txrxb;
 668                         hw->irq_callback = &au1550_spi_dma_irq_callback;
 669                 } else {
 670                         hw->rx_word = &au1550_spi_rx_word_8;
 671                         hw->tx_word = &au1550_spi_tx_word_8;
 672                         hw->txrx_bufs = &au1550_spi_pio_txrxb;
 673                         hw->irq_callback = &au1550_spi_pio_irq_callback;
 674                 }
 675         } else if (bpw <= 16) {
 676                 hw->rx_word = &au1550_spi_rx_word_16;
 677                 hw->tx_word = &au1550_spi_tx_word_16;
 678                 hw->txrx_bufs = &au1550_spi_pio_txrxb;
 679                 hw->irq_callback = &au1550_spi_pio_irq_callback;
 680         } else {
 681                 hw->rx_word = &au1550_spi_rx_word_32;
 682                 hw->tx_word = &au1550_spi_tx_word_32;
 683                 hw->txrx_bufs = &au1550_spi_pio_txrxb;
 684                 hw->irq_callback = &au1550_spi_pio_irq_callback;
 685         }
 686 }
 687
 688 static void __init au1550_spi_setup_psc_as_spi(struct au1550_spi *hw)
 689 {
 690         u32 stat, cfg;
 691
 692         /* set up the PSC for SPI mode */
 693         hw->regs->psc_ctrl = PSC_CTRL_DISABLE;
 694         au_sync();
 695         hw->regs->psc_sel = PSC_SEL_PS_SPIMODE;
 696         au_sync();
 697
 698         hw->regs->psc_spicfg = 0;
 699         au_sync();
 700
 701         hw->regs->psc_ctrl = PSC_CTRL_ENABLE;
 702         au_sync();
 703
 704         do {
 705                 stat = hw->regs->psc_spistat;
 706                 au_sync();
 707         } while ((stat & PSC_SPISTAT_SR) == 0);
 708
 709
 710         cfg = hw->usedma ? 0 : PSC_SPICFG_DD_DISABLE;
 711         cfg |= PSC_SPICFG_SET_LEN(8);
 712         cfg |= PSC_SPICFG_RT_FIFO8 | PSC_SPICFG_TT_FIFO8;
 713         /* use minimal allowed brg and div values as initial setting: */
 714         cfg |= PSC_SPICFG_SET_BAUD(4) | PSC_SPICFG_SET_DIV(0);
 715
 716 #ifdef AU1550_SPI_DEBUG_LOOPBACK
 717         cfg |= PSC_SPICFG_LB;
 718 #endif
 719
 720         hw->regs->psc_spicfg = cfg;
 721         au_sync();
 722
 723         au1550_spi_mask_ack_all(hw);
 724
 725         hw->regs->psc_spicfg |= PSC_SPICFG_DE_ENABLE;
 726         au_sync();
 727
 728         do {
 729                 stat = hw->regs->psc_spistat;
 730                 au_sync();
 731         } while ((stat & PSC_SPISTAT_DR) == 0);
 732 }
 733
 734
 735 static int __init au1550_spi_probe(struct platform_device *pdev)
 736 {
 737         struct au1550_spi *hw;
 738         struct spi_master *master;
 739         struct resource *r;
 740         int err = 0;
 741
 742         master = spi_alloc_master(&pdev->dev, sizeof(struct au1550_spi));
 743         if (master == NULL) {
 744                 dev_err(&pdev->dev, "No memory for spi_master\n");
 745                 err = -ENOMEM;
 746                 goto err_nomem;
 747         }
 748
 749         hw = spi_master_get_devdata(master);
 750
 751         hw->master = spi_master_get(master);
 752         hw->pdata = pdev->dev.platform_data;
 753         hw->dev = &pdev->dev;
 754
 755         if (hw->pdata == NULL) {
 756                 dev_err(&pdev->dev, "No platform data supplied\n");
 757                 err = -ENOENT;
 758                 goto err_no_pdata;
 759         }
 760
 761         r = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 762         if (!r) {
 763                 dev_err(&pdev->dev, "no IRQ\n");
 764                 err = -ENODEV;
 765                 goto err_no_iores;
 766         }
 767         hw->irq = r->start;
 768
 769         hw->usedma = 0;
 770         r = platform_get_resource(pdev, IORESOURCE_DMA, 0);
 771         if (r) {
 772                 hw->dma_tx_id = r->start;
 773                 r = platform_get_resource(pdev, IORESOURCE_DMA, 1);
 774                 if (r) {
 775                         hw->dma_rx_id = r->start;
 776                         if (usedma && ddma_memid) {
 777                                 if (pdev->dev.dma_mask == NULL)
 778                                         dev_warn(&pdev->dev, "no dma mask\n");
 779                                 else
 780                                         hw->usedma = 1;
 781                         }
 782                 }
 783         }
 784
 785         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 786         if (!r) {
 787                 dev_err(&pdev->dev, "no mmio resource\n");
 788                 err = -ENODEV;
 789                 goto err_no_iores;
 790         }
 791
 792         hw->ioarea = request_mem_region(r->start, sizeof(psc_spi_t),
 793                                         pdev->name);
 794         if (!hw->ioarea) {
 795                 dev_err(&pdev->dev, "Cannot reserve iomem region\n");
 796                 err = -ENXIO;
 797                 goto err_no_iores;
 798         }
 799
 800         hw->regs = (psc_spi_t __iomem *)ioremap(r->start, sizeof(psc_spi_t));
 801         if (!hw->regs) {
 802                 dev_err(&pdev->dev, "cannot ioremap\n");
 803                 err = -ENXIO;
 804                 goto err_ioremap;
 805         }
 806
 807         platform_set_drvdata(pdev, hw);
 808
 809         init_completion(&hw->master_done);
 810
 811         hw->bitbang.master = hw->master;
 812         hw->bitbang.setup_transfer = au1550_spi_setupxfer;
 813         hw->bitbang.chipselect = au1550_spi_chipsel;
 814         hw->bitbang.master->setup = au1550_spi_setup;
 815         hw->bitbang.txrx_bufs = au1550_spi_txrx_bufs;
 816
 817         if (hw->usedma) {
 818                 hw->dma_tx_ch = au1xxx_dbdma_chan_alloc(ddma_memid,
 819                         hw->dma_tx_id, NULL, (void *)hw);
 820                 if (hw->dma_tx_ch == 0) {
 821                         dev_err(&pdev->dev,
 822                                 "Cannot allocate tx dma channel\n");
 823                         err = -ENXIO;
 824                         goto err_no_txdma;
 825                 }
 826                 au1xxx_dbdma_set_devwidth(hw->dma_tx_ch, 8);
 827                 if (au1xxx_dbdma_ring_alloc(hw->dma_tx_ch,
 828                         AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
 829                         dev_err(&pdev->dev,
 830                                 "Cannot allocate tx dma descriptors\n");
 831                         err = -ENXIO;
 832                         goto err_no_txdma_descr;
 833                 }
 834
 835
 836                 hw->dma_rx_ch = au1xxx_dbdma_chan_alloc(hw->dma_rx_id,
 837                         ddma_memid, NULL, (void *)hw);
 838                 if (hw->dma_rx_ch == 0) {
 839                         dev_err(&pdev->dev,
 840                                 "Cannot allocate rx dma channel\n");
 841                         err = -ENXIO;
 842                         goto err_no_rxdma;
 843                 }
 844                 au1xxx_dbdma_set_devwidth(hw->dma_rx_ch, 8);
 845                 if (au1xxx_dbdma_ring_alloc(hw->dma_rx_ch,
 846                         AU1550_SPI_DBDMA_DESCRIPTORS) == 0) {
 847                         dev_err(&pdev->dev,
 848                                 "Cannot allocate rx dma descriptors\n");
 849                         err = -ENXIO;
 850                         goto err_no_rxdma_descr;
 851                 }
 852
 853                 err = au1550_spi_dma_rxtmp_alloc(hw,
 854                         AU1550_SPI_DMA_RXTMP_MINSIZE);
 855                 if (err < 0) {
 856                         dev_err(&pdev->dev,
 857                                 "Cannot allocate initial rx dma tmp buffer\n");
 858                         goto err_dma_rxtmp_alloc;
 859                 }
 860         }
 861
 862         au1550_spi_bits_handlers_set(hw, 8);
 863
 864         err = request_irq(hw->irq, au1550_spi_irq, 0, pdev->name, hw);
 865         if (err) {
 866                 dev_err(&pdev->dev, "Cannot claim IRQ\n");
 867                 goto err_no_irq;
 868         }
 869
 870         master->bus_num = pdev->id;
 871         master->num_chipselect = hw->pdata->num_chipselect;
 872
 873         /*
 874          *  precompute valid range for spi freq - from au1550 datasheet:
 875          *    psc_tempclk = psc_mainclk / (2 << DIV)
 876          *    spiclk = psc_tempclk / (2 * (BRG + 1))
 877          *    BRG valid range is 4..63
 878          *    DIV valid range is 0..3
 879          *  round the min and max frequencies to values that would still
 880          *  produce valid brg and div
 881          */
 882         {
 883                 int min_div = (2 << 0) * (2 * (4 + 1));
 884                 int max_div = (2 << 3) * (2 * (63 + 1));
 885                 hw->freq_max = hw->pdata->mainclk_hz / min_div;
 886                 hw->freq_min = hw->pdata->mainclk_hz / (max_div + 1) + 1;
 887         }
 888
 889         au1550_spi_setup_psc_as_spi(hw);
 890
 891         err = spi_bitbang_start(&hw->bitbang);
 892         if (err) {
 893                 dev_err(&pdev->dev, "Failed to register SPI master\n");
 894                 goto err_register;
 895         }
 896
 897         dev_info(&pdev->dev,
 898                 "spi master registered: bus_num=%d num_chipselect=%d\n",
 899                 master->bus_num, master->num_chipselect);
 900
 901         return 0;
 902
 903 err_register:
 904         free_irq(hw->irq, hw);
 905
 906 err_no_irq:
 907         au1550_spi_dma_rxtmp_free(hw);
 908
 909 err_dma_rxtmp_alloc:
 910 err_no_rxdma_descr:
 911         if (hw->usedma)
 912                 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
 913
 914 err_no_rxdma:
 915 err_no_txdma_descr:
 916         if (hw->usedma)
 917                 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
 918
 919 err_no_txdma:
 920         iounmap((void __iomem *)hw->regs);
 921
 922 err_ioremap:
 923         release_resource(hw->ioarea);
 924         kfree(hw->ioarea);
 925
 926 err_no_iores:
 927 err_no_pdata:
 928         spi_master_put(hw->master);
 929
 930 err_nomem:
 931         return err;
 932 }
 933
 934 static int __exit au1550_spi_remove(struct platform_device *pdev)
 935 {
 936         struct au1550_spi *hw = platform_get_drvdata(pdev);
 937
 938         dev_info(&pdev->dev, "spi master remove: bus_num=%d\n",
 939                 hw->master->bus_num);
 940
 941         spi_bitbang_stop(&hw->bitbang);
 942         free_irq(hw->irq, hw);
 943         iounmap((void __iomem *)hw->regs);
 944         release_resource(hw->ioarea);
 945         kfree(hw->ioarea);
 946
 947         if (hw->usedma) {
 948                 au1550_spi_dma_rxtmp_free(hw);
 949                 au1xxx_dbdma_chan_free(hw->dma_rx_ch);
 950                 au1xxx_dbdma_chan_free(hw->dma_tx_ch);
 951         }
 952
 953         platform_set_drvdata(pdev, NULL);
 954
 955         spi_master_put(hw->master);
 956         return 0;
 957 }
 958
 959 /* work with hotplug and coldplug */
 960 MODULE_ALIAS("platform:au1550-spi");
 961
 962 static struct platform_driver au1550_spi_drv = {
 963         .remove = __exit_p(au1550_spi_remove),
 964         .driver = {
 965                 .name = "au1550-spi",
 966                 .owner = THIS_MODULE,
 967         },
 968 };
 969
 970 static int __init au1550_spi_init(void)
 971 {
 972         /*
 973          * create memory device with 8 bits dev_devwidth
 974          * needed for proper byte ordering to spi fifo
 975          */
 976         if (usedma) {
 977                 ddma_memid = au1xxx_ddma_add_device(&au1550_spi_mem_dbdev);
 978                 if (!ddma_memid)
 979                         printk(KERN_ERR "au1550-spi: cannot add memory"
 980                                         "dbdma device\n");
 981         }
 982         return platform_driver_probe(&au1550_spi_drv, au1550_spi_probe);
 983 }
 984 module_init(au1550_spi_init);
 985
 986 static void __exit au1550_spi_exit(void)
 987 {
 988         if (usedma && ddma_memid)
 989                 au1xxx_ddma_del_device(ddma_memid);
 990         platform_driver_unregister(&au1550_spi_drv);
 991 }
 992 module_exit(au1550_spi_exit);
 993
 994 MODULE_DESCRIPTION("Au1550 PSC SPI Driver");
 995 MODULE_AUTHOR("Jan Nikitenko <jan.nikitenko@gmail.com>");
 996 MODULE_LICENSE("GPL");