1 /* $Id: sh-sci.h,v 1.4 2004/02/19 16:43:56 lethal Exp $
3 * linux/drivers/serial/sh-sci.h
5 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
6 * Copyright (C) 1999, 2000 Niibe Yutaka
7 * Copyright (C) 2000 Greg Banks
8 * Copyright (C) 2002, 2003 Paul Mundt
9 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
10 * Modified to support SH7300(SH-Mobile) SCIF. Takashi Kusuda (Jun 2003).
11 * Modified to support H8/300 Series Yoshinori Sato (Feb 2004).
13 #include <linux/serial_core.h>
16 #if defined(__H8300H__) || defined(__H8300S__)
18 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
19 #include <asm/regs306x.h>
21 #if defined(CONFIG_H8S2678)
22 #include <asm/regs267x.h>
26 #if defined(CONFIG_CPU_SUBTYPE_SH7708)
27 # define SCSPTR 0xffffff7c /* 8 bit */
28 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
30 #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || \
31 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
32 defined(CONFIG_CPU_SUBTYPE_SH7706)
33 # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
34 # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
35 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
37 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
38 # define SCIF0 0xA4400000
39 # define SCIF2 0xA4410000
40 # define SCSMR_Ir 0xA44A0000
41 # define IRDA_SCIF SCIF0
42 # define SCPCR 0xA4000116
43 # define SCPDR 0xA4000136
45 /* Set the clock source,
46 * SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input
47 * SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output
49 # define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0
51 #elif defined(CONFIG_SH_RTS7751R2D)
52 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
53 # define SCIF_ORER 0x0001 /* overrun error bit */
54 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
56 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
57 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
58 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
59 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
60 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
61 defined(CONFIG_CPU_SUBTYPE_SH7751R)
62 # define SCSPTR1 0xffe0001c /* 8 bit SCI */
63 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
64 # define SCIF_ORER 0x0001 /* overrun error bit */
65 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
66 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
67 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
69 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
70 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */
71 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */
72 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */
73 # define SCIF_ORER 0x0001 /* overrun error bit */
74 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
76 #elif defined(CONFIG_CPU_SUBTYPE_SH7300)
77 # define SCPCR 0xA4050116 /* 16 bit SCIF */
78 # define SCPDR 0xA4050136 /* 16 bit SCIF */
79 # define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */
81 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
82 # define SCSPTR0 0xA4400000 /* 16 bit SCIF */
84 # define SCIF_ORER 0x0001 /* overrun error bit */
85 # define PACR 0xa4050100
86 # define PBCR 0xa4050102
87 # define SCSCR_INIT(port) 0x3B
89 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
90 # define SCSPTR0 0xffe00010 /* 16 bit SCIF */
91 # define SCSPTR1 0xffe10010 /* 16 bit SCIF */
92 # define SCSPTR2 0xffe20010 /* 16 bit SCIF */
93 # define SCSPTR3 0xffe30010 /* 16 bit SCIF */
94 # define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
96 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
97 # define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
98 # define SCSPTR0 SCPDR0
99 # define SCIF_ORER 0x0001 /* overrun error bit */
100 # define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
102 # define PORT_PSCR 0xA405011E
103 #elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
104 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
105 # define SCIF_ORER 0x0001 /* overrun error bit */
106 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
108 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
109 # define SCSPTR1 0xffe00020 /* 16 bit SCIF */
110 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
111 # define SCIF_ORER 0x0001 /* overrun error bit */
112 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
114 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
115 # include <asm/hardware.h>
116 # define SCIF_BASE_ADDR 0x01030000
117 # define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR
118 # define SCIF_PTR2_OFFS 0x0000020
119 # define SCIF_LSR2_OFFS 0x0000024
120 # define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */
121 # define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */
122 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,
125 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
126 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
128 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
129 #elif defined(CONFIG_H8S2678)
130 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
132 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
133 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
134 # define SCSPTR0 0xff923020 /* 16 bit SCIF */
135 # define SCSPTR1 0xff924020 /* 16 bit SCIF */
136 # define SCSPTR2 0xff925020 /* 16 bit SCIF */
137 # define SCIF_ORER 0x0001 /* overrun error bit */
138 # define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */
140 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
141 # define SCSPTR0 0xffe00024 /* 16 bit SCIF */
142 # define SCSPTR1 0xffe10024 /* 16 bit SCIF */
143 # define SCIF_ORER 0x0001 /* Overrun error bit */
144 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
146 #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
147 # define SCSPTR0 0xffea0024 /* 16 bit SCIF */
148 # define SCSPTR1 0xffeb0024 /* 16 bit SCIF */
149 # define SCSPTR2 0xffec0024 /* 16 bit SCIF */
150 # define SCSPTR3 0xffed0024 /* 16 bit SCIF */
151 # define SCSPTR4 0xffee0024 /* 16 bit SCIF */
152 # define SCSPTR5 0xffef0024 /* 16 bit SCIF */
153 # define SCIF_OPER 0x0001 /* Overrun error bit */
154 # define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
156 #elif defined(CONFIG_CPU_SUBTYPE_SH7206)
157 # define SCSPTR0 0xfffe8020 /* 16 bit SCIF */
158 # define SCSPTR1 0xfffe8820 /* 16 bit SCIF */
159 # define SCSPTR2 0xfffe9020 /* 16 bit SCIF */
160 # define SCSPTR3 0xfffe9820 /* 16 bit SCIF */
161 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
163 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
164 # define SCSPTR0 0xf8400020 /* 16 bit SCIF */
165 # define SCSPTR1 0xf8410020 /* 16 bit SCIF */
166 # define SCSPTR2 0xf8420020 /* 16 bit SCIF */
167 # define SCIF_ORER 0x0001 /* overrun error bit */
168 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
170 #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
171 # define SCSPTR0 0xffc30020 /* 16 bit SCIF */
172 # define SCSPTR1 0xffc40020 /* 16 bit SCIF */
173 # define SCSPTR2 0xffc50020 /* 16 bit SCIF */
174 # define SCSPTR3 0xffc60020 /* 16 bit SCIF */
175 # define SCIF_ORER 0x0001 /* Overrun error bit */
176 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
179 # error CPU subtype not defined
183 #define SCI_CTRL_FLAGS_TIE 0x80 /* all */
184 #define SCI_CTRL_FLAGS_RIE 0x40 /* all */
185 #define SCI_CTRL_FLAGS_TE 0x20 /* all */
186 #define SCI_CTRL_FLAGS_RE 0x10 /* all */
187 #if defined(CONFIG_CPU_SUBTYPE_SH7750) || \
188 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
189 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
190 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
191 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
192 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
193 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
194 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
195 defined(CONFIG_CPU_SUBTYPE_SHX3)
196 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
198 #define SCI_CTRL_FLAGS_REIE 0
200 /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
201 /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
202 /* SCI_CTRL_FLAGS_CKE1 0x02 * all */
203 /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
206 #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
207 #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
208 #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
209 #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
210 #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
211 #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
212 /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
213 /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
215 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
218 #define SCIF_ER 0x0080 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
219 #define SCIF_TEND 0x0040 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
220 #define SCIF_TDFE 0x0020 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
221 #define SCIF_BRK 0x0010 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
222 #define SCIF_FER 0x0008 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
223 #define SCIF_PER 0x0004 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
224 #define SCIF_RDF 0x0002 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
225 #define SCIF_DR 0x0001 /* 7705 SCIF, 7707 SCIF, 7709 SCIF, 7750 SCIF */
227 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
228 #define SCIF_ORER 0x0200
229 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK | SCIF_ORER)
230 #define SCIF_RFDC_MASK 0x007f
231 #define SCIF_TXROOM_MAX 64
233 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
234 #define SCIF_RFDC_MASK 0x001f
235 #define SCIF_TXROOM_MAX 16
238 #if defined(SCI_ONLY)
239 # define SCxSR_TEND(port) SCI_TEND
240 # define SCxSR_ERRORS(port) SCI_ERRORS
241 # define SCxSR_RDxF(port) SCI_RDRF
242 # define SCxSR_TDxE(port) SCI_TDRE
243 # define SCxSR_ORER(port) SCI_ORER
244 # define SCxSR_FER(port) SCI_FER
245 # define SCxSR_PER(port) SCI_PER
246 # define SCxSR_BRK(port) 0x00
247 # define SCxSR_RDxF_CLEAR(port) 0xbc
248 # define SCxSR_ERROR_CLEAR(port) 0xc4
249 # define SCxSR_TDxE_CLEAR(port) 0x78
250 # define SCxSR_BREAK_CLEAR(port) 0xc4
251 #elif defined(SCIF_ONLY)
252 # define SCxSR_TEND(port) SCIF_TEND
253 # define SCxSR_ERRORS(port) SCIF_ERRORS
254 # define SCxSR_RDxF(port) SCIF_RDF
255 # define SCxSR_TDxE(port) SCIF_TDFE
256 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
257 # define SCxSR_ORER(port) SCIF_ORER
259 # define SCxSR_ORER(port) 0x0000
261 # define SCxSR_FER(port) SCIF_FER
262 # define SCxSR_PER(port) SCIF_PER
263 # define SCxSR_BRK(port) SCIF_BRK
264 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
265 # define SCxSR_RDxF_CLEAR(port) (sci_in(port,SCxSR)&0xfffc)
266 # define SCxSR_ERROR_CLEAR(port) (sci_in(port,SCxSR)&0xfd73)
267 # define SCxSR_TDxE_CLEAR(port) (sci_in(port,SCxSR)&0xffdf)
268 # define SCxSR_BREAK_CLEAR(port) (sci_in(port,SCxSR)&0xffe3)
270 /* SH7705 can also use this, clearing is same between 7705 and 7709 and 7300 */
271 # define SCxSR_RDxF_CLEAR(port) 0x00fc
272 # define SCxSR_ERROR_CLEAR(port) 0x0073
273 # define SCxSR_TDxE_CLEAR(port) 0x00df
274 # define SCxSR_BREAK_CLEAR(port) 0x00e3
277 # define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
278 # define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
279 # define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
280 # define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
281 # define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000)
282 # define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
283 # define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
284 # define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
285 # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
286 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
287 # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
288 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
292 #define SCFCR_RFRST 0x0002
293 #define SCFCR_TFRST 0x0004
294 #define SCFCR_TCRST 0x4000
295 #define SCFCR_MCE 0x0008
297 #define SCI_MAJOR 204
298 #define SCI_MINOR_START 8
300 /* Generic serial flags */
301 #define SCI_RX_THROTTLE 0x0000001
303 #define SCI_MAGIC 0xbabeface
306 * Events are used to schedule things to happen at timer-interrupt
307 * time, instead of at rs interrupt time.
309 #define SCI_EVENT_WRITE_WAKEUP 0
311 #define SCI_IN(size, offset) \
312 unsigned int addr = port->mapbase + (offset); \
314 return ctrl_inb(addr); \
316 return ctrl_inw(addr); \
318 #define SCI_OUT(size, offset, value) \
319 unsigned int addr = port->mapbase + (offset); \
321 ctrl_outb(value, addr); \
323 ctrl_outw(value, addr); \
326 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
327 static inline unsigned int sci_##name##_in(struct uart_port *port) \
329 if (port->type == PORT_SCI) { \
330 SCI_IN(sci_size, sci_offset) \
332 SCI_IN(scif_size, scif_offset); \
335 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
337 if (port->type == PORT_SCI) { \
338 SCI_OUT(sci_size, sci_offset, value) \
340 SCI_OUT(scif_size, scif_offset, value); \
344 #define CPU_SCIF_FNS(name, scif_offset, scif_size) \
345 static inline unsigned int sci_##name##_in(struct uart_port *port) \
347 SCI_IN(scif_size, scif_offset); \
349 static inline void sci_##name##_out(struct uart_port *port, unsigned int value) \
351 SCI_OUT(scif_size, scif_offset, value); \
354 #define CPU_SCI_FNS(name, sci_offset, sci_size) \
355 static inline unsigned int sci_##name##_in(struct uart_port* port) \
357 SCI_IN(sci_size, sci_offset); \
359 static inline void sci_##name##_out(struct uart_port* port, unsigned int value) \
361 SCI_OUT(sci_size, sci_offset, value); \
364 #ifdef CONFIG_CPU_SH3
365 #if defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
366 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
367 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
368 h8_sci_offset, h8_sci_size) \
369 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
370 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
371 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
372 #elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \
373 defined(CONFIG_CPU_SUBTYPE_SH7705)
374 #define SCIF_FNS(name, scif_offset, scif_size) \
375 CPU_SCIF_FNS(name, scif_offset, scif_size)
377 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
378 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
379 h8_sci_offset, h8_sci_size) \
380 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
381 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
382 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
384 #elif defined(__H8300H__) || defined(__H8300S__)
385 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
386 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
387 h8_sci_offset, h8_sci_size) \
388 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
389 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
391 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
392 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
393 h8_sci_offset, h8_sci_size) \
394 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
395 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
396 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
399 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
400 defined(CONFIG_CPU_SUBTYPE_SH7705)
402 SCIF_FNS(SCSMR, 0x00, 16)
403 SCIF_FNS(SCBRR, 0x04, 8)
404 SCIF_FNS(SCSCR, 0x08, 16)
405 SCIF_FNS(SCTDSR, 0x0c, 8)
406 SCIF_FNS(SCFER, 0x10, 16)
407 SCIF_FNS(SCxSR, 0x14, 16)
408 SCIF_FNS(SCFCR, 0x18, 16)
409 SCIF_FNS(SCFDR, 0x1c, 16)
410 SCIF_FNS(SCxTDR, 0x20, 8)
411 SCIF_FNS(SCxRDR, 0x24, 8)
412 SCIF_FNS(SCLSR, 0x24, 16)
414 /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
415 /* name off sz off sz off sz off sz off sz*/
416 SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
417 SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
418 SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
419 SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
420 SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
421 SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
422 SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
423 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
424 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
425 defined(CONFIG_CPU_SUBTYPE_SH7785)
426 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
427 SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16)
428 SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16)
429 SCIF_FNS(SCSPTR, 0, 0, 0x24, 16)
430 SCIF_FNS(SCLSR, 0, 0, 0x28, 16)
432 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
433 SCIF_FNS(SCSPTR, 0, 0, 0x20, 16)
434 SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
437 #define sci_in(port, reg) sci_##reg##_in(port)
438 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
440 /* H8/300 series SCI pins assignment */
441 #if defined(__H8300H__) || defined(__H8300S__)
442 static const struct __attribute__((packed)) {
443 int port; /* GPIO port no */
444 unsigned short rx,tx; /* GPIO bit no */
445 } h8300_sci_pins[] = {
446 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
448 .port = H8300_GPIO_P9,
453 .port = H8300_GPIO_P9,
458 .port = H8300_GPIO_PB,
462 #elif defined(CONFIG_H8S2678)
464 .port = H8300_GPIO_P3,
469 .port = H8300_GPIO_P3,
474 .port = H8300_GPIO_P5,
482 #if defined(CONFIG_CPU_SUBTYPE_SH7708)
483 static inline int sci_rxd_in(struct uart_port *port)
485 if (port->mapbase == 0xfffffe80)
486 return ctrl_inb(SCSPTR)&0x01 ? 1 : 0; /* SCI */
489 #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || \
490 defined(CONFIG_CPU_SUBTYPE_SH7709) || \
491 defined(CONFIG_CPU_SUBTYPE_SH7706)
492 static inline int sci_rxd_in(struct uart_port *port)
494 if (port->mapbase == 0xfffffe80)
495 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
496 if (port->mapbase == 0xa4000150)
497 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
498 if (port->mapbase == 0xa4000140)
499 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
502 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
503 static inline int sci_rxd_in(struct uart_port *port)
505 if (port->mapbase == SCIF0)
506 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
507 if (port->mapbase == SCIF2)
508 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
511 #elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712)
512 static inline int sci_rxd_in(struct uart_port *port)
514 return sci_in(port,SCxSR)&0x0010 ? 1 : 0;
516 static inline void set_sh771x_scif_pfc(struct uart_port *port)
518 if (port->mapbase == 0xA4400000){
519 ctrl_outw(ctrl_inw(PACR)&0xffc0,PACR);
520 ctrl_outw(ctrl_inw(PBCR)&0x0fff,PBCR);
523 if (port->mapbase == 0xA4410000){
524 ctrl_outw(ctrl_inw(PBCR)&0xf003,PBCR);
529 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \
530 defined(CONFIG_CPU_SUBTYPE_SH7751) || \
531 defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
532 defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
533 defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
534 defined(CONFIG_CPU_SUBTYPE_SH7091) || \
535 defined(CONFIG_CPU_SUBTYPE_SH4_202)
536 static inline int sci_rxd_in(struct uart_port *port)
539 if (port->mapbase == 0xffe00000)
540 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
543 if (port->mapbase == 0xffe80000)
544 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
548 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
549 static inline int sci_rxd_in(struct uart_port *port)
551 if (port->mapbase == 0xfe600000)
552 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
553 if (port->mapbase == 0xfe610000)
554 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
555 if (port->mapbase == 0xfe620000)
556 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
559 #elif defined(CONFIG_CPU_SUBTYPE_SH7300)
560 static inline int sci_rxd_in(struct uart_port *port)
562 if (port->mapbase == 0xa4430000)
563 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCIF0 */
566 #elif defined(CONFIG_CPU_SUBTYPE_SH7343)
567 static inline int sci_rxd_in(struct uart_port *port)
569 if (port->mapbase == 0xffe00000)
570 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
571 if (port->mapbase == 0xffe10000)
572 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
573 if (port->mapbase == 0xffe20000)
574 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
575 if (port->mapbase == 0xffe30000)
576 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
579 #elif defined(CONFIG_CPU_SUBTYPE_SH7722)
580 static inline int sci_rxd_in(struct uart_port *port)
582 if (port->mapbase == 0xffe00000)
583 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
586 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
587 static inline int sci_rxd_in(struct uart_port *port)
589 if (port->mapbase == 0xffe00000)
590 return ctrl_inw(SCSPTR1)&0x0001 ? 1 : 0; /* SCIF */
592 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
595 #elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103)
596 static inline int sci_rxd_in(struct uart_port *port)
598 return sci_in(port, SCSPTR)&0x0001 ? 1 : 0; /* SCIF */
600 #elif defined(__H8300H__) || defined(__H8300S__)
601 static inline int sci_rxd_in(struct uart_port *port)
603 int ch = (port->mapbase - SMR0) >> 3;
604 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
606 #elif defined(CONFIG_CPU_SUBTYPE_SH7770)
607 static inline int sci_rxd_in(struct uart_port *port)
609 if (port->mapbase == 0xff923000)
610 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
611 if (port->mapbase == 0xff924000)
612 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
613 if (port->mapbase == 0xff925000)
614 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
617 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
618 static inline int sci_rxd_in(struct uart_port *port)
620 if (port->mapbase == 0xffe00000)
621 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
622 if (port->mapbase == 0xffe10000)
623 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
626 #elif defined(CONFIG_CPU_SUBTYPE_SH7785)
627 static inline int sci_rxd_in(struct uart_port *port)
629 if (port->mapbase == 0xffea0000)
630 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
631 if (port->mapbase == 0xffeb0000)
632 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
633 if (port->mapbase == 0xffec0000)
634 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
635 if (port->mapbase == 0xffed0000)
636 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
637 if (port->mapbase == 0xffee0000)
638 return ctrl_inw(SCSPTR4) & 0x0001 ? 1 : 0; /* SCIF */
639 if (port->mapbase == 0xffef0000)
640 return ctrl_inw(SCSPTR5) & 0x0001 ? 1 : 0; /* SCIF */
643 #elif defined(CONFIG_CPU_SUBTYPE_SH7206)
644 static inline int sci_rxd_in(struct uart_port *port)
646 if (port->mapbase == 0xfffe8000)
647 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
648 if (port->mapbase == 0xfffe8800)
649 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
650 if (port->mapbase == 0xfffe9000)
651 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
652 if (port->mapbase == 0xfffe9800)
653 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
656 #elif defined(CONFIG_CPU_SUBTYPE_SH7619)
657 static inline int sci_rxd_in(struct uart_port *port)
659 if (port->mapbase == 0xf8400000)
660 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
661 if (port->mapbase == 0xf8410000)
662 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
663 if (port->mapbase == 0xf8420000)
664 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
667 #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
668 static inline int sci_rxd_in(struct uart_port *port)
670 if (port->mapbase == 0xffc30000)
671 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
672 if (port->mapbase == 0xffc40000)
673 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
674 if (port->mapbase == 0xffc50000)
675 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
676 if (port->mapbase == 0xffc60000)
677 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
682 * Values for the BitRate Register (SCBRR)
684 * The values are actually divisors for a frequency which can
685 * be internal to the SH3 (14.7456MHz) or derived from an external
686 * clock source. This driver assumes the internal clock is used;
687 * to support using an external clock source, config options or
688 * possibly command-line options would need to be added.
690 * Also, to support speeds below 2400 (why?) the lower 2 bits of
691 * the SCSMR register would also need to be set to non-zero values.
693 * -- Greg Banks 27Feb2000
695 * Answer: The SCBRR register is only eight bits, and the value in
696 * it gets larger with lower baud rates. At around 2400 (depending on
697 * the peripherial module clock) you run out of bits. However the
698 * lower two bits of SCSMR allow the module clock to be divided down,
699 * scaling the value which is needed in SCBRR.
701 * -- Stuart Menefy - 23 May 2000
703 * I meant, why would anyone bother with bitrates below 2400.
705 * -- Greg Banks - 7Jul2000
707 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
708 * tape reader as a console!
710 * -- Mitch Davis - 15 Jul 2000
713 #if defined(CONFIG_CPU_SUBTYPE_SH7300) || \
714 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
715 defined(CONFIG_CPU_SUBTYPE_SH7785)
716 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
717 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
718 #define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1)
719 #elif defined(__H8300H__) || defined(__H8300S__)
720 #define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
721 #elif defined(CONFIG_SUPERH64)
722 #define SCBRR_VALUE(bps) ((current_cpu_data.module_clock+16*bps)/(32*bps)-1)
723 #else /* Generic SH */
724 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1)