2 * linux/drivers/serial/s3c2410.c
4 * Driver for onboard UARTs on the Samsung S3C24XX
6 * Based on drivers/char/serial.c and drivers/char/21285.c
8 * Ben Dooks, (c) 2003-2005 Simtec Electronics
9 * http://www.simtec.co.uk/products/SWLINUX/
13 * 22-Jul-2004 BJD Finished off device rewrite
15 * 21-Jul-2004 BJD Thanks to <herbet@13thfloor.at> for pointing out
16 * problems with baud rate and loss of IR settings. Update
17 * to add configuration via platform_device structure
19 * 28-Sep-2004 BJD Re-write for the following items
20 * - S3C2410 and S3C2440 serial support
21 * - Power Management support
22 * - Fix console via IrDA devices
23 * - SysReq (Herbert Pötzl)
24 * - Break character handling (Herbert Pötzl)
25 * - spin-lock initialisation (Dimitry Andric)
26 * - added clock control
27 * - updated init code to use platform_device info
29 * 06-Mar-2005 BJD Add s3c2440 fclk clock source
31 * 09-Mar-2005 BJD Add s3c2400 support
33 * 10-Mar-2005 LCVR Changed S3C2410_VA_UART to S3C24XX_VA_UART
36 /* Note on 2440 fclk clock source handling
38 * Whilst it is possible to use the fclk as clock source, the method
39 * of properly switching too/from this is currently un-implemented, so
40 * whichever way is configured at startup is the one that will be used.
43 /* Hote on 2410 error handling
45 * The s3c2410 manual has a love/hate affair with the contents of the
46 * UERSTAT register in the UART blocks, and keeps marking some of the
47 * error bits as reserved. Having checked with the s3c2410x01,
48 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
49 * feature from the latter versions of the manual.
51 * If it becomes aparrent that latter versions of the 2410 remove these
52 * bits, then action will have to be taken to differentiate the versions
53 * and change the policy on BREAK
59 #if defined(CONFIG_SERIAL_S3C2410_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
63 #include <linux/module.h>
64 #include <linux/ioport.h>
65 #include <linux/platform_device.h>
66 #include <linux/init.h>
67 #include <linux/sysrq.h>
68 #include <linux/console.h>
69 #include <linux/tty.h>
70 #include <linux/tty_flip.h>
71 #include <linux/serial_core.h>
72 #include <linux/serial.h>
73 #include <linux/delay.h>
74 #include <linux/clk.h>
79 #include <asm/hardware.h>
81 #include <asm/plat-s3c/regs-serial.h>
82 #include <asm/arch/regs-gpio.h>
86 struct s3c24xx_uart_info {
89 unsigned int fifosize;
90 unsigned long rx_fifomask;
91 unsigned long rx_fifoshift;
92 unsigned long rx_fifofull;
93 unsigned long tx_fifomask;
94 unsigned long tx_fifoshift;
95 unsigned long tx_fifofull;
97 /* clock source control */
99 int (*get_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
100 int (*set_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
103 int (*reset_port)(struct uart_port *, struct s3c2410_uartcfg *);
106 struct s3c24xx_uart_port {
107 unsigned char rx_claimed;
108 unsigned char tx_claimed;
110 struct s3c24xx_uart_info *info;
111 struct s3c24xx_uart_clksrc *clksrc;
114 struct uart_port port;
118 /* configuration defines */
122 /* send debug to the low-level output routines */
124 extern void printascii(const char *);
127 s3c24xx_serial_dbg(const char *fmt, ...)
133 vsprintf(buff, fmt, va);
139 #define dbg(x...) s3c24xx_serial_dbg(x)
142 #define dbg(x...) printk(KERN_DEBUG "s3c24xx: ");
145 #define dbg(x...) do {} while(0)
148 /* UART name and device definitions */
150 #define S3C24XX_SERIAL_NAME "ttySAC"
151 #define S3C24XX_SERIAL_MAJOR 204
152 #define S3C24XX_SERIAL_MINOR 64
155 /* conversion functions */
157 #define s3c24xx_dev_to_port(__dev) (struct uart_port *)dev_get_drvdata(__dev)
158 #define s3c24xx_dev_to_cfg(__dev) (struct s3c2410_uartcfg *)((__dev)->platform_data)
160 /* we can support 3 uarts, but not always use them */
162 #ifdef CONFIG_CPU_S3C2400
168 /* port irq numbers */
170 #define TX_IRQ(port) ((port)->irq + 1)
171 #define RX_IRQ(port) ((port)->irq)
173 /* register access controls */
175 #define portaddr(port, reg) ((port)->membase + (reg))
177 #define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
178 #define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
180 #define wr_regb(port, reg, val) \
181 do { __raw_writeb(val, portaddr(port, reg)); } while(0)
183 #define wr_regl(port, reg, val) \
184 do { __raw_writel(val, portaddr(port, reg)); } while(0)
186 /* macros to change one thing to another */
188 #define tx_enabled(port) ((port)->unused[0])
189 #define rx_enabled(port) ((port)->unused[1])
191 /* flag to ignore all characters comming in */
192 #define RXSTAT_DUMMY_READ (0x10000000)
194 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
196 return container_of(port, struct s3c24xx_uart_port, port);
199 /* translate a port to the device name */
201 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
203 return to_platform_device(port->dev)->name;
206 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
208 return (rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE);
211 static void s3c24xx_serial_rx_enable(struct uart_port *port)
214 unsigned int ucon, ufcon;
217 spin_lock_irqsave(&port->lock, flags);
219 while (--count && !s3c24xx_serial_txempty_nofifo(port))
222 ufcon = rd_regl(port, S3C2410_UFCON);
223 ufcon |= S3C2410_UFCON_RESETRX;
224 wr_regl(port, S3C2410_UFCON, ufcon);
226 ucon = rd_regl(port, S3C2410_UCON);
227 ucon |= S3C2410_UCON_RXIRQMODE;
228 wr_regl(port, S3C2410_UCON, ucon);
230 rx_enabled(port) = 1;
231 spin_unlock_irqrestore(&port->lock, flags);
234 static void s3c24xx_serial_rx_disable(struct uart_port *port)
239 spin_lock_irqsave(&port->lock, flags);
241 ucon = rd_regl(port, S3C2410_UCON);
242 ucon &= ~S3C2410_UCON_RXIRQMODE;
243 wr_regl(port, S3C2410_UCON, ucon);
245 rx_enabled(port) = 0;
246 spin_unlock_irqrestore(&port->lock, flags);
249 static void s3c24xx_serial_stop_tx(struct uart_port *port)
251 if (tx_enabled(port)) {
252 disable_irq(TX_IRQ(port));
253 tx_enabled(port) = 0;
254 if (port->flags & UPF_CONS_FLOW)
255 s3c24xx_serial_rx_enable(port);
259 static void s3c24xx_serial_start_tx(struct uart_port *port)
261 if (!tx_enabled(port)) {
262 if (port->flags & UPF_CONS_FLOW)
263 s3c24xx_serial_rx_disable(port);
265 enable_irq(TX_IRQ(port));
266 tx_enabled(port) = 1;
271 static void s3c24xx_serial_stop_rx(struct uart_port *port)
273 if (rx_enabled(port)) {
274 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
275 disable_irq(RX_IRQ(port));
276 rx_enabled(port) = 0;
280 static void s3c24xx_serial_enable_ms(struct uart_port *port)
284 static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
286 return to_ourport(port)->info;
289 static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
291 if (port->dev == NULL)
294 return (struct s3c2410_uartcfg *)port->dev->platform_data;
297 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
298 unsigned long ufstat)
300 struct s3c24xx_uart_info *info = ourport->info;
302 if (ufstat & info->rx_fifofull)
303 return info->fifosize;
305 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
309 /* ? - where has parity gone?? */
310 #define S3C2410_UERSTAT_PARITY (0x1000)
313 s3c24xx_serial_rx_chars(int irq, void *dev_id)
315 struct s3c24xx_uart_port *ourport = dev_id;
316 struct uart_port *port = &ourport->port;
317 struct tty_struct *tty = port->info->tty;
318 unsigned int ufcon, ch, flag, ufstat, uerstat;
321 while (max_count-- > 0) {
322 ufcon = rd_regl(port, S3C2410_UFCON);
323 ufstat = rd_regl(port, S3C2410_UFSTAT);
325 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
328 uerstat = rd_regl(port, S3C2410_UERSTAT);
329 ch = rd_regb(port, S3C2410_URXH);
331 if (port->flags & UPF_CONS_FLOW) {
332 int txe = s3c24xx_serial_txempty_nofifo(port);
334 if (rx_enabled(port)) {
336 rx_enabled(port) = 0;
341 ufcon |= S3C2410_UFCON_RESETRX;
342 wr_regl(port, S3C2410_UFCON, ufcon);
343 rx_enabled(port) = 1;
350 /* insert the character into the buffer */
355 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
356 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
359 /* check for break */
360 if (uerstat & S3C2410_UERSTAT_BREAK) {
363 if (uart_handle_break(port))
367 if (uerstat & S3C2410_UERSTAT_FRAME)
368 port->icount.frame++;
369 if (uerstat & S3C2410_UERSTAT_OVERRUN)
370 port->icount.overrun++;
372 uerstat &= port->read_status_mask;
374 if (uerstat & S3C2410_UERSTAT_BREAK)
376 else if (uerstat & S3C2410_UERSTAT_PARITY)
378 else if (uerstat & ( S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_OVERRUN))
382 if (uart_handle_sysrq_char(port, ch))
385 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN, ch, flag);
390 tty_flip_buffer_push(tty);
396 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
398 struct s3c24xx_uart_port *ourport = id;
399 struct uart_port *port = &ourport->port;
400 struct circ_buf *xmit = &port->info->xmit;
404 wr_regb(port, S3C2410_UTXH, port->x_char);
410 /* if there isnt anything more to transmit, or the uart is now
411 * stopped, disable the uart and exit
414 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
415 s3c24xx_serial_stop_tx(port);
419 /* try and drain the buffer... */
421 while (!uart_circ_empty(xmit) && count-- > 0) {
422 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
425 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
426 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
430 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
431 uart_write_wakeup(port);
433 if (uart_circ_empty(xmit))
434 s3c24xx_serial_stop_tx(port);
440 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
442 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
443 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
444 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
446 if (ufcon & S3C2410_UFCON_FIFOMODE) {
447 if ((ufstat & info->tx_fifomask) != 0 ||
448 (ufstat & info->tx_fifofull))
454 return s3c24xx_serial_txempty_nofifo(port);
457 /* no modem control lines */
458 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
460 unsigned int umstat = rd_regb(port,S3C2410_UMSTAT);
462 if (umstat & S3C2410_UMSTAT_CTS)
463 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
465 return TIOCM_CAR | TIOCM_DSR;
468 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
470 /* todo - possibly remove AFC and do manual CTS */
473 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
478 spin_lock_irqsave(&port->lock, flags);
480 ucon = rd_regl(port, S3C2410_UCON);
483 ucon |= S3C2410_UCON_SBREAK;
485 ucon &= ~S3C2410_UCON_SBREAK;
487 wr_regl(port, S3C2410_UCON, ucon);
489 spin_unlock_irqrestore(&port->lock, flags);
492 static void s3c24xx_serial_shutdown(struct uart_port *port)
494 struct s3c24xx_uart_port *ourport = to_ourport(port);
496 if (ourport->tx_claimed) {
497 free_irq(TX_IRQ(port), ourport);
498 tx_enabled(port) = 0;
499 ourport->tx_claimed = 0;
502 if (ourport->rx_claimed) {
503 free_irq(RX_IRQ(port), ourport);
504 ourport->rx_claimed = 0;
505 rx_enabled(port) = 0;
510 static int s3c24xx_serial_startup(struct uart_port *port)
512 struct s3c24xx_uart_port *ourport = to_ourport(port);
515 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
516 port->mapbase, port->membase);
518 rx_enabled(port) = 1;
520 ret = request_irq(RX_IRQ(port),
521 s3c24xx_serial_rx_chars, 0,
522 s3c24xx_serial_portname(port), ourport);
525 printk(KERN_ERR "cannot get irq %d\n", RX_IRQ(port));
529 ourport->rx_claimed = 1;
531 dbg("requesting tx irq...\n");
533 tx_enabled(port) = 1;
535 ret = request_irq(TX_IRQ(port),
536 s3c24xx_serial_tx_chars, 0,
537 s3c24xx_serial_portname(port), ourport);
540 printk(KERN_ERR "cannot get irq %d\n", TX_IRQ(port));
544 ourport->tx_claimed = 1;
546 dbg("s3c24xx_serial_startup ok\n");
548 /* the port reset code should have done the correct
549 * register setup for the port controls */
554 s3c24xx_serial_shutdown(port);
558 /* power power management control */
560 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
563 struct s3c24xx_uart_port *ourport = to_ourport(port);
567 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
568 clk_disable(ourport->baudclk);
570 clk_disable(ourport->clk);
574 clk_enable(ourport->clk);
576 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
577 clk_enable(ourport->baudclk);
581 printk(KERN_ERR "s3c24xx_serial: unknown pm %d\n", level);
585 /* baud rate calculation
587 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
588 * of different sources, including the peripheral clock ("pclk") and an
589 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
590 * with a programmable extra divisor.
592 * The following code goes through the clock sources, and calculates the
593 * baud clocks (and the resultant actual baud rates) and then tries to
594 * pick the closest one and select that.
601 static struct s3c24xx_uart_clksrc tmp_clksrc = {
609 s3c24xx_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
611 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
613 return (info->get_clksrc)(port, c);
617 s3c24xx_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
619 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
621 return (info->set_clksrc)(port, c);
625 struct s3c24xx_uart_clksrc *clksrc;
631 static int s3c24xx_serial_calcbaud(struct baud_calc *calc,
632 struct uart_port *port,
633 struct s3c24xx_uart_clksrc *clksrc,
638 calc->src = clk_get(port->dev, clksrc->name);
639 if (calc->src == NULL || IS_ERR(calc->src))
642 rate = clk_get_rate(calc->src);
643 rate /= clksrc->divisor;
645 calc->clksrc = clksrc;
646 calc->quot = (rate + (8 * baud)) / (16 * baud);
647 calc->calc = (rate / (calc->quot * 16));
653 static unsigned int s3c24xx_serial_getclk(struct uart_port *port,
654 struct s3c24xx_uart_clksrc **clksrc,
658 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
659 struct s3c24xx_uart_clksrc *clkp;
660 struct baud_calc res[MAX_CLKS];
661 struct baud_calc *resptr, *best, *sptr;
667 if (cfg->clocks_size < 2) {
668 if (cfg->clocks_size == 0)
671 /* check to see if we're sourcing fclk, and if so we're
672 * going to have to update the clock source
675 if (strcmp(clkp->name, "fclk") == 0) {
676 struct s3c24xx_uart_clksrc src;
678 s3c24xx_serial_getsource(port, &src);
680 /* check that the port already using fclk, and if
681 * not, then re-select fclk
684 if (strcmp(src.name, clkp->name) == 0) {
685 s3c24xx_serial_setsource(port, clkp);
686 s3c24xx_serial_getsource(port, &src);
689 clkp->divisor = src.divisor;
692 s3c24xx_serial_calcbaud(res, port, clkp, baud);
698 for (i = 0; i < cfg->clocks_size; i++, clkp++) {
699 if (s3c24xx_serial_calcbaud(resptr, port, clkp, baud))
704 /* ok, we now need to select the best clock we found */
707 unsigned int deviation = (1<<30)|((1<<30)-1);
710 for (sptr = res; sptr < resptr; sptr++) {
712 "found clk %p (%s) quot %d, calc %d\n",
713 sptr->clksrc, sptr->clksrc->name,
714 sptr->quot, sptr->calc);
716 calc_deviation = baud - sptr->calc;
717 if (calc_deviation < 0)
718 calc_deviation = -calc_deviation;
720 if (calc_deviation < deviation) {
722 deviation = calc_deviation;
726 printk(KERN_DEBUG "best %p (deviation %d)\n", best, deviation);
729 printk(KERN_DEBUG "selected clock %p (%s) quot %d, calc %d\n",
730 best->clksrc, best->clksrc->name, best->quot, best->calc);
732 /* store results to pass back */
734 *clksrc = best->clksrc;
740 static void s3c24xx_serial_set_termios(struct uart_port *port,
741 struct ktermios *termios,
742 struct ktermios *old)
744 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
745 struct s3c24xx_uart_port *ourport = to_ourport(port);
746 struct s3c24xx_uart_clksrc *clksrc = NULL;
747 struct clk *clk = NULL;
749 unsigned int baud, quot;
754 * We don't support modem control lines.
756 termios->c_cflag &= ~(HUPCL | CMSPAR);
757 termios->c_cflag |= CLOCAL;
760 * Ask the core to calculate the divisor for us.
763 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
765 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
766 quot = port->custom_divisor;
768 quot = s3c24xx_serial_getclk(port, &clksrc, &clk, baud);
770 /* check to see if we need to change clock source */
772 if (ourport->clksrc != clksrc || ourport->baudclk != clk) {
773 s3c24xx_serial_setsource(port, clksrc);
775 if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
776 clk_disable(ourport->baudclk);
777 ourport->baudclk = NULL;
782 ourport->clksrc = clksrc;
783 ourport->baudclk = clk;
786 switch (termios->c_cflag & CSIZE) {
788 dbg("config: 5bits/char\n");
789 ulcon = S3C2410_LCON_CS5;
792 dbg("config: 6bits/char\n");
793 ulcon = S3C2410_LCON_CS6;
796 dbg("config: 7bits/char\n");
797 ulcon = S3C2410_LCON_CS7;
801 dbg("config: 8bits/char\n");
802 ulcon = S3C2410_LCON_CS8;
806 /* preserve original lcon IR settings */
807 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
809 if (termios->c_cflag & CSTOPB)
810 ulcon |= S3C2410_LCON_STOPB;
812 umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
814 if (termios->c_cflag & PARENB) {
815 if (termios->c_cflag & PARODD)
816 ulcon |= S3C2410_LCON_PODD;
818 ulcon |= S3C2410_LCON_PEVEN;
820 ulcon |= S3C2410_LCON_PNONE;
823 spin_lock_irqsave(&port->lock, flags);
825 dbg("setting ulcon to %08x, brddiv to %d\n", ulcon, quot);
827 wr_regl(port, S3C2410_ULCON, ulcon);
828 wr_regl(port, S3C2410_UBRDIV, quot);
829 wr_regl(port, S3C2410_UMCON, umcon);
831 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
832 rd_regl(port, S3C2410_ULCON),
833 rd_regl(port, S3C2410_UCON),
834 rd_regl(port, S3C2410_UFCON));
837 * Update the per-port timeout.
839 uart_update_timeout(port, termios->c_cflag, baud);
842 * Which character status flags are we interested in?
844 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
845 if (termios->c_iflag & INPCK)
846 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
849 * Which character status flags should we ignore?
851 port->ignore_status_mask = 0;
852 if (termios->c_iflag & IGNPAR)
853 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
854 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
855 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
858 * Ignore all characters if CREAD is not set.
860 if ((termios->c_cflag & CREAD) == 0)
861 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
863 spin_unlock_irqrestore(&port->lock, flags);
866 static const char *s3c24xx_serial_type(struct uart_port *port)
868 switch (port->type) {
880 #define MAP_SIZE (0x100)
882 static void s3c24xx_serial_release_port(struct uart_port *port)
884 release_mem_region(port->mapbase, MAP_SIZE);
887 static int s3c24xx_serial_request_port(struct uart_port *port)
889 const char *name = s3c24xx_serial_portname(port);
890 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
893 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
895 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
897 if (flags & UART_CONFIG_TYPE &&
898 s3c24xx_serial_request_port(port) == 0)
899 port->type = info->type;
903 * verify the new serial_struct (for TIOCSSERIAL).
906 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
908 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
910 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
917 #ifdef CONFIG_SERIAL_S3C2410_CONSOLE
919 static struct console s3c24xx_serial_console;
921 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
923 #define S3C24XX_SERIAL_CONSOLE NULL
926 static struct uart_ops s3c24xx_serial_ops = {
927 .pm = s3c24xx_serial_pm,
928 .tx_empty = s3c24xx_serial_tx_empty,
929 .get_mctrl = s3c24xx_serial_get_mctrl,
930 .set_mctrl = s3c24xx_serial_set_mctrl,
931 .stop_tx = s3c24xx_serial_stop_tx,
932 .start_tx = s3c24xx_serial_start_tx,
933 .stop_rx = s3c24xx_serial_stop_rx,
934 .enable_ms = s3c24xx_serial_enable_ms,
935 .break_ctl = s3c24xx_serial_break_ctl,
936 .startup = s3c24xx_serial_startup,
937 .shutdown = s3c24xx_serial_shutdown,
938 .set_termios = s3c24xx_serial_set_termios,
939 .type = s3c24xx_serial_type,
940 .release_port = s3c24xx_serial_release_port,
941 .request_port = s3c24xx_serial_request_port,
942 .config_port = s3c24xx_serial_config_port,
943 .verify_port = s3c24xx_serial_verify_port,
947 static struct uart_driver s3c24xx_uart_drv = {
948 .owner = THIS_MODULE,
949 .dev_name = "s3c2410_serial",
951 .cons = S3C24XX_SERIAL_CONSOLE,
952 .driver_name = S3C24XX_SERIAL_NAME,
953 .major = S3C24XX_SERIAL_MAJOR,
954 .minor = S3C24XX_SERIAL_MINOR,
957 static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = {
960 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
962 .irq = IRQ_S3CUART_RX0,
965 .ops = &s3c24xx_serial_ops,
966 .flags = UPF_BOOT_AUTOCONF,
972 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock),
974 .irq = IRQ_S3CUART_RX1,
977 .ops = &s3c24xx_serial_ops,
978 .flags = UPF_BOOT_AUTOCONF,
986 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
988 .irq = IRQ_S3CUART_RX2,
991 .ops = &s3c24xx_serial_ops,
992 .flags = UPF_BOOT_AUTOCONF,
999 /* s3c24xx_serial_resetport
1001 * wrapper to call the specific reset for this port (reset the fifos
1005 static inline int s3c24xx_serial_resetport(struct uart_port * port,
1006 struct s3c2410_uartcfg *cfg)
1008 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1010 return (info->reset_port)(port, cfg);
1013 /* s3c24xx_serial_init_port
1015 * initialise a single serial port from the platform device given
1018 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
1019 struct s3c24xx_uart_info *info,
1020 struct platform_device *platdev)
1022 struct uart_port *port = &ourport->port;
1023 struct s3c2410_uartcfg *cfg;
1024 struct resource *res;
1027 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1029 if (platdev == NULL)
1032 cfg = s3c24xx_dev_to_cfg(&platdev->dev);
1034 if (port->mapbase != 0)
1037 if (cfg->hwport > 3)
1040 /* setup info for port */
1041 port->dev = &platdev->dev;
1042 ourport->info = info;
1044 /* copy the info in from provided structure */
1045 ourport->port.fifosize = info->fifosize;
1047 dbg("s3c24xx_serial_init_port: %p (hw %d)...\n", port, cfg->hwport);
1051 if (cfg->uart_flags & UPF_CONS_FLOW) {
1052 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1053 port->flags |= UPF_CONS_FLOW;
1056 /* sort our the physical and virtual addresses for each UART */
1058 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1060 printk(KERN_ERR "failed to find memory resource for uart\n");
1064 dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
1066 port->mapbase = res->start;
1067 port->membase = S3C24XX_VA_UART + (res->start - S3C24XX_PA_UART);
1068 ret = platform_get_irq(platdev, 0);
1074 ourport->clk = clk_get(&platdev->dev, "uart");
1076 dbg("port: map=%08x, mem=%08x, irq=%d, clock=%ld\n",
1077 port->mapbase, port->membase, port->irq, port->uartclk);
1079 /* reset the fifos (and setup the uart) */
1080 s3c24xx_serial_resetport(port, cfg);
1084 /* Device driver serial port probe */
1086 static int probe_index = 0;
1088 static int s3c24xx_serial_probe(struct platform_device *dev,
1089 struct s3c24xx_uart_info *info)
1091 struct s3c24xx_uart_port *ourport;
1094 dbg("s3c24xx_serial_probe(%p, %p) %d\n", dev, info, probe_index);
1096 ourport = &s3c24xx_serial_ports[probe_index];
1099 dbg("%s: initialising port %p...\n", __func__, ourport);
1101 ret = s3c24xx_serial_init_port(ourport, info, dev);
1105 dbg("%s: adding port\n", __func__);
1106 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1107 platform_set_drvdata(dev, &ourport->port);
1115 static int s3c24xx_serial_remove(struct platform_device *dev)
1117 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1120 uart_remove_one_port(&s3c24xx_uart_drv, port);
1125 /* UART power management code */
1129 static int s3c24xx_serial_suspend(struct platform_device *dev, pm_message_t state)
1131 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1134 uart_suspend_port(&s3c24xx_uart_drv, port);
1139 static int s3c24xx_serial_resume(struct platform_device *dev)
1141 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1142 struct s3c24xx_uart_port *ourport = to_ourport(port);
1145 clk_enable(ourport->clk);
1146 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1147 clk_disable(ourport->clk);
1149 uart_resume_port(&s3c24xx_uart_drv, port);
1156 #define s3c24xx_serial_suspend NULL
1157 #define s3c24xx_serial_resume NULL
1160 static int s3c24xx_serial_init(struct platform_driver *drv,
1161 struct s3c24xx_uart_info *info)
1163 dbg("s3c24xx_serial_init(%p,%p)\n", drv, info);
1164 return platform_driver_register(drv);
1168 /* now comes the code to initialise either the s3c2410 or s3c2440 serial
1172 /* cpu specific variations on the serial port support */
1174 #ifdef CONFIG_CPU_S3C2400
1176 static int s3c2400_serial_getsource(struct uart_port *port,
1177 struct s3c24xx_uart_clksrc *clk)
1185 static int s3c2400_serial_setsource(struct uart_port *port,
1186 struct s3c24xx_uart_clksrc *clk)
1191 static int s3c2400_serial_resetport(struct uart_port *port,
1192 struct s3c2410_uartcfg *cfg)
1194 dbg("s3c2400_serial_resetport: port=%p (%08lx), cfg=%p\n",
1195 port, port->mapbase, cfg);
1197 wr_regl(port, S3C2410_UCON, cfg->ucon);
1198 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1200 /* reset both fifos */
1202 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1203 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1208 static struct s3c24xx_uart_info s3c2400_uart_inf = {
1209 .name = "Samsung S3C2400 UART",
1210 .type = PORT_S3C2400,
1212 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1213 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1214 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1215 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1216 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1217 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1218 .get_clksrc = s3c2400_serial_getsource,
1219 .set_clksrc = s3c2400_serial_setsource,
1220 .reset_port = s3c2400_serial_resetport,
1223 static int s3c2400_serial_probe(struct platform_device *dev)
1225 return s3c24xx_serial_probe(dev, &s3c2400_uart_inf);
1228 static struct platform_driver s3c2400_serial_drv = {
1229 .probe = s3c2400_serial_probe,
1230 .remove = s3c24xx_serial_remove,
1231 .suspend = s3c24xx_serial_suspend,
1232 .resume = s3c24xx_serial_resume,
1234 .name = "s3c2400-uart",
1235 .owner = THIS_MODULE,
1239 static inline int s3c2400_serial_init(void)
1241 return s3c24xx_serial_init(&s3c2400_serial_drv, &s3c2400_uart_inf);
1244 static inline void s3c2400_serial_exit(void)
1246 platform_driver_unregister(&s3c2400_serial_drv);
1249 #define s3c2400_uart_inf_at &s3c2400_uart_inf
1252 static inline int s3c2400_serial_init(void)
1257 static inline void s3c2400_serial_exit(void)
1261 #define s3c2400_uart_inf_at NULL
1263 #endif /* CONFIG_CPU_S3C2400 */
1265 /* S3C2410 support */
1267 #ifdef CONFIG_CPU_S3C2410
1269 static int s3c2410_serial_setsource(struct uart_port *port,
1270 struct s3c24xx_uart_clksrc *clk)
1272 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1274 if (strcmp(clk->name, "uclk") == 0)
1275 ucon |= S3C2410_UCON_UCLK;
1277 ucon &= ~S3C2410_UCON_UCLK;
1279 wr_regl(port, S3C2410_UCON, ucon);
1283 static int s3c2410_serial_getsource(struct uart_port *port,
1284 struct s3c24xx_uart_clksrc *clk)
1286 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1289 clk->name = (ucon & S3C2410_UCON_UCLK) ? "uclk" : "pclk";
1294 static int s3c2410_serial_resetport(struct uart_port *port,
1295 struct s3c2410_uartcfg *cfg)
1297 dbg("s3c2410_serial_resetport: port=%p (%08lx), cfg=%p\n",
1298 port, port->mapbase, cfg);
1300 wr_regl(port, S3C2410_UCON, cfg->ucon);
1301 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1303 /* reset both fifos */
1305 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1306 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1311 static struct s3c24xx_uart_info s3c2410_uart_inf = {
1312 .name = "Samsung S3C2410 UART",
1313 .type = PORT_S3C2410,
1315 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1316 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1317 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1318 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1319 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1320 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1321 .get_clksrc = s3c2410_serial_getsource,
1322 .set_clksrc = s3c2410_serial_setsource,
1323 .reset_port = s3c2410_serial_resetport,
1326 /* device management */
1328 static int s3c2410_serial_probe(struct platform_device *dev)
1330 return s3c24xx_serial_probe(dev, &s3c2410_uart_inf);
1333 static struct platform_driver s3c2410_serial_drv = {
1334 .probe = s3c2410_serial_probe,
1335 .remove = s3c24xx_serial_remove,
1336 .suspend = s3c24xx_serial_suspend,
1337 .resume = s3c24xx_serial_resume,
1339 .name = "s3c2410-uart",
1340 .owner = THIS_MODULE,
1344 static inline int s3c2410_serial_init(void)
1346 return s3c24xx_serial_init(&s3c2410_serial_drv, &s3c2410_uart_inf);
1349 static inline void s3c2410_serial_exit(void)
1351 platform_driver_unregister(&s3c2410_serial_drv);
1354 #define s3c2410_uart_inf_at &s3c2410_uart_inf
1357 static inline int s3c2410_serial_init(void)
1362 static inline void s3c2410_serial_exit(void)
1366 #define s3c2410_uart_inf_at NULL
1368 #endif /* CONFIG_CPU_S3C2410 */
1370 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
1372 static int s3c2440_serial_setsource(struct uart_port *port,
1373 struct s3c24xx_uart_clksrc *clk)
1375 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1377 // todo - proper fclk<>nonfclk switch //
1379 ucon &= ~S3C2440_UCON_CLKMASK;
1381 if (strcmp(clk->name, "uclk") == 0)
1382 ucon |= S3C2440_UCON_UCLK;
1383 else if (strcmp(clk->name, "pclk") == 0)
1384 ucon |= S3C2440_UCON_PCLK;
1385 else if (strcmp(clk->name, "fclk") == 0)
1386 ucon |= S3C2440_UCON_FCLK;
1388 printk(KERN_ERR "unknown clock source %s\n", clk->name);
1392 wr_regl(port, S3C2410_UCON, ucon);
1397 static int s3c2440_serial_getsource(struct uart_port *port,
1398 struct s3c24xx_uart_clksrc *clk)
1400 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1401 unsigned long ucon0, ucon1, ucon2;
1403 switch (ucon & S3C2440_UCON_CLKMASK) {
1404 case S3C2440_UCON_UCLK:
1409 case S3C2440_UCON_PCLK:
1410 case S3C2440_UCON_PCLK2:
1415 case S3C2440_UCON_FCLK:
1416 /* the fun of calculating the uart divisors on
1419 ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
1420 ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
1421 ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
1423 printk("ucons: %08lx, %08lx, %08lx\n", ucon0, ucon1, ucon2);
1425 ucon0 &= S3C2440_UCON0_DIVMASK;
1426 ucon1 &= S3C2440_UCON1_DIVMASK;
1427 ucon2 &= S3C2440_UCON2_DIVMASK;
1430 clk->divisor = ucon0 >> S3C2440_UCON_DIVSHIFT;
1432 } else if (ucon1 != 0) {
1433 clk->divisor = ucon1 >> S3C2440_UCON_DIVSHIFT;
1435 } else if (ucon2 != 0) {
1436 clk->divisor = ucon2 >> S3C2440_UCON_DIVSHIFT;
1439 /* manual calims 44, seems to be 9 */
1450 static int s3c2440_serial_resetport(struct uart_port *port,
1451 struct s3c2410_uartcfg *cfg)
1453 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1455 dbg("s3c2440_serial_resetport: port=%p (%08lx), cfg=%p\n",
1456 port, port->mapbase, cfg);
1458 /* ensure we don't change the clock settings... */
1460 ucon &= (S3C2440_UCON0_DIVMASK | (3<<10));
1462 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1463 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1465 /* reset both fifos */
1467 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1468 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1473 static struct s3c24xx_uart_info s3c2440_uart_inf = {
1474 .name = "Samsung S3C2440 UART",
1475 .type = PORT_S3C2440,
1477 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1478 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1479 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1480 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1481 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1482 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1483 .get_clksrc = s3c2440_serial_getsource,
1484 .set_clksrc = s3c2440_serial_setsource,
1485 .reset_port = s3c2440_serial_resetport,
1488 /* device management */
1490 static int s3c2440_serial_probe(struct platform_device *dev)
1492 dbg("s3c2440_serial_probe: dev=%p\n", dev);
1493 return s3c24xx_serial_probe(dev, &s3c2440_uart_inf);
1496 static struct platform_driver s3c2440_serial_drv = {
1497 .probe = s3c2440_serial_probe,
1498 .remove = s3c24xx_serial_remove,
1499 .suspend = s3c24xx_serial_suspend,
1500 .resume = s3c24xx_serial_resume,
1502 .name = "s3c2440-uart",
1503 .owner = THIS_MODULE,
1508 static inline int s3c2440_serial_init(void)
1510 return s3c24xx_serial_init(&s3c2440_serial_drv, &s3c2440_uart_inf);
1513 static inline void s3c2440_serial_exit(void)
1515 platform_driver_unregister(&s3c2440_serial_drv);
1518 #define s3c2440_uart_inf_at &s3c2440_uart_inf
1521 static inline int s3c2440_serial_init(void)
1526 static inline void s3c2440_serial_exit(void)
1530 #define s3c2440_uart_inf_at NULL
1531 #endif /* CONFIG_CPU_S3C2440 */
1533 #if defined(CONFIG_CPU_S3C2412)
1535 static int s3c2412_serial_setsource(struct uart_port *port,
1536 struct s3c24xx_uart_clksrc *clk)
1538 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1540 ucon &= ~S3C2412_UCON_CLKMASK;
1542 if (strcmp(clk->name, "uclk") == 0)
1543 ucon |= S3C2440_UCON_UCLK;
1544 else if (strcmp(clk->name, "pclk") == 0)
1545 ucon |= S3C2440_UCON_PCLK;
1546 else if (strcmp(clk->name, "usysclk") == 0)
1547 ucon |= S3C2412_UCON_USYSCLK;
1549 printk(KERN_ERR "unknown clock source %s\n", clk->name);
1553 wr_regl(port, S3C2410_UCON, ucon);
1558 static int s3c2412_serial_getsource(struct uart_port *port,
1559 struct s3c24xx_uart_clksrc *clk)
1561 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1563 switch (ucon & S3C2412_UCON_CLKMASK) {
1564 case S3C2412_UCON_UCLK:
1569 case S3C2412_UCON_PCLK:
1570 case S3C2412_UCON_PCLK2:
1575 case S3C2412_UCON_USYSCLK:
1577 clk->name = "usysclk";
1584 static int s3c2412_serial_resetport(struct uart_port *port,
1585 struct s3c2410_uartcfg *cfg)
1587 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1589 dbg("%s: port=%p (%08lx), cfg=%p\n",
1590 __func__, port, port->mapbase, cfg);
1592 /* ensure we don't change the clock settings... */
1594 ucon &= S3C2412_UCON_CLKMASK;
1596 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1597 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1599 /* reset both fifos */
1601 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1602 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1607 static struct s3c24xx_uart_info s3c2412_uart_inf = {
1608 .name = "Samsung S3C2412 UART",
1609 .type = PORT_S3C2412,
1611 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1612 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1613 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1614 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1615 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1616 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1617 .get_clksrc = s3c2412_serial_getsource,
1618 .set_clksrc = s3c2412_serial_setsource,
1619 .reset_port = s3c2412_serial_resetport,
1622 /* device management */
1624 static int s3c2412_serial_probe(struct platform_device *dev)
1626 dbg("s3c2440_serial_probe: dev=%p\n", dev);
1627 return s3c24xx_serial_probe(dev, &s3c2412_uart_inf);
1630 static struct platform_driver s3c2412_serial_drv = {
1631 .probe = s3c2412_serial_probe,
1632 .remove = s3c24xx_serial_remove,
1633 .suspend = s3c24xx_serial_suspend,
1634 .resume = s3c24xx_serial_resume,
1636 .name = "s3c2412-uart",
1637 .owner = THIS_MODULE,
1642 static inline int s3c2412_serial_init(void)
1644 return s3c24xx_serial_init(&s3c2412_serial_drv, &s3c2412_uart_inf);
1647 static inline void s3c2412_serial_exit(void)
1649 platform_driver_unregister(&s3c2412_serial_drv);
1652 #define s3c2412_uart_inf_at &s3c2412_uart_inf
1655 static inline int s3c2412_serial_init(void)
1660 static inline void s3c2412_serial_exit(void)
1664 #define s3c2412_uart_inf_at NULL
1665 #endif /* CONFIG_CPU_S3C2440 */
1668 /* module initialisation code */
1670 static int __init s3c24xx_serial_modinit(void)
1674 ret = uart_register_driver(&s3c24xx_uart_drv);
1676 printk(KERN_ERR "failed to register UART driver\n");
1680 s3c2400_serial_init();
1681 s3c2410_serial_init();
1682 s3c2412_serial_init();
1683 s3c2440_serial_init();
1688 static void __exit s3c24xx_serial_modexit(void)
1690 s3c2400_serial_exit();
1691 s3c2410_serial_exit();
1692 s3c2412_serial_exit();
1693 s3c2440_serial_exit();
1695 uart_unregister_driver(&s3c24xx_uart_drv);
1699 module_init(s3c24xx_serial_modinit);
1700 module_exit(s3c24xx_serial_modexit);
1704 #ifdef CONFIG_SERIAL_S3C2410_CONSOLE
1706 static struct uart_port *cons_uart;
1709 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1711 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1712 unsigned long ufstat, utrstat;
1714 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1715 /* fifo mode - check ammount of data in fifo registers... */
1717 ufstat = rd_regl(port, S3C2410_UFSTAT);
1718 return (ufstat & info->tx_fifofull) ? 0 : 1;
1721 /* in non-fifo mode, we go and use the tx buffer empty */
1723 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1724 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1728 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
1730 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1731 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1733 wr_regb(cons_uart, S3C2410_UTXH, ch);
1737 s3c24xx_serial_console_write(struct console *co, const char *s,
1740 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
1744 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1745 int *parity, int *bits)
1747 struct s3c24xx_uart_clksrc clksrc;
1751 unsigned int ubrdiv;
1754 ulcon = rd_regl(port, S3C2410_ULCON);
1755 ucon = rd_regl(port, S3C2410_UCON);
1756 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1758 dbg("s3c24xx_serial_get_options: port=%p\n"
1759 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1760 port, ulcon, ucon, ubrdiv);
1762 if ((ucon & 0xf) != 0) {
1763 /* consider the serial port configured if the tx/rx mode set */
1765 switch (ulcon & S3C2410_LCON_CSMASK) {
1766 case S3C2410_LCON_CS5:
1769 case S3C2410_LCON_CS6:
1772 case S3C2410_LCON_CS7:
1776 case S3C2410_LCON_CS8:
1781 switch (ulcon & S3C2410_LCON_PMASK) {
1782 case S3C2410_LCON_PEVEN:
1786 case S3C2410_LCON_PODD:
1790 case S3C2410_LCON_PNONE:
1795 /* now calculate the baud rate */
1797 s3c24xx_serial_getsource(port, &clksrc);
1799 clk = clk_get(port->dev, clksrc.name);
1800 if (!IS_ERR(clk) && clk != NULL)
1801 rate = clk_get_rate(clk) / clksrc.divisor;
1806 *baud = rate / ( 16 * (ubrdiv + 1));
1807 dbg("calculated baud %d\n", *baud);
1812 /* s3c24xx_serial_init_ports
1814 * initialise the serial ports from the machine provided initialisation
1818 static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info *info)
1820 struct s3c24xx_uart_port *ptr = s3c24xx_serial_ports;
1821 struct platform_device **platdev_ptr;
1824 dbg("s3c24xx_serial_init_ports: initialising ports...\n");
1826 platdev_ptr = s3c24xx_uart_devs;
1828 for (i = 0; i < NR_PORTS; i++, ptr++, platdev_ptr++) {
1829 s3c24xx_serial_init_port(ptr, info, *platdev_ptr);
1836 s3c24xx_serial_console_setup(struct console *co, char *options)
1838 struct uart_port *port;
1844 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1845 co, co->index, options);
1847 /* is this a valid port */
1849 if (co->index == -1 || co->index >= NR_PORTS)
1852 port = &s3c24xx_serial_ports[co->index].port;
1854 /* is the port configured? */
1856 if (port->mapbase == 0x0) {
1858 port = &s3c24xx_serial_ports[co->index].port;
1863 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1866 * Check whether an invalid uart number has been specified, and
1867 * if so, search for the first available port that does have
1871 uart_parse_options(options, &baud, &parity, &bits, &flow);
1873 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1875 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1877 return uart_set_options(port, co, baud, parity, bits, flow);
1880 /* s3c24xx_serial_initconsole
1882 * initialise the console from one of the uart drivers
1885 static struct console s3c24xx_serial_console =
1887 .name = S3C24XX_SERIAL_NAME,
1888 .device = uart_console_device,
1889 .flags = CON_PRINTBUFFER,
1891 .write = s3c24xx_serial_console_write,
1892 .setup = s3c24xx_serial_console_setup
1895 static int s3c24xx_serial_initconsole(void)
1897 struct s3c24xx_uart_info *info;
1898 struct platform_device *dev = s3c24xx_uart_devs[0];
1900 dbg("s3c24xx_serial_initconsole\n");
1902 /* select driver based on the cpu */
1905 printk(KERN_ERR "s3c24xx: no devices for console init\n");
1909 if (strcmp(dev->name, "s3c2400-uart") == 0) {
1910 info = s3c2400_uart_inf_at;
1911 } else if (strcmp(dev->name, "s3c2410-uart") == 0) {
1912 info = s3c2410_uart_inf_at;
1913 } else if (strcmp(dev->name, "s3c2440-uart") == 0) {
1914 info = s3c2440_uart_inf_at;
1915 } else if (strcmp(dev->name, "s3c2412-uart") == 0) {
1916 info = s3c2412_uart_inf_at;
1918 printk(KERN_ERR "s3c24xx: no driver for %s\n", dev->name);
1923 printk(KERN_ERR "s3c24xx: no driver for console\n");
1927 s3c24xx_serial_console.data = &s3c24xx_uart_drv;
1928 s3c24xx_serial_init_ports(info);
1930 register_console(&s3c24xx_serial_console);
1934 console_initcall(s3c24xx_serial_initconsole);
1936 #endif /* CONFIG_SERIAL_S3C2410_CONSOLE */
1938 MODULE_LICENSE("GPL");
1939 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1940 MODULE_DESCRIPTION("Samsung S3C2410/S3C2440/S3C2412 Serial port driver");
1941 MODULE_ALIAS("platform:s3c2400-uart");
1942 MODULE_ALIAS("platform:s3c2410-uart");
1943 MODULE_ALIAS("platform:s3c2412-uart");
1944 MODULE_ALIAS("platform:s3c2440-uart");