1 /* linux/drivers/serial/s3c2410.c
3 * Driver for Samsung SoC onboard UARTs.
5 * Ben Dooks, Copyright (c) 2003-2005 Simtec Electronics
6 * http://armlinux.simtec.co.uk/
9 /* Note on 2440 fclk clock source handling
11 * Whilst it is possible to use the fclk as clock source, the method
12 * of properly switching too/from this is currently un-implemented, so
13 * whichever way is configured at startup is the one that will be used.
16 /* Hote on 2410 error handling
18 * The s3c2410 manual has a love/hate affair with the contents of the
19 * UERSTAT register in the UART blocks, and keeps marking some of the
20 * error bits as reserved. Having checked with the s3c2410x01,
21 * it copes with BREAKs properly, so I am happy to ignore the RESERVED
22 * feature from the latter versions of the manual.
24 * If it becomes aparrent that latter versions of the 2410 remove these
25 * bits, then action will have to be taken to differentiate the versions
26 * and change the policy on BREAK
32 #if defined(CONFIG_SERIAL_S3C2410_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
36 #include <linux/module.h>
37 #include <linux/ioport.h>
38 #include <linux/platform_device.h>
39 #include <linux/init.h>
40 #include <linux/sysrq.h>
41 #include <linux/console.h>
42 #include <linux/tty.h>
43 #include <linux/tty_flip.h>
44 #include <linux/serial_core.h>
45 #include <linux/serial.h>
46 #include <linux/delay.h>
47 #include <linux/clk.h>
52 #include <asm/hardware.h>
54 #include <asm/plat-s3c/regs-serial.h>
55 #include <asm/arch/regs-gpio.h>
59 struct s3c24xx_uart_info {
62 unsigned int fifosize;
63 unsigned long rx_fifomask;
64 unsigned long rx_fifoshift;
65 unsigned long rx_fifofull;
66 unsigned long tx_fifomask;
67 unsigned long tx_fifoshift;
68 unsigned long tx_fifofull;
70 /* clock source control */
72 int (*get_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
73 int (*set_clksrc)(struct uart_port *, struct s3c24xx_uart_clksrc *clk);
76 int (*reset_port)(struct uart_port *, struct s3c2410_uartcfg *);
79 struct s3c24xx_uart_port {
80 unsigned char rx_claimed;
81 unsigned char tx_claimed;
83 struct s3c24xx_uart_info *info;
84 struct s3c24xx_uart_clksrc *clksrc;
87 struct uart_port port;
91 /* configuration defines */
95 /* send debug to the low-level output routines */
97 extern void printascii(const char *);
100 s3c24xx_serial_dbg(const char *fmt, ...)
106 vsprintf(buff, fmt, va);
112 #define dbg(x...) s3c24xx_serial_dbg(x)
115 #define dbg(x...) printk(KERN_DEBUG "s3c24xx: ");
118 #define dbg(x...) do {} while(0)
121 /* UART name and device definitions */
123 #define S3C24XX_SERIAL_NAME "ttySAC"
124 #define S3C24XX_SERIAL_MAJOR 204
125 #define S3C24XX_SERIAL_MINOR 64
128 /* conversion functions */
130 #define s3c24xx_dev_to_port(__dev) (struct uart_port *)dev_get_drvdata(__dev)
131 #define s3c24xx_dev_to_cfg(__dev) (struct s3c2410_uartcfg *)((__dev)->platform_data)
133 /* we can support 3 uarts, but not always use them */
135 #ifdef CONFIG_CPU_S3C2400
141 /* port irq numbers */
143 #define TX_IRQ(port) ((port)->irq + 1)
144 #define RX_IRQ(port) ((port)->irq)
146 /* register access controls */
148 #define portaddr(port, reg) ((port)->membase + (reg))
150 #define rd_regb(port, reg) (__raw_readb(portaddr(port, reg)))
151 #define rd_regl(port, reg) (__raw_readl(portaddr(port, reg)))
153 #define wr_regb(port, reg, val) \
154 do { __raw_writeb(val, portaddr(port, reg)); } while(0)
156 #define wr_regl(port, reg, val) \
157 do { __raw_writel(val, portaddr(port, reg)); } while(0)
159 /* macros to change one thing to another */
161 #define tx_enabled(port) ((port)->unused[0])
162 #define rx_enabled(port) ((port)->unused[1])
164 /* flag to ignore all characters comming in */
165 #define RXSTAT_DUMMY_READ (0x10000000)
167 static inline struct s3c24xx_uart_port *to_ourport(struct uart_port *port)
169 return container_of(port, struct s3c24xx_uart_port, port);
172 /* translate a port to the device name */
174 static inline const char *s3c24xx_serial_portname(struct uart_port *port)
176 return to_platform_device(port->dev)->name;
179 static int s3c24xx_serial_txempty_nofifo(struct uart_port *port)
181 return (rd_regl(port, S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE);
184 static void s3c24xx_serial_rx_enable(struct uart_port *port)
187 unsigned int ucon, ufcon;
190 spin_lock_irqsave(&port->lock, flags);
192 while (--count && !s3c24xx_serial_txempty_nofifo(port))
195 ufcon = rd_regl(port, S3C2410_UFCON);
196 ufcon |= S3C2410_UFCON_RESETRX;
197 wr_regl(port, S3C2410_UFCON, ufcon);
199 ucon = rd_regl(port, S3C2410_UCON);
200 ucon |= S3C2410_UCON_RXIRQMODE;
201 wr_regl(port, S3C2410_UCON, ucon);
203 rx_enabled(port) = 1;
204 spin_unlock_irqrestore(&port->lock, flags);
207 static void s3c24xx_serial_rx_disable(struct uart_port *port)
212 spin_lock_irqsave(&port->lock, flags);
214 ucon = rd_regl(port, S3C2410_UCON);
215 ucon &= ~S3C2410_UCON_RXIRQMODE;
216 wr_regl(port, S3C2410_UCON, ucon);
218 rx_enabled(port) = 0;
219 spin_unlock_irqrestore(&port->lock, flags);
222 static void s3c24xx_serial_stop_tx(struct uart_port *port)
224 if (tx_enabled(port)) {
225 disable_irq(TX_IRQ(port));
226 tx_enabled(port) = 0;
227 if (port->flags & UPF_CONS_FLOW)
228 s3c24xx_serial_rx_enable(port);
232 static void s3c24xx_serial_start_tx(struct uart_port *port)
234 if (!tx_enabled(port)) {
235 if (port->flags & UPF_CONS_FLOW)
236 s3c24xx_serial_rx_disable(port);
238 enable_irq(TX_IRQ(port));
239 tx_enabled(port) = 1;
244 static void s3c24xx_serial_stop_rx(struct uart_port *port)
246 if (rx_enabled(port)) {
247 dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
248 disable_irq(RX_IRQ(port));
249 rx_enabled(port) = 0;
253 static void s3c24xx_serial_enable_ms(struct uart_port *port)
257 static inline struct s3c24xx_uart_info *s3c24xx_port_to_info(struct uart_port *port)
259 return to_ourport(port)->info;
262 static inline struct s3c2410_uartcfg *s3c24xx_port_to_cfg(struct uart_port *port)
264 if (port->dev == NULL)
267 return (struct s3c2410_uartcfg *)port->dev->platform_data;
270 static int s3c24xx_serial_rx_fifocnt(struct s3c24xx_uart_port *ourport,
271 unsigned long ufstat)
273 struct s3c24xx_uart_info *info = ourport->info;
275 if (ufstat & info->rx_fifofull)
276 return info->fifosize;
278 return (ufstat & info->rx_fifomask) >> info->rx_fifoshift;
282 /* ? - where has parity gone?? */
283 #define S3C2410_UERSTAT_PARITY (0x1000)
286 s3c24xx_serial_rx_chars(int irq, void *dev_id)
288 struct s3c24xx_uart_port *ourport = dev_id;
289 struct uart_port *port = &ourport->port;
290 struct tty_struct *tty = port->info->tty;
291 unsigned int ufcon, ch, flag, ufstat, uerstat;
294 while (max_count-- > 0) {
295 ufcon = rd_regl(port, S3C2410_UFCON);
296 ufstat = rd_regl(port, S3C2410_UFSTAT);
298 if (s3c24xx_serial_rx_fifocnt(ourport, ufstat) == 0)
301 uerstat = rd_regl(port, S3C2410_UERSTAT);
302 ch = rd_regb(port, S3C2410_URXH);
304 if (port->flags & UPF_CONS_FLOW) {
305 int txe = s3c24xx_serial_txempty_nofifo(port);
307 if (rx_enabled(port)) {
309 rx_enabled(port) = 0;
314 ufcon |= S3C2410_UFCON_RESETRX;
315 wr_regl(port, S3C2410_UFCON, ufcon);
316 rx_enabled(port) = 1;
323 /* insert the character into the buffer */
328 if (unlikely(uerstat & S3C2410_UERSTAT_ANY)) {
329 dbg("rxerr: port ch=0x%02x, rxs=0x%08x\n",
332 /* check for break */
333 if (uerstat & S3C2410_UERSTAT_BREAK) {
336 if (uart_handle_break(port))
340 if (uerstat & S3C2410_UERSTAT_FRAME)
341 port->icount.frame++;
342 if (uerstat & S3C2410_UERSTAT_OVERRUN)
343 port->icount.overrun++;
345 uerstat &= port->read_status_mask;
347 if (uerstat & S3C2410_UERSTAT_BREAK)
349 else if (uerstat & S3C2410_UERSTAT_PARITY)
351 else if (uerstat & ( S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_OVERRUN))
355 if (uart_handle_sysrq_char(port, ch))
358 uart_insert_char(port, uerstat, S3C2410_UERSTAT_OVERRUN, ch, flag);
363 tty_flip_buffer_push(tty);
369 static irqreturn_t s3c24xx_serial_tx_chars(int irq, void *id)
371 struct s3c24xx_uart_port *ourport = id;
372 struct uart_port *port = &ourport->port;
373 struct circ_buf *xmit = &port->info->xmit;
377 wr_regb(port, S3C2410_UTXH, port->x_char);
383 /* if there isnt anything more to transmit, or the uart is now
384 * stopped, disable the uart and exit
387 if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
388 s3c24xx_serial_stop_tx(port);
392 /* try and drain the buffer... */
394 while (!uart_circ_empty(xmit) && count-- > 0) {
395 if (rd_regl(port, S3C2410_UFSTAT) & ourport->info->tx_fifofull)
398 wr_regb(port, S3C2410_UTXH, xmit->buf[xmit->tail]);
399 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
403 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
404 uart_write_wakeup(port);
406 if (uart_circ_empty(xmit))
407 s3c24xx_serial_stop_tx(port);
413 static unsigned int s3c24xx_serial_tx_empty(struct uart_port *port)
415 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
416 unsigned long ufstat = rd_regl(port, S3C2410_UFSTAT);
417 unsigned long ufcon = rd_regl(port, S3C2410_UFCON);
419 if (ufcon & S3C2410_UFCON_FIFOMODE) {
420 if ((ufstat & info->tx_fifomask) != 0 ||
421 (ufstat & info->tx_fifofull))
427 return s3c24xx_serial_txempty_nofifo(port);
430 /* no modem control lines */
431 static unsigned int s3c24xx_serial_get_mctrl(struct uart_port *port)
433 unsigned int umstat = rd_regb(port,S3C2410_UMSTAT);
435 if (umstat & S3C2410_UMSTAT_CTS)
436 return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
438 return TIOCM_CAR | TIOCM_DSR;
441 static void s3c24xx_serial_set_mctrl(struct uart_port *port, unsigned int mctrl)
443 /* todo - possibly remove AFC and do manual CTS */
446 static void s3c24xx_serial_break_ctl(struct uart_port *port, int break_state)
451 spin_lock_irqsave(&port->lock, flags);
453 ucon = rd_regl(port, S3C2410_UCON);
456 ucon |= S3C2410_UCON_SBREAK;
458 ucon &= ~S3C2410_UCON_SBREAK;
460 wr_regl(port, S3C2410_UCON, ucon);
462 spin_unlock_irqrestore(&port->lock, flags);
465 static void s3c24xx_serial_shutdown(struct uart_port *port)
467 struct s3c24xx_uart_port *ourport = to_ourport(port);
469 if (ourport->tx_claimed) {
470 free_irq(TX_IRQ(port), ourport);
471 tx_enabled(port) = 0;
472 ourport->tx_claimed = 0;
475 if (ourport->rx_claimed) {
476 free_irq(RX_IRQ(port), ourport);
477 ourport->rx_claimed = 0;
478 rx_enabled(port) = 0;
483 static int s3c24xx_serial_startup(struct uart_port *port)
485 struct s3c24xx_uart_port *ourport = to_ourport(port);
488 dbg("s3c24xx_serial_startup: port=%p (%08lx,%p)\n",
489 port->mapbase, port->membase);
491 rx_enabled(port) = 1;
493 ret = request_irq(RX_IRQ(port),
494 s3c24xx_serial_rx_chars, 0,
495 s3c24xx_serial_portname(port), ourport);
498 printk(KERN_ERR "cannot get irq %d\n", RX_IRQ(port));
502 ourport->rx_claimed = 1;
504 dbg("requesting tx irq...\n");
506 tx_enabled(port) = 1;
508 ret = request_irq(TX_IRQ(port),
509 s3c24xx_serial_tx_chars, 0,
510 s3c24xx_serial_portname(port), ourport);
513 printk(KERN_ERR "cannot get irq %d\n", TX_IRQ(port));
517 ourport->tx_claimed = 1;
519 dbg("s3c24xx_serial_startup ok\n");
521 /* the port reset code should have done the correct
522 * register setup for the port controls */
527 s3c24xx_serial_shutdown(port);
531 /* power power management control */
533 static void s3c24xx_serial_pm(struct uart_port *port, unsigned int level,
536 struct s3c24xx_uart_port *ourport = to_ourport(port);
540 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
541 clk_disable(ourport->baudclk);
543 clk_disable(ourport->clk);
547 clk_enable(ourport->clk);
549 if (!IS_ERR(ourport->baudclk) && ourport->baudclk != NULL)
550 clk_enable(ourport->baudclk);
554 printk(KERN_ERR "s3c24xx_serial: unknown pm %d\n", level);
558 /* baud rate calculation
560 * The UARTs on the S3C2410/S3C2440 can take their clocks from a number
561 * of different sources, including the peripheral clock ("pclk") and an
562 * external clock ("uclk"). The S3C2440 also adds the core clock ("fclk")
563 * with a programmable extra divisor.
565 * The following code goes through the clock sources, and calculates the
566 * baud clocks (and the resultant actual baud rates) and then tries to
567 * pick the closest one and select that.
574 static struct s3c24xx_uart_clksrc tmp_clksrc = {
582 s3c24xx_serial_getsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
584 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
586 return (info->get_clksrc)(port, c);
590 s3c24xx_serial_setsource(struct uart_port *port, struct s3c24xx_uart_clksrc *c)
592 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
594 return (info->set_clksrc)(port, c);
598 struct s3c24xx_uart_clksrc *clksrc;
604 static int s3c24xx_serial_calcbaud(struct baud_calc *calc,
605 struct uart_port *port,
606 struct s3c24xx_uart_clksrc *clksrc,
611 calc->src = clk_get(port->dev, clksrc->name);
612 if (calc->src == NULL || IS_ERR(calc->src))
615 rate = clk_get_rate(calc->src);
616 rate /= clksrc->divisor;
618 calc->clksrc = clksrc;
619 calc->quot = (rate + (8 * baud)) / (16 * baud);
620 calc->calc = (rate / (calc->quot * 16));
626 static unsigned int s3c24xx_serial_getclk(struct uart_port *port,
627 struct s3c24xx_uart_clksrc **clksrc,
631 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
632 struct s3c24xx_uart_clksrc *clkp;
633 struct baud_calc res[MAX_CLKS];
634 struct baud_calc *resptr, *best, *sptr;
640 if (cfg->clocks_size < 2) {
641 if (cfg->clocks_size == 0)
644 /* check to see if we're sourcing fclk, and if so we're
645 * going to have to update the clock source
648 if (strcmp(clkp->name, "fclk") == 0) {
649 struct s3c24xx_uart_clksrc src;
651 s3c24xx_serial_getsource(port, &src);
653 /* check that the port already using fclk, and if
654 * not, then re-select fclk
657 if (strcmp(src.name, clkp->name) == 0) {
658 s3c24xx_serial_setsource(port, clkp);
659 s3c24xx_serial_getsource(port, &src);
662 clkp->divisor = src.divisor;
665 s3c24xx_serial_calcbaud(res, port, clkp, baud);
671 for (i = 0; i < cfg->clocks_size; i++, clkp++) {
672 if (s3c24xx_serial_calcbaud(resptr, port, clkp, baud))
677 /* ok, we now need to select the best clock we found */
680 unsigned int deviation = (1<<30)|((1<<30)-1);
683 for (sptr = res; sptr < resptr; sptr++) {
685 "found clk %p (%s) quot %d, calc %d\n",
686 sptr->clksrc, sptr->clksrc->name,
687 sptr->quot, sptr->calc);
689 calc_deviation = baud - sptr->calc;
690 if (calc_deviation < 0)
691 calc_deviation = -calc_deviation;
693 if (calc_deviation < deviation) {
695 deviation = calc_deviation;
699 printk(KERN_DEBUG "best %p (deviation %d)\n", best, deviation);
702 printk(KERN_DEBUG "selected clock %p (%s) quot %d, calc %d\n",
703 best->clksrc, best->clksrc->name, best->quot, best->calc);
705 /* store results to pass back */
707 *clksrc = best->clksrc;
713 static void s3c24xx_serial_set_termios(struct uart_port *port,
714 struct ktermios *termios,
715 struct ktermios *old)
717 struct s3c2410_uartcfg *cfg = s3c24xx_port_to_cfg(port);
718 struct s3c24xx_uart_port *ourport = to_ourport(port);
719 struct s3c24xx_uart_clksrc *clksrc = NULL;
720 struct clk *clk = NULL;
722 unsigned int baud, quot;
727 * We don't support modem control lines.
729 termios->c_cflag &= ~(HUPCL | CMSPAR);
730 termios->c_cflag |= CLOCAL;
733 * Ask the core to calculate the divisor for us.
736 baud = uart_get_baud_rate(port, termios, old, 0, 115200*8);
738 if (baud == 38400 && (port->flags & UPF_SPD_MASK) == UPF_SPD_CUST)
739 quot = port->custom_divisor;
741 quot = s3c24xx_serial_getclk(port, &clksrc, &clk, baud);
743 /* check to see if we need to change clock source */
745 if (ourport->clksrc != clksrc || ourport->baudclk != clk) {
746 s3c24xx_serial_setsource(port, clksrc);
748 if (ourport->baudclk != NULL && !IS_ERR(ourport->baudclk)) {
749 clk_disable(ourport->baudclk);
750 ourport->baudclk = NULL;
755 ourport->clksrc = clksrc;
756 ourport->baudclk = clk;
759 switch (termios->c_cflag & CSIZE) {
761 dbg("config: 5bits/char\n");
762 ulcon = S3C2410_LCON_CS5;
765 dbg("config: 6bits/char\n");
766 ulcon = S3C2410_LCON_CS6;
769 dbg("config: 7bits/char\n");
770 ulcon = S3C2410_LCON_CS7;
774 dbg("config: 8bits/char\n");
775 ulcon = S3C2410_LCON_CS8;
779 /* preserve original lcon IR settings */
780 ulcon |= (cfg->ulcon & S3C2410_LCON_IRM);
782 if (termios->c_cflag & CSTOPB)
783 ulcon |= S3C2410_LCON_STOPB;
785 umcon = (termios->c_cflag & CRTSCTS) ? S3C2410_UMCOM_AFC : 0;
787 if (termios->c_cflag & PARENB) {
788 if (termios->c_cflag & PARODD)
789 ulcon |= S3C2410_LCON_PODD;
791 ulcon |= S3C2410_LCON_PEVEN;
793 ulcon |= S3C2410_LCON_PNONE;
796 spin_lock_irqsave(&port->lock, flags);
798 dbg("setting ulcon to %08x, brddiv to %d\n", ulcon, quot);
800 wr_regl(port, S3C2410_ULCON, ulcon);
801 wr_regl(port, S3C2410_UBRDIV, quot);
802 wr_regl(port, S3C2410_UMCON, umcon);
804 dbg("uart: ulcon = 0x%08x, ucon = 0x%08x, ufcon = 0x%08x\n",
805 rd_regl(port, S3C2410_ULCON),
806 rd_regl(port, S3C2410_UCON),
807 rd_regl(port, S3C2410_UFCON));
810 * Update the per-port timeout.
812 uart_update_timeout(port, termios->c_cflag, baud);
815 * Which character status flags are we interested in?
817 port->read_status_mask = S3C2410_UERSTAT_OVERRUN;
818 if (termios->c_iflag & INPCK)
819 port->read_status_mask |= S3C2410_UERSTAT_FRAME | S3C2410_UERSTAT_PARITY;
822 * Which character status flags should we ignore?
824 port->ignore_status_mask = 0;
825 if (termios->c_iflag & IGNPAR)
826 port->ignore_status_mask |= S3C2410_UERSTAT_OVERRUN;
827 if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
828 port->ignore_status_mask |= S3C2410_UERSTAT_FRAME;
831 * Ignore all characters if CREAD is not set.
833 if ((termios->c_cflag & CREAD) == 0)
834 port->ignore_status_mask |= RXSTAT_DUMMY_READ;
836 spin_unlock_irqrestore(&port->lock, flags);
839 static const char *s3c24xx_serial_type(struct uart_port *port)
841 switch (port->type) {
853 #define MAP_SIZE (0x100)
855 static void s3c24xx_serial_release_port(struct uart_port *port)
857 release_mem_region(port->mapbase, MAP_SIZE);
860 static int s3c24xx_serial_request_port(struct uart_port *port)
862 const char *name = s3c24xx_serial_portname(port);
863 return request_mem_region(port->mapbase, MAP_SIZE, name) ? 0 : -EBUSY;
866 static void s3c24xx_serial_config_port(struct uart_port *port, int flags)
868 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
870 if (flags & UART_CONFIG_TYPE &&
871 s3c24xx_serial_request_port(port) == 0)
872 port->type = info->type;
876 * verify the new serial_struct (for TIOCSSERIAL).
879 s3c24xx_serial_verify_port(struct uart_port *port, struct serial_struct *ser)
881 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
883 if (ser->type != PORT_UNKNOWN && ser->type != info->type)
890 #ifdef CONFIG_SERIAL_S3C2410_CONSOLE
892 static struct console s3c24xx_serial_console;
894 #define S3C24XX_SERIAL_CONSOLE &s3c24xx_serial_console
896 #define S3C24XX_SERIAL_CONSOLE NULL
899 static struct uart_ops s3c24xx_serial_ops = {
900 .pm = s3c24xx_serial_pm,
901 .tx_empty = s3c24xx_serial_tx_empty,
902 .get_mctrl = s3c24xx_serial_get_mctrl,
903 .set_mctrl = s3c24xx_serial_set_mctrl,
904 .stop_tx = s3c24xx_serial_stop_tx,
905 .start_tx = s3c24xx_serial_start_tx,
906 .stop_rx = s3c24xx_serial_stop_rx,
907 .enable_ms = s3c24xx_serial_enable_ms,
908 .break_ctl = s3c24xx_serial_break_ctl,
909 .startup = s3c24xx_serial_startup,
910 .shutdown = s3c24xx_serial_shutdown,
911 .set_termios = s3c24xx_serial_set_termios,
912 .type = s3c24xx_serial_type,
913 .release_port = s3c24xx_serial_release_port,
914 .request_port = s3c24xx_serial_request_port,
915 .config_port = s3c24xx_serial_config_port,
916 .verify_port = s3c24xx_serial_verify_port,
920 static struct uart_driver s3c24xx_uart_drv = {
921 .owner = THIS_MODULE,
922 .dev_name = "s3c2410_serial",
924 .cons = S3C24XX_SERIAL_CONSOLE,
925 .driver_name = S3C24XX_SERIAL_NAME,
926 .major = S3C24XX_SERIAL_MAJOR,
927 .minor = S3C24XX_SERIAL_MINOR,
930 static struct s3c24xx_uart_port s3c24xx_serial_ports[NR_PORTS] = {
933 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[0].port.lock),
935 .irq = IRQ_S3CUART_RX0,
938 .ops = &s3c24xx_serial_ops,
939 .flags = UPF_BOOT_AUTOCONF,
945 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[1].port.lock),
947 .irq = IRQ_S3CUART_RX1,
950 .ops = &s3c24xx_serial_ops,
951 .flags = UPF_BOOT_AUTOCONF,
959 .lock = __SPIN_LOCK_UNLOCKED(s3c24xx_serial_ports[2].port.lock),
961 .irq = IRQ_S3CUART_RX2,
964 .ops = &s3c24xx_serial_ops,
965 .flags = UPF_BOOT_AUTOCONF,
972 /* s3c24xx_serial_resetport
974 * wrapper to call the specific reset for this port (reset the fifos
978 static inline int s3c24xx_serial_resetport(struct uart_port * port,
979 struct s3c2410_uartcfg *cfg)
981 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
983 return (info->reset_port)(port, cfg);
986 /* s3c24xx_serial_init_port
988 * initialise a single serial port from the platform device given
991 static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
992 struct s3c24xx_uart_info *info,
993 struct platform_device *platdev)
995 struct uart_port *port = &ourport->port;
996 struct s3c2410_uartcfg *cfg;
997 struct resource *res;
1000 dbg("s3c24xx_serial_init_port: port=%p, platdev=%p\n", port, platdev);
1002 if (platdev == NULL)
1005 cfg = s3c24xx_dev_to_cfg(&platdev->dev);
1007 if (port->mapbase != 0)
1010 if (cfg->hwport > 3)
1013 /* setup info for port */
1014 port->dev = &platdev->dev;
1015 ourport->info = info;
1017 /* copy the info in from provided structure */
1018 ourport->port.fifosize = info->fifosize;
1020 dbg("s3c24xx_serial_init_port: %p (hw %d)...\n", port, cfg->hwport);
1024 if (cfg->uart_flags & UPF_CONS_FLOW) {
1025 dbg("s3c24xx_serial_init_port: enabling flow control\n");
1026 port->flags |= UPF_CONS_FLOW;
1029 /* sort our the physical and virtual addresses for each UART */
1031 res = platform_get_resource(platdev, IORESOURCE_MEM, 0);
1033 printk(KERN_ERR "failed to find memory resource for uart\n");
1037 dbg("resource %p (%lx..%lx)\n", res, res->start, res->end);
1039 port->mapbase = res->start;
1040 port->membase = S3C24XX_VA_UART + (res->start - S3C24XX_PA_UART);
1041 ret = platform_get_irq(platdev, 0);
1047 ourport->clk = clk_get(&platdev->dev, "uart");
1049 dbg("port: map=%08x, mem=%08x, irq=%d, clock=%ld\n",
1050 port->mapbase, port->membase, port->irq, port->uartclk);
1052 /* reset the fifos (and setup the uart) */
1053 s3c24xx_serial_resetport(port, cfg);
1057 /* Device driver serial port probe */
1059 static int probe_index = 0;
1061 static int s3c24xx_serial_probe(struct platform_device *dev,
1062 struct s3c24xx_uart_info *info)
1064 struct s3c24xx_uart_port *ourport;
1067 dbg("s3c24xx_serial_probe(%p, %p) %d\n", dev, info, probe_index);
1069 ourport = &s3c24xx_serial_ports[probe_index];
1072 dbg("%s: initialising port %p...\n", __func__, ourport);
1074 ret = s3c24xx_serial_init_port(ourport, info, dev);
1078 dbg("%s: adding port\n", __func__);
1079 uart_add_one_port(&s3c24xx_uart_drv, &ourport->port);
1080 platform_set_drvdata(dev, &ourport->port);
1088 static int s3c24xx_serial_remove(struct platform_device *dev)
1090 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1093 uart_remove_one_port(&s3c24xx_uart_drv, port);
1098 /* UART power management code */
1102 static int s3c24xx_serial_suspend(struct platform_device *dev, pm_message_t state)
1104 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1107 uart_suspend_port(&s3c24xx_uart_drv, port);
1112 static int s3c24xx_serial_resume(struct platform_device *dev)
1114 struct uart_port *port = s3c24xx_dev_to_port(&dev->dev);
1115 struct s3c24xx_uart_port *ourport = to_ourport(port);
1118 clk_enable(ourport->clk);
1119 s3c24xx_serial_resetport(port, s3c24xx_port_to_cfg(port));
1120 clk_disable(ourport->clk);
1122 uart_resume_port(&s3c24xx_uart_drv, port);
1129 #define s3c24xx_serial_suspend NULL
1130 #define s3c24xx_serial_resume NULL
1133 static int s3c24xx_serial_init(struct platform_driver *drv,
1134 struct s3c24xx_uart_info *info)
1136 dbg("s3c24xx_serial_init(%p,%p)\n", drv, info);
1137 return platform_driver_register(drv);
1141 /* now comes the code to initialise either the s3c2410 or s3c2440 serial
1145 /* cpu specific variations on the serial port support */
1147 #ifdef CONFIG_CPU_S3C2400
1149 static int s3c2400_serial_getsource(struct uart_port *port,
1150 struct s3c24xx_uart_clksrc *clk)
1158 static int s3c2400_serial_setsource(struct uart_port *port,
1159 struct s3c24xx_uart_clksrc *clk)
1164 static int s3c2400_serial_resetport(struct uart_port *port,
1165 struct s3c2410_uartcfg *cfg)
1167 dbg("s3c2400_serial_resetport: port=%p (%08lx), cfg=%p\n",
1168 port, port->mapbase, cfg);
1170 wr_regl(port, S3C2410_UCON, cfg->ucon);
1171 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1173 /* reset both fifos */
1175 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1176 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1181 static struct s3c24xx_uart_info s3c2400_uart_inf = {
1182 .name = "Samsung S3C2400 UART",
1183 .type = PORT_S3C2400,
1185 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1186 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1187 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1188 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1189 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1190 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1191 .get_clksrc = s3c2400_serial_getsource,
1192 .set_clksrc = s3c2400_serial_setsource,
1193 .reset_port = s3c2400_serial_resetport,
1196 static int s3c2400_serial_probe(struct platform_device *dev)
1198 return s3c24xx_serial_probe(dev, &s3c2400_uart_inf);
1201 static struct platform_driver s3c2400_serial_drv = {
1202 .probe = s3c2400_serial_probe,
1203 .remove = s3c24xx_serial_remove,
1204 .suspend = s3c24xx_serial_suspend,
1205 .resume = s3c24xx_serial_resume,
1207 .name = "s3c2400-uart",
1208 .owner = THIS_MODULE,
1212 static inline int s3c2400_serial_init(void)
1214 return s3c24xx_serial_init(&s3c2400_serial_drv, &s3c2400_uart_inf);
1217 static inline void s3c2400_serial_exit(void)
1219 platform_driver_unregister(&s3c2400_serial_drv);
1222 #define s3c2400_uart_inf_at &s3c2400_uart_inf
1225 static inline int s3c2400_serial_init(void)
1230 static inline void s3c2400_serial_exit(void)
1234 #define s3c2400_uart_inf_at NULL
1236 #endif /* CONFIG_CPU_S3C2400 */
1238 /* S3C2410 support */
1240 #ifdef CONFIG_CPU_S3C2410
1242 static int s3c2410_serial_setsource(struct uart_port *port,
1243 struct s3c24xx_uart_clksrc *clk)
1245 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1247 if (strcmp(clk->name, "uclk") == 0)
1248 ucon |= S3C2410_UCON_UCLK;
1250 ucon &= ~S3C2410_UCON_UCLK;
1252 wr_regl(port, S3C2410_UCON, ucon);
1256 static int s3c2410_serial_getsource(struct uart_port *port,
1257 struct s3c24xx_uart_clksrc *clk)
1259 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1262 clk->name = (ucon & S3C2410_UCON_UCLK) ? "uclk" : "pclk";
1267 static int s3c2410_serial_resetport(struct uart_port *port,
1268 struct s3c2410_uartcfg *cfg)
1270 dbg("s3c2410_serial_resetport: port=%p (%08lx), cfg=%p\n",
1271 port, port->mapbase, cfg);
1273 wr_regl(port, S3C2410_UCON, cfg->ucon);
1274 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1276 /* reset both fifos */
1278 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1279 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1284 static struct s3c24xx_uart_info s3c2410_uart_inf = {
1285 .name = "Samsung S3C2410 UART",
1286 .type = PORT_S3C2410,
1288 .rx_fifomask = S3C2410_UFSTAT_RXMASK,
1289 .rx_fifoshift = S3C2410_UFSTAT_RXSHIFT,
1290 .rx_fifofull = S3C2410_UFSTAT_RXFULL,
1291 .tx_fifofull = S3C2410_UFSTAT_TXFULL,
1292 .tx_fifomask = S3C2410_UFSTAT_TXMASK,
1293 .tx_fifoshift = S3C2410_UFSTAT_TXSHIFT,
1294 .get_clksrc = s3c2410_serial_getsource,
1295 .set_clksrc = s3c2410_serial_setsource,
1296 .reset_port = s3c2410_serial_resetport,
1299 /* device management */
1301 static int s3c2410_serial_probe(struct platform_device *dev)
1303 return s3c24xx_serial_probe(dev, &s3c2410_uart_inf);
1306 static struct platform_driver s3c2410_serial_drv = {
1307 .probe = s3c2410_serial_probe,
1308 .remove = s3c24xx_serial_remove,
1309 .suspend = s3c24xx_serial_suspend,
1310 .resume = s3c24xx_serial_resume,
1312 .name = "s3c2410-uart",
1313 .owner = THIS_MODULE,
1317 static inline int s3c2410_serial_init(void)
1319 return s3c24xx_serial_init(&s3c2410_serial_drv, &s3c2410_uart_inf);
1322 static inline void s3c2410_serial_exit(void)
1324 platform_driver_unregister(&s3c2410_serial_drv);
1327 #define s3c2410_uart_inf_at &s3c2410_uart_inf
1330 static inline int s3c2410_serial_init(void)
1335 static inline void s3c2410_serial_exit(void)
1339 #define s3c2410_uart_inf_at NULL
1341 #endif /* CONFIG_CPU_S3C2410 */
1343 #if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
1345 static int s3c2440_serial_setsource(struct uart_port *port,
1346 struct s3c24xx_uart_clksrc *clk)
1348 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1350 // todo - proper fclk<>nonfclk switch //
1352 ucon &= ~S3C2440_UCON_CLKMASK;
1354 if (strcmp(clk->name, "uclk") == 0)
1355 ucon |= S3C2440_UCON_UCLK;
1356 else if (strcmp(clk->name, "pclk") == 0)
1357 ucon |= S3C2440_UCON_PCLK;
1358 else if (strcmp(clk->name, "fclk") == 0)
1359 ucon |= S3C2440_UCON_FCLK;
1361 printk(KERN_ERR "unknown clock source %s\n", clk->name);
1365 wr_regl(port, S3C2410_UCON, ucon);
1370 static int s3c2440_serial_getsource(struct uart_port *port,
1371 struct s3c24xx_uart_clksrc *clk)
1373 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1374 unsigned long ucon0, ucon1, ucon2;
1376 switch (ucon & S3C2440_UCON_CLKMASK) {
1377 case S3C2440_UCON_UCLK:
1382 case S3C2440_UCON_PCLK:
1383 case S3C2440_UCON_PCLK2:
1388 case S3C2440_UCON_FCLK:
1389 /* the fun of calculating the uart divisors on
1392 ucon0 = __raw_readl(S3C24XX_VA_UART0 + S3C2410_UCON);
1393 ucon1 = __raw_readl(S3C24XX_VA_UART1 + S3C2410_UCON);
1394 ucon2 = __raw_readl(S3C24XX_VA_UART2 + S3C2410_UCON);
1396 printk("ucons: %08lx, %08lx, %08lx\n", ucon0, ucon1, ucon2);
1398 ucon0 &= S3C2440_UCON0_DIVMASK;
1399 ucon1 &= S3C2440_UCON1_DIVMASK;
1400 ucon2 &= S3C2440_UCON2_DIVMASK;
1403 clk->divisor = ucon0 >> S3C2440_UCON_DIVSHIFT;
1405 } else if (ucon1 != 0) {
1406 clk->divisor = ucon1 >> S3C2440_UCON_DIVSHIFT;
1408 } else if (ucon2 != 0) {
1409 clk->divisor = ucon2 >> S3C2440_UCON_DIVSHIFT;
1412 /* manual calims 44, seems to be 9 */
1423 static int s3c2440_serial_resetport(struct uart_port *port,
1424 struct s3c2410_uartcfg *cfg)
1426 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1428 dbg("s3c2440_serial_resetport: port=%p (%08lx), cfg=%p\n",
1429 port, port->mapbase, cfg);
1431 /* ensure we don't change the clock settings... */
1433 ucon &= (S3C2440_UCON0_DIVMASK | (3<<10));
1435 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1436 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1438 /* reset both fifos */
1440 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1441 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1446 static struct s3c24xx_uart_info s3c2440_uart_inf = {
1447 .name = "Samsung S3C2440 UART",
1448 .type = PORT_S3C2440,
1450 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1451 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1452 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1453 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1454 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1455 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1456 .get_clksrc = s3c2440_serial_getsource,
1457 .set_clksrc = s3c2440_serial_setsource,
1458 .reset_port = s3c2440_serial_resetport,
1461 /* device management */
1463 static int s3c2440_serial_probe(struct platform_device *dev)
1465 dbg("s3c2440_serial_probe: dev=%p\n", dev);
1466 return s3c24xx_serial_probe(dev, &s3c2440_uart_inf);
1469 static struct platform_driver s3c2440_serial_drv = {
1470 .probe = s3c2440_serial_probe,
1471 .remove = s3c24xx_serial_remove,
1472 .suspend = s3c24xx_serial_suspend,
1473 .resume = s3c24xx_serial_resume,
1475 .name = "s3c2440-uart",
1476 .owner = THIS_MODULE,
1481 static inline int s3c2440_serial_init(void)
1483 return s3c24xx_serial_init(&s3c2440_serial_drv, &s3c2440_uart_inf);
1486 static inline void s3c2440_serial_exit(void)
1488 platform_driver_unregister(&s3c2440_serial_drv);
1491 #define s3c2440_uart_inf_at &s3c2440_uart_inf
1494 static inline int s3c2440_serial_init(void)
1499 static inline void s3c2440_serial_exit(void)
1503 #define s3c2440_uart_inf_at NULL
1504 #endif /* CONFIG_CPU_S3C2440 */
1506 #if defined(CONFIG_CPU_S3C2412)
1508 static int s3c2412_serial_setsource(struct uart_port *port,
1509 struct s3c24xx_uart_clksrc *clk)
1511 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1513 ucon &= ~S3C2412_UCON_CLKMASK;
1515 if (strcmp(clk->name, "uclk") == 0)
1516 ucon |= S3C2440_UCON_UCLK;
1517 else if (strcmp(clk->name, "pclk") == 0)
1518 ucon |= S3C2440_UCON_PCLK;
1519 else if (strcmp(clk->name, "usysclk") == 0)
1520 ucon |= S3C2412_UCON_USYSCLK;
1522 printk(KERN_ERR "unknown clock source %s\n", clk->name);
1526 wr_regl(port, S3C2410_UCON, ucon);
1531 static int s3c2412_serial_getsource(struct uart_port *port,
1532 struct s3c24xx_uart_clksrc *clk)
1534 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1536 switch (ucon & S3C2412_UCON_CLKMASK) {
1537 case S3C2412_UCON_UCLK:
1542 case S3C2412_UCON_PCLK:
1543 case S3C2412_UCON_PCLK2:
1548 case S3C2412_UCON_USYSCLK:
1550 clk->name = "usysclk";
1557 static int s3c2412_serial_resetport(struct uart_port *port,
1558 struct s3c2410_uartcfg *cfg)
1560 unsigned long ucon = rd_regl(port, S3C2410_UCON);
1562 dbg("%s: port=%p (%08lx), cfg=%p\n",
1563 __func__, port, port->mapbase, cfg);
1565 /* ensure we don't change the clock settings... */
1567 ucon &= S3C2412_UCON_CLKMASK;
1569 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
1570 wr_regl(port, S3C2410_ULCON, cfg->ulcon);
1572 /* reset both fifos */
1574 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
1575 wr_regl(port, S3C2410_UFCON, cfg->ufcon);
1580 static struct s3c24xx_uart_info s3c2412_uart_inf = {
1581 .name = "Samsung S3C2412 UART",
1582 .type = PORT_S3C2412,
1584 .rx_fifomask = S3C2440_UFSTAT_RXMASK,
1585 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
1586 .rx_fifofull = S3C2440_UFSTAT_RXFULL,
1587 .tx_fifofull = S3C2440_UFSTAT_TXFULL,
1588 .tx_fifomask = S3C2440_UFSTAT_TXMASK,
1589 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
1590 .get_clksrc = s3c2412_serial_getsource,
1591 .set_clksrc = s3c2412_serial_setsource,
1592 .reset_port = s3c2412_serial_resetport,
1595 /* device management */
1597 static int s3c2412_serial_probe(struct platform_device *dev)
1599 dbg("s3c2440_serial_probe: dev=%p\n", dev);
1600 return s3c24xx_serial_probe(dev, &s3c2412_uart_inf);
1603 static struct platform_driver s3c2412_serial_drv = {
1604 .probe = s3c2412_serial_probe,
1605 .remove = s3c24xx_serial_remove,
1606 .suspend = s3c24xx_serial_suspend,
1607 .resume = s3c24xx_serial_resume,
1609 .name = "s3c2412-uart",
1610 .owner = THIS_MODULE,
1615 static inline int s3c2412_serial_init(void)
1617 return s3c24xx_serial_init(&s3c2412_serial_drv, &s3c2412_uart_inf);
1620 static inline void s3c2412_serial_exit(void)
1622 platform_driver_unregister(&s3c2412_serial_drv);
1625 #define s3c2412_uart_inf_at &s3c2412_uart_inf
1628 static inline int s3c2412_serial_init(void)
1633 static inline void s3c2412_serial_exit(void)
1637 #define s3c2412_uart_inf_at NULL
1638 #endif /* CONFIG_CPU_S3C2440 */
1641 /* module initialisation code */
1643 static int __init s3c24xx_serial_modinit(void)
1647 ret = uart_register_driver(&s3c24xx_uart_drv);
1649 printk(KERN_ERR "failed to register UART driver\n");
1653 s3c2400_serial_init();
1654 s3c2410_serial_init();
1655 s3c2412_serial_init();
1656 s3c2440_serial_init();
1661 static void __exit s3c24xx_serial_modexit(void)
1663 s3c2400_serial_exit();
1664 s3c2410_serial_exit();
1665 s3c2412_serial_exit();
1666 s3c2440_serial_exit();
1668 uart_unregister_driver(&s3c24xx_uart_drv);
1672 module_init(s3c24xx_serial_modinit);
1673 module_exit(s3c24xx_serial_modexit);
1677 #ifdef CONFIG_SERIAL_S3C2410_CONSOLE
1679 static struct uart_port *cons_uart;
1682 s3c24xx_serial_console_txrdy(struct uart_port *port, unsigned int ufcon)
1684 struct s3c24xx_uart_info *info = s3c24xx_port_to_info(port);
1685 unsigned long ufstat, utrstat;
1687 if (ufcon & S3C2410_UFCON_FIFOMODE) {
1688 /* fifo mode - check ammount of data in fifo registers... */
1690 ufstat = rd_regl(port, S3C2410_UFSTAT);
1691 return (ufstat & info->tx_fifofull) ? 0 : 1;
1694 /* in non-fifo mode, we go and use the tx buffer empty */
1696 utrstat = rd_regl(port, S3C2410_UTRSTAT);
1697 return (utrstat & S3C2410_UTRSTAT_TXE) ? 1 : 0;
1701 s3c24xx_serial_console_putchar(struct uart_port *port, int ch)
1703 unsigned int ufcon = rd_regl(cons_uart, S3C2410_UFCON);
1704 while (!s3c24xx_serial_console_txrdy(port, ufcon))
1706 wr_regb(cons_uart, S3C2410_UTXH, ch);
1710 s3c24xx_serial_console_write(struct console *co, const char *s,
1713 uart_console_write(cons_uart, s, count, s3c24xx_serial_console_putchar);
1717 s3c24xx_serial_get_options(struct uart_port *port, int *baud,
1718 int *parity, int *bits)
1720 struct s3c24xx_uart_clksrc clksrc;
1724 unsigned int ubrdiv;
1727 ulcon = rd_regl(port, S3C2410_ULCON);
1728 ucon = rd_regl(port, S3C2410_UCON);
1729 ubrdiv = rd_regl(port, S3C2410_UBRDIV);
1731 dbg("s3c24xx_serial_get_options: port=%p\n"
1732 "registers: ulcon=%08x, ucon=%08x, ubdriv=%08x\n",
1733 port, ulcon, ucon, ubrdiv);
1735 if ((ucon & 0xf) != 0) {
1736 /* consider the serial port configured if the tx/rx mode set */
1738 switch (ulcon & S3C2410_LCON_CSMASK) {
1739 case S3C2410_LCON_CS5:
1742 case S3C2410_LCON_CS6:
1745 case S3C2410_LCON_CS7:
1749 case S3C2410_LCON_CS8:
1754 switch (ulcon & S3C2410_LCON_PMASK) {
1755 case S3C2410_LCON_PEVEN:
1759 case S3C2410_LCON_PODD:
1763 case S3C2410_LCON_PNONE:
1768 /* now calculate the baud rate */
1770 s3c24xx_serial_getsource(port, &clksrc);
1772 clk = clk_get(port->dev, clksrc.name);
1773 if (!IS_ERR(clk) && clk != NULL)
1774 rate = clk_get_rate(clk) / clksrc.divisor;
1779 *baud = rate / ( 16 * (ubrdiv + 1));
1780 dbg("calculated baud %d\n", *baud);
1785 /* s3c24xx_serial_init_ports
1787 * initialise the serial ports from the machine provided initialisation
1791 static int s3c24xx_serial_init_ports(struct s3c24xx_uart_info *info)
1793 struct s3c24xx_uart_port *ptr = s3c24xx_serial_ports;
1794 struct platform_device **platdev_ptr;
1797 dbg("s3c24xx_serial_init_ports: initialising ports...\n");
1799 platdev_ptr = s3c24xx_uart_devs;
1801 for (i = 0; i < NR_PORTS; i++, ptr++, platdev_ptr++) {
1802 s3c24xx_serial_init_port(ptr, info, *platdev_ptr);
1809 s3c24xx_serial_console_setup(struct console *co, char *options)
1811 struct uart_port *port;
1817 dbg("s3c24xx_serial_console_setup: co=%p (%d), %s\n",
1818 co, co->index, options);
1820 /* is this a valid port */
1822 if (co->index == -1 || co->index >= NR_PORTS)
1825 port = &s3c24xx_serial_ports[co->index].port;
1827 /* is the port configured? */
1829 if (port->mapbase == 0x0) {
1831 port = &s3c24xx_serial_ports[co->index].port;
1836 dbg("s3c24xx_serial_console_setup: port=%p (%d)\n", port, co->index);
1839 * Check whether an invalid uart number has been specified, and
1840 * if so, search for the first available port that does have
1844 uart_parse_options(options, &baud, &parity, &bits, &flow);
1846 s3c24xx_serial_get_options(port, &baud, &parity, &bits);
1848 dbg("s3c24xx_serial_console_setup: baud %d\n", baud);
1850 return uart_set_options(port, co, baud, parity, bits, flow);
1853 /* s3c24xx_serial_initconsole
1855 * initialise the console from one of the uart drivers
1858 static struct console s3c24xx_serial_console =
1860 .name = S3C24XX_SERIAL_NAME,
1861 .device = uart_console_device,
1862 .flags = CON_PRINTBUFFER,
1864 .write = s3c24xx_serial_console_write,
1865 .setup = s3c24xx_serial_console_setup
1868 static int s3c24xx_serial_initconsole(void)
1870 struct s3c24xx_uart_info *info;
1871 struct platform_device *dev = s3c24xx_uart_devs[0];
1873 dbg("s3c24xx_serial_initconsole\n");
1875 /* select driver based on the cpu */
1878 printk(KERN_ERR "s3c24xx: no devices for console init\n");
1882 if (strcmp(dev->name, "s3c2400-uart") == 0) {
1883 info = s3c2400_uart_inf_at;
1884 } else if (strcmp(dev->name, "s3c2410-uart") == 0) {
1885 info = s3c2410_uart_inf_at;
1886 } else if (strcmp(dev->name, "s3c2440-uart") == 0) {
1887 info = s3c2440_uart_inf_at;
1888 } else if (strcmp(dev->name, "s3c2412-uart") == 0) {
1889 info = s3c2412_uart_inf_at;
1891 printk(KERN_ERR "s3c24xx: no driver for %s\n", dev->name);
1896 printk(KERN_ERR "s3c24xx: no driver for console\n");
1900 s3c24xx_serial_console.data = &s3c24xx_uart_drv;
1901 s3c24xx_serial_init_ports(info);
1903 register_console(&s3c24xx_serial_console);
1907 console_initcall(s3c24xx_serial_initconsole);
1909 #endif /* CONFIG_SERIAL_S3C2410_CONSOLE */
1911 MODULE_LICENSE("GPL");
1912 MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1913 MODULE_DESCRIPTION("Samsung S3C2410/S3C2440/S3C2412 Serial port driver");
1914 MODULE_ALIAS("platform:s3c2400-uart");
1915 MODULE_ALIAS("platform:s3c2410-uart");
1916 MODULE_ALIAS("platform:s3c2412-uart");
1917 MODULE_ALIAS("platform:s3c2440-uart");