2 * linux/drivers/serial/cpm_uart_cpm2.c
4 * Driver for CPM (SCC/SMC) serial ports; CPM2 definitions
6 * Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
7 * Pantelis Antoniou (panto@intracom.gr) (CPM1)
9 * Copyright (C) 2004 Freescale Semiconductor, Inc.
10 * (C) 2004 Intracom, S.A.
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
28 #include <linux/config.h>
29 #include <linux/module.h>
30 #include <linux/tty.h>
31 #include <linux/ioport.h>
32 #include <linux/init.h>
33 #include <linux/serial.h>
34 #include <linux/console.h>
35 #include <linux/sysrq.h>
36 #include <linux/device.h>
37 #include <linux/bootmem.h>
38 #include <linux/dma-mapping.h>
43 #include <linux/serial_core.h>
44 #include <linux/kernel.h>
48 /**************************************************************/
50 void cpm_line_cr_cmd(int line, int cmd)
52 volatile cpm_cpm2_t *cp = cpmp;
57 val = mk_cr_cmd(CPM_CR_SMC1_PAGE, CPM_CR_SMC1_SBLOCK, 0,
61 val = mk_cr_cmd(CPM_CR_SMC2_PAGE, CPM_CR_SMC2_SBLOCK, 0,
65 val = mk_cr_cmd(CPM_CR_SCC1_PAGE, CPM_CR_SCC1_SBLOCK, 0,
69 val = mk_cr_cmd(CPM_CR_SCC2_PAGE, CPM_CR_SCC2_SBLOCK, 0,
73 val = mk_cr_cmd(CPM_CR_SCC3_PAGE, CPM_CR_SCC3_SBLOCK, 0,
77 val = mk_cr_cmd(CPM_CR_SCC4_PAGE, CPM_CR_SCC4_SBLOCK, 0,
85 while (cp->cp_cpcr & CPM_CR_FLG) ;
88 void smc1_lineif(struct uart_cpm_port *pinfo)
90 volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
92 /* SMC1 is only on port D */
93 io->iop_ppard |= 0x00c00000;
94 io->iop_pdird |= 0x00400000;
95 io->iop_pdird &= ~0x00800000;
96 io->iop_psord &= ~0x00c00000;
98 /* Wire BRG1 to SMC1 */
99 cpm2_immr->im_cpmux.cmx_smr &= 0x0f;
103 void smc2_lineif(struct uart_cpm_port *pinfo)
105 volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
107 /* SMC2 is only on port A */
108 io->iop_ppara |= 0x00c00000;
109 io->iop_pdira |= 0x00400000;
110 io->iop_pdira &= ~0x00800000;
111 io->iop_psora &= ~0x00c00000;
113 /* Wire BRG2 to SMC2 */
114 cpm2_immr->im_cpmux.cmx_smr &= 0xf0;
118 void scc1_lineif(struct uart_cpm_port *pinfo)
120 volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
122 /* Use Port D for SCC1 instead of other functions. */
123 io->iop_ppard |= 0x00000003;
124 io->iop_psord &= ~0x00000001; /* Rx */
125 io->iop_psord |= 0x00000002; /* Tx */
126 io->iop_pdird &= ~0x00000001; /* Rx */
127 io->iop_pdird |= 0x00000002; /* Tx */
129 /* Wire BRG1 to SCC1 */
130 cpm2_immr->im_cpmux.cmx_scr &= 0x00ffffff;
131 cpm2_immr->im_cpmux.cmx_scr |= 0x00000000;
135 void scc2_lineif(struct uart_cpm_port *pinfo)
138 * STx GP3 uses the SCC2 secondary option pin assignment
139 * which this driver doesn't account for in the static
140 * pin assignments. This kind of board specific info
141 * really has to get out of the driver so boards can
142 * be supported in a sane fashion.
144 #ifndef CONFIG_STX_GP3
145 volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
146 io->iop_pparb |= 0x008b0000;
147 io->iop_pdirb |= 0x00880000;
148 io->iop_psorb |= 0x00880000;
149 io->iop_pdirb &= ~0x00030000;
150 io->iop_psorb &= ~0x00030000;
152 cpm2_immr->im_cpmux.cmx_scr &= 0xff00ffff;
153 cpm2_immr->im_cpmux.cmx_scr |= 0x00090000;
157 void scc3_lineif(struct uart_cpm_port *pinfo)
159 volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
160 io->iop_pparb |= 0x008b0000;
161 io->iop_pdirb |= 0x00880000;
162 io->iop_psorb |= 0x00880000;
163 io->iop_pdirb &= ~0x00030000;
164 io->iop_psorb &= ~0x00030000;
165 cpm2_immr->im_cpmux.cmx_scr &= 0xffff00ff;
166 cpm2_immr->im_cpmux.cmx_scr |= 0x00001200;
170 void scc4_lineif(struct uart_cpm_port *pinfo)
172 volatile iop_cpm2_t *io = &cpm2_immr->im_ioport;
174 io->iop_ppard |= 0x00000600;
175 io->iop_psord &= ~0x00000600; /* Tx/Rx */
176 io->iop_pdird &= ~0x00000200; /* Rx */
177 io->iop_pdird |= 0x00000400; /* Tx */
179 cpm2_immr->im_cpmux.cmx_scr &= 0xffffff00;
180 cpm2_immr->im_cpmux.cmx_scr |= 0x0000001b;
185 * Allocate DP-Ram and memory buffers. We need to allocate a transmit and
186 * receive buffer descriptors from dual port ram, and a character
187 * buffer area from host mem. If we are allocating for the console we need
188 * to do it from bootmem
190 int cpm_uart_allocbuf(struct uart_cpm_port *pinfo, unsigned int is_con)
196 dma_addr_t dma_addr = 0;
198 pr_debug("CPM uart[%d]:allocbuf\n", pinfo->port.line);
200 dpmemsz = sizeof(cbd_t) * (pinfo->rx_nrfifos + pinfo->tx_nrfifos);
201 dp_offset = cpm_dpalloc(dpmemsz, 8);
202 if (IS_DPERR(dp_offset)) {
204 "cpm_uart_cpm.c: could not allocate buffer descriptors\n");
208 dp_mem = cpm_dpram_addr(dp_offset);
210 memsz = L1_CACHE_ALIGN(pinfo->rx_nrfifos * pinfo->rx_fifosize) +
211 L1_CACHE_ALIGN(pinfo->tx_nrfifos * pinfo->tx_fifosize);
213 mem_addr = alloc_bootmem(memsz);
217 mem_addr = dma_alloc_coherent(NULL, memsz, &dma_addr,
220 if (mem_addr == NULL) {
221 cpm_dpfree(dp_offset);
223 "cpm_uart_cpm.c: could not allocate coherent memory\n");
227 pinfo->dp_addr = dp_offset;
228 pinfo->mem_addr = mem_addr;
229 pinfo->dma_addr = dma_addr;
230 pinfo->mem_size = memsz;
232 pinfo->rx_buf = mem_addr;
233 pinfo->tx_buf = pinfo->rx_buf + L1_CACHE_ALIGN(pinfo->rx_nrfifos
234 * pinfo->rx_fifosize);
236 pinfo->rx_bd_base = (volatile cbd_t *)dp_mem;
237 pinfo->tx_bd_base = pinfo->rx_bd_base + pinfo->rx_nrfifos;
242 void cpm_uart_freebuf(struct uart_cpm_port *pinfo)
244 dma_free_coherent(NULL, L1_CACHE_ALIGN(pinfo->rx_nrfifos *
245 pinfo->rx_fifosize) +
246 L1_CACHE_ALIGN(pinfo->tx_nrfifos *
247 pinfo->tx_fifosize), pinfo->mem_addr,
250 cpm_dpfree(pinfo->dp_addr);
253 /* Setup any dynamic params in the uart desc */
254 int cpm_uart_init_portdesc(void)
256 pr_debug("CPM uart[-]:init portdesc\n");
259 #ifdef CONFIG_SERIAL_CPM_SMC1
260 cpm_uart_ports[UART_SMC1].smcp = (smc_t *) & cpm2_immr->im_smc[0];
261 cpm_uart_ports[UART_SMC1].smcup =
262 (smc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SMC1];
263 *(u16 *)(&cpm2_immr->im_dprambase[PROFF_SMC1_BASE]) = PROFF_SMC1;
264 cpm_uart_ports[UART_SMC1].port.mapbase =
265 (unsigned long)&cpm2_immr->im_smc[0];
266 cpm_uart_ports[UART_SMC1].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
267 cpm_uart_ports[UART_SMC1].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
268 cpm_uart_ports[UART_SMC1].port.uartclk = (((bd_t *) __res)->bi_intfreq);
269 cpm_uart_port_map[cpm_uart_nr++] = UART_SMC1;
272 #ifdef CONFIG_SERIAL_CPM_SMC2
273 cpm_uart_ports[UART_SMC2].smcp = (smc_t *) & cpm2_immr->im_smc[1];
274 cpm_uart_ports[UART_SMC2].smcup =
275 (smc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SMC2];
276 *(u16 *)(&cpm2_immr->im_dprambase[PROFF_SMC2_BASE]) = PROFF_SMC2;
277 cpm_uart_ports[UART_SMC2].port.mapbase =
278 (unsigned long)&cpm2_immr->im_smc[1];
279 cpm_uart_ports[UART_SMC2].smcp->smc_smcm |= (SMCM_RX | SMCM_TX);
280 cpm_uart_ports[UART_SMC2].smcp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN);
281 cpm_uart_ports[UART_SMC2].port.uartclk = (((bd_t *) __res)->bi_intfreq);
282 cpm_uart_port_map[cpm_uart_nr++] = UART_SMC2;
285 #ifdef CONFIG_SERIAL_CPM_SCC1
286 cpm_uart_ports[UART_SCC1].sccp = (scc_t *) & cpm2_immr->im_scc[0];
287 cpm_uart_ports[UART_SCC1].sccup =
288 (scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC1];
289 cpm_uart_ports[UART_SCC1].port.mapbase =
290 (unsigned long)&cpm2_immr->im_scc[0];
291 cpm_uart_ports[UART_SCC1].sccp->scc_sccm &=
292 ~(UART_SCCM_TX | UART_SCCM_RX);
293 cpm_uart_ports[UART_SCC1].sccp->scc_gsmrl &=
294 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
295 cpm_uart_ports[UART_SCC1].port.uartclk = (((bd_t *) __res)->bi_intfreq);
296 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC1;
299 #ifdef CONFIG_SERIAL_CPM_SCC2
300 cpm_uart_ports[UART_SCC2].sccp = (scc_t *) & cpm2_immr->im_scc[1];
301 cpm_uart_ports[UART_SCC2].sccup =
302 (scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC2];
303 cpm_uart_ports[UART_SCC2].port.mapbase =
304 (unsigned long)&cpm2_immr->im_scc[1];
305 cpm_uart_ports[UART_SCC2].sccp->scc_sccm &=
306 ~(UART_SCCM_TX | UART_SCCM_RX);
307 cpm_uart_ports[UART_SCC2].sccp->scc_gsmrl &=
308 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
309 cpm_uart_ports[UART_SCC2].port.uartclk = (((bd_t *) __res)->bi_intfreq);
310 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC2;
313 #ifdef CONFIG_SERIAL_CPM_SCC3
314 cpm_uart_ports[UART_SCC3].sccp = (scc_t *) & cpm2_immr->im_scc[2];
315 cpm_uart_ports[UART_SCC3].sccup =
316 (scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC3];
317 cpm_uart_ports[UART_SCC3].port.mapbase =
318 (unsigned long)&cpm2_immr->im_scc[2];
319 cpm_uart_ports[UART_SCC3].sccp->scc_sccm &=
320 ~(UART_SCCM_TX | UART_SCCM_RX);
321 cpm_uart_ports[UART_SCC3].sccp->scc_gsmrl &=
322 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
323 cpm_uart_ports[UART_SCC3].port.uartclk = (((bd_t *) __res)->bi_intfreq);
324 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC3;
327 #ifdef CONFIG_SERIAL_CPM_SCC4
328 cpm_uart_ports[UART_SCC4].sccp = (scc_t *) & cpm2_immr->im_scc[3];
329 cpm_uart_ports[UART_SCC4].sccup =
330 (scc_uart_t *) & cpm2_immr->im_dprambase[PROFF_SCC4];
331 cpm_uart_ports[UART_SCC4].port.mapbase =
332 (unsigned long)&cpm2_immr->im_scc[3];
333 cpm_uart_ports[UART_SCC4].sccp->scc_sccm &=
334 ~(UART_SCCM_TX | UART_SCCM_RX);
335 cpm_uart_ports[UART_SCC4].sccp->scc_gsmrl &=
336 ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT);
337 cpm_uart_ports[UART_SCC4].port.uartclk = (((bd_t *) __res)->bi_intfreq);
338 cpm_uart_port_map[cpm_uart_nr++] = UART_SCC4;