2 * linux/drivers/char/8250.c
4 * Driver for 8250/16550-type serial ports
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
8 * Copyright (C) 2001 Russell King.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $
17 * A note about mapbase / membase
19 * mapbase is the physical address of the IO port.
20 * membase is an 'ioremapped' cookie.
23 #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
27 #include <linux/module.h>
28 #include <linux/moduleparam.h>
29 #include <linux/ioport.h>
30 #include <linux/init.h>
31 #include <linux/console.h>
32 #include <linux/sysrq.h>
33 #include <linux/delay.h>
34 #include <linux/platform_device.h>
35 #include <linux/tty.h>
36 #include <linux/tty_flip.h>
37 #include <linux/serial_reg.h>
38 #include <linux/serial_core.h>
39 #include <linux/serial.h>
40 #include <linux/serial_8250.h>
41 #include <linux/nmi.h>
42 #include <linux/mutex.h>
46 #include <asm/serial.h>
52 * share_irqs - whether we pass IRQF_SHARED to request_irq(). This option
53 * is unsafe when used on edge-triggered interrupts.
55 static unsigned int share_irqs = SERIAL8250_SHARE_IRQS;
57 static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS;
63 #define DEBUG_AUTOCONF(fmt...) printk(fmt)
65 #define DEBUG_AUTOCONF(fmt...) do { } while (0)
69 #define DEBUG_INTR(fmt...) printk(fmt)
71 #define DEBUG_INTR(fmt...) do { } while (0)
74 #define PASS_LIMIT 256
77 * We default to IRQ0 for the "no irq" hack. Some
78 * machine types want others as well - they're free
79 * to redefine this in their header file.
81 #define is_real_interrupt(irq) ((irq) != 0)
83 #ifdef CONFIG_SERIAL_8250_DETECT_IRQ
84 #define CONFIG_SERIAL_DETECT_IRQ 1
86 #ifdef CONFIG_SERIAL_8250_MANY_PORTS
87 #define CONFIG_SERIAL_MANY_PORTS 1
91 * HUB6 is always on. This will be removed once the header
92 * files have been cleaned.
97 * SERIAL_PORT_DFNS tells us about built-in ports that have no
98 * standard enumeration mechanism. Platforms that can find all
99 * serial ports via mechanisms like ACPI or PCI need not supply it.
101 #ifndef SERIAL_PORT_DFNS
102 #define SERIAL_PORT_DFNS
105 static const struct old_serial_port old_serial_port[] = {
106 SERIAL_PORT_DFNS /* defined in asm/serial.h */
109 #define UART_NR CONFIG_SERIAL_8250_NR_UARTS
111 #ifdef CONFIG_SERIAL_8250_RSA
113 #define PORT_RSA_MAX 4
114 static unsigned long probe_rsa[PORT_RSA_MAX];
115 static unsigned int probe_rsa_count;
116 #endif /* CONFIG_SERIAL_8250_RSA */
118 struct uart_8250_port {
119 struct uart_port port;
120 struct timer_list timer; /* "no irq" timer */
121 struct list_head list; /* ports on this IRQ */
122 unsigned short capabilities; /* port capabilities */
123 unsigned short bugs; /* port bugs */
124 unsigned int tx_loadsz; /* transmit fifo load size */
129 unsigned char mcr_mask; /* mask of user bits */
130 unsigned char mcr_force; /* mask of forced bits */
133 * Some bits in registers are cleared on a read, so they must
134 * be saved whenever the register is read but the bits will not
135 * be immediately processed.
137 #define LSR_SAVE_FLAGS UART_LSR_BRK_ERROR_BITS
138 unsigned char lsr_saved_flags;
139 #define MSR_SAVE_FLAGS UART_MSR_ANY_DELTA
140 unsigned char msr_saved_flags;
143 * We provide a per-port pm hook.
145 void (*pm)(struct uart_port *port,
146 unsigned int state, unsigned int old);
151 struct list_head *head;
154 static struct irq_info irq_lists[NR_IRQS];
157 * Here we define the default xmit fifo size used for each type of UART.
159 static const struct serial8250_config uart_config[] = {
184 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
185 .flags = UART_CAP_FIFO,
196 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
202 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
204 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
210 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
212 .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE,
220 .name = "16C950/954",
223 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
224 .flags = UART_CAP_FIFO,
230 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
232 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
238 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
239 .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP,
245 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11,
246 .flags = UART_CAP_FIFO,
252 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
253 .flags = UART_CAP_FIFO | UART_NATSEMI,
259 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
260 .flags = UART_CAP_FIFO | UART_CAP_UUE,
266 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
267 .flags = UART_CAP_FIFO,
271 #if defined (CONFIG_SERIAL_8250_AU1X00)
273 /* Au1x00 UART hardware has a weird register layout */
274 static const u8 au_io_in_map[] = {
284 static const u8 au_io_out_map[] = {
292 /* sane hardware needs no mapping */
293 static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
295 if (up->port.iotype != UPIO_AU)
297 return au_io_in_map[offset];
300 static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
302 if (up->port.iotype != UPIO_AU)
304 return au_io_out_map[offset];
307 #elif defined(CONFIG_SERIAL_8250_RM9K)
331 static inline int map_8250_in_reg(struct uart_8250_port *up, int offset)
333 if (up->port.iotype != UPIO_RM9000)
335 return regmap_in[offset];
338 static inline int map_8250_out_reg(struct uart_8250_port *up, int offset)
340 if (up->port.iotype != UPIO_RM9000)
342 return regmap_out[offset];
347 /* sane hardware needs no mapping */
348 #define map_8250_in_reg(up, offset) (offset)
349 #define map_8250_out_reg(up, offset) (offset)
353 static unsigned int serial_in(struct uart_8250_port *up, int offset)
356 offset = map_8250_in_reg(up, offset) << up->port.regshift;
358 switch (up->port.iotype) {
360 outb(up->port.hub6 - 1 + offset, up->port.iobase);
361 return inb(up->port.iobase + 1);
365 return readb(up->port.membase + offset);
369 return readl(up->port.membase + offset);
371 #ifdef CONFIG_SERIAL_8250_AU1X00
373 return __raw_readl(up->port.membase + offset);
377 if (offset == UART_IIR) {
378 tmp = readl(up->port.membase + (UART_IIR & ~3));
379 return (tmp >> 16) & 0xff; /* UART_IIR % 4 == 2 */
381 return readb(up->port.membase + offset);
384 return inb(up->port.iobase + offset);
389 serial_out(struct uart_8250_port *up, int offset, int value)
391 /* Save the offset before it's remapped */
392 int save_offset = offset;
393 offset = map_8250_out_reg(up, offset) << up->port.regshift;
395 switch (up->port.iotype) {
397 outb(up->port.hub6 - 1 + offset, up->port.iobase);
398 outb(value, up->port.iobase + 1);
402 writeb(value, up->port.membase + offset);
407 writel(value, up->port.membase + offset);
410 #ifdef CONFIG_SERIAL_8250_AU1X00
412 __raw_writel(value, up->port.membase + offset);
416 if (!((offset == UART_IER) && (value & UART_IER_UUE)))
417 writeb(value, up->port.membase + offset);
421 /* Save the LCR value so it can be re-written when a
422 * Busy Detect interrupt occurs. */
423 if (save_offset == UART_LCR)
425 writeb(value, up->port.membase + offset);
426 /* Read the IER to ensure any interrupt is cleared before
427 * returning from ISR. */
428 if (save_offset == UART_TX || save_offset == UART_IER)
429 value = serial_in(up, UART_IER);
433 outb(value, up->port.iobase + offset);
438 serial_out_sync(struct uart_8250_port *up, int offset, int value)
440 switch (up->port.iotype) {
443 #ifdef CONFIG_SERIAL_8250_AU1X00
447 serial_out(up, offset, value);
448 serial_in(up, UART_LCR); /* safe, no side-effects */
451 serial_out(up, offset, value);
456 * We used to support using pause I/O for certain machines. We
457 * haven't supported this for a while, but just in case it's badly
458 * needed for certain old 386 machines, I've left these #define's
461 #define serial_inp(up, offset) serial_in(up, offset)
462 #define serial_outp(up, offset, value) serial_out(up, offset, value)
464 /* Uart divisor latch read */
465 static inline int _serial_dl_read(struct uart_8250_port *up)
467 return serial_inp(up, UART_DLL) | serial_inp(up, UART_DLM) << 8;
470 /* Uart divisor latch write */
471 static inline void _serial_dl_write(struct uart_8250_port *up, int value)
473 serial_outp(up, UART_DLL, value & 0xff);
474 serial_outp(up, UART_DLM, value >> 8 & 0xff);
477 #if defined(CONFIG_SERIAL_8250_AU1X00)
478 /* Au1x00 haven't got a standard divisor latch */
479 static int serial_dl_read(struct uart_8250_port *up)
481 if (up->port.iotype == UPIO_AU)
482 return __raw_readl(up->port.membase + 0x28);
484 return _serial_dl_read(up);
487 static void serial_dl_write(struct uart_8250_port *up, int value)
489 if (up->port.iotype == UPIO_AU)
490 __raw_writel(value, up->port.membase + 0x28);
492 _serial_dl_write(up, value);
494 #elif defined(CONFIG_SERIAL_8250_RM9K)
495 static int serial_dl_read(struct uart_8250_port *up)
497 return (up->port.iotype == UPIO_RM9000) ?
498 (((__raw_readl(up->port.membase + 0x10) << 8) |
499 (__raw_readl(up->port.membase + 0x08) & 0xff)) & 0xffff) :
503 static void serial_dl_write(struct uart_8250_port *up, int value)
505 if (up->port.iotype == UPIO_RM9000) {
506 __raw_writel(value, up->port.membase + 0x08);
507 __raw_writel(value >> 8, up->port.membase + 0x10);
509 _serial_dl_write(up, value);
513 #define serial_dl_read(up) _serial_dl_read(up)
514 #define serial_dl_write(up, value) _serial_dl_write(up, value)
520 static void serial_icr_write(struct uart_8250_port *up, int offset, int value)
522 serial_out(up, UART_SCR, offset);
523 serial_out(up, UART_ICR, value);
526 static unsigned int serial_icr_read(struct uart_8250_port *up, int offset)
530 serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD);
531 serial_out(up, UART_SCR, offset);
532 value = serial_in(up, UART_ICR);
533 serial_icr_write(up, UART_ACR, up->acr);
541 static inline void serial8250_clear_fifos(struct uart_8250_port *p)
543 if (p->capabilities & UART_CAP_FIFO) {
544 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO);
545 serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO |
546 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
547 serial_outp(p, UART_FCR, 0);
552 * IER sleep support. UARTs which have EFRs need the "extended
553 * capability" bit enabled. Note that on XR16C850s, we need to
554 * reset LCR to write to IER.
556 static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep)
558 if (p->capabilities & UART_CAP_SLEEP) {
559 if (p->capabilities & UART_CAP_EFR) {
560 serial_outp(p, UART_LCR, 0xBF);
561 serial_outp(p, UART_EFR, UART_EFR_ECB);
562 serial_outp(p, UART_LCR, 0);
564 serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0);
565 if (p->capabilities & UART_CAP_EFR) {
566 serial_outp(p, UART_LCR, 0xBF);
567 serial_outp(p, UART_EFR, 0);
568 serial_outp(p, UART_LCR, 0);
573 #ifdef CONFIG_SERIAL_8250_RSA
575 * Attempts to turn on the RSA FIFO. Returns zero on failure.
576 * We set the port uart clock rate if we succeed.
578 static int __enable_rsa(struct uart_8250_port *up)
583 mode = serial_inp(up, UART_RSA_MSR);
584 result = mode & UART_RSA_MSR_FIFO;
587 serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO);
588 mode = serial_inp(up, UART_RSA_MSR);
589 result = mode & UART_RSA_MSR_FIFO;
593 up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16;
598 static void enable_rsa(struct uart_8250_port *up)
600 if (up->port.type == PORT_RSA) {
601 if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) {
602 spin_lock_irq(&up->port.lock);
604 spin_unlock_irq(&up->port.lock);
606 if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16)
607 serial_outp(up, UART_RSA_FRR, 0);
612 * Attempts to turn off the RSA FIFO. Returns zero on failure.
613 * It is unknown why interrupts were disabled in here. However,
614 * the caller is expected to preserve this behaviour by grabbing
615 * the spinlock before calling this function.
617 static void disable_rsa(struct uart_8250_port *up)
622 if (up->port.type == PORT_RSA &&
623 up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) {
624 spin_lock_irq(&up->port.lock);
626 mode = serial_inp(up, UART_RSA_MSR);
627 result = !(mode & UART_RSA_MSR_FIFO);
630 serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO);
631 mode = serial_inp(up, UART_RSA_MSR);
632 result = !(mode & UART_RSA_MSR_FIFO);
636 up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16;
637 spin_unlock_irq(&up->port.lock);
640 #endif /* CONFIG_SERIAL_8250_RSA */
643 * This is a quickie test to see how big the FIFO is.
644 * It doesn't work at all the time, more's the pity.
646 static int size_fifo(struct uart_8250_port *up)
648 unsigned char old_fcr, old_mcr, old_lcr;
649 unsigned short old_dl;
652 old_lcr = serial_inp(up, UART_LCR);
653 serial_outp(up, UART_LCR, 0);
654 old_fcr = serial_inp(up, UART_FCR);
655 old_mcr = serial_inp(up, UART_MCR);
656 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO |
657 UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
658 serial_outp(up, UART_MCR, UART_MCR_LOOP);
659 serial_outp(up, UART_LCR, UART_LCR_DLAB);
660 old_dl = serial_dl_read(up);
661 serial_dl_write(up, 0x0001);
662 serial_outp(up, UART_LCR, 0x03);
663 for (count = 0; count < 256; count++)
664 serial_outp(up, UART_TX, count);
665 mdelay(20);/* FIXME - schedule_timeout */
666 for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) &&
667 (count < 256); count++)
668 serial_inp(up, UART_RX);
669 serial_outp(up, UART_FCR, old_fcr);
670 serial_outp(up, UART_MCR, old_mcr);
671 serial_outp(up, UART_LCR, UART_LCR_DLAB);
672 serial_dl_write(up, old_dl);
673 serial_outp(up, UART_LCR, old_lcr);
679 * Read UART ID using the divisor method - set DLL and DLM to zero
680 * and the revision will be in DLL and device type in DLM. We
681 * preserve the device state across this.
683 static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p)
685 unsigned char old_dll, old_dlm, old_lcr;
688 old_lcr = serial_inp(p, UART_LCR);
689 serial_outp(p, UART_LCR, UART_LCR_DLAB);
691 old_dll = serial_inp(p, UART_DLL);
692 old_dlm = serial_inp(p, UART_DLM);
694 serial_outp(p, UART_DLL, 0);
695 serial_outp(p, UART_DLM, 0);
697 id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8;
699 serial_outp(p, UART_DLL, old_dll);
700 serial_outp(p, UART_DLM, old_dlm);
701 serial_outp(p, UART_LCR, old_lcr);
707 * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's.
708 * When this function is called we know it is at least a StarTech
709 * 16650 V2, but it might be one of several StarTech UARTs, or one of
710 * its clones. (We treat the broken original StarTech 16650 V1 as a
711 * 16550, and why not? Startech doesn't seem to even acknowledge its
714 * What evil have men's minds wrought...
716 static void autoconfig_has_efr(struct uart_8250_port *up)
718 unsigned int id1, id2, id3, rev;
721 * Everything with an EFR has SLEEP
723 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
726 * First we check to see if it's an Oxford Semiconductor UART.
728 * If we have to do this here because some non-National
729 * Semiconductor clone chips lock up if you try writing to the
730 * LSR register (which serial_icr_read does)
734 * Check for Oxford Semiconductor 16C950.
736 * EFR [4] must be set else this test fails.
738 * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca)
739 * claims that it's needed for 952 dual UART's (which are not
740 * recommended for new designs).
743 serial_out(up, UART_LCR, 0xBF);
744 serial_out(up, UART_EFR, UART_EFR_ECB);
745 serial_out(up, UART_LCR, 0x00);
746 id1 = serial_icr_read(up, UART_ID1);
747 id2 = serial_icr_read(up, UART_ID2);
748 id3 = serial_icr_read(up, UART_ID3);
749 rev = serial_icr_read(up, UART_REV);
751 DEBUG_AUTOCONF("950id=%02x:%02x:%02x:%02x ", id1, id2, id3, rev);
753 if (id1 == 0x16 && id2 == 0xC9 &&
754 (id3 == 0x50 || id3 == 0x52 || id3 == 0x54)) {
755 up->port.type = PORT_16C950;
758 * Enable work around for the Oxford Semiconductor 952 rev B
759 * chip which causes it to seriously miscalculate baud rates
762 if (id3 == 0x52 && rev == 0x01)
763 up->bugs |= UART_BUG_QUOT;
768 * We check for a XR16C850 by setting DLL and DLM to 0, and then
769 * reading back DLL and DLM. The chip type depends on the DLM
771 * 0x10 - XR16C850 and the DLL contains the chip revision.
775 id1 = autoconfig_read_divisor_id(up);
776 DEBUG_AUTOCONF("850id=%04x ", id1);
779 if (id2 == 0x10 || id2 == 0x12 || id2 == 0x14) {
780 up->port.type = PORT_16850;
785 * It wasn't an XR16C850.
787 * We distinguish between the '654 and the '650 by counting
788 * how many bytes are in the FIFO. I'm using this for now,
789 * since that's the technique that was sent to me in the
790 * serial driver update, but I'm not convinced this works.
791 * I've had problems doing this in the past. -TYT
793 if (size_fifo(up) == 64)
794 up->port.type = PORT_16654;
796 up->port.type = PORT_16650V2;
800 * We detected a chip without a FIFO. Only two fall into
801 * this category - the original 8250 and the 16450. The
802 * 16450 has a scratch register (accessible with LCR=0)
804 static void autoconfig_8250(struct uart_8250_port *up)
806 unsigned char scratch, status1, status2;
808 up->port.type = PORT_8250;
810 scratch = serial_in(up, UART_SCR);
811 serial_outp(up, UART_SCR, 0xa5);
812 status1 = serial_in(up, UART_SCR);
813 serial_outp(up, UART_SCR, 0x5a);
814 status2 = serial_in(up, UART_SCR);
815 serial_outp(up, UART_SCR, scratch);
817 if (status1 == 0xa5 && status2 == 0x5a)
818 up->port.type = PORT_16450;
821 static int broken_efr(struct uart_8250_port *up)
824 * Exar ST16C2550 "A2" devices incorrectly detect as
825 * having an EFR, and report an ID of 0x0201. See
826 * http://www.exar.com/info.php?pdf=dan180_oct2004.pdf
828 if (autoconfig_read_divisor_id(up) == 0x0201 && size_fifo(up) == 16)
835 * We know that the chip has FIFOs. Does it have an EFR? The
836 * EFR is located in the same register position as the IIR and
837 * we know the top two bits of the IIR are currently set. The
838 * EFR should contain zero. Try to read the EFR.
840 static void autoconfig_16550a(struct uart_8250_port *up)
842 unsigned char status1, status2;
843 unsigned int iersave;
845 up->port.type = PORT_16550A;
846 up->capabilities |= UART_CAP_FIFO;
849 * Check for presence of the EFR when DLAB is set.
850 * Only ST16C650V1 UARTs pass this test.
852 serial_outp(up, UART_LCR, UART_LCR_DLAB);
853 if (serial_in(up, UART_EFR) == 0) {
854 serial_outp(up, UART_EFR, 0xA8);
855 if (serial_in(up, UART_EFR) != 0) {
856 DEBUG_AUTOCONF("EFRv1 ");
857 up->port.type = PORT_16650;
858 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
860 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
862 serial_outp(up, UART_EFR, 0);
867 * Maybe it requires 0xbf to be written to the LCR.
868 * (other ST16C650V2 UARTs, TI16C752A, etc)
870 serial_outp(up, UART_LCR, 0xBF);
871 if (serial_in(up, UART_EFR) == 0 && !broken_efr(up)) {
872 DEBUG_AUTOCONF("EFRv2 ");
873 autoconfig_has_efr(up);
878 * Check for a National Semiconductor SuperIO chip.
879 * Attempt to switch to bank 2, read the value of the LOOP bit
880 * from EXCR1. Switch back to bank 0, change it in MCR. Then
881 * switch back to bank 2, read it from EXCR1 again and check
882 * it's changed. If so, set baud_base in EXCR2 to 921600. -- dwmw2
884 serial_outp(up, UART_LCR, 0);
885 status1 = serial_in(up, UART_MCR);
886 serial_outp(up, UART_LCR, 0xE0);
887 status2 = serial_in(up, 0x02); /* EXCR1 */
889 if (!((status2 ^ status1) & UART_MCR_LOOP)) {
890 serial_outp(up, UART_LCR, 0);
891 serial_outp(up, UART_MCR, status1 ^ UART_MCR_LOOP);
892 serial_outp(up, UART_LCR, 0xE0);
893 status2 = serial_in(up, 0x02); /* EXCR1 */
894 serial_outp(up, UART_LCR, 0);
895 serial_outp(up, UART_MCR, status1);
897 if ((status2 ^ status1) & UART_MCR_LOOP) {
900 serial_outp(up, UART_LCR, 0xE0);
902 quot = serial_dl_read(up);
905 status1 = serial_in(up, 0x04); /* EXCR2 */
906 status1 &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
907 status1 |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
908 serial_outp(up, 0x04, status1);
910 serial_dl_write(up, quot);
912 serial_outp(up, UART_LCR, 0);
914 up->port.uartclk = 921600*16;
915 up->port.type = PORT_NS16550A;
916 up->capabilities |= UART_NATSEMI;
922 * No EFR. Try to detect a TI16750, which only sets bit 5 of
923 * the IIR when 64 byte FIFO mode is enabled when DLAB is set.
924 * Try setting it with and without DLAB set. Cheap clones
925 * set bit 5 without DLAB set.
927 serial_outp(up, UART_LCR, 0);
928 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
929 status1 = serial_in(up, UART_IIR) >> 5;
930 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
931 serial_outp(up, UART_LCR, UART_LCR_DLAB);
932 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR7_64BYTE);
933 status2 = serial_in(up, UART_IIR) >> 5;
934 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
935 serial_outp(up, UART_LCR, 0);
937 DEBUG_AUTOCONF("iir1=%d iir2=%d ", status1, status2);
939 if (status1 == 6 && status2 == 7) {
940 up->port.type = PORT_16750;
941 up->capabilities |= UART_CAP_AFE | UART_CAP_SLEEP;
946 * Try writing and reading the UART_IER_UUE bit (b6).
947 * If it works, this is probably one of the Xscale platform's
949 * We're going to explicitly set the UUE bit to 0 before
950 * trying to write and read a 1 just to make sure it's not
951 * already a 1 and maybe locked there before we even start start.
953 iersave = serial_in(up, UART_IER);
954 serial_outp(up, UART_IER, iersave & ~UART_IER_UUE);
955 if (!(serial_in(up, UART_IER) & UART_IER_UUE)) {
957 * OK it's in a known zero state, try writing and reading
958 * without disturbing the current state of the other bits.
960 serial_outp(up, UART_IER, iersave | UART_IER_UUE);
961 if (serial_in(up, UART_IER) & UART_IER_UUE) {
964 * We'll leave the UART_IER_UUE bit set to 1 (enabled).
966 DEBUG_AUTOCONF("Xscale ");
967 up->port.type = PORT_XSCALE;
968 up->capabilities |= UART_CAP_UUE;
973 * If we got here we couldn't force the IER_UUE bit to 0.
974 * Log it and continue.
976 DEBUG_AUTOCONF("Couldn't force IER_UUE to 0 ");
978 serial_outp(up, UART_IER, iersave);
982 * This routine is called by rs_init() to initialize a specific serial
983 * port. It determines what type of UART chip this serial port is
984 * using: 8250, 16450, 16550, 16550A. The important question is
985 * whether or not this UART is a 16550A or not, since this will
986 * determine whether or not we can use its FIFO features or not.
988 static void autoconfig(struct uart_8250_port *up, unsigned int probeflags)
990 unsigned char status1, scratch, scratch2, scratch3;
991 unsigned char save_lcr, save_mcr;
994 if (!up->port.iobase && !up->port.mapbase && !up->port.membase)
997 DEBUG_AUTOCONF("ttyS%d: autoconf (0x%04x, 0x%p): ",
998 up->port.line, up->port.iobase, up->port.membase);
1001 * We really do need global IRQs disabled here - we're going to
1002 * be frobbing the chips IRQ enable register to see if it exists.
1004 spin_lock_irqsave(&up->port.lock, flags);
1006 up->capabilities = 0;
1009 if (!(up->port.flags & UPF_BUGGY_UART)) {
1011 * Do a simple existence test first; if we fail this,
1012 * there's no point trying anything else.
1014 * 0x80 is used as a nonsense port to prevent against
1015 * false positives due to ISA bus float. The
1016 * assumption is that 0x80 is a non-existent port;
1017 * which should be safe since include/asm/io.h also
1018 * makes this assumption.
1020 * Note: this is safe as long as MCR bit 4 is clear
1021 * and the device is in "PC" mode.
1023 scratch = serial_inp(up, UART_IER);
1024 serial_outp(up, UART_IER, 0);
1029 * Mask out IER[7:4] bits for test as some UARTs (e.g. TL
1030 * 16C754B) allow only to modify them if an EFR bit is set.
1032 scratch2 = serial_inp(up, UART_IER) & 0x0f;
1033 serial_outp(up, UART_IER, 0x0F);
1037 scratch3 = serial_inp(up, UART_IER) & 0x0f;
1038 serial_outp(up, UART_IER, scratch);
1039 if (scratch2 != 0 || scratch3 != 0x0F) {
1041 * We failed; there's nothing here
1043 DEBUG_AUTOCONF("IER test failed (%02x, %02x) ",
1044 scratch2, scratch3);
1049 save_mcr = serial_in(up, UART_MCR);
1050 save_lcr = serial_in(up, UART_LCR);
1053 * Check to see if a UART is really there. Certain broken
1054 * internal modems based on the Rockwell chipset fail this
1055 * test, because they apparently don't implement the loopback
1056 * test mode. So this test is skipped on the COM 1 through
1057 * COM 4 ports. This *should* be safe, since no board
1058 * manufacturer would be stupid enough to design a board
1059 * that conflicts with COM 1-4 --- we hope!
1061 if (!(up->port.flags & UPF_SKIP_TEST)) {
1062 serial_outp(up, UART_MCR, UART_MCR_LOOP | 0x0A);
1063 status1 = serial_inp(up, UART_MSR) & 0xF0;
1064 serial_outp(up, UART_MCR, save_mcr);
1065 if (status1 != 0x90) {
1066 DEBUG_AUTOCONF("LOOP test failed (%02x) ",
1073 * We're pretty sure there's a port here. Lets find out what
1074 * type of port it is. The IIR top two bits allows us to find
1075 * out if it's 8250 or 16450, 16550, 16550A or later. This
1076 * determines what we test for next.
1078 * We also initialise the EFR (if any) to zero for later. The
1079 * EFR occupies the same register location as the FCR and IIR.
1081 serial_outp(up, UART_LCR, 0xBF);
1082 serial_outp(up, UART_EFR, 0);
1083 serial_outp(up, UART_LCR, 0);
1085 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
1086 scratch = serial_in(up, UART_IIR) >> 6;
1088 DEBUG_AUTOCONF("iir=%d ", scratch);
1092 autoconfig_8250(up);
1095 up->port.type = PORT_UNKNOWN;
1098 up->port.type = PORT_16550;
1101 autoconfig_16550a(up);
1105 #ifdef CONFIG_SERIAL_8250_RSA
1107 * Only probe for RSA ports if we got the region.
1109 if (up->port.type == PORT_16550A && probeflags & PROBE_RSA) {
1112 for (i = 0 ; i < probe_rsa_count; ++i) {
1113 if (probe_rsa[i] == up->port.iobase &&
1115 up->port.type = PORT_RSA;
1122 #ifdef CONFIG_SERIAL_8250_AU1X00
1123 /* if access method is AU, it is a 16550 with a quirk */
1124 if (up->port.type == PORT_16550A && up->port.iotype == UPIO_AU)
1125 up->bugs |= UART_BUG_NOMSR;
1128 serial_outp(up, UART_LCR, save_lcr);
1130 if (up->capabilities != uart_config[up->port.type].flags) {
1132 "ttyS%d: detected caps %08x should be %08x\n",
1133 up->port.line, up->capabilities,
1134 uart_config[up->port.type].flags);
1137 up->port.fifosize = uart_config[up->port.type].fifo_size;
1138 up->capabilities = uart_config[up->port.type].flags;
1139 up->tx_loadsz = uart_config[up->port.type].tx_loadsz;
1141 if (up->port.type == PORT_UNKNOWN)
1147 #ifdef CONFIG_SERIAL_8250_RSA
1148 if (up->port.type == PORT_RSA)
1149 serial_outp(up, UART_RSA_FRR, 0);
1151 serial_outp(up, UART_MCR, save_mcr);
1152 serial8250_clear_fifos(up);
1153 serial_in(up, UART_RX);
1154 if (up->capabilities & UART_CAP_UUE)
1155 serial_outp(up, UART_IER, UART_IER_UUE);
1157 serial_outp(up, UART_IER, 0);
1160 spin_unlock_irqrestore(&up->port.lock, flags);
1161 DEBUG_AUTOCONF("type=%s\n", uart_config[up->port.type].name);
1164 static void autoconfig_irq(struct uart_8250_port *up)
1166 unsigned char save_mcr, save_ier;
1167 unsigned char save_ICP = 0;
1168 unsigned int ICP = 0;
1172 if (up->port.flags & UPF_FOURPORT) {
1173 ICP = (up->port.iobase & 0xfe0) | 0x1f;
1174 save_ICP = inb_p(ICP);
1179 /* forget possible initially masked and pending IRQ */
1180 probe_irq_off(probe_irq_on());
1181 save_mcr = serial_inp(up, UART_MCR);
1182 save_ier = serial_inp(up, UART_IER);
1183 serial_outp(up, UART_MCR, UART_MCR_OUT1 | UART_MCR_OUT2);
1185 irqs = probe_irq_on();
1186 serial_outp(up, UART_MCR, 0);
1188 if (up->port.flags & UPF_FOURPORT) {
1189 serial_outp(up, UART_MCR,
1190 UART_MCR_DTR | UART_MCR_RTS);
1192 serial_outp(up, UART_MCR,
1193 UART_MCR_DTR | UART_MCR_RTS | UART_MCR_OUT2);
1195 serial_outp(up, UART_IER, 0x0f); /* enable all intrs */
1196 (void)serial_inp(up, UART_LSR);
1197 (void)serial_inp(up, UART_RX);
1198 (void)serial_inp(up, UART_IIR);
1199 (void)serial_inp(up, UART_MSR);
1200 serial_outp(up, UART_TX, 0xFF);
1202 irq = probe_irq_off(irqs);
1204 serial_outp(up, UART_MCR, save_mcr);
1205 serial_outp(up, UART_IER, save_ier);
1207 if (up->port.flags & UPF_FOURPORT)
1208 outb_p(save_ICP, ICP);
1210 up->port.irq = (irq > 0) ? irq : 0;
1213 static inline void __stop_tx(struct uart_8250_port *p)
1215 if (p->ier & UART_IER_THRI) {
1216 p->ier &= ~UART_IER_THRI;
1217 serial_out(p, UART_IER, p->ier);
1221 static void serial8250_stop_tx(struct uart_port *port)
1223 struct uart_8250_port *up = (struct uart_8250_port *)port;
1228 * We really want to stop the transmitter from sending.
1230 if (up->port.type == PORT_16C950) {
1231 up->acr |= UART_ACR_TXDIS;
1232 serial_icr_write(up, UART_ACR, up->acr);
1236 static void transmit_chars(struct uart_8250_port *up);
1238 static void serial8250_start_tx(struct uart_port *port)
1240 struct uart_8250_port *up = (struct uart_8250_port *)port;
1242 if (!(up->ier & UART_IER_THRI)) {
1243 up->ier |= UART_IER_THRI;
1244 serial_out(up, UART_IER, up->ier);
1246 if (up->bugs & UART_BUG_TXEN) {
1247 unsigned char lsr, iir;
1248 lsr = serial_in(up, UART_LSR);
1249 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1250 iir = serial_in(up, UART_IIR) & 0x0f;
1251 if ((up->port.type == PORT_RM9000) ?
1252 (lsr & UART_LSR_THRE &&
1253 (iir == UART_IIR_NO_INT || iir == UART_IIR_THRI)) :
1254 (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT))
1260 * Re-enable the transmitter if we disabled it.
1262 if (up->port.type == PORT_16C950 && up->acr & UART_ACR_TXDIS) {
1263 up->acr &= ~UART_ACR_TXDIS;
1264 serial_icr_write(up, UART_ACR, up->acr);
1268 static void serial8250_stop_rx(struct uart_port *port)
1270 struct uart_8250_port *up = (struct uart_8250_port *)port;
1272 up->ier &= ~UART_IER_RLSI;
1273 up->port.read_status_mask &= ~UART_LSR_DR;
1274 serial_out(up, UART_IER, up->ier);
1277 static void serial8250_enable_ms(struct uart_port *port)
1279 struct uart_8250_port *up = (struct uart_8250_port *)port;
1281 /* no MSR capabilities */
1282 if (up->bugs & UART_BUG_NOMSR)
1285 up->ier |= UART_IER_MSI;
1286 serial_out(up, UART_IER, up->ier);
1290 receive_chars(struct uart_8250_port *up, unsigned int *status)
1292 struct tty_struct *tty = up->port.info->tty;
1293 unsigned char ch, lsr = *status;
1294 int max_count = 256;
1298 ch = serial_inp(up, UART_RX);
1300 up->port.icount.rx++;
1302 lsr |= up->lsr_saved_flags;
1303 up->lsr_saved_flags = 0;
1305 if (unlikely(lsr & UART_LSR_BRK_ERROR_BITS)) {
1307 * For statistics only
1309 if (lsr & UART_LSR_BI) {
1310 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
1311 up->port.icount.brk++;
1313 * We do the SysRQ and SAK checking
1314 * here because otherwise the break
1315 * may get masked by ignore_status_mask
1316 * or read_status_mask.
1318 if (uart_handle_break(&up->port))
1320 } else if (lsr & UART_LSR_PE)
1321 up->port.icount.parity++;
1322 else if (lsr & UART_LSR_FE)
1323 up->port.icount.frame++;
1324 if (lsr & UART_LSR_OE)
1325 up->port.icount.overrun++;
1328 * Mask off conditions which should be ignored.
1330 lsr &= up->port.read_status_mask;
1332 if (lsr & UART_LSR_BI) {
1333 DEBUG_INTR("handling break....");
1335 } else if (lsr & UART_LSR_PE)
1337 else if (lsr & UART_LSR_FE)
1340 if (uart_handle_sysrq_char(&up->port, ch))
1343 uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
1346 lsr = serial_inp(up, UART_LSR);
1347 } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
1348 spin_unlock(&up->port.lock);
1349 tty_flip_buffer_push(tty);
1350 spin_lock(&up->port.lock);
1354 static void transmit_chars(struct uart_8250_port *up)
1356 struct circ_buf *xmit = &up->port.info->xmit;
1359 if (up->port.x_char) {
1360 serial_outp(up, UART_TX, up->port.x_char);
1361 up->port.icount.tx++;
1362 up->port.x_char = 0;
1365 if (uart_tx_stopped(&up->port)) {
1366 serial8250_stop_tx(&up->port);
1369 if (uart_circ_empty(xmit)) {
1374 count = up->tx_loadsz;
1376 serial_out(up, UART_TX, xmit->buf[xmit->tail]);
1377 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
1378 up->port.icount.tx++;
1379 if (uart_circ_empty(xmit))
1381 } while (--count > 0);
1383 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1384 uart_write_wakeup(&up->port);
1386 DEBUG_INTR("THRE...");
1388 if (uart_circ_empty(xmit))
1392 static unsigned int check_modem_status(struct uart_8250_port *up)
1394 unsigned int status = serial_in(up, UART_MSR);
1396 status |= up->msr_saved_flags;
1397 up->msr_saved_flags = 0;
1398 if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
1399 up->port.info != NULL) {
1400 if (status & UART_MSR_TERI)
1401 up->port.icount.rng++;
1402 if (status & UART_MSR_DDSR)
1403 up->port.icount.dsr++;
1404 if (status & UART_MSR_DDCD)
1405 uart_handle_dcd_change(&up->port, status & UART_MSR_DCD);
1406 if (status & UART_MSR_DCTS)
1407 uart_handle_cts_change(&up->port, status & UART_MSR_CTS);
1409 wake_up_interruptible(&up->port.info->delta_msr_wait);
1416 * This handles the interrupt from one port.
1419 serial8250_handle_port(struct uart_8250_port *up)
1421 unsigned int status;
1422 unsigned long flags;
1424 spin_lock_irqsave(&up->port.lock, flags);
1426 status = serial_inp(up, UART_LSR);
1428 DEBUG_INTR("status = %x...", status);
1430 if (status & UART_LSR_DR)
1431 receive_chars(up, &status);
1432 check_modem_status(up);
1433 if (status & UART_LSR_THRE)
1436 spin_unlock_irqrestore(&up->port.lock, flags);
1440 * This is the serial driver's interrupt routine.
1442 * Arjan thinks the old way was overly complex, so it got simplified.
1443 * Alan disagrees, saying that need the complexity to handle the weird
1444 * nature of ISA shared interrupts. (This is a special exception.)
1446 * In order to handle ISA shared interrupts properly, we need to check
1447 * that all ports have been serviced, and therefore the ISA interrupt
1448 * line has been de-asserted.
1450 * This means we need to loop through all ports. checking that they
1451 * don't have an interrupt pending.
1453 static irqreturn_t serial8250_interrupt(int irq, void *dev_id)
1455 struct irq_info *i = dev_id;
1456 struct list_head *l, *end = NULL;
1457 int pass_counter = 0, handled = 0;
1459 DEBUG_INTR("serial8250_interrupt(%d)...", irq);
1461 spin_lock(&i->lock);
1465 struct uart_8250_port *up;
1468 up = list_entry(l, struct uart_8250_port, list);
1470 iir = serial_in(up, UART_IIR);
1471 if (!(iir & UART_IIR_NO_INT)) {
1472 serial8250_handle_port(up);
1477 } else if (up->port.iotype == UPIO_DWAPB &&
1478 (iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
1479 /* The DesignWare APB UART has an Busy Detect (0x07)
1480 * interrupt meaning an LCR write attempt occured while the
1481 * UART was busy. The interrupt must be cleared by reading
1482 * the UART status register (USR) and the LCR re-written. */
1483 unsigned int status;
1484 status = *(volatile u32 *)up->port.private_data;
1485 serial_out(up, UART_LCR, up->lcr);
1490 } else if (end == NULL)
1495 if (l == i->head && pass_counter++ > PASS_LIMIT) {
1496 /* If we hit this, we're dead. */
1497 printk(KERN_ERR "serial8250: too much work for "
1503 spin_unlock(&i->lock);
1505 DEBUG_INTR("end.\n");
1507 return IRQ_RETVAL(handled);
1511 * To support ISA shared interrupts, we need to have one interrupt
1512 * handler that ensures that the IRQ line has been deasserted
1513 * before returning. Failing to do this will result in the IRQ
1514 * line being stuck active, and, since ISA irqs are edge triggered,
1515 * no more IRQs will be seen.
1517 static void serial_do_unlink(struct irq_info *i, struct uart_8250_port *up)
1519 spin_lock_irq(&i->lock);
1521 if (!list_empty(i->head)) {
1522 if (i->head == &up->list)
1523 i->head = i->head->next;
1524 list_del(&up->list);
1526 BUG_ON(i->head != &up->list);
1530 spin_unlock_irq(&i->lock);
1533 static int serial_link_irq_chain(struct uart_8250_port *up)
1535 struct irq_info *i = irq_lists + up->port.irq;
1536 int ret, irq_flags = up->port.flags & UPF_SHARE_IRQ ? IRQF_SHARED : 0;
1538 spin_lock_irq(&i->lock);
1541 list_add(&up->list, i->head);
1542 spin_unlock_irq(&i->lock);
1546 INIT_LIST_HEAD(&up->list);
1547 i->head = &up->list;
1548 spin_unlock_irq(&i->lock);
1550 irq_flags |= SERIAL_EXTRA_IRQ_FLAGS;
1552 ret = request_irq(up->port.irq, serial8250_interrupt,
1553 irq_flags, "serial", i);
1555 serial_do_unlink(i, up);
1561 static void serial_unlink_irq_chain(struct uart_8250_port *up)
1563 struct irq_info *i = irq_lists + up->port.irq;
1565 BUG_ON(i->head == NULL);
1567 if (list_empty(i->head))
1568 free_irq(up->port.irq, i);
1570 serial_do_unlink(i, up);
1573 /* Base timer interval for polling */
1574 static inline int poll_timeout(int timeout)
1576 return timeout > 6 ? (timeout / 2 - 2) : 1;
1580 * This function is used to handle ports that do not have an
1581 * interrupt. This doesn't work very well for 16450's, but gives
1582 * barely passable results for a 16550A. (Although at the expense
1583 * of much CPU overhead).
1585 static void serial8250_timeout(unsigned long data)
1587 struct uart_8250_port *up = (struct uart_8250_port *)data;
1590 iir = serial_in(up, UART_IIR);
1591 if (!(iir & UART_IIR_NO_INT))
1592 serial8250_handle_port(up);
1593 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1596 static void serial8250_backup_timeout(unsigned long data)
1598 struct uart_8250_port *up = (struct uart_8250_port *)data;
1599 unsigned int iir, ier = 0, lsr;
1600 unsigned long flags;
1603 * Must disable interrupts or else we risk racing with the interrupt
1606 if (is_real_interrupt(up->port.irq)) {
1607 ier = serial_in(up, UART_IER);
1608 serial_out(up, UART_IER, 0);
1611 iir = serial_in(up, UART_IIR);
1614 * This should be a safe test for anyone who doesn't trust the
1615 * IIR bits on their UART, but it's specifically designed for
1616 * the "Diva" UART used on the management processor on many HP
1617 * ia64 and parisc boxes.
1619 spin_lock_irqsave(&up->port.lock, flags);
1620 lsr = serial_in(up, UART_LSR);
1621 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1622 spin_unlock_irqrestore(&up->port.lock, flags);
1623 if ((iir & UART_IIR_NO_INT) && (up->ier & UART_IER_THRI) &&
1624 (!uart_circ_empty(&up->port.info->xmit) || up->port.x_char) &&
1625 (lsr & UART_LSR_THRE)) {
1626 iir &= ~(UART_IIR_ID | UART_IIR_NO_INT);
1627 iir |= UART_IIR_THRI;
1630 if (!(iir & UART_IIR_NO_INT))
1631 serial8250_handle_port(up);
1633 if (is_real_interrupt(up->port.irq))
1634 serial_out(up, UART_IER, ier);
1636 /* Standard timer interval plus 0.2s to keep the port running */
1637 mod_timer(&up->timer,
1638 jiffies + poll_timeout(up->port.timeout) + HZ / 5);
1641 static unsigned int serial8250_tx_empty(struct uart_port *port)
1643 struct uart_8250_port *up = (struct uart_8250_port *)port;
1644 unsigned long flags;
1647 spin_lock_irqsave(&up->port.lock, flags);
1648 lsr = serial_in(up, UART_LSR);
1649 up->lsr_saved_flags |= lsr & LSR_SAVE_FLAGS;
1650 spin_unlock_irqrestore(&up->port.lock, flags);
1652 return lsr & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
1655 static unsigned int serial8250_get_mctrl(struct uart_port *port)
1657 struct uart_8250_port *up = (struct uart_8250_port *)port;
1658 unsigned int status;
1661 status = check_modem_status(up);
1664 if (status & UART_MSR_DCD)
1666 if (status & UART_MSR_RI)
1668 if (status & UART_MSR_DSR)
1670 if (status & UART_MSR_CTS)
1675 static void serial8250_set_mctrl(struct uart_port *port, unsigned int mctrl)
1677 struct uart_8250_port *up = (struct uart_8250_port *)port;
1678 unsigned char mcr = 0;
1680 if (mctrl & TIOCM_RTS)
1681 mcr |= UART_MCR_RTS;
1682 if (mctrl & TIOCM_DTR)
1683 mcr |= UART_MCR_DTR;
1684 if (mctrl & TIOCM_OUT1)
1685 mcr |= UART_MCR_OUT1;
1686 if (mctrl & TIOCM_OUT2)
1687 mcr |= UART_MCR_OUT2;
1688 if (mctrl & TIOCM_LOOP)
1689 mcr |= UART_MCR_LOOP;
1691 mcr = (mcr & up->mcr_mask) | up->mcr_force | up->mcr;
1693 serial_out(up, UART_MCR, mcr);
1696 static void serial8250_break_ctl(struct uart_port *port, int break_state)
1698 struct uart_8250_port *up = (struct uart_8250_port *)port;
1699 unsigned long flags;
1701 spin_lock_irqsave(&up->port.lock, flags);
1702 if (break_state == -1)
1703 up->lcr |= UART_LCR_SBC;
1705 up->lcr &= ~UART_LCR_SBC;
1706 serial_out(up, UART_LCR, up->lcr);
1707 spin_unlock_irqrestore(&up->port.lock, flags);
1710 #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
1713 * Wait for transmitter & holding register to empty
1715 static inline void wait_for_xmitr(struct uart_8250_port *up, int bits)
1717 unsigned int status, tmout = 10000;
1719 /* Wait up to 10ms for the character(s) to be sent. */
1721 status = serial_in(up, UART_LSR);
1723 up->lsr_saved_flags |= status & LSR_SAVE_FLAGS;
1728 } while ((status & bits) != bits);
1730 /* Wait up to 1s for flow control if necessary */
1731 if (up->port.flags & UPF_CONS_FLOW) {
1733 for (tmout = 1000000; tmout; tmout--) {
1734 unsigned int msr = serial_in(up, UART_MSR);
1735 up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1736 if (msr & UART_MSR_CTS)
1739 touch_nmi_watchdog();
1744 #ifdef CONFIG_CONSOLE_POLL
1746 * Console polling routines for writing and reading from the uart while
1747 * in an interrupt or debug context.
1750 static int serial8250_get_poll_char(struct uart_port *port)
1752 struct uart_8250_port *up = (struct uart_8250_port *)port;
1753 unsigned char lsr = serial_inp(up, UART_LSR);
1755 while (!(lsr & UART_LSR_DR))
1756 lsr = serial_inp(up, UART_LSR);
1758 return serial_inp(up, UART_RX);
1762 static void serial8250_put_poll_char(struct uart_port *port,
1766 struct uart_8250_port *up = (struct uart_8250_port *)port;
1769 * First save the IER then disable the interrupts
1771 ier = serial_in(up, UART_IER);
1772 if (up->capabilities & UART_CAP_UUE)
1773 serial_out(up, UART_IER, UART_IER_UUE);
1775 serial_out(up, UART_IER, 0);
1777 wait_for_xmitr(up, BOTH_EMPTY);
1779 * Send the character out.
1780 * If a LF, also do CR...
1782 serial_out(up, UART_TX, c);
1784 wait_for_xmitr(up, BOTH_EMPTY);
1785 serial_out(up, UART_TX, 13);
1789 * Finally, wait for transmitter to become empty
1790 * and restore the IER
1792 wait_for_xmitr(up, BOTH_EMPTY);
1793 serial_out(up, UART_IER, ier);
1796 #endif /* CONFIG_CONSOLE_POLL */
1798 static int serial8250_startup(struct uart_port *port)
1800 struct uart_8250_port *up = (struct uart_8250_port *)port;
1801 unsigned long flags;
1802 unsigned char lsr, iir;
1805 up->capabilities = uart_config[up->port.type].flags;
1808 if (up->port.type == PORT_16C950) {
1809 /* Wake up and initialize UART */
1811 serial_outp(up, UART_LCR, 0xBF);
1812 serial_outp(up, UART_EFR, UART_EFR_ECB);
1813 serial_outp(up, UART_IER, 0);
1814 serial_outp(up, UART_LCR, 0);
1815 serial_icr_write(up, UART_CSR, 0); /* Reset the UART */
1816 serial_outp(up, UART_LCR, 0xBF);
1817 serial_outp(up, UART_EFR, UART_EFR_ECB);
1818 serial_outp(up, UART_LCR, 0);
1821 #ifdef CONFIG_SERIAL_8250_RSA
1823 * If this is an RSA port, see if we can kick it up to the
1824 * higher speed clock.
1830 * Clear the FIFO buffers and disable them.
1831 * (they will be reenabled in set_termios())
1833 serial8250_clear_fifos(up);
1836 * Clear the interrupt registers.
1838 (void) serial_inp(up, UART_LSR);
1839 (void) serial_inp(up, UART_RX);
1840 (void) serial_inp(up, UART_IIR);
1841 (void) serial_inp(up, UART_MSR);
1844 * At this point, there's no way the LSR could still be 0xff;
1845 * if it is, then bail out, because there's likely no UART
1848 if (!(up->port.flags & UPF_BUGGY_UART) &&
1849 (serial_inp(up, UART_LSR) == 0xff)) {
1850 printk("ttyS%d: LSR safety check engaged!\n", up->port.line);
1855 * For a XR16C850, we need to set the trigger levels
1857 if (up->port.type == PORT_16850) {
1860 serial_outp(up, UART_LCR, 0xbf);
1862 fctr = serial_inp(up, UART_FCTR) & ~(UART_FCTR_RX|UART_FCTR_TX);
1863 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_RX);
1864 serial_outp(up, UART_TRG, UART_TRG_96);
1865 serial_outp(up, UART_FCTR, fctr | UART_FCTR_TRGD | UART_FCTR_TX);
1866 serial_outp(up, UART_TRG, UART_TRG_96);
1868 serial_outp(up, UART_LCR, 0);
1871 if (is_real_interrupt(up->port.irq)) {
1874 * Test for UARTs that do not reassert THRE when the
1875 * transmitter is idle and the interrupt has already
1876 * been cleared. Real 16550s should always reassert
1877 * this interrupt whenever the transmitter is idle and
1878 * the interrupt is enabled. Delays are necessary to
1879 * allow register changes to become visible.
1881 spin_lock_irqsave(&up->port.lock, flags);
1883 wait_for_xmitr(up, UART_LSR_THRE);
1884 serial_out_sync(up, UART_IER, UART_IER_THRI);
1885 udelay(1); /* allow THRE to set */
1886 iir1 = serial_in(up, UART_IIR);
1887 serial_out(up, UART_IER, 0);
1888 serial_out_sync(up, UART_IER, UART_IER_THRI);
1889 udelay(1); /* allow a working UART time to re-assert THRE */
1890 iir = serial_in(up, UART_IIR);
1891 serial_out(up, UART_IER, 0);
1893 spin_unlock_irqrestore(&up->port.lock, flags);
1896 * If the interrupt is not reasserted, setup a timer to
1897 * kick the UART on a regular basis.
1899 if (!(iir1 & UART_IIR_NO_INT) && (iir & UART_IIR_NO_INT)) {
1900 pr_debug("ttyS%d - using backup timer\n", port->line);
1901 up->timer.function = serial8250_backup_timeout;
1902 up->timer.data = (unsigned long)up;
1903 mod_timer(&up->timer, jiffies +
1904 poll_timeout(up->port.timeout) + HZ / 5);
1909 * If the "interrupt" for this port doesn't correspond with any
1910 * hardware interrupt, we use a timer-based system. The original
1911 * driver used to do this with IRQ0.
1913 if (!is_real_interrupt(up->port.irq)) {
1914 up->timer.data = (unsigned long)up;
1915 mod_timer(&up->timer, jiffies + poll_timeout(up->port.timeout));
1917 retval = serial_link_irq_chain(up);
1923 * Now, initialize the UART
1925 serial_outp(up, UART_LCR, UART_LCR_WLEN8);
1927 spin_lock_irqsave(&up->port.lock, flags);
1928 if (up->port.flags & UPF_FOURPORT) {
1929 if (!is_real_interrupt(up->port.irq))
1930 up->port.mctrl |= TIOCM_OUT1;
1933 * Most PC uarts need OUT2 raised to enable interrupts.
1935 if (is_real_interrupt(up->port.irq))
1936 up->port.mctrl |= TIOCM_OUT2;
1938 serial8250_set_mctrl(&up->port, up->port.mctrl);
1941 * Do a quick test to see if we receive an
1942 * interrupt when we enable the TX irq.
1944 serial_outp(up, UART_IER, UART_IER_THRI);
1945 lsr = serial_in(up, UART_LSR);
1946 iir = serial_in(up, UART_IIR);
1947 serial_outp(up, UART_IER, 0);
1949 if (lsr & UART_LSR_TEMT && iir & UART_IIR_NO_INT) {
1950 if (!(up->bugs & UART_BUG_TXEN)) {
1951 up->bugs |= UART_BUG_TXEN;
1952 pr_debug("ttyS%d - enabling bad tx status workarounds\n",
1956 up->bugs &= ~UART_BUG_TXEN;
1959 spin_unlock_irqrestore(&up->port.lock, flags);
1962 * Clear the interrupt registers again for luck, and clear the
1963 * saved flags to avoid getting false values from polling
1964 * routines or the previous session.
1966 serial_inp(up, UART_LSR);
1967 serial_inp(up, UART_RX);
1968 serial_inp(up, UART_IIR);
1969 serial_inp(up, UART_MSR);
1970 up->lsr_saved_flags = 0;
1971 up->msr_saved_flags = 0;
1974 * Finally, enable interrupts. Note: Modem status interrupts
1975 * are set via set_termios(), which will be occurring imminently
1976 * anyway, so we don't enable them here.
1978 up->ier = UART_IER_RLSI | UART_IER_RDI;
1979 serial_outp(up, UART_IER, up->ier);
1981 if (up->port.flags & UPF_FOURPORT) {
1984 * Enable interrupts on the AST Fourport board
1986 icp = (up->port.iobase & 0xfe0) | 0x01f;
1994 static void serial8250_shutdown(struct uart_port *port)
1996 struct uart_8250_port *up = (struct uart_8250_port *)port;
1997 unsigned long flags;
2000 * Disable interrupts from this port
2003 serial_outp(up, UART_IER, 0);
2005 spin_lock_irqsave(&up->port.lock, flags);
2006 if (up->port.flags & UPF_FOURPORT) {
2007 /* reset interrupts on the AST Fourport board */
2008 inb((up->port.iobase & 0xfe0) | 0x1f);
2009 up->port.mctrl |= TIOCM_OUT1;
2011 up->port.mctrl &= ~TIOCM_OUT2;
2013 serial8250_set_mctrl(&up->port, up->port.mctrl);
2014 spin_unlock_irqrestore(&up->port.lock, flags);
2017 * Disable break condition and FIFOs
2019 serial_out(up, UART_LCR, serial_inp(up, UART_LCR) & ~UART_LCR_SBC);
2020 serial8250_clear_fifos(up);
2022 #ifdef CONFIG_SERIAL_8250_RSA
2024 * Reset the RSA board back to 115kbps compat mode.
2030 * Read data port to reset things, and then unlink from
2033 (void) serial_in(up, UART_RX);
2035 del_timer_sync(&up->timer);
2036 up->timer.function = serial8250_timeout;
2037 if (is_real_interrupt(up->port.irq))
2038 serial_unlink_irq_chain(up);
2041 static unsigned int serial8250_get_divisor(struct uart_port *port, unsigned int baud)
2046 * Handle magic divisors for baud rates above baud_base on
2047 * SMSC SuperIO chips.
2049 if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2050 baud == (port->uartclk/4))
2052 else if ((port->flags & UPF_MAGIC_MULTIPLIER) &&
2053 baud == (port->uartclk/8))
2056 quot = uart_get_divisor(port, baud);
2062 serial8250_set_termios(struct uart_port *port, struct ktermios *termios,
2063 struct ktermios *old)
2065 struct uart_8250_port *up = (struct uart_8250_port *)port;
2066 unsigned char cval, fcr = 0;
2067 unsigned long flags;
2068 unsigned int baud, quot;
2070 switch (termios->c_cflag & CSIZE) {
2072 cval = UART_LCR_WLEN5;
2075 cval = UART_LCR_WLEN6;
2078 cval = UART_LCR_WLEN7;
2082 cval = UART_LCR_WLEN8;
2086 if (termios->c_cflag & CSTOPB)
2087 cval |= UART_LCR_STOP;
2088 if (termios->c_cflag & PARENB)
2089 cval |= UART_LCR_PARITY;
2090 if (!(termios->c_cflag & PARODD))
2091 cval |= UART_LCR_EPAR;
2093 if (termios->c_cflag & CMSPAR)
2094 cval |= UART_LCR_SPAR;
2098 * Ask the core to calculate the divisor for us.
2100 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
2101 quot = serial8250_get_divisor(port, baud);
2104 * Oxford Semi 952 rev B workaround
2106 if (up->bugs & UART_BUG_QUOT && (quot & 0xff) == 0)
2109 if (up->capabilities & UART_CAP_FIFO && up->port.fifosize > 1) {
2111 fcr = UART_FCR_ENABLE_FIFO | UART_FCR_TRIGGER_1;
2113 fcr = uart_config[up->port.type].fcr;
2117 * MCR-based auto flow control. When AFE is enabled, RTS will be
2118 * deasserted when the receive FIFO contains more characters than
2119 * the trigger, or the MCR RTS bit is cleared. In the case where
2120 * the remote UART is not using CTS auto flow control, we must
2121 * have sufficient FIFO entries for the latency of the remote
2122 * UART to respond. IOW, at least 32 bytes of FIFO.
2124 if (up->capabilities & UART_CAP_AFE && up->port.fifosize >= 32) {
2125 up->mcr &= ~UART_MCR_AFE;
2126 if (termios->c_cflag & CRTSCTS)
2127 up->mcr |= UART_MCR_AFE;
2131 * Ok, we're now changing the port state. Do it with
2132 * interrupts disabled.
2134 spin_lock_irqsave(&up->port.lock, flags);
2137 * Update the per-port timeout.
2139 uart_update_timeout(port, termios->c_cflag, baud);
2141 up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
2142 if (termios->c_iflag & INPCK)
2143 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
2144 if (termios->c_iflag & (BRKINT | PARMRK))
2145 up->port.read_status_mask |= UART_LSR_BI;
2148 * Characteres to ignore
2150 up->port.ignore_status_mask = 0;
2151 if (termios->c_iflag & IGNPAR)
2152 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
2153 if (termios->c_iflag & IGNBRK) {
2154 up->port.ignore_status_mask |= UART_LSR_BI;
2156 * If we're ignoring parity and break indicators,
2157 * ignore overruns too (for real raw support).
2159 if (termios->c_iflag & IGNPAR)
2160 up->port.ignore_status_mask |= UART_LSR_OE;
2164 * ignore all characters if CREAD is not set
2166 if ((termios->c_cflag & CREAD) == 0)
2167 up->port.ignore_status_mask |= UART_LSR_DR;
2170 * CTS flow control flag and modem status interrupts
2172 up->ier &= ~UART_IER_MSI;
2173 if (!(up->bugs & UART_BUG_NOMSR) &&
2174 UART_ENABLE_MS(&up->port, termios->c_cflag))
2175 up->ier |= UART_IER_MSI;
2176 if (up->capabilities & UART_CAP_UUE)
2177 up->ier |= UART_IER_UUE | UART_IER_RTOIE;
2179 serial_out(up, UART_IER, up->ier);
2181 if (up->capabilities & UART_CAP_EFR) {
2182 unsigned char efr = 0;
2184 * TI16C752/Startech hardware flow control. FIXME:
2185 * - TI16C752 requires control thresholds to be set.
2186 * - UART_MCR_RTS is ineffective if auto-RTS mode is enabled.
2188 if (termios->c_cflag & CRTSCTS)
2189 efr |= UART_EFR_CTS;
2191 serial_outp(up, UART_LCR, 0xBF);
2192 serial_outp(up, UART_EFR, efr);
2195 #ifdef CONFIG_ARCH_OMAP15XX
2196 /* Workaround to enable 115200 baud on OMAP1510 internal ports */
2197 if (cpu_is_omap1510() && is_omap_port((unsigned int)up->port.membase)) {
2198 if (baud == 115200) {
2200 serial_out(up, UART_OMAP_OSC_12M_SEL, 1);
2202 serial_out(up, UART_OMAP_OSC_12M_SEL, 0);
2206 if (up->capabilities & UART_NATSEMI) {
2207 /* Switch to bank 2 not bank 1, to avoid resetting EXCR2 */
2208 serial_outp(up, UART_LCR, 0xe0);
2210 serial_outp(up, UART_LCR, cval | UART_LCR_DLAB);/* set DLAB */
2213 serial_dl_write(up, quot);
2216 * LCR DLAB must be set to enable 64-byte FIFO mode. If the FCR
2217 * is written without DLAB set, this mode will be disabled.
2219 if (up->port.type == PORT_16750)
2220 serial_outp(up, UART_FCR, fcr);
2222 serial_outp(up, UART_LCR, cval); /* reset DLAB */
2223 up->lcr = cval; /* Save LCR */
2224 if (up->port.type != PORT_16750) {
2225 if (fcr & UART_FCR_ENABLE_FIFO) {
2226 /* emulated UARTs (Lucent Venus 167x) need two steps */
2227 serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO);
2229 serial_outp(up, UART_FCR, fcr); /* set fcr */
2231 serial8250_set_mctrl(&up->port, up->port.mctrl);
2232 spin_unlock_irqrestore(&up->port.lock, flags);
2233 /* Don't rewrite B0 */
2234 if (tty_termios_baud_rate(termios))
2235 tty_termios_encode_baud_rate(termios, baud, baud);
2239 serial8250_pm(struct uart_port *port, unsigned int state,
2240 unsigned int oldstate)
2242 struct uart_8250_port *p = (struct uart_8250_port *)port;
2244 serial8250_set_sleep(p, state != 0);
2247 p->pm(port, state, oldstate);
2251 * Resource handling.
2253 static int serial8250_request_std_resource(struct uart_8250_port *up)
2255 unsigned int size = 8 << up->port.regshift;
2258 switch (up->port.iotype) {
2266 if (!up->port.mapbase)
2269 if (!request_mem_region(up->port.mapbase, size, "serial")) {
2274 if (up->port.flags & UPF_IOREMAP) {
2275 up->port.membase = ioremap_nocache(up->port.mapbase,
2277 if (!up->port.membase) {
2278 release_mem_region(up->port.mapbase, size);
2286 if (!request_region(up->port.iobase, size, "serial"))
2293 static void serial8250_release_std_resource(struct uart_8250_port *up)
2295 unsigned int size = 8 << up->port.regshift;
2297 switch (up->port.iotype) {
2305 if (!up->port.mapbase)
2308 if (up->port.flags & UPF_IOREMAP) {
2309 iounmap(up->port.membase);
2310 up->port.membase = NULL;
2313 release_mem_region(up->port.mapbase, size);
2318 release_region(up->port.iobase, size);
2323 static int serial8250_request_rsa_resource(struct uart_8250_port *up)
2325 unsigned long start = UART_RSA_BASE << up->port.regshift;
2326 unsigned int size = 8 << up->port.regshift;
2329 switch (up->port.iotype) {
2332 start += up->port.iobase;
2333 if (request_region(start, size, "serial-rsa"))
2343 static void serial8250_release_rsa_resource(struct uart_8250_port *up)
2345 unsigned long offset = UART_RSA_BASE << up->port.regshift;
2346 unsigned int size = 8 << up->port.regshift;
2348 switch (up->port.iotype) {
2351 release_region(up->port.iobase + offset, size);
2356 static void serial8250_release_port(struct uart_port *port)
2358 struct uart_8250_port *up = (struct uart_8250_port *)port;
2360 serial8250_release_std_resource(up);
2361 if (up->port.type == PORT_RSA)
2362 serial8250_release_rsa_resource(up);
2365 static int serial8250_request_port(struct uart_port *port)
2367 struct uart_8250_port *up = (struct uart_8250_port *)port;
2370 ret = serial8250_request_std_resource(up);
2371 if (ret == 0 && up->port.type == PORT_RSA) {
2372 ret = serial8250_request_rsa_resource(up);
2374 serial8250_release_std_resource(up);
2380 static void serial8250_config_port(struct uart_port *port, int flags)
2382 struct uart_8250_port *up = (struct uart_8250_port *)port;
2383 int probeflags = PROBE_ANY;
2387 * Find the region that we can probe for. This in turn
2388 * tells us whether we can probe for the type of port.
2390 ret = serial8250_request_std_resource(up);
2394 ret = serial8250_request_rsa_resource(up);
2396 probeflags &= ~PROBE_RSA;
2398 if (flags & UART_CONFIG_TYPE)
2399 autoconfig(up, probeflags);
2400 if (up->port.type != PORT_UNKNOWN && flags & UART_CONFIG_IRQ)
2403 if (up->port.type != PORT_RSA && probeflags & PROBE_RSA)
2404 serial8250_release_rsa_resource(up);
2405 if (up->port.type == PORT_UNKNOWN)
2406 serial8250_release_std_resource(up);
2410 serial8250_verify_port(struct uart_port *port, struct serial_struct *ser)
2412 if (ser->irq >= NR_IRQS || ser->irq < 0 ||
2413 ser->baud_base < 9600 || ser->type < PORT_UNKNOWN ||
2414 ser->type >= ARRAY_SIZE(uart_config) || ser->type == PORT_CIRRUS ||
2415 ser->type == PORT_STARTECH)
2421 serial8250_type(struct uart_port *port)
2423 int type = port->type;
2425 if (type >= ARRAY_SIZE(uart_config))
2427 return uart_config[type].name;
2430 static struct uart_ops serial8250_pops = {
2431 .tx_empty = serial8250_tx_empty,
2432 .set_mctrl = serial8250_set_mctrl,
2433 .get_mctrl = serial8250_get_mctrl,
2434 .stop_tx = serial8250_stop_tx,
2435 .start_tx = serial8250_start_tx,
2436 .stop_rx = serial8250_stop_rx,
2437 .enable_ms = serial8250_enable_ms,
2438 .break_ctl = serial8250_break_ctl,
2439 .startup = serial8250_startup,
2440 .shutdown = serial8250_shutdown,
2441 .set_termios = serial8250_set_termios,
2442 .pm = serial8250_pm,
2443 .type = serial8250_type,
2444 .release_port = serial8250_release_port,
2445 .request_port = serial8250_request_port,
2446 .config_port = serial8250_config_port,
2447 .verify_port = serial8250_verify_port,
2448 #ifdef CONFIG_CONSOLE_POLL
2449 .poll_get_char = serial8250_get_poll_char,
2450 .poll_put_char = serial8250_put_poll_char,
2454 static struct uart_8250_port serial8250_ports[UART_NR];
2456 static void __init serial8250_isa_init_ports(void)
2458 struct uart_8250_port *up;
2459 static int first = 1;
2466 for (i = 0; i < nr_uarts; i++) {
2467 struct uart_8250_port *up = &serial8250_ports[i];
2470 spin_lock_init(&up->port.lock);
2472 init_timer(&up->timer);
2473 up->timer.function = serial8250_timeout;
2476 * ALPHA_KLUDGE_MCR needs to be killed.
2478 up->mcr_mask = ~ALPHA_KLUDGE_MCR;
2479 up->mcr_force = ALPHA_KLUDGE_MCR;
2481 up->port.ops = &serial8250_pops;
2484 for (i = 0, up = serial8250_ports;
2485 i < ARRAY_SIZE(old_serial_port) && i < nr_uarts;
2487 up->port.iobase = old_serial_port[i].port;
2488 up->port.irq = irq_canonicalize(old_serial_port[i].irq);
2489 up->port.uartclk = old_serial_port[i].baud_base * 16;
2490 up->port.flags = old_serial_port[i].flags;
2491 up->port.hub6 = old_serial_port[i].hub6;
2492 up->port.membase = old_serial_port[i].iomem_base;
2493 up->port.iotype = old_serial_port[i].io_type;
2494 up->port.regshift = old_serial_port[i].iomem_reg_shift;
2496 up->port.flags |= UPF_SHARE_IRQ;
2501 serial8250_register_ports(struct uart_driver *drv, struct device *dev)
2505 serial8250_isa_init_ports();
2507 for (i = 0; i < nr_uarts; i++) {
2508 struct uart_8250_port *up = &serial8250_ports[i];
2511 uart_add_one_port(drv, &up->port);
2515 #ifdef CONFIG_SERIAL_8250_CONSOLE
2517 static void serial8250_console_putchar(struct uart_port *port, int ch)
2519 struct uart_8250_port *up = (struct uart_8250_port *)port;
2521 wait_for_xmitr(up, UART_LSR_THRE);
2522 serial_out(up, UART_TX, ch);
2526 * Print a string to the serial port trying not to disturb
2527 * any possible real use of the port...
2529 * The console_lock must be held when we get here.
2532 serial8250_console_write(struct console *co, const char *s, unsigned int count)
2534 struct uart_8250_port *up = &serial8250_ports[co->index];
2535 unsigned long flags;
2539 touch_nmi_watchdog();
2541 local_irq_save(flags);
2542 if (up->port.sysrq) {
2543 /* serial8250_handle_port() already took the lock */
2545 } else if (oops_in_progress) {
2546 locked = spin_trylock(&up->port.lock);
2548 spin_lock(&up->port.lock);
2551 * First save the IER then disable the interrupts
2553 ier = serial_in(up, UART_IER);
2555 if (up->capabilities & UART_CAP_UUE)
2556 serial_out(up, UART_IER, UART_IER_UUE);
2558 serial_out(up, UART_IER, 0);
2560 uart_console_write(&up->port, s, count, serial8250_console_putchar);
2563 * Finally, wait for transmitter to become empty
2564 * and restore the IER
2566 wait_for_xmitr(up, BOTH_EMPTY);
2567 serial_out(up, UART_IER, ier);
2570 * The receive handling will happen properly because the
2571 * receive ready bit will still be set; it is not cleared
2572 * on read. However, modem control will not, we must
2573 * call it if we have saved something in the saved flags
2574 * while processing with interrupts off.
2576 if (up->msr_saved_flags)
2577 check_modem_status(up);
2580 spin_unlock(&up->port.lock);
2581 local_irq_restore(flags);
2584 static int __init serial8250_console_setup(struct console *co, char *options)
2586 struct uart_port *port;
2593 * Check whether an invalid uart number has been specified, and
2594 * if so, search for the first available port that does have
2597 if (co->index >= nr_uarts)
2599 port = &serial8250_ports[co->index].port;
2600 if (!port->iobase && !port->membase)
2604 uart_parse_options(options, &baud, &parity, &bits, &flow);
2606 return uart_set_options(port, co, baud, parity, bits, flow);
2609 static int serial8250_console_early_setup(void)
2611 return serial8250_find_port_for_earlycon();
2614 static struct uart_driver serial8250_reg;
2615 static struct console serial8250_console = {
2617 .write = serial8250_console_write,
2618 .device = uart_console_device,
2619 .setup = serial8250_console_setup,
2620 .early_setup = serial8250_console_early_setup,
2621 .flags = CON_PRINTBUFFER,
2623 .data = &serial8250_reg,
2626 static int __init serial8250_console_init(void)
2628 serial8250_isa_init_ports();
2629 register_console(&serial8250_console);
2632 console_initcall(serial8250_console_init);
2634 int serial8250_find_port(struct uart_port *p)
2637 struct uart_port *port;
2639 for (line = 0; line < nr_uarts; line++) {
2640 port = &serial8250_ports[line].port;
2641 if (uart_match_port(p, port))
2647 #define SERIAL8250_CONSOLE &serial8250_console
2649 #define SERIAL8250_CONSOLE NULL
2652 static struct uart_driver serial8250_reg = {
2653 .owner = THIS_MODULE,
2654 .driver_name = "serial",
2659 .cons = SERIAL8250_CONSOLE,
2663 * early_serial_setup - early registration for 8250 ports
2665 * Setup an 8250 port structure prior to console initialisation. Use
2666 * after console initialisation will cause undefined behaviour.
2668 int __init early_serial_setup(struct uart_port *port)
2670 if (port->line >= ARRAY_SIZE(serial8250_ports))
2673 serial8250_isa_init_ports();
2674 serial8250_ports[port->line].port = *port;
2675 serial8250_ports[port->line].port.ops = &serial8250_pops;
2680 * serial8250_suspend_port - suspend one serial port
2681 * @line: serial line number
2683 * Suspend one serial port.
2685 void serial8250_suspend_port(int line)
2687 uart_suspend_port(&serial8250_reg, &serial8250_ports[line].port);
2691 * serial8250_resume_port - resume one serial port
2692 * @line: serial line number
2694 * Resume one serial port.
2696 void serial8250_resume_port(int line)
2698 struct uart_8250_port *up = &serial8250_ports[line];
2700 if (up->capabilities & UART_NATSEMI) {
2703 /* Ensure it's still in high speed mode */
2704 serial_outp(up, UART_LCR, 0xE0);
2706 tmp = serial_in(up, 0x04); /* EXCR2 */
2707 tmp &= ~0xB0; /* Disable LOCK, mask out PRESL[01] */
2708 tmp |= 0x10; /* 1.625 divisor for baud_base --> 921600 */
2709 serial_outp(up, 0x04, tmp);
2711 serial_outp(up, UART_LCR, 0);
2713 uart_resume_port(&serial8250_reg, &up->port);
2717 * Register a set of serial devices attached to a platform device. The
2718 * list is terminated with a zero flags entry, which means we expect
2719 * all entries to have at least UPF_BOOT_AUTOCONF set.
2721 static int __devinit serial8250_probe(struct platform_device *dev)
2723 struct plat_serial8250_port *p = dev->dev.platform_data;
2724 struct uart_port port;
2727 memset(&port, 0, sizeof(struct uart_port));
2729 for (i = 0; p && p->flags != 0; p++, i++) {
2730 port.iobase = p->iobase;
2731 port.membase = p->membase;
2733 port.uartclk = p->uartclk;
2734 port.regshift = p->regshift;
2735 port.iotype = p->iotype;
2736 port.flags = p->flags;
2737 port.mapbase = p->mapbase;
2738 port.hub6 = p->hub6;
2739 port.private_data = p->private_data;
2740 port.dev = &dev->dev;
2742 port.flags |= UPF_SHARE_IRQ;
2743 ret = serial8250_register_port(&port);
2745 dev_err(&dev->dev, "unable to register port at index %d "
2746 "(IO%lx MEM%llx IRQ%d): %d\n", i,
2747 p->iobase, (unsigned long long)p->mapbase,
2755 * Remove serial ports registered against a platform device.
2757 static int __devexit serial8250_remove(struct platform_device *dev)
2761 for (i = 0; i < nr_uarts; i++) {
2762 struct uart_8250_port *up = &serial8250_ports[i];
2764 if (up->port.dev == &dev->dev)
2765 serial8250_unregister_port(i);
2770 static int serial8250_suspend(struct platform_device *dev, pm_message_t state)
2774 for (i = 0; i < UART_NR; i++) {
2775 struct uart_8250_port *up = &serial8250_ports[i];
2777 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
2778 uart_suspend_port(&serial8250_reg, &up->port);
2784 static int serial8250_resume(struct platform_device *dev)
2788 for (i = 0; i < UART_NR; i++) {
2789 struct uart_8250_port *up = &serial8250_ports[i];
2791 if (up->port.type != PORT_UNKNOWN && up->port.dev == &dev->dev)
2792 serial8250_resume_port(i);
2798 static struct platform_driver serial8250_isa_driver = {
2799 .probe = serial8250_probe,
2800 .remove = __devexit_p(serial8250_remove),
2801 .suspend = serial8250_suspend,
2802 .resume = serial8250_resume,
2804 .name = "serial8250",
2805 .owner = THIS_MODULE,
2810 * This "device" covers _all_ ISA 8250-compatible serial devices listed
2811 * in the table in include/asm/serial.h
2813 static struct platform_device *serial8250_isa_devs;
2816 * serial8250_register_port and serial8250_unregister_port allows for
2817 * 16x50 serial ports to be configured at run-time, to support PCMCIA
2818 * modems and PCI multiport cards.
2820 static DEFINE_MUTEX(serial_mutex);
2822 static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *port)
2827 * First, find a port entry which matches.
2829 for (i = 0; i < nr_uarts; i++)
2830 if (uart_match_port(&serial8250_ports[i].port, port))
2831 return &serial8250_ports[i];
2834 * We didn't find a matching entry, so look for the first
2835 * free entry. We look for one which hasn't been previously
2836 * used (indicated by zero iobase).
2838 for (i = 0; i < nr_uarts; i++)
2839 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
2840 serial8250_ports[i].port.iobase == 0)
2841 return &serial8250_ports[i];
2844 * That also failed. Last resort is to find any entry which
2845 * doesn't have a real port associated with it.
2847 for (i = 0; i < nr_uarts; i++)
2848 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
2849 return &serial8250_ports[i];
2855 * serial8250_register_port - register a serial port
2856 * @port: serial port template
2858 * Configure the serial port specified by the request. If the
2859 * port exists and is in use, it is hung up and unregistered
2862 * The port is then probed and if necessary the IRQ is autodetected
2863 * If this fails an error is returned.
2865 * On success the port is ready to use and the line number is returned.
2867 int serial8250_register_port(struct uart_port *port)
2869 struct uart_8250_port *uart;
2872 if (port->uartclk == 0)
2875 mutex_lock(&serial_mutex);
2877 uart = serial8250_find_match_or_unused(port);
2879 uart_remove_one_port(&serial8250_reg, &uart->port);
2881 uart->port.iobase = port->iobase;
2882 uart->port.membase = port->membase;
2883 uart->port.irq = port->irq;
2884 uart->port.uartclk = port->uartclk;
2885 uart->port.fifosize = port->fifosize;
2886 uart->port.regshift = port->regshift;
2887 uart->port.iotype = port->iotype;
2888 uart->port.flags = port->flags | UPF_BOOT_AUTOCONF;
2889 uart->port.mapbase = port->mapbase;
2890 uart->port.private_data = port->private_data;
2892 uart->port.dev = port->dev;
2894 ret = uart_add_one_port(&serial8250_reg, &uart->port);
2896 ret = uart->port.line;
2898 mutex_unlock(&serial_mutex);
2902 EXPORT_SYMBOL(serial8250_register_port);
2905 * serial8250_unregister_port - remove a 16x50 serial port at runtime
2906 * @line: serial line number
2908 * Remove one serial port. This may not be called from interrupt
2909 * context. We hand the port back to the our control.
2911 void serial8250_unregister_port(int line)
2913 struct uart_8250_port *uart = &serial8250_ports[line];
2915 mutex_lock(&serial_mutex);
2916 uart_remove_one_port(&serial8250_reg, &uart->port);
2917 if (serial8250_isa_devs) {
2918 uart->port.flags &= ~UPF_BOOT_AUTOCONF;
2919 uart->port.type = PORT_UNKNOWN;
2920 uart->port.dev = &serial8250_isa_devs->dev;
2921 uart_add_one_port(&serial8250_reg, &uart->port);
2923 uart->port.dev = NULL;
2925 mutex_unlock(&serial_mutex);
2927 EXPORT_SYMBOL(serial8250_unregister_port);
2929 static int __init serial8250_init(void)
2933 if (nr_uarts > UART_NR)
2936 printk(KERN_INFO "Serial: 8250/16550 driver $Revision: 1.90 $ "
2937 "%d ports, IRQ sharing %sabled\n", nr_uarts,
2938 share_irqs ? "en" : "dis");
2940 for (i = 0; i < NR_IRQS; i++)
2941 spin_lock_init(&irq_lists[i].lock);
2943 ret = uart_register_driver(&serial8250_reg);
2947 serial8250_isa_devs = platform_device_alloc("serial8250",
2948 PLAT8250_DEV_LEGACY);
2949 if (!serial8250_isa_devs) {
2951 goto unreg_uart_drv;
2954 ret = platform_device_add(serial8250_isa_devs);
2958 serial8250_register_ports(&serial8250_reg, &serial8250_isa_devs->dev);
2960 ret = platform_driver_register(&serial8250_isa_driver);
2964 platform_device_del(serial8250_isa_devs);
2966 platform_device_put(serial8250_isa_devs);
2968 uart_unregister_driver(&serial8250_reg);
2973 static void __exit serial8250_exit(void)
2975 struct platform_device *isa_dev = serial8250_isa_devs;
2978 * This tells serial8250_unregister_port() not to re-register
2979 * the ports (thereby making serial8250_isa_driver permanently
2982 serial8250_isa_devs = NULL;
2984 platform_driver_unregister(&serial8250_isa_driver);
2985 platform_device_unregister(isa_dev);
2987 uart_unregister_driver(&serial8250_reg);
2990 module_init(serial8250_init);
2991 module_exit(serial8250_exit);
2993 EXPORT_SYMBOL(serial8250_suspend_port);
2994 EXPORT_SYMBOL(serial8250_resume_port);
2996 MODULE_LICENSE("GPL");
2997 MODULE_DESCRIPTION("Generic 8250/16x50 serial driver $Revision: 1.90 $");
2999 module_param(share_irqs, uint, 0644);
3000 MODULE_PARM_DESC(share_irqs, "Share IRQs with other non-8250/16x50 devices"
3003 module_param(nr_uarts, uint, 0644);
3004 MODULE_PARM_DESC(nr_uarts, "Maximum number of UARTs supported. (1-" __MODULE_STRING(CONFIG_SERIAL_8250_NR_UARTS) ")");
3006 #ifdef CONFIG_SERIAL_8250_RSA
3007 module_param_array(probe_rsa, ulong, &probe_rsa_count, 0444);
3008 MODULE_PARM_DESC(probe_rsa, "Probe I/O ports for RSA");
3010 MODULE_ALIAS_CHARDEV_MAJOR(TTY_MAJOR);