err.no Git - linux-2.6/blob - drivers/scsi/sata_sx4.c

   1 /*
   2  *  sata_sx4.c - Promise SATA
   3  *
   4  *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
   5  *                  Please ALWAYS copy linux-ide@vger.kernel.org
   6  *                  on emails.
   7  *
   8  *  Copyright 2003-2004 Red Hat, Inc.
   9  *
  10  *  The contents of this file are subject to the Open
  11  *  Software License version 1.1 that can be found at
  12  *  http://www.opensource.org/licenses/osl-1.1.txt and is included herein
  13  *  by reference.
  14  *
  15  *  Alternatively, the contents of this file may be used under the terms
  16  *  of the GNU General Public License version 2 (the "GPL") as distributed
  17  *  in the kernel source COPYING file, in which case the provisions of
  18  *  the GPL are applicable instead of the above.  If you wish to allow
  19  *  the use of your version of this file only under the terms of the
  20  *  GPL and not to allow others to use your version of this file under
  21  *  the OSL, indicate your decision by deleting the provisions above and
  22  *  replace them with the notice and other provisions required by the GPL.
  23  *  If you do not delete the provisions above, a recipient may use your
  24  *  version of this file under either the OSL or the GPL.
  25  *
  26  */
  27
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/init.h>
  32 #include <linux/blkdev.h>
  33 #include <linux/delay.h>
  34 #include <linux/interrupt.h>
  35 #include <linux/sched.h>
  36 #include "scsi.h"
  37 #include <scsi/scsi_host.h>
  38 #include <linux/libata.h>
  39 #include <asm/io.h>
  40 #include "sata_promise.h"
  41
  42 #define DRV_NAME        "sata_sx4"
  43 #define DRV_VERSION     "0.7"
  44
  45
  46 enum {
  47         PDC_PRD_TBL             = 0x44, /* Direct command DMA table addr */
  48
  49         PDC_PKT_SUBMIT          = 0x40, /* Command packet pointer addr */
  50         PDC_HDMA_PKT_SUBMIT     = 0x100, /* Host DMA packet pointer addr */
  51         PDC_INT_SEQMASK         = 0x40, /* Mask of asserted SEQ INTs */
  52         PDC_HDMA_CTLSTAT        = 0x12C, /* Host DMA control / status */
  53
  54         PDC_20621_SEQCTL        = 0x400,
  55         PDC_20621_SEQMASK       = 0x480,
  56         PDC_20621_GENERAL_CTL   = 0x484,
  57         PDC_20621_PAGE_SIZE     = (32 * 1024),
  58
  59         /* chosen, not constant, values; we design our own DIMM mem map */
  60         PDC_20621_DIMM_WINDOW   = 0x0C, /* page# for 32K DIMM window */
  61         PDC_20621_DIMM_BASE     = 0x00200000,
  62         PDC_20621_DIMM_DATA     = (64 * 1024),
  63         PDC_DIMM_DATA_STEP      = (256 * 1024),
  64         PDC_DIMM_WINDOW_STEP    = (8 * 1024),
  65         PDC_DIMM_HOST_PRD       = (6 * 1024),
  66         PDC_DIMM_HOST_PKT       = (128 * 0),
  67         PDC_DIMM_HPKT_PRD       = (128 * 1),
  68         PDC_DIMM_ATA_PKT        = (128 * 2),
  69         PDC_DIMM_APKT_PRD       = (128 * 3),
  70         PDC_DIMM_HEADER_SZ      = PDC_DIMM_APKT_PRD + 128,
  71         PDC_PAGE_WINDOW         = 0x40,
  72         PDC_PAGE_DATA           = PDC_PAGE_WINDOW +
  73                                   (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE),
  74         PDC_PAGE_SET            = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE,
  75
  76         PDC_CHIP0_OFS           = 0xC0000, /* offset of chip #0 */
  77
  78         PDC_20621_ERR_MASK      = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
  79                                   (1<<23),
  80
  81         board_20621             = 0,    /* FastTrak S150 SX4 */
  82
  83         PDC_RESET               = (1 << 11), /* HDMA reset */
  84
  85         PDC_MAX_HDMA            = 32,
  86         PDC_HDMA_Q_MASK         = (PDC_MAX_HDMA - 1),
  87
  88         PDC_DIMM0_SPD_DEV_ADDRESS     = 0x50,
  89         PDC_DIMM1_SPD_DEV_ADDRESS     = 0x51,
  90         PDC_MAX_DIMM_MODULE           = 0x02,
  91         PDC_I2C_CONTROL_OFFSET        = 0x48,
  92         PDC_I2C_ADDR_DATA_OFFSET      = 0x4C,
  93         PDC_DIMM0_CONTROL_OFFSET      = 0x80,
  94         PDC_DIMM1_CONTROL_OFFSET      = 0x84,
  95         PDC_SDRAM_CONTROL_OFFSET      = 0x88,
  96         PDC_I2C_WRITE                 = 0x00000000,
  97         PDC_I2C_READ                  = 0x00000040,
  98         PDC_I2C_START                 = 0x00000080,
  99         PDC_I2C_MASK_INT              = 0x00000020,
 100         PDC_I2C_COMPLETE              = 0x00010000,
 101         PDC_I2C_NO_ACK                = 0x00100000,
 102         PDC_DIMM_SPD_SUBADDRESS_START = 0x00,
 103         PDC_DIMM_SPD_SUBADDRESS_END   = 0x7F,
 104         PDC_DIMM_SPD_ROW_NUM          = 3,
 105         PDC_DIMM_SPD_COLUMN_NUM       = 4,
 106         PDC_DIMM_SPD_MODULE_ROW       = 5,
 107         PDC_DIMM_SPD_TYPE             = 11,
 108         PDC_DIMM_SPD_FRESH_RATE       = 12,
 109         PDC_DIMM_SPD_BANK_NUM         = 17,
 110         PDC_DIMM_SPD_CAS_LATENCY      = 18,
 111         PDC_DIMM_SPD_ATTRIBUTE        = 21,
 112         PDC_DIMM_SPD_ROW_PRE_CHARGE   = 27,
 113         PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28,
 114         PDC_DIMM_SPD_RAS_CAS_DELAY    = 29,
 115         PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30,
 116         PDC_DIMM_SPD_SYSTEM_FREQ      = 126,
 117         PDC_CTL_STATUS                = 0x08,
 118         PDC_DIMM_WINDOW_CTLR          = 0x0C,
 119         PDC_TIME_CONTROL              = 0x3C,
 120         PDC_TIME_PERIOD               = 0x40,
 121         PDC_TIME_COUNTER              = 0x44,
 122         PDC_GENERAL_CTLR              = 0x484,
 123         PCI_PLL_INIT                  = 0x8A531824,
 124         PCI_X_TCOUNT                  = 0xEE1E5CFF
 125 };
 126
 127
 128 struct pdc_port_priv {
 129         u8                      dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512];
 130         u8                      *pkt;
 131         dma_addr_t              pkt_dma;
 132 };
 133
 134 struct pdc_host_priv {
 135         void                    *dimm_mmio;
 136
 137         unsigned int            doing_hdma;
 138         unsigned int            hdma_prod;
 139         unsigned int            hdma_cons;
 140         struct {
 141                 struct ata_queued_cmd *qc;
 142                 unsigned int    seq;
 143                 unsigned long   pkt_ofs;
 144         } hdma[32];
 145 };
 146
 147
 148 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
 149 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
 150 static void pdc_eng_timeout(struct ata_port *ap);
 151 static void pdc_20621_phy_reset (struct ata_port *ap);
 152 static int pdc_port_start(struct ata_port *ap);
 153 static void pdc_port_stop(struct ata_port *ap);
 154 static void pdc20621_qc_prep(struct ata_queued_cmd *qc);
 155 static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf);
 156 static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf);
 157 static void pdc20621_host_stop(struct ata_host_set *host_set);
 158 static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe);
 159 static int pdc20621_detect_dimm(struct ata_probe_ent *pe);
 160 static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe,
 161                                       u32 device, u32 subaddr, u32 *pdata);
 162 static int pdc20621_prog_dimm0(struct ata_probe_ent *pe);
 163 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe);
 164 #ifdef ATA_VERBOSE_DEBUG
 165 static void pdc20621_get_from_dimm(struct ata_probe_ent *pe,
 166                                    void *psource, u32 offset, u32 size);
 167 #endif
 168 static void pdc20621_put_to_dimm(struct ata_probe_ent *pe,
 169                                  void *psource, u32 offset, u32 size);
 170 static void pdc20621_irq_clear(struct ata_port *ap);
 171 static int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc);
 172
 173
 174 static Scsi_Host_Template pdc_sata_sht = {
 175         .module                 = THIS_MODULE,
 176         .name                   = DRV_NAME,
 177         .ioctl                  = ata_scsi_ioctl,
 178         .queuecommand           = ata_scsi_queuecmd,
 179         .eh_strategy_handler    = ata_scsi_error,
 180         .can_queue              = ATA_DEF_QUEUE,
 181         .this_id                = ATA_SHT_THIS_ID,
 182         .sg_tablesize           = LIBATA_MAX_PRD,
 183         .max_sectors            = ATA_MAX_SECTORS,
 184         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
 185         .emulated               = ATA_SHT_EMULATED,
 186         .use_clustering         = ATA_SHT_USE_CLUSTERING,
 187         .proc_name              = DRV_NAME,
 188         .dma_boundary           = ATA_DMA_BOUNDARY,
 189         .slave_configure        = ata_scsi_slave_config,
 190         .bios_param             = ata_std_bios_param,
 191         .ordered_flush          = 1,
 192 };
 193
 194 static struct ata_port_operations pdc_20621_ops = {
 195         .port_disable           = ata_port_disable,
 196         .tf_load                = pdc_tf_load_mmio,
 197         .tf_read                = ata_tf_read,
 198         .check_status           = ata_check_status,
 199         .exec_command           = pdc_exec_command_mmio,
 200         .dev_select             = ata_std_dev_select,
 201         .phy_reset              = pdc_20621_phy_reset,
 202         .qc_prep                = pdc20621_qc_prep,
 203         .qc_issue               = pdc20621_qc_issue_prot,
 204         .eng_timeout            = pdc_eng_timeout,
 205         .irq_handler            = pdc20621_interrupt,
 206         .irq_clear              = pdc20621_irq_clear,
 207         .port_start             = pdc_port_start,
 208         .port_stop              = pdc_port_stop,
 209         .host_stop              = pdc20621_host_stop,
 210 };
 211
 212 static struct ata_port_info pdc_port_info[] = {
 213         /* board_20621 */
 214         {
 215                 .sht            = &pdc_sata_sht,
 216                 .host_flags     = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
 217                                   ATA_FLAG_SRST | ATA_FLAG_MMIO,
 218                 .pio_mask       = 0x1f, /* pio0-4 */
 219                 .mwdma_mask     = 0x07, /* mwdma0-2 */
 220                 .udma_mask      = 0x7f, /* udma0-6 ; FIXME */
 221                 .port_ops       = &pdc_20621_ops,
 222         },
 223
 224 };
 225
 226 static struct pci_device_id pdc_sata_pci_tbl[] = {
 227         { PCI_VENDOR_ID_PROMISE, 0x6622, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
 228           board_20621 },
 229         { }     /* terminate list */
 230 };
 231
 232
 233 static struct pci_driver pdc_sata_pci_driver = {
 234         .name                   = DRV_NAME,
 235         .id_table               = pdc_sata_pci_tbl,
 236         .probe                  = pdc_sata_init_one,
 237         .remove                 = ata_pci_remove_one,
 238 };
 239
 240
 241 static void pdc20621_host_stop(struct ata_host_set *host_set)
 242 {
 243         struct pdc_host_priv *hpriv = host_set->private_data;
 244         void *dimm_mmio = hpriv->dimm_mmio;
 245
 246         iounmap(dimm_mmio);
 247         kfree(hpriv);
 248
 249         ata_host_stop(host_set);
 250 }
 251
 252 static int pdc_port_start(struct ata_port *ap)
 253 {
 254         struct device *dev = ap->host_set->dev;
 255         struct pdc_port_priv *pp;
 256         int rc;
 257
 258         rc = ata_port_start(ap);
 259         if (rc)
 260                 return rc;
 261
 262         pp = kmalloc(sizeof(*pp), GFP_KERNEL);
 263         if (!pp) {
 264                 rc = -ENOMEM;
 265                 goto err_out;
 266         }
 267         memset(pp, 0, sizeof(*pp));
 268
 269         pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
 270         if (!pp->pkt) {
 271                 rc = -ENOMEM;
 272                 goto err_out_kfree;
 273         }
 274
 275         ap->private_data = pp;
 276
 277         return 0;
 278
 279 err_out_kfree:
 280         kfree(pp);
 281 err_out:
 282         ata_port_stop(ap);
 283         return rc;
 284 }
 285
 286
 287 static void pdc_port_stop(struct ata_port *ap)
 288 {
 289         struct device *dev = ap->host_set->dev;
 290         struct pdc_port_priv *pp = ap->private_data;
 291
 292         ap->private_data = NULL;
 293         dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
 294         kfree(pp);
 295         ata_port_stop(ap);
 296 }
 297
 298
 299 static void pdc_20621_phy_reset (struct ata_port *ap)
 300 {
 301         VPRINTK("ENTER\n");
 302         ap->cbl = ATA_CBL_SATA;
 303         ata_port_probe(ap);
 304         ata_bus_reset(ap);
 305 }
 306
 307 static inline void pdc20621_ata_sg(struct ata_taskfile *tf, u8 *buf,
 308                                            unsigned int portno,
 309                                            unsigned int total_len)
 310 {
 311         u32 addr;
 312         unsigned int dw = PDC_DIMM_APKT_PRD >> 2;
 313         u32 *buf32 = (u32 *) buf;
 314
 315         /* output ATA packet S/G table */
 316         addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
 317                (PDC_DIMM_DATA_STEP * portno);
 318         VPRINTK("ATA sg addr 0x%x, %d\n", addr, addr);
 319         buf32[dw] = cpu_to_le32(addr);
 320         buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
 321
 322         VPRINTK("ATA PSG @ %x == (0x%x, 0x%x)\n",
 323                 PDC_20621_DIMM_BASE +
 324                        (PDC_DIMM_WINDOW_STEP * portno) +
 325                        PDC_DIMM_APKT_PRD,
 326                 buf32[dw], buf32[dw + 1]);
 327 }
 328
 329 static inline void pdc20621_host_sg(struct ata_taskfile *tf, u8 *buf,
 330                                             unsigned int portno,
 331                                             unsigned int total_len)
 332 {
 333         u32 addr;
 334         unsigned int dw = PDC_DIMM_HPKT_PRD >> 2;
 335         u32 *buf32 = (u32 *) buf;
 336
 337         /* output Host DMA packet S/G table */
 338         addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
 339                (PDC_DIMM_DATA_STEP * portno);
 340
 341         buf32[dw] = cpu_to_le32(addr);
 342         buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
 343
 344         VPRINTK("HOST PSG @ %x == (0x%x, 0x%x)\n",
 345                 PDC_20621_DIMM_BASE +
 346                        (PDC_DIMM_WINDOW_STEP * portno) +
 347                        PDC_DIMM_HPKT_PRD,
 348                 buf32[dw], buf32[dw + 1]);
 349 }
 350
 351 static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
 352                                             unsigned int devno, u8 *buf,
 353                                             unsigned int portno)
 354 {
 355         unsigned int i, dw;
 356         u32 *buf32 = (u32 *) buf;
 357         u8 dev_reg;
 358
 359         unsigned int dimm_sg = PDC_20621_DIMM_BASE +
 360                                (PDC_DIMM_WINDOW_STEP * portno) +
 361                                PDC_DIMM_APKT_PRD;
 362         VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
 363
 364         i = PDC_DIMM_ATA_PKT;
 365
 366         /*
 367          * Set up ATA packet
 368          */
 369         if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
 370                 buf[i++] = PDC_PKT_READ;
 371         else if (tf->protocol == ATA_PROT_NODATA)
 372                 buf[i++] = PDC_PKT_NODATA;
 373         else
 374                 buf[i++] = 0;
 375         buf[i++] = 0;                   /* reserved */
 376         buf[i++] = portno + 1;          /* seq. id */
 377         buf[i++] = 0xff;                /* delay seq. id */
 378
 379         /* dimm dma S/G, and next-pkt */
 380         dw = i >> 2;
 381         if (tf->protocol == ATA_PROT_NODATA)
 382                 buf32[dw] = 0;
 383         else
 384                 buf32[dw] = cpu_to_le32(dimm_sg);
 385         buf32[dw + 1] = 0;
 386         i += 8;
 387
 388         if (devno == 0)
 389                 dev_reg = ATA_DEVICE_OBS;
 390         else
 391                 dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
 392
 393         /* select device */
 394         buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
 395         buf[i++] = dev_reg;
 396
 397         /* device control register */
 398         buf[i++] = (1 << 5) | PDC_REG_DEVCTL;
 399         buf[i++] = tf->ctl;
 400
 401         return i;
 402 }
 403
 404 static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
 405                                      unsigned int portno)
 406 {
 407         unsigned int dw;
 408         u32 tmp, *buf32 = (u32 *) buf;
 409
 410         unsigned int host_sg = PDC_20621_DIMM_BASE +
 411                                (PDC_DIMM_WINDOW_STEP * portno) +
 412                                PDC_DIMM_HOST_PRD;
 413         unsigned int dimm_sg = PDC_20621_DIMM_BASE +
 414                                (PDC_DIMM_WINDOW_STEP * portno) +
 415                                PDC_DIMM_HPKT_PRD;
 416         VPRINTK("ENTER, dimm_sg == 0x%x, %d\n", dimm_sg, dimm_sg);
 417         VPRINTK("host_sg == 0x%x, %d\n", host_sg, host_sg);
 418
 419         dw = PDC_DIMM_HOST_PKT >> 2;
 420
 421         /*
 422          * Set up Host DMA packet
 423          */
 424         if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
 425                 tmp = PDC_PKT_READ;
 426         else
 427                 tmp = 0;
 428         tmp |= ((portno + 1 + 4) << 16);        /* seq. id */
 429         tmp |= (0xff << 24);                    /* delay seq. id */
 430         buf32[dw + 0] = cpu_to_le32(tmp);
 431         buf32[dw + 1] = cpu_to_le32(host_sg);
 432         buf32[dw + 2] = cpu_to_le32(dimm_sg);
 433         buf32[dw + 3] = 0;
 434
 435         VPRINTK("HOST PKT @ %x == (0x%x 0x%x 0x%x 0x%x)\n",
 436                 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * portno) +
 437                         PDC_DIMM_HOST_PKT,
 438                 buf32[dw + 0],
 439                 buf32[dw + 1],
 440                 buf32[dw + 2],
 441                 buf32[dw + 3]);
 442 }
 443
 444 static void pdc20621_dma_prep(struct ata_queued_cmd *qc)
 445 {
 446         struct scatterlist *sg = qc->sg;
 447         struct ata_port *ap = qc->ap;
 448         struct pdc_port_priv *pp = ap->private_data;
 449         void *mmio = ap->host_set->mmio_base;
 450         struct pdc_host_priv *hpriv = ap->host_set->private_data;
 451         void *dimm_mmio = hpriv->dimm_mmio;
 452         unsigned int portno = ap->port_no;
 453         unsigned int i, last, idx, total_len = 0, sgt_len;
 454         u32 *buf = (u32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ];
 455
 456         assert(qc->flags & ATA_QCFLAG_DMAMAP);
 457
 458         VPRINTK("ata%u: ENTER\n", ap->id);
 459
 460         /* hard-code chip #0 */
 461         mmio += PDC_CHIP0_OFS;
 462
 463         /*
 464          * Build S/G table
 465          */
 466         last = qc->n_elem;
 467         idx = 0;
 468         for (i = 0; i < last; i++) {
 469                 buf[idx++] = cpu_to_le32(sg_dma_address(&sg[i]));
 470                 buf[idx++] = cpu_to_le32(sg_dma_len(&sg[i]));
 471                 total_len += sg_dma_len(&sg[i]);
 472         }
 473         buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT);
 474         sgt_len = idx * 4;
 475
 476         /*
 477          * Build ATA, host DMA packets
 478          */
 479         pdc20621_host_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
 480         pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno);
 481
 482         pdc20621_ata_sg(&qc->tf, &pp->dimm_buf[0], portno, total_len);
 483         i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
 484
 485         if (qc->tf.flags & ATA_TFLAG_LBA48)
 486                 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
 487         else
 488                 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
 489
 490         pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
 491
 492         /* copy three S/G tables and two packets to DIMM MMIO window */
 493         memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
 494                     &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
 495         memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) +
 496                     PDC_DIMM_HOST_PRD,
 497                     &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len);
 498
 499         /* force host FIFO dump */
 500         writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
 501
 502         readl(dimm_mmio);       /* MMIO PCI posting flush */
 503
 504         VPRINTK("ata pkt buf ofs %u, prd size %u, mmio copied\n", i, sgt_len);
 505 }
 506
 507 static void pdc20621_nodata_prep(struct ata_queued_cmd *qc)
 508 {
 509         struct ata_port *ap = qc->ap;
 510         struct pdc_port_priv *pp = ap->private_data;
 511         void *mmio = ap->host_set->mmio_base;
 512         struct pdc_host_priv *hpriv = ap->host_set->private_data;
 513         void *dimm_mmio = hpriv->dimm_mmio;
 514         unsigned int portno = ap->port_no;
 515         unsigned int i;
 516
 517         VPRINTK("ata%u: ENTER\n", ap->id);
 518
 519         /* hard-code chip #0 */
 520         mmio += PDC_CHIP0_OFS;
 521
 522         i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
 523
 524         if (qc->tf.flags & ATA_TFLAG_LBA48)
 525                 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
 526         else
 527                 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
 528
 529         pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
 530
 531         /* copy three S/G tables and two packets to DIMM MMIO window */
 532         memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
 533                     &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
 534
 535         /* force host FIFO dump */
 536         writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
 537
 538         readl(dimm_mmio);       /* MMIO PCI posting flush */
 539
 540         VPRINTK("ata pkt buf ofs %u, mmio copied\n", i);
 541 }
 542
 543 static void pdc20621_qc_prep(struct ata_queued_cmd *qc)
 544 {
 545         switch (qc->tf.protocol) {
 546         case ATA_PROT_DMA:
 547                 pdc20621_dma_prep(qc);
 548                 break;
 549         case ATA_PROT_NODATA:
 550                 pdc20621_nodata_prep(qc);
 551                 break;
 552         default:
 553                 break;
 554         }
 555 }
 556
 557 static void __pdc20621_push_hdma(struct ata_queued_cmd *qc,
 558                                  unsigned int seq,
 559                                  u32 pkt_ofs)
 560 {
 561         struct ata_port *ap = qc->ap;
 562         struct ata_host_set *host_set = ap->host_set;
 563         void *mmio = host_set->mmio_base;
 564
 565         /* hard-code chip #0 */
 566         mmio += PDC_CHIP0_OFS;
 567
 568         writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
 569         readl(mmio + PDC_20621_SEQCTL + (seq * 4));     /* flush */
 570
 571         writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
 572         readl(mmio + PDC_HDMA_PKT_SUBMIT);      /* flush */
 573 }
 574
 575 static void pdc20621_push_hdma(struct ata_queued_cmd *qc,
 576                                 unsigned int seq,
 577                                 u32 pkt_ofs)
 578 {
 579         struct ata_port *ap = qc->ap;
 580         struct pdc_host_priv *pp = ap->host_set->private_data;
 581         unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK;
 582
 583         if (!pp->doing_hdma) {
 584                 __pdc20621_push_hdma(qc, seq, pkt_ofs);
 585                 pp->doing_hdma = 1;
 586                 return;
 587         }
 588
 589         pp->hdma[idx].qc = qc;
 590         pp->hdma[idx].seq = seq;
 591         pp->hdma[idx].pkt_ofs = pkt_ofs;
 592         pp->hdma_prod++;
 593 }
 594
 595 static void pdc20621_pop_hdma(struct ata_queued_cmd *qc)
 596 {
 597         struct ata_port *ap = qc->ap;
 598         struct pdc_host_priv *pp = ap->host_set->private_data;
 599         unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK;
 600
 601         /* if nothing on queue, we're done */
 602         if (pp->hdma_prod == pp->hdma_cons) {
 603                 pp->doing_hdma = 0;
 604                 return;
 605         }
 606
 607         __pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq,
 608                              pp->hdma[idx].pkt_ofs);
 609         pp->hdma_cons++;
 610 }
 611
 612 #ifdef ATA_VERBOSE_DEBUG
 613 static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
 614 {
 615         struct ata_port *ap = qc->ap;
 616         unsigned int port_no = ap->port_no;
 617         struct pdc_host_priv *hpriv = ap->host_set->private_data;
 618         void *dimm_mmio = hpriv->dimm_mmio;
 619
 620         dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP);
 621         dimm_mmio += PDC_DIMM_HOST_PKT;
 622
 623         printk(KERN_ERR "HDMA[0] == 0x%08X\n", readl(dimm_mmio));
 624         printk(KERN_ERR "HDMA[1] == 0x%08X\n", readl(dimm_mmio + 4));
 625         printk(KERN_ERR "HDMA[2] == 0x%08X\n", readl(dimm_mmio + 8));
 626         printk(KERN_ERR "HDMA[3] == 0x%08X\n", readl(dimm_mmio + 12));
 627 }
 628 #else
 629 static inline void pdc20621_dump_hdma(struct ata_queued_cmd *qc) { }
 630 #endif /* ATA_VERBOSE_DEBUG */
 631
 632 static void pdc20621_packet_start(struct ata_queued_cmd *qc)
 633 {
 634         struct ata_port *ap = qc->ap;
 635         struct ata_host_set *host_set = ap->host_set;
 636         unsigned int port_no = ap->port_no;
 637         void *mmio = host_set->mmio_base;
 638         unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
 639         u8 seq = (u8) (port_no + 1);
 640         unsigned int port_ofs;
 641
 642         /* hard-code chip #0 */
 643         mmio += PDC_CHIP0_OFS;
 644
 645         VPRINTK("ata%u: ENTER\n", ap->id);
 646
 647         wmb();                  /* flush PRD, pkt writes */
 648
 649         port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
 650
 651         /* if writing, we (1) DMA to DIMM, then (2) do ATA command */
 652         if (rw && qc->tf.protocol == ATA_PROT_DMA) {
 653                 seq += 4;
 654
 655                 pdc20621_dump_hdma(qc);
 656                 pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT);
 657                 VPRINTK("queued ofs 0x%x (%u), seq %u\n",
 658                         port_ofs + PDC_DIMM_HOST_PKT,
 659                         port_ofs + PDC_DIMM_HOST_PKT,
 660                         seq);
 661         } else {
 662                 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
 663                 readl(mmio + PDC_20621_SEQCTL + (seq * 4));     /* flush */
 664
 665                 writel(port_ofs + PDC_DIMM_ATA_PKT,
 666                        (void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 667                 readl((void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 668                 VPRINTK("submitted ofs 0x%x (%u), seq %u\n",
 669                         port_ofs + PDC_DIMM_ATA_PKT,
 670                         port_ofs + PDC_DIMM_ATA_PKT,
 671                         seq);
 672         }
 673 }
 674
 675 static int pdc20621_qc_issue_prot(struct ata_queued_cmd *qc)
 676 {
 677         switch (qc->tf.protocol) {
 678         case ATA_PROT_DMA:
 679         case ATA_PROT_NODATA:
 680                 pdc20621_packet_start(qc);
 681                 return 0;
 682
 683         case ATA_PROT_ATAPI_DMA:
 684                 BUG();
 685                 break;
 686
 687         default:
 688                 break;
 689         }
 690
 691         return ata_qc_issue_prot(qc);
 692 }
 693
 694 static inline unsigned int pdc20621_host_intr( struct ata_port *ap,
 695                                           struct ata_queued_cmd *qc,
 696                                           unsigned int doing_hdma,
 697                                           void *mmio)
 698 {
 699         unsigned int port_no = ap->port_no;
 700         unsigned int port_ofs =
 701                 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
 702         u8 status;
 703         unsigned int handled = 0;
 704
 705         VPRINTK("ENTER\n");
 706
 707         if ((qc->tf.protocol == ATA_PROT_DMA) &&        /* read */
 708             (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
 709
 710                 /* step two - DMA from DIMM to host */
 711                 if (doing_hdma) {
 712                         VPRINTK("ata%u: read hdma, 0x%x 0x%x\n", ap->id,
 713                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 714                         /* get drive status; clear intr; complete txn */
 715                         ata_qc_complete(qc, ata_wait_idle(ap));
 716                         pdc20621_pop_hdma(qc);
 717                 }
 718
 719                 /* step one - exec ATA command */
 720                 else {
 721                         u8 seq = (u8) (port_no + 1 + 4);
 722                         VPRINTK("ata%u: read ata, 0x%x 0x%x\n", ap->id,
 723                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 724
 725                         /* submit hdma pkt */
 726                         pdc20621_dump_hdma(qc);
 727                         pdc20621_push_hdma(qc, seq,
 728                                            port_ofs + PDC_DIMM_HOST_PKT);
 729                 }
 730                 handled = 1;
 731
 732         } else if (qc->tf.protocol == ATA_PROT_DMA) {   /* write */
 733
 734                 /* step one - DMA from host to DIMM */
 735                 if (doing_hdma) {
 736                         u8 seq = (u8) (port_no + 1);
 737                         VPRINTK("ata%u: write hdma, 0x%x 0x%x\n", ap->id,
 738                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 739
 740                         /* submit ata pkt */
 741                         writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
 742                         readl(mmio + PDC_20621_SEQCTL + (seq * 4));
 743                         writel(port_ofs + PDC_DIMM_ATA_PKT,
 744                                (void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 745                         readl((void *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
 746                 }
 747
 748                 /* step two - execute ATA command */
 749                 else {
 750                         VPRINTK("ata%u: write ata, 0x%x 0x%x\n", ap->id,
 751                                 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
 752                         /* get drive status; clear intr; complete txn */
 753                         ata_qc_complete(qc, ata_wait_idle(ap));
 754                         pdc20621_pop_hdma(qc);
 755                 }
 756                 handled = 1;
 757
 758         /* command completion, but no data xfer */
 759         } else if (qc->tf.protocol == ATA_PROT_NODATA) {
 760
 761                 status = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
 762                 DPRINTK("BUS_NODATA (drv_stat 0x%X)\n", status);
 763                 ata_qc_complete(qc, status);
 764                 handled = 1;
 765
 766         } else {
 767                 ap->stats.idle_irq++;
 768         }
 769
 770         return handled;
 771 }
 772
 773 static void pdc20621_irq_clear(struct ata_port *ap)
 774 {
 775         struct ata_host_set *host_set = ap->host_set;
 776         void *mmio = host_set->mmio_base;
 777
 778         mmio += PDC_CHIP0_OFS;
 779
 780         readl(mmio + PDC_20621_SEQMASK);
 781 }
 782
 783 static irqreturn_t pdc20621_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
 784 {
 785         struct ata_host_set *host_set = dev_instance;
 786         struct ata_port *ap;
 787         u32 mask = 0;
 788         unsigned int i, tmp, port_no;
 789         unsigned int handled = 0;
 790         void *mmio_base;
 791
 792         VPRINTK("ENTER\n");
 793
 794         if (!host_set || !host_set->mmio_base) {
 795                 VPRINTK("QUICK EXIT\n");
 796                 return IRQ_NONE;
 797         }
 798
 799         mmio_base = host_set->mmio_base;
 800
 801         /* reading should also clear interrupts */
 802         mmio_base += PDC_CHIP0_OFS;
 803         mask = readl(mmio_base + PDC_20621_SEQMASK);
 804         VPRINTK("mask == 0x%x\n", mask);
 805
 806         if (mask == 0xffffffff) {
 807                 VPRINTK("QUICK EXIT 2\n");
 808                 return IRQ_NONE;
 809         }
 810         mask &= 0xffff;         /* only 16 tags possible */
 811         if (!mask) {
 812                 VPRINTK("QUICK EXIT 3\n");
 813                 return IRQ_NONE;
 814         }
 815
 816         spin_lock(&host_set->lock);
 817
 818         for (i = 1; i < 9; i++) {
 819                 port_no = i - 1;
 820                 if (port_no > 3)
 821                         port_no -= 4;
 822                 if (port_no >= host_set->n_ports)
 823                         ap = NULL;
 824                 else
 825                         ap = host_set->ports[port_no];
 826                 tmp = mask & (1 << i);
 827                 VPRINTK("seq %u, port_no %u, ap %p, tmp %x\n", i, port_no, ap, tmp);
 828                 if (tmp && ap &&
 829                     !(ap->flags & (ATA_FLAG_PORT_DISABLED | ATA_FLAG_NOINTR))) {
 830                         struct ata_queued_cmd *qc;
 831
 832                         qc = ata_qc_from_tag(ap, ap->active_tag);
 833                         if (qc && (!(qc->tf.ctl & ATA_NIEN)))
 834                                 handled += pdc20621_host_intr(ap, qc, (i > 4),
 835                                                               mmio_base);
 836                 }
 837         }
 838
 839         spin_unlock(&host_set->lock);
 840
 841         VPRINTK("mask == 0x%x\n", mask);
 842
 843         VPRINTK("EXIT\n");
 844
 845         return IRQ_RETVAL(handled);
 846 }
 847
 848 static void pdc_eng_timeout(struct ata_port *ap)
 849 {
 850         u8 drv_stat;
 851         struct ata_host_set *host_set = ap->host_set;
 852         struct ata_queued_cmd *qc;
 853         unsigned long flags;
 854
 855         DPRINTK("ENTER\n");
 856
 857         spin_lock_irqsave(&host_set->lock, flags);
 858
 859         qc = ata_qc_from_tag(ap, ap->active_tag);
 860         if (!qc) {
 861                 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
 862                        ap->id);
 863                 goto out;
 864         }
 865
 866         /* hack alert!  We cannot use the supplied completion
 867          * function from inside the ->eh_strategy_handler() thread.
 868          * libata is the only user of ->eh_strategy_handler() in
 869          * any kernel, so the default scsi_done() assumes it is
 870          * not being called from the SCSI EH.
 871          */
 872         qc->scsidone = scsi_finish_command;
 873
 874         switch (qc->tf.protocol) {
 875         case ATA_PROT_DMA:
 876         case ATA_PROT_NODATA:
 877                 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
 878                 ata_qc_complete(qc, ata_wait_idle(ap) | ATA_ERR);
 879                 break;
 880
 881         default:
 882                 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
 883
 884                 printk(KERN_ERR "ata%u: unknown timeout, cmd 0x%x stat 0x%x\n",
 885                        ap->id, qc->tf.command, drv_stat);
 886
 887                 ata_qc_complete(qc, drv_stat);
 888                 break;
 889         }
 890
 891 out:
 892         spin_unlock_irqrestore(&host_set->lock, flags);
 893         DPRINTK("EXIT\n");
 894 }
 895
 896 static void pdc_tf_load_mmio(struct ata_port *ap, struct ata_taskfile *tf)
 897 {
 898         WARN_ON (tf->protocol == ATA_PROT_DMA ||
 899                  tf->protocol == ATA_PROT_NODATA);
 900         ata_tf_load(ap, tf);
 901 }
 902
 903
 904 static void pdc_exec_command_mmio(struct ata_port *ap, struct ata_taskfile *tf)
 905 {
 906         WARN_ON (tf->protocol == ATA_PROT_DMA ||
 907                  tf->protocol == ATA_PROT_NODATA);
 908         ata_exec_command(ap, tf);
 909 }
 910
 911
 912 static void pdc_sata_setup_port(struct ata_ioports *port, unsigned long base)
 913 {
 914         port->cmd_addr          = base;
 915         port->data_addr         = base;
 916         port->feature_addr      =
 917         port->error_addr        = base + 0x4;
 918         port->nsect_addr        = base + 0x8;
 919         port->lbal_addr         = base + 0xc;
 920         port->lbam_addr         = base + 0x10;
 921         port->lbah_addr         = base + 0x14;
 922         port->device_addr       = base + 0x18;
 923         port->command_addr      =
 924         port->status_addr       = base + 0x1c;
 925         port->altstatus_addr    =
 926         port->ctl_addr          = base + 0x38;
 927 }
 928
 929
 930 #ifdef ATA_VERBOSE_DEBUG
 931 static void pdc20621_get_from_dimm(struct ata_probe_ent *pe, void *psource,
 932                                    u32 offset, u32 size)
 933 {
 934         u32 window_size;
 935         u16 idx;
 936         u8 page_mask;
 937         long dist;
 938         void *mmio = pe->mmio_base;
 939         struct pdc_host_priv *hpriv = pe->private_data;
 940         void *dimm_mmio = hpriv->dimm_mmio;
 941
 942         /* hard-code chip #0 */
 943         mmio += PDC_CHIP0_OFS;
 944
 945         page_mask = 0x00;
 946         window_size = 0x2000 * 4; /* 32K byte uchar size */
 947         idx = (u16) (offset / window_size);
 948
 949         writel(0x01, mmio + PDC_GENERAL_CTLR);
 950         readl(mmio + PDC_GENERAL_CTLR);
 951         writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 952         readl(mmio + PDC_DIMM_WINDOW_CTLR);
 953
 954         offset -= (idx * window_size);
 955         idx++;
 956         dist = ((long) (window_size - (offset + size))) >= 0 ? size :
 957                 (long) (window_size - offset);
 958         memcpy_fromio((char *) psource, (char *) (dimm_mmio + offset / 4),
 959                       dist);
 960
 961         psource += dist;
 962         size -= dist;
 963         for (; (long) size >= (long) window_size ;) {
 964                 writel(0x01, mmio + PDC_GENERAL_CTLR);
 965                 readl(mmio + PDC_GENERAL_CTLR);
 966                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 967                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
 968                 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
 969                               window_size / 4);
 970                 psource += window_size;
 971                 size -= window_size;
 972                 idx ++;
 973         }
 974
 975         if (size) {
 976                 writel(0x01, mmio + PDC_GENERAL_CTLR);
 977                 readl(mmio + PDC_GENERAL_CTLR);
 978                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
 979                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
 980                 memcpy_fromio((char *) psource, (char *) (dimm_mmio),
 981                               size / 4);
 982         }
 983 }
 984 #endif
 985
 986
 987 static void pdc20621_put_to_dimm(struct ata_probe_ent *pe, void *psource,
 988                                  u32 offset, u32 size)
 989 {
 990         u32 window_size;
 991         u16 idx;
 992         u8 page_mask;
 993         long dist;
 994         void *mmio = pe->mmio_base;
 995         struct pdc_host_priv *hpriv = pe->private_data;
 996         void *dimm_mmio = hpriv->dimm_mmio;
 997
 998         /* hard-code chip #0 */
 999         mmio += PDC_CHIP0_OFS;
1000
1001         page_mask = 0x00;
1002         window_size = 0x2000 * 4;       /* 32K byte uchar size */
1003         idx = (u16) (offset / window_size);
1004
1005         writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1006         readl(mmio + PDC_DIMM_WINDOW_CTLR);
1007         offset -= (idx * window_size);
1008         idx++;
1009         dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size :
1010                 (long) (window_size - offset);
1011         memcpy_toio((char *) (dimm_mmio + offset / 4), (char *) psource, dist);
1012         writel(0x01, mmio + PDC_GENERAL_CTLR);
1013         readl(mmio + PDC_GENERAL_CTLR);
1014
1015         psource += dist;
1016         size -= dist;
1017         for (; (long) size >= (long) window_size ;) {
1018                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1019                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1020                 memcpy_toio((char *) (dimm_mmio), (char *) psource,
1021                             window_size / 4);
1022                 writel(0x01, mmio + PDC_GENERAL_CTLR);
1023                 readl(mmio + PDC_GENERAL_CTLR);
1024                 psource += window_size;
1025                 size -= window_size;
1026                 idx ++;
1027         }
1028
1029         if (size) {
1030                 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1031                 readl(mmio + PDC_DIMM_WINDOW_CTLR);
1032                 memcpy_toio((char *) (dimm_mmio), (char *) psource, size / 4);
1033                 writel(0x01, mmio + PDC_GENERAL_CTLR);
1034                 readl(mmio + PDC_GENERAL_CTLR);
1035         }
1036 }
1037
1038
1039 static unsigned int pdc20621_i2c_read(struct ata_probe_ent *pe, u32 device,
1040                                       u32 subaddr, u32 *pdata)
1041 {
1042         void *mmio = pe->mmio_base;
1043         u32 i2creg  = 0;
1044         u32 status;
1045         u32 count =0;
1046
1047         /* hard-code chip #0 */
1048         mmio += PDC_CHIP0_OFS;
1049
1050         i2creg |= device << 24;
1051         i2creg |= subaddr << 16;
1052
1053         /* Set the device and subaddress */
1054         writel(i2creg, mmio + PDC_I2C_ADDR_DATA_OFFSET);
1055         readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1056
1057         /* Write Control to perform read operation, mask int */
1058         writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
1059                mmio + PDC_I2C_CONTROL_OFFSET);
1060
1061         for (count = 0; count <= 1000; count ++) {
1062                 status = readl(mmio + PDC_I2C_CONTROL_OFFSET);
1063                 if (status & PDC_I2C_COMPLETE) {
1064                         status = readl(mmio + PDC_I2C_ADDR_DATA_OFFSET);
1065                         break;
1066                 } else if (count == 1000)
1067                         return 0;
1068         }
1069
1070         *pdata = (status >> 8) & 0x000000ff;
1071         return 1;
1072 }
1073
1074
1075 static int pdc20621_detect_dimm(struct ata_probe_ent *pe)
1076 {
1077         u32 data=0 ;
1078         if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1079                              PDC_DIMM_SPD_SYSTEM_FREQ, &data)) {
1080                 if (data == 100)
1081                         return 100;
1082         } else
1083                 return 0;
1084
1085         if (pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) {
1086                 if(data <= 0x75)
1087                         return 133;
1088         } else
1089                 return 0;
1090
1091         return 0;
1092 }
1093
1094
1095 static int pdc20621_prog_dimm0(struct ata_probe_ent *pe)
1096 {
1097         u32 spd0[50];
1098         u32 data = 0;
1099         int size, i;
1100         u8 bdimmsize;
1101         void *mmio = pe->mmio_base;
1102         static const struct {
1103                 unsigned int reg;
1104                 unsigned int ofs;
1105         } pdc_i2c_read_data [] = {
1106                 { PDC_DIMM_SPD_TYPE, 11 },
1107                 { PDC_DIMM_SPD_FRESH_RATE, 12 },
1108                 { PDC_DIMM_SPD_COLUMN_NUM, 4 },
1109                 { PDC_DIMM_SPD_ATTRIBUTE, 21 },
1110                 { PDC_DIMM_SPD_ROW_NUM, 3 },
1111                 { PDC_DIMM_SPD_BANK_NUM, 17 },
1112                 { PDC_DIMM_SPD_MODULE_ROW, 5 },
1113                 { PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 },
1114                 { PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 },
1115                 { PDC_DIMM_SPD_RAS_CAS_DELAY, 29 },
1116                 { PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 },
1117                 { PDC_DIMM_SPD_CAS_LATENCY, 18 },
1118         };
1119
1120         /* hard-code chip #0 */
1121         mmio += PDC_CHIP0_OFS;
1122
1123         for(i=0; i<ARRAY_SIZE(pdc_i2c_read_data); i++)
1124                 pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1125                                   pdc_i2c_read_data[i].reg,
1126                                   &spd0[pdc_i2c_read_data[i].ofs]);
1127
1128         data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
1129         data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
1130                 ((((spd0[27] + 9) / 10) - 1) << 8) ;
1131         data |= (((((spd0[29] > spd0[28])
1132                     ? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10;
1133         data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12;
1134
1135         if (spd0[18] & 0x08)
1136                 data |= ((0x03) << 14);
1137         else if (spd0[18] & 0x04)
1138                 data |= ((0x02) << 14);
1139         else if (spd0[18] & 0x01)
1140                 data |= ((0x01) << 14);
1141         else
1142                 data |= (0 << 14);
1143
1144         /*
1145            Calculate the size of bDIMMSize (power of 2) and
1146            merge the DIMM size by program start/end address.
1147         */
1148
1149         bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3;
1150         size = (1 << bdimmsize) >> 20;  /* size = xxx(MB) */
1151         data |= (((size / 16) - 1) << 16);
1152         data |= (0 << 23);
1153         data |= 8;
1154         writel(data, mmio + PDC_DIMM0_CONTROL_OFFSET);
1155         readl(mmio + PDC_DIMM0_CONTROL_OFFSET);
1156         return size;
1157 }
1158
1159
1160 static unsigned int pdc20621_prog_dimm_global(struct ata_probe_ent *pe)
1161 {
1162         u32 data, spd0;
1163         int error, i;
1164         void *mmio = pe->mmio_base;
1165
1166         /* hard-code chip #0 */
1167         mmio += PDC_CHIP0_OFS;
1168
1169         /*
1170           Set To Default : DIMM Module Global Control Register (0x022259F1)
1171           DIMM Arbitration Disable (bit 20)
1172           DIMM Data/Control Output Driving Selection (bit12 - bit15)
1173           Refresh Enable (bit 17)
1174         */
1175
1176         data = 0x022259F1;
1177         writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1178         readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1179
1180         /* Turn on for ECC */
1181         pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1182                           PDC_DIMM_SPD_TYPE, &spd0);
1183         if (spd0 == 0x02) {
1184                 data |= (0x01 << 16);
1185                 writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1186                 readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1187                 printk(KERN_ERR "Local DIMM ECC Enabled\n");
1188         }
1189
1190         /* DIMM Initialization Select/Enable (bit 18/19) */
1191         data &= (~(1<<18));
1192         data |= (1<<19);
1193         writel(data, mmio + PDC_SDRAM_CONTROL_OFFSET);
1194
1195         error = 1;
1196         for (i = 1; i <= 10; i++) {   /* polling ~5 secs */
1197                 data = readl(mmio + PDC_SDRAM_CONTROL_OFFSET);
1198                 if (!(data & (1<<19))) {
1199                         error = 0;
1200                         break;
1201                 }
1202                 msleep(i*100);
1203         }
1204         return error;
1205 }
1206
1207
1208 static unsigned int pdc20621_dimm_init(struct ata_probe_ent *pe)
1209 {
1210         int speed, size, length;
1211         u32 addr,spd0,pci_status;
1212         u32 tmp=0;
1213         u32 time_period=0;
1214         u32 tcount=0;
1215         u32 ticks=0;
1216         u32 clock=0;
1217         u32 fparam=0;
1218         void *mmio = pe->mmio_base;
1219
1220         /* hard-code chip #0 */
1221         mmio += PDC_CHIP0_OFS;
1222
1223         /* Initialize PLL based upon PCI Bus Frequency */
1224
1225         /* Initialize Time Period Register */
1226         writel(0xffffffff, mmio + PDC_TIME_PERIOD);
1227         time_period = readl(mmio + PDC_TIME_PERIOD);
1228         VPRINTK("Time Period Register (0x40): 0x%x\n", time_period);
1229
1230         /* Enable timer */
1231         writel(0x00001a0, mmio + PDC_TIME_CONTROL);
1232         readl(mmio + PDC_TIME_CONTROL);
1233
1234         /* Wait 3 seconds */
1235         msleep(3000);
1236
1237         /*
1238            When timer is enabled, counter is decreased every internal
1239            clock cycle.
1240         */
1241
1242         tcount = readl(mmio + PDC_TIME_COUNTER);
1243         VPRINTK("Time Counter Register (0x44): 0x%x\n", tcount);
1244
1245         /*
1246            If SX4 is on PCI-X bus, after 3 seconds, the timer counter
1247            register should be >= (0xffffffff - 3x10^8).
1248         */
1249         if(tcount >= PCI_X_TCOUNT) {
1250                 ticks = (time_period - tcount);
1251                 VPRINTK("Num counters 0x%x (%d)\n", ticks, ticks);
1252
1253                 clock = (ticks / 300000);
1254                 VPRINTK("10 * Internal clk = 0x%x (%d)\n", clock, clock);
1255
1256                 clock = (clock * 33);
1257                 VPRINTK("10 * Internal clk * 33 = 0x%x (%d)\n", clock, clock);
1258
1259                 /* PLL F Param (bit 22:16) */
1260                 fparam = (1400000 / clock) - 2;
1261                 VPRINTK("PLL F Param: 0x%x (%d)\n", fparam, fparam);
1262
1263                 /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
1264                 pci_status = (0x8a001824 | (fparam << 16));
1265         } else
1266                 pci_status = PCI_PLL_INIT;
1267
1268         /* Initialize PLL. */
1269         VPRINTK("pci_status: 0x%x\n", pci_status);
1270         writel(pci_status, mmio + PDC_CTL_STATUS);
1271         readl(mmio + PDC_CTL_STATUS);
1272
1273         /*
1274            Read SPD of DIMM by I2C interface,
1275            and program the DIMM Module Controller.
1276         */
1277         if (!(speed = pdc20621_detect_dimm(pe))) {
1278                 printk(KERN_ERR "Detect Local DIMM Fail\n");
1279                 return 1;       /* DIMM error */
1280         }
1281         VPRINTK("Local DIMM Speed = %d\n", speed);
1282
1283         /* Programming DIMM0 Module Control Register (index_CID0:80h) */
1284         size = pdc20621_prog_dimm0(pe);
1285         VPRINTK("Local DIMM Size = %dMB\n",size);
1286
1287         /* Programming DIMM Module Global Control Register (index_CID0:88h) */
1288         if (pdc20621_prog_dimm_global(pe)) {
1289                 printk(KERN_ERR "Programming DIMM Module Global Control Register Fail\n");
1290                 return 1;
1291         }
1292
1293 #ifdef ATA_VERBOSE_DEBUG
1294         {
1295                 u8 test_parttern1[40] = {0x55,0xAA,'P','r','o','m','i','s','e',' ',
1296                                 'N','o','t',' ','Y','e','t',' ','D','e','f','i','n','e','d',' ',
1297                                  '1','.','1','0',
1298                                 '9','8','0','3','1','6','1','2',0,0};
1299                 u8 test_parttern2[40] = {0};
1300
1301                 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x10040, 40);
1302                 pdc20621_put_to_dimm(pe, (void *) test_parttern2, 0x40, 40);
1303
1304                 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x10040, 40);
1305                 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
1306                 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1307                        test_parttern2[1], &(test_parttern2[2]));
1308                 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x10040,
1309                                        40);
1310                 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1311                        test_parttern2[1], &(test_parttern2[2]));
1312
1313                 pdc20621_put_to_dimm(pe, (void *) test_parttern1, 0x40, 40);
1314                 pdc20621_get_from_dimm(pe, (void *) test_parttern2, 0x40, 40);
1315                 printk(KERN_ERR "%x, %x, %s\n", test_parttern2[0],
1316                        test_parttern2[1], &(test_parttern2[2]));
1317         }
1318 #endif
1319
1320         /* ECC initiliazation. */
1321
1322         pdc20621_i2c_read(pe, PDC_DIMM0_SPD_DEV_ADDRESS,
1323                           PDC_DIMM_SPD_TYPE, &spd0);
1324         if (spd0 == 0x02) {
1325                 VPRINTK("Start ECC initialization\n");
1326                 addr = 0;
1327                 length = size * 1024 * 1024;
1328                 while (addr < length) {
1329                         pdc20621_put_to_dimm(pe, (void *) &tmp, addr,
1330                                              sizeof(u32));
1331                         addr += sizeof(u32);
1332                 }
1333                 VPRINTK("Finish ECC initialization\n");
1334         }
1335         return 0;
1336 }
1337
1338
1339 static void pdc_20621_init(struct ata_probe_ent *pe)
1340 {
1341         u32 tmp;
1342         void *mmio = pe->mmio_base;
1343
1344         /* hard-code chip #0 */
1345         mmio += PDC_CHIP0_OFS;
1346
1347         /*
1348          * Select page 0x40 for our 32k DIMM window
1349          */
1350         tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
1351         tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */
1352         writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
1353
1354         /*
1355          * Reset Host DMA
1356          */
1357         tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1358         tmp |= PDC_RESET;
1359         writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1360         readl(mmio + PDC_HDMA_CTLSTAT);         /* flush */
1361
1362         udelay(10);
1363
1364         tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1365         tmp &= ~PDC_RESET;
1366         writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1367         readl(mmio + PDC_HDMA_CTLSTAT);         /* flush */
1368 }
1369
1370 static int pdc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1371 {
1372         static int printed_version;
1373         struct ata_probe_ent *probe_ent = NULL;
1374         unsigned long base;
1375         void *mmio_base, *dimm_mmio = NULL;
1376         struct pdc_host_priv *hpriv = NULL;
1377         unsigned int board_idx = (unsigned int) ent->driver_data;
1378         int pci_dev_busy = 0;
1379         int rc;
1380
1381         if (!printed_version++)
1382                 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
1383
1384         /*
1385          * If this driver happens to only be useful on Apple's K2, then
1386          * we should check that here as it has a normal Serverworks ID
1387          */
1388         rc = pci_enable_device(pdev);
1389         if (rc)
1390                 return rc;
1391
1392         rc = pci_request_regions(pdev, DRV_NAME);
1393         if (rc) {
1394                 pci_dev_busy = 1;
1395                 goto err_out;
1396         }
1397
1398         rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1399         if (rc)
1400                 goto err_out_regions;
1401         rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1402         if (rc)
1403                 goto err_out_regions;
1404
1405         probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1406         if (probe_ent == NULL) {
1407                 rc = -ENOMEM;
1408                 goto err_out_regions;
1409         }
1410
1411         memset(probe_ent, 0, sizeof(*probe_ent));
1412         probe_ent->dev = pci_dev_to_dev(pdev);
1413         INIT_LIST_HEAD(&probe_ent->node);
1414
1415         mmio_base = ioremap(pci_resource_start(pdev, 3),
1416                             pci_resource_len(pdev, 3));
1417         if (mmio_base == NULL) {
1418                 rc = -ENOMEM;
1419                 goto err_out_free_ent;
1420         }
1421         base = (unsigned long) mmio_base;
1422
1423         hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1424         if (!hpriv) {
1425                 rc = -ENOMEM;
1426                 goto err_out_iounmap;
1427         }
1428         memset(hpriv, 0, sizeof(*hpriv));
1429
1430         dimm_mmio = ioremap(pci_resource_start(pdev, 4),
1431                             pci_resource_len(pdev, 4));
1432         if (!dimm_mmio) {
1433                 kfree(hpriv);
1434                 rc = -ENOMEM;
1435                 goto err_out_iounmap;
1436         }
1437
1438         hpriv->dimm_mmio = dimm_mmio;
1439
1440         probe_ent->sht          = pdc_port_info[board_idx].sht;
1441         probe_ent->host_flags   = pdc_port_info[board_idx].host_flags;
1442         probe_ent->pio_mask     = pdc_port_info[board_idx].pio_mask;
1443         probe_ent->mwdma_mask   = pdc_port_info[board_idx].mwdma_mask;
1444         probe_ent->udma_mask    = pdc_port_info[board_idx].udma_mask;
1445         probe_ent->port_ops     = pdc_port_info[board_idx].port_ops;
1446
1447         probe_ent->irq = pdev->irq;
1448         probe_ent->irq_flags = SA_SHIRQ;
1449         probe_ent->mmio_base = mmio_base;
1450
1451         probe_ent->private_data = hpriv;
1452         base += PDC_CHIP0_OFS;
1453
1454         probe_ent->n_ports = 4;
1455         pdc_sata_setup_port(&probe_ent->port[0], base + 0x200);
1456         pdc_sata_setup_port(&probe_ent->port[1], base + 0x280);
1457         pdc_sata_setup_port(&probe_ent->port[2], base + 0x300);
1458         pdc_sata_setup_port(&probe_ent->port[3], base + 0x380);
1459
1460         pci_set_master(pdev);
1461
1462         /* initialize adapter */
1463         /* initialize local dimm */
1464         if (pdc20621_dimm_init(probe_ent)) {
1465                 rc = -ENOMEM;
1466                 goto err_out_iounmap_dimm;
1467         }
1468         pdc_20621_init(probe_ent);
1469
1470         /* FIXME: check ata_device_add return value */
1471         ata_device_add(probe_ent);
1472         kfree(probe_ent);
1473
1474         return 0;
1475
1476 err_out_iounmap_dimm:           /* only get to this label if 20621 */
1477         kfree(hpriv);
1478         iounmap(dimm_mmio);
1479 err_out_iounmap:
1480         iounmap(mmio_base);
1481 err_out_free_ent:
1482         kfree(probe_ent);
1483 err_out_regions:
1484         pci_release_regions(pdev);
1485 err_out:
1486         if (!pci_dev_busy)
1487                 pci_disable_device(pdev);
1488         return rc;
1489 }
1490
1491
1492 static int __init pdc_sata_init(void)
1493 {
1494         return pci_module_init(&pdc_sata_pci_driver);
1495 }
1496
1497
1498 static void __exit pdc_sata_exit(void)
1499 {
1500         pci_unregister_driver(&pdc_sata_pci_driver);
1501 }
1502
1503
1504 MODULE_AUTHOR("Jeff Garzik");
1505 MODULE_DESCRIPTION("Promise SATA low-level driver");
1506 MODULE_LICENSE("GPL");
1507 MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
1508 MODULE_VERSION(DRV_VERSION);
1509
1510 module_init(pdc_sata_init);
1511 module_exit(pdc_sata_exit);