2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
4 * Copyright 2005 Tejun Heo
6 * Based on preview driver from Silicon Image.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/blkdev.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/device.h>
28 #include <scsi/scsi_host.h>
29 #include <scsi/scsi_cmnd.h>
30 #include <linux/libata.h>
33 #define DRV_NAME "sata_sil24"
34 #define DRV_VERSION "0.24"
37 * Port request block (PRB) 32 bytes
47 * Scatter gather entry (SGE) 16 bytes
58 struct sil24_port_multiplier {
65 * Global controller registers (128 bytes @ BAR0)
68 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
72 HOST_BIST_CTRL = 0x50,
73 HOST_BIST_PTRN = 0x54,
74 HOST_BIST_STAT = 0x58,
75 HOST_MEM_BIST_STAT = 0x5c,
76 HOST_FLASH_CMD = 0x70,
78 HOST_FLASH_DATA = 0x74,
79 HOST_TRANSITION_DETECT = 0x75,
80 HOST_GPIO_CTRL = 0x76,
81 HOST_I2C_ADDR = 0x78, /* 32 bit */
83 HOST_I2C_XFER_CNT = 0x7e,
86 /* HOST_SLOT_STAT bits */
87 HOST_SSTAT_ATTN = (1 << 31),
90 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
91 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
92 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
93 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
94 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
98 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
100 PORT_REGS_SIZE = 0x2000,
102 PORT_LRAM = 0x0000, /* 31 LRAM slots and PM regs */
103 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
105 PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */
107 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
108 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
109 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
110 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
111 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
112 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
113 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
114 PORT_CMD_ERR = 0x1024, /* command error number */
115 PORT_FIS_CFG = 0x1028,
116 PORT_FIFO_THRES = 0x102c,
118 PORT_DECODE_ERR_CNT = 0x1040,
119 PORT_DECODE_ERR_THRESH = 0x1042,
120 PORT_CRC_ERR_CNT = 0x1044,
121 PORT_CRC_ERR_THRESH = 0x1046,
122 PORT_HSHK_ERR_CNT = 0x1048,
123 PORT_HSHK_ERR_THRESH = 0x104a,
125 PORT_PHY_CFG = 0x1050,
126 PORT_SLOT_STAT = 0x1800,
127 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
128 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
129 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
130 PORT_SCONTROL = 0x1f00,
131 PORT_SSTATUS = 0x1f04,
132 PORT_SERROR = 0x1f08,
133 PORT_SACTIVE = 0x1f0c,
135 /* PORT_CTRL_STAT bits */
136 PORT_CS_PORT_RST = (1 << 0), /* port reset */
137 PORT_CS_DEV_RST = (1 << 1), /* device reset */
138 PORT_CS_INIT = (1 << 2), /* port initialize */
139 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
140 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
141 PORT_CS_RESUME = (1 << 6), /* port resume */
142 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
143 PORT_CS_PM_EN = (1 << 13), /* port multiplier enable */
144 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
146 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
147 /* bits[11:0] are masked */
148 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
149 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
150 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
151 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
152 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
153 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
154 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
155 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
156 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
157 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
158 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
159 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
161 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
162 PORT_IRQ_DEV_XCHG | PORT_IRQ_UNK_FIS,
164 /* bits[27:16] are unmasked (raw) */
165 PORT_IRQ_RAW_SHIFT = 16,
166 PORT_IRQ_MASKED_MASK = 0x7ff,
167 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
169 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
170 PORT_IRQ_STEER_SHIFT = 30,
171 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
173 /* PORT_CMD_ERR constants */
174 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
175 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
176 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
177 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
178 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
179 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
180 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
181 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
182 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
183 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
184 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
185 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
186 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
187 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
188 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
189 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
190 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
191 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
192 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
193 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
194 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
195 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
197 /* bits of PRB control field */
198 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
199 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
200 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
201 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
202 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
204 /* PRB protocol field */
205 PRB_PROT_PACKET = (1 << 0),
206 PRB_PROT_TCQ = (1 << 1),
207 PRB_PROT_NCQ = (1 << 2),
208 PRB_PROT_READ = (1 << 3),
209 PRB_PROT_WRITE = (1 << 4),
210 PRB_PROT_TRANSPARENT = (1 << 5),
215 SGE_TRM = (1 << 31), /* Last SGE in chain */
216 SGE_LNK = (1 << 30), /* linked list
217 Points to SGT, not SGE */
218 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
219 data address ignored */
229 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
230 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
232 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
234 IRQ_STAT_4PORTS = 0xf,
237 struct sil24_ata_block {
238 struct sil24_prb prb;
239 struct sil24_sge sge[LIBATA_MAX_PRD];
242 struct sil24_atapi_block {
243 struct sil24_prb prb;
245 struct sil24_sge sge[LIBATA_MAX_PRD - 1];
248 union sil24_cmd_block {
249 struct sil24_ata_block ata;
250 struct sil24_atapi_block atapi;
253 static struct sil24_cerr_info {
254 unsigned int err_mask, action;
256 } sil24_cerr_db[] = {
257 [0] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
259 [PORT_CERR_DEV] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
260 "device error via D2H FIS" },
261 [PORT_CERR_SDB] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
262 "device error via SDB FIS" },
263 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
264 "error in data FIS" },
265 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
266 "failed to transmit command FIS" },
267 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
268 "protocol mismatch" },
269 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
270 "data directon mismatch" },
271 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
272 "ran out of SGEs while writing" },
273 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
274 "ran out of SGEs while reading" },
275 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
276 "invalid data directon for ATAPI CDB" },
277 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
278 "SGT no on qword boundary" },
279 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
280 "PCI target abort while fetching SGT" },
281 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
282 "PCI master abort while fetching SGT" },
283 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
284 "PCI parity error while fetching SGT" },
285 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
286 "PRB not on qword boundary" },
287 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
288 "PCI target abort while fetching PRB" },
289 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
290 "PCI master abort while fetching PRB" },
291 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
292 "PCI parity error while fetching PRB" },
293 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
294 "undefined error while transferring data" },
295 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
296 "PCI target abort while transferring data" },
297 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
298 "PCI master abort while transferring data" },
299 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
300 "PCI parity error while transferring data" },
301 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
302 "FIS received while sending service FIS" },
308 * The preview driver always returned 0 for status. We emulate it
309 * here from the previous interrupt.
311 struct sil24_port_priv {
312 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
313 dma_addr_t cmd_block_dma; /* DMA base addr for them */
314 struct ata_taskfile tf; /* Cached taskfile registers */
317 /* ap->host_set->private_data */
318 struct sil24_host_priv {
319 void __iomem *host_base; /* global controller control (128 bytes @BAR0) */
320 void __iomem *port_base; /* port registers (4 * 8192 bytes @BAR2) */
323 static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev);
324 static u8 sil24_check_status(struct ata_port *ap);
325 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg);
326 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
327 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
328 static int sil24_probe_reset(struct ata_port *ap, unsigned int *classes);
329 static void sil24_qc_prep(struct ata_queued_cmd *qc);
330 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
331 static void sil24_irq_clear(struct ata_port *ap);
332 static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
333 static void sil24_freeze(struct ata_port *ap);
334 static void sil24_thaw(struct ata_port *ap);
335 static void sil24_error_handler(struct ata_port *ap);
336 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
337 static int sil24_port_start(struct ata_port *ap);
338 static void sil24_port_stop(struct ata_port *ap);
339 static void sil24_host_stop(struct ata_host_set *host_set);
340 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
342 static const struct pci_device_id sil24_pci_tbl[] = {
343 { 0x1095, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
344 { 0x8086, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
345 { 0x1095, 0x3132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3132 },
346 { 0x1095, 0x3131, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
347 { 0x1095, 0x3531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
348 { } /* terminate list */
351 static struct pci_driver sil24_pci_driver = {
353 .id_table = sil24_pci_tbl,
354 .probe = sil24_init_one,
355 .remove = ata_pci_remove_one, /* safe? */
358 static struct scsi_host_template sil24_sht = {
359 .module = THIS_MODULE,
361 .ioctl = ata_scsi_ioctl,
362 .queuecommand = ata_scsi_queuecmd,
363 .change_queue_depth = ata_scsi_change_queue_depth,
364 .can_queue = SIL24_MAX_CMDS,
365 .this_id = ATA_SHT_THIS_ID,
366 .sg_tablesize = LIBATA_MAX_PRD,
367 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
368 .emulated = ATA_SHT_EMULATED,
369 .use_clustering = ATA_SHT_USE_CLUSTERING,
370 .proc_name = DRV_NAME,
371 .dma_boundary = ATA_DMA_BOUNDARY,
372 .slave_configure = ata_scsi_slave_config,
373 .bios_param = ata_std_bios_param,
376 static const struct ata_port_operations sil24_ops = {
377 .port_disable = ata_port_disable,
379 .dev_config = sil24_dev_config,
381 .check_status = sil24_check_status,
382 .check_altstatus = sil24_check_status,
383 .dev_select = ata_noop_dev_select,
385 .tf_read = sil24_tf_read,
387 .probe_reset = sil24_probe_reset,
389 .qc_prep = sil24_qc_prep,
390 .qc_issue = sil24_qc_issue,
392 .irq_handler = sil24_interrupt,
393 .irq_clear = sil24_irq_clear,
395 .scr_read = sil24_scr_read,
396 .scr_write = sil24_scr_write,
398 .freeze = sil24_freeze,
400 .error_handler = sil24_error_handler,
401 .post_internal_cmd = sil24_post_internal_cmd,
403 .port_start = sil24_port_start,
404 .port_stop = sil24_port_stop,
405 .host_stop = sil24_host_stop,
409 * Use bits 30-31 of host_flags to encode available port numbers.
410 * Current maxium is 4.
412 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
413 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
415 static struct ata_port_info sil24_port_info[] = {
419 .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
420 SIL24_FLAG_PCIX_IRQ_WOC,
421 .pio_mask = 0x1f, /* pio0-4 */
422 .mwdma_mask = 0x07, /* mwdma0-2 */
423 .udma_mask = 0x3f, /* udma0-5 */
424 .port_ops = &sil24_ops,
429 .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
430 .pio_mask = 0x1f, /* pio0-4 */
431 .mwdma_mask = 0x07, /* mwdma0-2 */
432 .udma_mask = 0x3f, /* udma0-5 */
433 .port_ops = &sil24_ops,
435 /* sil_3131/sil_3531 */
438 .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
439 .pio_mask = 0x1f, /* pio0-4 */
440 .mwdma_mask = 0x07, /* mwdma0-2 */
441 .udma_mask = 0x3f, /* udma0-5 */
442 .port_ops = &sil24_ops,
446 static int sil24_tag(int tag)
448 if (unlikely(ata_tag_internal(tag)))
453 static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev)
455 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
457 if (dev->cdb_len == 16)
458 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
460 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
463 static inline void sil24_update_tf(struct ata_port *ap)
465 struct sil24_port_priv *pp = ap->private_data;
466 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
467 struct sil24_prb __iomem *prb = port;
470 memcpy_fromio(fis, prb->fis, 6 * 4);
471 ata_tf_from_fis(fis, &pp->tf);
474 static u8 sil24_check_status(struct ata_port *ap)
476 struct sil24_port_priv *pp = ap->private_data;
477 return pp->tf.command;
480 static int sil24_scr_map[] = {
487 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg)
489 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
490 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
492 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
493 return readl(scr_addr + sil24_scr_map[sc_reg] * 4);
498 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
500 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
501 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
503 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
504 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
508 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
510 struct sil24_port_priv *pp = ap->private_data;
514 static int sil24_init_port(struct ata_port *ap)
516 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
519 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
520 ata_wait_register(port + PORT_CTRL_STAT,
521 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
522 tmp = ata_wait_register(port + PORT_CTRL_STAT,
523 PORT_CS_RDY, 0, 10, 100);
525 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
530 static int sil24_softreset(struct ata_port *ap, unsigned int *class)
532 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
533 struct sil24_port_priv *pp = ap->private_data;
534 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
535 dma_addr_t paddr = pp->cmd_block_dma;
541 if (ata_port_offline(ap)) {
542 DPRINTK("PHY reports no device\n");
543 *class = ATA_DEV_NONE;
547 /* put the port into known state */
548 if (sil24_init_port(ap)) {
549 reason ="port not ready";
554 prb->ctrl = cpu_to_le16(PRB_CTRL_SRST);
555 prb->fis[1] = 0; /* no PM yet */
557 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
558 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
560 mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
561 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, mask, 0x0,
562 100, ATA_TMOUT_BOOT / HZ * 1000);
564 writel(irq_stat, port + PORT_IRQ_STAT); /* clear IRQs */
565 irq_stat >>= PORT_IRQ_RAW_SHIFT;
567 if (!(irq_stat & PORT_IRQ_COMPLETE)) {
568 if (irq_stat & PORT_IRQ_ERROR)
569 reason = "SRST command error";
576 *class = ata_dev_classify(&pp->tf);
578 if (*class == ATA_DEV_UNKNOWN)
579 *class = ATA_DEV_NONE;
582 DPRINTK("EXIT, class=%u\n", *class);
586 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
590 static int sil24_hardreset(struct ata_port *ap, unsigned int *class)
592 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
597 /* sil24 does the right thing(tm) without any protection */
601 if (ata_port_online(ap))
604 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
605 tmp = ata_wait_register(port + PORT_CTRL_STAT,
606 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, tout_msec);
608 /* SStatus oscillates between zero and valid status for short
609 * duration after DEV_RST, give it time to settle.
613 if (tmp & PORT_CS_DEV_RST) {
614 if (ata_port_offline(ap))
616 reason = "link not ready";
620 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
621 reason = "device not ready";
625 /* sil24 doesn't report device class code after hardreset,
626 * leave *class alone.
631 ata_port_printk(ap, KERN_ERR, "hardreset failed (%s)\n", reason);
635 static int sil24_probe_reset(struct ata_port *ap, unsigned int *classes)
637 return ata_drive_probe_reset(ap, ata_std_probeinit,
638 sil24_softreset, sil24_hardreset,
639 ata_std_postreset, classes);
642 static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
643 struct sil24_sge *sge)
645 struct scatterlist *sg;
646 unsigned int idx = 0;
648 ata_for_each_sg(sg, qc) {
649 sge->addr = cpu_to_le64(sg_dma_address(sg));
650 sge->cnt = cpu_to_le32(sg_dma_len(sg));
651 if (ata_sg_is_last(sg, qc))
652 sge->flags = cpu_to_le32(SGE_TRM);
661 static void sil24_qc_prep(struct ata_queued_cmd *qc)
663 struct ata_port *ap = qc->ap;
664 struct sil24_port_priv *pp = ap->private_data;
665 union sil24_cmd_block *cb;
666 struct sil24_prb *prb;
667 struct sil24_sge *sge;
670 cb = &pp->cmd_block[sil24_tag(qc->tag)];
672 switch (qc->tf.protocol) {
676 case ATA_PROT_NODATA:
682 case ATA_PROT_ATAPI_DMA:
683 case ATA_PROT_ATAPI_NODATA:
684 prb = &cb->atapi.prb;
686 memset(cb->atapi.cdb, 0, 32);
687 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
689 if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) {
690 if (qc->tf.flags & ATA_TFLAG_WRITE)
691 ctrl = PRB_CTRL_PACKET_WRITE;
693 ctrl = PRB_CTRL_PACKET_READ;
698 prb = NULL; /* shut up, gcc */
703 prb->ctrl = cpu_to_le16(ctrl);
704 ata_tf_to_fis(&qc->tf, prb->fis, 0);
706 if (qc->flags & ATA_QCFLAG_DMAMAP)
707 sil24_fill_sg(qc, sge);
710 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
712 struct ata_port *ap = qc->ap;
713 struct sil24_port_priv *pp = ap->private_data;
714 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
715 unsigned int tag = sil24_tag(qc->tag);
717 void __iomem *activate;
719 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
720 activate = port + PORT_CMD_ACTIVATE + tag * 8;
722 writel((u32)paddr, activate);
723 writel((u64)paddr >> 32, activate + 4);
728 static void sil24_irq_clear(struct ata_port *ap)
733 static void sil24_freeze(struct ata_port *ap)
735 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
737 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
738 * PORT_IRQ_ENABLE instead.
740 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
743 static void sil24_thaw(struct ata_port *ap)
745 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
749 tmp = readl(port + PORT_IRQ_STAT);
750 writel(tmp, port + PORT_IRQ_STAT);
752 /* turn IRQ back on */
753 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
756 static void sil24_error_intr(struct ata_port *ap)
758 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
759 struct ata_eh_info *ehi = &ap->eh_info;
763 /* on error, we need to clear IRQ explicitly */
764 irq_stat = readl(port + PORT_IRQ_STAT);
765 writel(irq_stat, port + PORT_IRQ_STAT);
767 /* first, analyze and record host port events */
768 ata_ehi_clear_desc(ehi);
770 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
772 if (irq_stat & PORT_IRQ_DEV_XCHG) {
773 ehi->err_mask |= AC_ERR_ATA_BUS;
774 /* sil24 doesn't recover very well from phy
775 * disconnection with a softreset. Force hardreset.
777 ehi->action |= ATA_EH_HARDRESET;
778 ata_ehi_push_desc(ehi, ", device_exchanged");
782 if (irq_stat & PORT_IRQ_UNK_FIS) {
783 ehi->err_mask |= AC_ERR_HSM;
784 ehi->action |= ATA_EH_SOFTRESET;
785 ata_ehi_push_desc(ehi , ", unknown FIS");
789 /* deal with command error */
790 if (irq_stat & PORT_IRQ_ERROR) {
791 struct sil24_cerr_info *ci = NULL;
792 unsigned int err_mask = 0, action = 0;
793 struct ata_queued_cmd *qc;
796 /* analyze CMD_ERR */
797 cerr = readl(port + PORT_CMD_ERR);
798 if (cerr < ARRAY_SIZE(sil24_cerr_db))
799 ci = &sil24_cerr_db[cerr];
801 if (ci && ci->desc) {
802 err_mask |= ci->err_mask;
803 action |= ci->action;
804 ata_ehi_push_desc(ehi, ", %s", ci->desc);
806 err_mask |= AC_ERR_OTHER;
807 action |= ATA_EH_SOFTRESET;
808 ata_ehi_push_desc(ehi, ", unknown command error %d",
812 /* record error info */
813 qc = ata_qc_from_tag(ap, ap->active_tag);
816 qc->err_mask |= err_mask;
818 ehi->err_mask |= err_mask;
820 ehi->action |= action;
823 /* freeze or abort */
830 static void sil24_finish_qc(struct ata_queued_cmd *qc)
832 if (qc->flags & ATA_QCFLAG_RESULT_TF)
833 sil24_update_tf(qc->ap);
836 static inline void sil24_host_intr(struct ata_port *ap)
838 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
839 u32 slot_stat, qc_active;
842 slot_stat = readl(port + PORT_SLOT_STAT);
844 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
845 sil24_error_intr(ap);
849 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
850 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
852 qc_active = slot_stat & ~HOST_SSTAT_ATTN;
853 rc = ata_qc_complete_multiple(ap, qc_active, sil24_finish_qc);
857 struct ata_eh_info *ehi = &ap->eh_info;
858 ehi->err_mask |= AC_ERR_HSM;
859 ehi->action |= ATA_EH_SOFTRESET;
865 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
866 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n",
867 slot_stat, ap->active_tag, ap->sactive);
870 static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
872 struct ata_host_set *host_set = dev_instance;
873 struct sil24_host_priv *hpriv = host_set->private_data;
874 unsigned handled = 0;
878 status = readl(hpriv->host_base + HOST_IRQ_STAT);
880 if (status == 0xffffffff) {
881 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
882 "PCI fault or device removal?\n");
886 if (!(status & IRQ_STAT_4PORTS))
889 spin_lock(&host_set->lock);
891 for (i = 0; i < host_set->n_ports; i++)
892 if (status & (1 << i)) {
893 struct ata_port *ap = host_set->ports[i];
894 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
895 sil24_host_intr(host_set->ports[i]);
898 printk(KERN_ERR DRV_NAME
899 ": interrupt from disabled port %d\n", i);
902 spin_unlock(&host_set->lock);
904 return IRQ_RETVAL(handled);
907 static void sil24_error_handler(struct ata_port *ap)
909 struct ata_eh_context *ehc = &ap->eh_context;
911 if (sil24_init_port(ap)) {
912 ata_eh_freeze_port(ap);
913 ehc->i.action |= ATA_EH_HARDRESET;
916 /* perform recovery */
917 ata_do_eh(ap, ata_std_prereset, sil24_softreset, sil24_hardreset,
921 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
923 struct ata_port *ap = qc->ap;
925 if (qc->flags & ATA_QCFLAG_FAILED)
926 qc->err_mask |= AC_ERR_OTHER;
928 /* make DMA engine forget about the failed command */
933 static inline void sil24_cblk_free(struct sil24_port_priv *pp, struct device *dev)
935 const size_t cb_size = sizeof(*pp->cmd_block) * SIL24_MAX_CMDS;
937 dma_free_coherent(dev, cb_size, pp->cmd_block, pp->cmd_block_dma);
940 static int sil24_port_start(struct ata_port *ap)
942 struct device *dev = ap->host_set->dev;
943 struct sil24_port_priv *pp;
944 union sil24_cmd_block *cb;
945 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
949 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
953 pp->tf.command = ATA_DRDY;
955 cb = dma_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
958 memset(cb, 0, cb_size);
960 rc = ata_pad_alloc(ap, dev);
965 pp->cmd_block_dma = cb_dma;
967 ap->private_data = pp;
972 sil24_cblk_free(pp, dev);
979 static void sil24_port_stop(struct ata_port *ap)
981 struct device *dev = ap->host_set->dev;
982 struct sil24_port_priv *pp = ap->private_data;
984 sil24_cblk_free(pp, dev);
985 ata_pad_free(ap, dev);
989 static void sil24_host_stop(struct ata_host_set *host_set)
991 struct sil24_host_priv *hpriv = host_set->private_data;
992 struct pci_dev *pdev = to_pci_dev(host_set->dev);
994 pci_iounmap(pdev, hpriv->host_base);
995 pci_iounmap(pdev, hpriv->port_base);
999 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1001 static int printed_version = 0;
1002 unsigned int board_id = (unsigned int)ent->driver_data;
1003 struct ata_port_info *pinfo = &sil24_port_info[board_id];
1004 struct ata_probe_ent *probe_ent = NULL;
1005 struct sil24_host_priv *hpriv = NULL;
1006 void __iomem *host_base = NULL;
1007 void __iomem *port_base = NULL;
1011 if (!printed_version++)
1012 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1014 rc = pci_enable_device(pdev);
1018 rc = pci_request_regions(pdev, DRV_NAME);
1023 /* map mmio registers */
1024 host_base = pci_iomap(pdev, 0, 0);
1027 port_base = pci_iomap(pdev, 2, 0);
1031 /* allocate & init probe_ent and hpriv */
1032 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
1036 hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
1040 probe_ent->dev = pci_dev_to_dev(pdev);
1041 INIT_LIST_HEAD(&probe_ent->node);
1043 probe_ent->sht = pinfo->sht;
1044 probe_ent->host_flags = pinfo->host_flags;
1045 probe_ent->pio_mask = pinfo->pio_mask;
1046 probe_ent->mwdma_mask = pinfo->mwdma_mask;
1047 probe_ent->udma_mask = pinfo->udma_mask;
1048 probe_ent->port_ops = pinfo->port_ops;
1049 probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->host_flags);
1051 probe_ent->irq = pdev->irq;
1052 probe_ent->irq_flags = SA_SHIRQ;
1053 probe_ent->mmio_base = port_base;
1054 probe_ent->private_data = hpriv;
1056 hpriv->host_base = host_base;
1057 hpriv->port_base = port_base;
1060 * Configure the device
1062 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1063 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1065 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1067 dev_printk(KERN_ERR, &pdev->dev,
1068 "64-bit DMA enable failed\n");
1073 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1075 dev_printk(KERN_ERR, &pdev->dev,
1076 "32-bit DMA enable failed\n");
1079 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1081 dev_printk(KERN_ERR, &pdev->dev,
1082 "32-bit consistent DMA enable failed\n");
1088 writel(0, host_base + HOST_FLASH_CMD);
1090 /* Apply workaround for completion IRQ loss on PCI-X errata */
1091 if (probe_ent->host_flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1092 tmp = readl(host_base + HOST_CTRL);
1093 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1094 dev_printk(KERN_INFO, &pdev->dev,
1095 "Applying completion IRQ loss on PCI-X "
1098 probe_ent->host_flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1101 /* clear global reset & mask interrupts during initialization */
1102 writel(0, host_base + HOST_CTRL);
1104 for (i = 0; i < probe_ent->n_ports; i++) {
1105 void __iomem *port = port_base + i * PORT_REGS_SIZE;
1106 unsigned long portu = (unsigned long)port;
1108 probe_ent->port[i].cmd_addr = portu;
1109 probe_ent->port[i].scr_addr = portu + PORT_SCONTROL;
1111 ata_std_ports(&probe_ent->port[i]);
1113 /* Initial PHY setting */
1114 writel(0x20c, port + PORT_PHY_CFG);
1116 /* Clear port RST */
1117 tmp = readl(port + PORT_CTRL_STAT);
1118 if (tmp & PORT_CS_PORT_RST) {
1119 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
1120 tmp = ata_wait_register(port + PORT_CTRL_STAT,
1122 PORT_CS_PORT_RST, 10, 100);
1123 if (tmp & PORT_CS_PORT_RST)
1124 dev_printk(KERN_ERR, &pdev->dev,
1125 "failed to clear port RST\n");
1128 /* Configure IRQ WoC */
1129 if (probe_ent->host_flags & SIL24_FLAG_PCIX_IRQ_WOC)
1130 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
1132 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
1134 /* Zero error counters. */
1135 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
1136 writel(0x8000, port + PORT_CRC_ERR_THRESH);
1137 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
1138 writel(0x0000, port + PORT_DECODE_ERR_CNT);
1139 writel(0x0000, port + PORT_CRC_ERR_CNT);
1140 writel(0x0000, port + PORT_HSHK_ERR_CNT);
1142 /* Always use 64bit activation */
1143 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
1145 /* Clear port multiplier enable and resume bits */
1146 writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR);
1149 /* Turn on interrupts */
1150 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1152 pci_set_master(pdev);
1154 /* FIXME: check ata_device_add return value */
1155 ata_device_add(probe_ent);
1162 pci_iounmap(pdev, host_base);
1164 pci_iounmap(pdev, port_base);
1167 pci_release_regions(pdev);
1169 pci_disable_device(pdev);
1173 static int __init sil24_init(void)
1175 return pci_module_init(&sil24_pci_driver);
1178 static void __exit sil24_exit(void)
1180 pci_unregister_driver(&sil24_pci_driver);
1183 MODULE_AUTHOR("Tejun Heo");
1184 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1185 MODULE_LICENSE("GPL");
1186 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1188 module_init(sil24_init);
1189 module_exit(sil24_exit);