2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
4 * Copyright 2005 Tejun Heo
6 * Based on preview driver from Silicon Image.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/blkdev.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/device.h>
28 #include <scsi/scsi_host.h>
29 #include <scsi/scsi_cmnd.h>
30 #include <linux/libata.h>
33 #define DRV_NAME "sata_sil24"
34 #define DRV_VERSION "0.24"
37 * Port request block (PRB) 32 bytes
47 * Scatter gather entry (SGE) 16 bytes
58 struct sil24_port_multiplier {
65 * Global controller registers (128 bytes @ BAR0)
68 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
72 HOST_BIST_CTRL = 0x50,
73 HOST_BIST_PTRN = 0x54,
74 HOST_BIST_STAT = 0x58,
75 HOST_MEM_BIST_STAT = 0x5c,
76 HOST_FLASH_CMD = 0x70,
78 HOST_FLASH_DATA = 0x74,
79 HOST_TRANSITION_DETECT = 0x75,
80 HOST_GPIO_CTRL = 0x76,
81 HOST_I2C_ADDR = 0x78, /* 32 bit */
83 HOST_I2C_XFER_CNT = 0x7e,
86 /* HOST_SLOT_STAT bits */
87 HOST_SSTAT_ATTN = (1 << 31),
90 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
91 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
92 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
93 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
94 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
98 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
100 PORT_REGS_SIZE = 0x2000,
101 PORT_PRB = 0x0000, /* (32 bytes PRB + 16 bytes SGEs * 6) * 31 (3968 bytes) */
103 PORT_PM = 0x0f80, /* 8 bytes PM * 16 (128 bytes) */
105 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
106 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
107 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
108 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
109 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
110 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
111 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
112 PORT_CMD_ERR = 0x1024, /* command error number */
113 PORT_FIS_CFG = 0x1028,
114 PORT_FIFO_THRES = 0x102c,
116 PORT_DECODE_ERR_CNT = 0x1040,
117 PORT_DECODE_ERR_THRESH = 0x1042,
118 PORT_CRC_ERR_CNT = 0x1044,
119 PORT_CRC_ERR_THRESH = 0x1046,
120 PORT_HSHK_ERR_CNT = 0x1048,
121 PORT_HSHK_ERR_THRESH = 0x104a,
123 PORT_PHY_CFG = 0x1050,
124 PORT_SLOT_STAT = 0x1800,
125 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
126 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
127 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
128 PORT_SCONTROL = 0x1f00,
129 PORT_SSTATUS = 0x1f04,
130 PORT_SERROR = 0x1f08,
131 PORT_SACTIVE = 0x1f0c,
133 /* PORT_CTRL_STAT bits */
134 PORT_CS_PORT_RST = (1 << 0), /* port reset */
135 PORT_CS_DEV_RST = (1 << 1), /* device reset */
136 PORT_CS_INIT = (1 << 2), /* port initialize */
137 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
138 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
139 PORT_CS_RESUME = (1 << 6), /* port resume */
140 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
141 PORT_CS_PM_EN = (1 << 13), /* port multiplier enable */
142 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
144 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
145 /* bits[11:0] are masked */
146 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
147 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
148 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
149 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
150 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
151 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
152 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
153 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
154 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
155 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
156 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
157 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
159 /* bits[27:16] are unmasked (raw) */
160 PORT_IRQ_RAW_SHIFT = 16,
161 PORT_IRQ_MASKED_MASK = 0x7ff,
162 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
164 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
165 PORT_IRQ_STEER_SHIFT = 30,
166 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
168 /* PORT_CMD_ERR constants */
169 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
170 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
171 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
172 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
173 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
174 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
175 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
176 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
177 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
178 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
179 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
180 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
181 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
182 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
183 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
184 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
185 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
186 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
187 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
188 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
189 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
190 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
192 /* bits of PRB control field */
193 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
194 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
195 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
196 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
197 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
199 /* PRB protocol field */
200 PRB_PROT_PACKET = (1 << 0),
201 PRB_PROT_TCQ = (1 << 1),
202 PRB_PROT_NCQ = (1 << 2),
203 PRB_PROT_READ = (1 << 3),
204 PRB_PROT_WRITE = (1 << 4),
205 PRB_PROT_TRANSPARENT = (1 << 5),
210 SGE_TRM = (1 << 31), /* Last SGE in chain */
211 SGE_LNK = (1 << 30), /* linked list
212 Points to SGT, not SGE */
213 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
214 data address ignored */
222 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
223 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
225 IRQ_STAT_4PORTS = 0xf,
228 struct sil24_ata_block {
229 struct sil24_prb prb;
230 struct sil24_sge sge[LIBATA_MAX_PRD];
233 struct sil24_atapi_block {
234 struct sil24_prb prb;
236 struct sil24_sge sge[LIBATA_MAX_PRD - 1];
239 union sil24_cmd_block {
240 struct sil24_ata_block ata;
241 struct sil24_atapi_block atapi;
247 * The preview driver always returned 0 for status. We emulate it
248 * here from the previous interrupt.
250 struct sil24_port_priv {
251 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
252 dma_addr_t cmd_block_dma; /* DMA base addr for them */
253 struct ata_taskfile tf; /* Cached taskfile registers */
256 /* ap->host_set->private_data */
257 struct sil24_host_priv {
258 void __iomem *host_base; /* global controller control (128 bytes @BAR0) */
259 void __iomem *port_base; /* port registers (4 * 8192 bytes @BAR2) */
262 static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev);
263 static u8 sil24_check_status(struct ata_port *ap);
264 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg);
265 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
266 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
267 static int sil24_probe_reset(struct ata_port *ap, unsigned int *classes);
268 static void sil24_qc_prep(struct ata_queued_cmd *qc);
269 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
270 static void sil24_irq_clear(struct ata_port *ap);
271 static void sil24_eng_timeout(struct ata_port *ap);
272 static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs);
273 static int sil24_port_start(struct ata_port *ap);
274 static void sil24_port_stop(struct ata_port *ap);
275 static void sil24_host_stop(struct ata_host_set *host_set);
276 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
278 static const struct pci_device_id sil24_pci_tbl[] = {
279 { 0x1095, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
280 { 0x8086, 0x3124, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3124 },
281 { 0x1095, 0x3132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3132 },
282 { 0x1095, 0x3131, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
283 { 0x1095, 0x3531, PCI_ANY_ID, PCI_ANY_ID, 0, 0, BID_SIL3131 },
284 { } /* terminate list */
287 static struct pci_driver sil24_pci_driver = {
289 .id_table = sil24_pci_tbl,
290 .probe = sil24_init_one,
291 .remove = ata_pci_remove_one, /* safe? */
294 static struct scsi_host_template sil24_sht = {
295 .module = THIS_MODULE,
297 .ioctl = ata_scsi_ioctl,
298 .queuecommand = ata_scsi_queuecmd,
299 .can_queue = ATA_DEF_QUEUE,
300 .this_id = ATA_SHT_THIS_ID,
301 .sg_tablesize = LIBATA_MAX_PRD,
302 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
303 .emulated = ATA_SHT_EMULATED,
304 .use_clustering = ATA_SHT_USE_CLUSTERING,
305 .proc_name = DRV_NAME,
306 .dma_boundary = ATA_DMA_BOUNDARY,
307 .slave_configure = ata_scsi_slave_config,
308 .bios_param = ata_std_bios_param,
311 static const struct ata_port_operations sil24_ops = {
312 .port_disable = ata_port_disable,
314 .dev_config = sil24_dev_config,
316 .check_status = sil24_check_status,
317 .check_altstatus = sil24_check_status,
318 .dev_select = ata_noop_dev_select,
320 .tf_read = sil24_tf_read,
322 .probe_reset = sil24_probe_reset,
324 .qc_prep = sil24_qc_prep,
325 .qc_issue = sil24_qc_issue,
327 .eng_timeout = sil24_eng_timeout,
329 .irq_handler = sil24_interrupt,
330 .irq_clear = sil24_irq_clear,
332 .scr_read = sil24_scr_read,
333 .scr_write = sil24_scr_write,
335 .port_start = sil24_port_start,
336 .port_stop = sil24_port_stop,
337 .host_stop = sil24_host_stop,
341 * Use bits 30-31 of host_flags to encode available port numbers.
342 * Current maxium is 4.
344 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
345 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
347 static struct ata_port_info sil24_port_info[] = {
351 .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4),
352 .pio_mask = 0x1f, /* pio0-4 */
353 .mwdma_mask = 0x07, /* mwdma0-2 */
354 .udma_mask = 0x3f, /* udma0-5 */
355 .port_ops = &sil24_ops,
360 .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
361 .pio_mask = 0x1f, /* pio0-4 */
362 .mwdma_mask = 0x07, /* mwdma0-2 */
363 .udma_mask = 0x3f, /* udma0-5 */
364 .port_ops = &sil24_ops,
366 /* sil_3131/sil_3531 */
369 .host_flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
370 .pio_mask = 0x1f, /* pio0-4 */
371 .mwdma_mask = 0x07, /* mwdma0-2 */
372 .udma_mask = 0x3f, /* udma0-5 */
373 .port_ops = &sil24_ops,
377 static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev)
379 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
381 if (dev->cdb_len == 16)
382 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
384 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
387 static inline void sil24_update_tf(struct ata_port *ap)
389 struct sil24_port_priv *pp = ap->private_data;
390 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
391 struct sil24_prb __iomem *prb = port;
394 memcpy_fromio(fis, prb->fis, 6 * 4);
395 ata_tf_from_fis(fis, &pp->tf);
398 static u8 sil24_check_status(struct ata_port *ap)
400 struct sil24_port_priv *pp = ap->private_data;
401 return pp->tf.command;
404 static int sil24_scr_map[] = {
411 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg)
413 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
414 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
416 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
417 return readl(scr_addr + sil24_scr_map[sc_reg] * 4);
422 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
424 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
425 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
427 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
428 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
432 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
434 struct sil24_port_priv *pp = ap->private_data;
438 static int sil24_softreset(struct ata_port *ap, unsigned int *class)
440 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
441 struct sil24_port_priv *pp = ap->private_data;
442 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
443 dma_addr_t paddr = pp->cmd_block_dma;
444 u32 mask, irq_enable, irq_stat;
449 if (!sata_dev_present(ap)) {
450 DPRINTK("PHY reports no device\n");
451 *class = ATA_DEV_NONE;
455 /* temporarily turn off IRQs during SRST */
456 irq_enable = readl(port + PORT_IRQ_ENABLE_SET);
457 writel(irq_enable, port + PORT_IRQ_ENABLE_CLR);
460 * XXX: Not sure whether the following sleep is needed or not.
461 * The original driver had it. So....
465 prb->ctrl = PRB_CTRL_SRST;
466 prb->fis[1] = 0; /* no PM yet */
468 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
470 mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
471 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, mask, 0x0,
472 100, ATA_TMOUT_BOOT / HZ * 1000);
474 writel(irq_stat, port + PORT_IRQ_STAT); /* clear IRQs */
475 irq_stat >>= PORT_IRQ_RAW_SHIFT;
478 writel(irq_enable, port + PORT_IRQ_ENABLE_SET);
480 if (!(irq_stat & PORT_IRQ_COMPLETE)) {
481 if (irq_stat & PORT_IRQ_ERROR)
482 reason = "SRST command error";
489 *class = ata_dev_classify(&pp->tf);
491 if (*class == ATA_DEV_UNKNOWN)
492 *class = ATA_DEV_NONE;
495 DPRINTK("EXIT, class=%u\n", *class);
499 printk(KERN_ERR "ata%u: softreset failed (%s)\n", ap->id, reason);
503 static int sil24_hardreset(struct ata_port *ap, unsigned int *class)
505 unsigned int dummy_class;
507 /* sil24 doesn't report device signature after hard reset */
508 return sata_std_hardreset(ap, &dummy_class);
511 static int sil24_probe_reset(struct ata_port *ap, unsigned int *classes)
513 return ata_drive_probe_reset(ap, ata_std_probeinit,
514 sil24_softreset, sil24_hardreset,
515 ata_std_postreset, classes);
518 static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
519 struct sil24_sge *sge)
521 struct scatterlist *sg;
522 unsigned int idx = 0;
524 ata_for_each_sg(sg, qc) {
525 sge->addr = cpu_to_le64(sg_dma_address(sg));
526 sge->cnt = cpu_to_le32(sg_dma_len(sg));
527 if (ata_sg_is_last(sg, qc))
528 sge->flags = cpu_to_le32(SGE_TRM);
537 static void sil24_qc_prep(struct ata_queued_cmd *qc)
539 struct ata_port *ap = qc->ap;
540 struct sil24_port_priv *pp = ap->private_data;
541 union sil24_cmd_block *cb = pp->cmd_block + qc->tag;
542 struct sil24_prb *prb;
543 struct sil24_sge *sge;
545 switch (qc->tf.protocol) {
548 case ATA_PROT_NODATA:
555 case ATA_PROT_ATAPI_DMA:
556 case ATA_PROT_ATAPI_NODATA:
557 prb = &cb->atapi.prb;
559 memset(cb->atapi.cdb, 0, 32);
560 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
562 if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) {
563 if (qc->tf.flags & ATA_TFLAG_WRITE)
564 prb->ctrl = PRB_CTRL_PACKET_WRITE;
566 prb->ctrl = PRB_CTRL_PACKET_READ;
573 prb = NULL; /* shut up, gcc */
578 ata_tf_to_fis(&qc->tf, prb->fis, 0);
580 if (qc->flags & ATA_QCFLAG_DMAMAP)
581 sil24_fill_sg(qc, sge);
584 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
586 struct ata_port *ap = qc->ap;
587 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
588 struct sil24_port_priv *pp = ap->private_data;
589 dma_addr_t paddr = pp->cmd_block_dma + qc->tag * sizeof(*pp->cmd_block);
591 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
595 static void sil24_irq_clear(struct ata_port *ap)
600 static int __sil24_restart_controller(void __iomem *port)
605 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
608 for (cnt = 0; cnt < 10000; cnt++) {
609 tmp = readl(port + PORT_CTRL_STAT);
610 if (tmp & PORT_CS_RDY)
618 static void sil24_restart_controller(struct ata_port *ap)
620 if (__sil24_restart_controller((void __iomem *)ap->ioaddr.cmd_addr))
621 printk(KERN_ERR DRV_NAME
622 " ata%u: failed to restart controller\n", ap->id);
625 static int __sil24_reset_controller(void __iomem *port)
630 /* Reset controller state. Is this correct? */
631 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
632 readl(port + PORT_CTRL_STAT); /* sync */
635 for (cnt = 0; cnt < 1000; cnt++) {
637 tmp = readl(port + PORT_CTRL_STAT);
638 if (!(tmp & PORT_CS_DEV_RST))
642 if (tmp & PORT_CS_DEV_RST)
645 if (tmp & PORT_CS_RDY)
648 return __sil24_restart_controller(port);
651 static void sil24_reset_controller(struct ata_port *ap)
653 printk(KERN_NOTICE DRV_NAME
654 " ata%u: resetting controller...\n", ap->id);
655 if (__sil24_reset_controller((void __iomem *)ap->ioaddr.cmd_addr))
656 printk(KERN_ERR DRV_NAME
657 " ata%u: failed to reset controller\n", ap->id);
660 static void sil24_eng_timeout(struct ata_port *ap)
662 struct ata_queued_cmd *qc;
664 qc = ata_qc_from_tag(ap, ap->active_tag);
666 printk(KERN_ERR "ata%u: command timeout\n", ap->id);
667 qc->err_mask |= AC_ERR_TIMEOUT;
668 ata_eh_qc_complete(qc);
670 sil24_reset_controller(ap);
673 static void sil24_error_intr(struct ata_port *ap, u32 slot_stat)
675 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
676 struct sil24_port_priv *pp = ap->private_data;
677 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
678 u32 irq_stat, cmd_err, sstatus, serror;
679 unsigned int err_mask;
681 irq_stat = readl(port + PORT_IRQ_STAT);
682 writel(irq_stat, port + PORT_IRQ_STAT); /* clear irq */
684 if (!(irq_stat & PORT_IRQ_ERROR)) {
685 /* ignore non-completion, non-error irqs for now */
686 printk(KERN_WARNING DRV_NAME
687 "ata%u: non-error exception irq (irq_stat %x)\n",
692 cmd_err = readl(port + PORT_CMD_ERR);
693 sstatus = readl(port + PORT_SSTATUS);
694 serror = readl(port + PORT_SERROR);
696 writel(serror, port + PORT_SERROR);
699 * Don't log ATAPI device errors. They're supposed to happen
700 * and any serious errors will be logged using sense data by
703 if (ap->device[0].class != ATA_DEV_ATAPI || cmd_err > PORT_CERR_SDB)
704 printk("ata%u: error interrupt on port%d\n"
705 " stat=0x%x irq=0x%x cmd_err=%d sstatus=0x%x serror=0x%x\n",
706 ap->id, ap->port_no, slot_stat, irq_stat, cmd_err, sstatus, serror);
708 if (cmd_err == PORT_CERR_DEV || cmd_err == PORT_CERR_SDB) {
710 * Device is reporting error, tf registers are valid.
713 err_mask = ac_err_mask(pp->tf.command);
714 sil24_restart_controller(ap);
717 * Other errors. libata currently doesn't have any
718 * mechanism to report these errors. Just turn on
721 err_mask = AC_ERR_OTHER;
722 sil24_reset_controller(ap);
726 qc->err_mask |= err_mask;
731 static inline void sil24_host_intr(struct ata_port *ap)
733 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
734 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
737 slot_stat = readl(port + PORT_SLOT_STAT);
738 if (!(slot_stat & HOST_SSTAT_ATTN)) {
739 struct sil24_port_priv *pp = ap->private_data;
741 * !HOST_SSAT_ATTN guarantees successful completion,
742 * so reading back tf registers is unnecessary for
743 * most commands. TODO: read tf registers for
744 * commands which require these values on successful
745 * completion (EXECUTE DEVICE DIAGNOSTIC, CHECK POWER,
746 * DEVICE RESET and READ PORT MULTIPLIER (any more?).
751 qc->err_mask |= ac_err_mask(pp->tf.command);
755 sil24_error_intr(ap, slot_stat);
758 static irqreturn_t sil24_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
760 struct ata_host_set *host_set = dev_instance;
761 struct sil24_host_priv *hpriv = host_set->private_data;
762 unsigned handled = 0;
766 status = readl(hpriv->host_base + HOST_IRQ_STAT);
768 if (status == 0xffffffff) {
769 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
770 "PCI fault or device removal?\n");
774 if (!(status & IRQ_STAT_4PORTS))
777 spin_lock(&host_set->lock);
779 for (i = 0; i < host_set->n_ports; i++)
780 if (status & (1 << i)) {
781 struct ata_port *ap = host_set->ports[i];
782 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
783 sil24_host_intr(host_set->ports[i]);
786 printk(KERN_ERR DRV_NAME
787 ": interrupt from disabled port %d\n", i);
790 spin_unlock(&host_set->lock);
792 return IRQ_RETVAL(handled);
795 static inline void sil24_cblk_free(struct sil24_port_priv *pp, struct device *dev)
797 const size_t cb_size = sizeof(*pp->cmd_block);
799 dma_free_coherent(dev, cb_size, pp->cmd_block, pp->cmd_block_dma);
802 static int sil24_port_start(struct ata_port *ap)
804 struct device *dev = ap->host_set->dev;
805 struct sil24_port_priv *pp;
806 union sil24_cmd_block *cb;
807 size_t cb_size = sizeof(*cb);
811 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
815 pp->tf.command = ATA_DRDY;
817 cb = dma_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
820 memset(cb, 0, cb_size);
822 rc = ata_pad_alloc(ap, dev);
827 pp->cmd_block_dma = cb_dma;
829 ap->private_data = pp;
834 sil24_cblk_free(pp, dev);
841 static void sil24_port_stop(struct ata_port *ap)
843 struct device *dev = ap->host_set->dev;
844 struct sil24_port_priv *pp = ap->private_data;
846 sil24_cblk_free(pp, dev);
847 ata_pad_free(ap, dev);
851 static void sil24_host_stop(struct ata_host_set *host_set)
853 struct sil24_host_priv *hpriv = host_set->private_data;
854 struct pci_dev *pdev = to_pci_dev(host_set->dev);
856 pci_iounmap(pdev, hpriv->host_base);
857 pci_iounmap(pdev, hpriv->port_base);
861 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
863 static int printed_version = 0;
864 unsigned int board_id = (unsigned int)ent->driver_data;
865 struct ata_port_info *pinfo = &sil24_port_info[board_id];
866 struct ata_probe_ent *probe_ent = NULL;
867 struct sil24_host_priv *hpriv = NULL;
868 void __iomem *host_base = NULL;
869 void __iomem *port_base = NULL;
872 if (!printed_version++)
873 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
875 rc = pci_enable_device(pdev);
879 rc = pci_request_regions(pdev, DRV_NAME);
884 /* map mmio registers */
885 host_base = pci_iomap(pdev, 0, 0);
888 port_base = pci_iomap(pdev, 2, 0);
892 /* allocate & init probe_ent and hpriv */
893 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
897 hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
901 probe_ent->dev = pci_dev_to_dev(pdev);
902 INIT_LIST_HEAD(&probe_ent->node);
904 probe_ent->sht = pinfo->sht;
905 probe_ent->host_flags = pinfo->host_flags;
906 probe_ent->pio_mask = pinfo->pio_mask;
907 probe_ent->mwdma_mask = pinfo->mwdma_mask;
908 probe_ent->udma_mask = pinfo->udma_mask;
909 probe_ent->port_ops = pinfo->port_ops;
910 probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->host_flags);
912 probe_ent->irq = pdev->irq;
913 probe_ent->irq_flags = SA_SHIRQ;
914 probe_ent->mmio_base = port_base;
915 probe_ent->private_data = hpriv;
917 hpriv->host_base = host_base;
918 hpriv->port_base = port_base;
921 * Configure the device
924 * FIXME: This device is certainly 64-bit capable. We just
925 * don't know how to use it. After fixing 32bit activation in
926 * this function, enable 64bit masks here.
928 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
930 dev_printk(KERN_ERR, &pdev->dev,
931 "32-bit DMA enable failed\n");
934 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
936 dev_printk(KERN_ERR, &pdev->dev,
937 "32-bit consistent DMA enable failed\n");
942 writel(0, host_base + HOST_FLASH_CMD);
944 /* clear global reset & mask interrupts during initialization */
945 writel(0, host_base + HOST_CTRL);
947 for (i = 0; i < probe_ent->n_ports; i++) {
948 void __iomem *port = port_base + i * PORT_REGS_SIZE;
949 unsigned long portu = (unsigned long)port;
952 probe_ent->port[i].cmd_addr = portu + PORT_PRB;
953 probe_ent->port[i].scr_addr = portu + PORT_SCONTROL;
955 ata_std_ports(&probe_ent->port[i]);
957 /* Initial PHY setting */
958 writel(0x20c, port + PORT_PHY_CFG);
961 tmp = readl(port + PORT_CTRL_STAT);
962 if (tmp & PORT_CS_PORT_RST) {
963 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
964 tmp = ata_wait_register(port + PORT_CTRL_STAT,
966 PORT_CS_PORT_RST, 10, 100);
967 if (tmp & PORT_CS_PORT_RST)
968 dev_printk(KERN_ERR, &pdev->dev,
969 "failed to clear port RST\n");
972 /* Zero error counters. */
973 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
974 writel(0x8000, port + PORT_CRC_ERR_THRESH);
975 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
976 writel(0x0000, port + PORT_DECODE_ERR_CNT);
977 writel(0x0000, port + PORT_CRC_ERR_CNT);
978 writel(0x0000, port + PORT_HSHK_ERR_CNT);
980 /* FIXME: 32bit activation? */
981 writel(0, port + PORT_ACTIVATE_UPPER_ADDR);
982 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_STAT);
984 /* Configure interrupts */
985 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
986 writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
987 PORT_IRQ_SDB_NOTIFY, port + PORT_IRQ_ENABLE_SET);
989 /* Clear interrupts */
990 writel(0x0fff0fff, port + PORT_IRQ_STAT);
991 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
993 /* Clear port multiplier enable and resume bits */
994 writel(PORT_CS_PM_EN | PORT_CS_RESUME, port + PORT_CTRL_CLR);
997 if (__sil24_reset_controller(port))
998 dev_printk(KERN_ERR, &pdev->dev,
999 "failed to reset controller\n");
1002 /* Turn on interrupts */
1003 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1005 pci_set_master(pdev);
1007 /* FIXME: check ata_device_add return value */
1008 ata_device_add(probe_ent);
1015 pci_iounmap(pdev, host_base);
1017 pci_iounmap(pdev, port_base);
1020 pci_release_regions(pdev);
1022 pci_disable_device(pdev);
1026 static int __init sil24_init(void)
1028 return pci_module_init(&sil24_pci_driver);
1031 static void __exit sil24_exit(void)
1033 pci_unregister_driver(&sil24_pci_driver);
1036 MODULE_AUTHOR("Tejun Heo");
1037 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1038 MODULE_LICENSE("GPL");
1039 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1041 module_init(sil24_init);
1042 module_exit(sil24_exit);