2 * sata_promise.c - Promise SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2004 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * Hardware information only available under NDA.
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
41 #include <linux/device.h>
42 #include <scsi/scsi_host.h>
43 #include <scsi/scsi_cmnd.h>
44 #include <linux/libata.h>
46 #include "sata_promise.h"
48 #define DRV_NAME "sata_promise"
49 #define DRV_VERSION "1.04"
53 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
54 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
55 PDC_TBG_MODE = 0x41, /* TBG mode */
56 PDC_FLASH_CTL = 0x44, /* Flash control register */
57 PDC_PCI_CTL = 0x48, /* PCI control and status register */
58 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
59 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
60 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
61 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
62 PDC_SLEW_CTL = 0x470, /* slew rate control reg */
64 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
65 (1<<8) | (1<<9) | (1<<10),
67 board_2037x = 0, /* FastTrak S150 TX2plus */
68 board_20319 = 1, /* FastTrak S150 TX4 */
69 board_20619 = 2, /* FastTrak TX4000 */
70 board_20771 = 3, /* FastTrak TX2300 */
71 board_2057x = 4, /* SATAII150 Tx2plus */
72 board_40518 = 5, /* SATAII150 Tx4 */
74 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
76 PDC_RESET = (1 << 11), /* HDMA reset */
78 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | ATA_FLAG_SRST |
79 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
84 struct pdc_port_priv {
89 struct pdc_host_priv {
93 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
94 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
95 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
96 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
97 static void pdc_eng_timeout(struct ata_port *ap);
98 static int pdc_port_start(struct ata_port *ap);
99 static void pdc_port_stop(struct ata_port *ap);
100 static void pdc_pata_phy_reset(struct ata_port *ap);
101 static void pdc_sata_phy_reset(struct ata_port *ap);
102 static void pdc_qc_prep(struct ata_queued_cmd *qc);
103 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
104 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
105 static void pdc_irq_clear(struct ata_port *ap);
106 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
107 static void pdc_host_stop(struct ata_host_set *host_set);
110 static struct scsi_host_template pdc_ata_sht = {
111 .module = THIS_MODULE,
113 .ioctl = ata_scsi_ioctl,
114 .queuecommand = ata_scsi_queuecmd,
115 .can_queue = ATA_DEF_QUEUE,
116 .this_id = ATA_SHT_THIS_ID,
117 .sg_tablesize = LIBATA_MAX_PRD,
118 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
119 .emulated = ATA_SHT_EMULATED,
120 .use_clustering = ATA_SHT_USE_CLUSTERING,
121 .proc_name = DRV_NAME,
122 .dma_boundary = ATA_DMA_BOUNDARY,
123 .slave_configure = ata_scsi_slave_config,
124 .bios_param = ata_std_bios_param,
127 static const struct ata_port_operations pdc_sata_ops = {
128 .port_disable = ata_port_disable,
129 .tf_load = pdc_tf_load_mmio,
130 .tf_read = ata_tf_read,
131 .check_status = ata_check_status,
132 .exec_command = pdc_exec_command_mmio,
133 .dev_select = ata_std_dev_select,
135 .phy_reset = pdc_sata_phy_reset,
137 .qc_prep = pdc_qc_prep,
138 .qc_issue = pdc_qc_issue_prot,
139 .eng_timeout = pdc_eng_timeout,
140 .data_xfer = ata_mmio_data_xfer,
141 .irq_handler = pdc_interrupt,
142 .irq_clear = pdc_irq_clear,
144 .scr_read = pdc_sata_scr_read,
145 .scr_write = pdc_sata_scr_write,
146 .port_start = pdc_port_start,
147 .port_stop = pdc_port_stop,
148 .host_stop = pdc_host_stop,
151 static const struct ata_port_operations pdc_pata_ops = {
152 .port_disable = ata_port_disable,
153 .tf_load = pdc_tf_load_mmio,
154 .tf_read = ata_tf_read,
155 .check_status = ata_check_status,
156 .exec_command = pdc_exec_command_mmio,
157 .dev_select = ata_std_dev_select,
159 .phy_reset = pdc_pata_phy_reset,
161 .qc_prep = pdc_qc_prep,
162 .qc_issue = pdc_qc_issue_prot,
163 .data_xfer = ata_mmio_data_xfer,
164 .eng_timeout = pdc_eng_timeout,
165 .irq_handler = pdc_interrupt,
166 .irq_clear = pdc_irq_clear,
168 .port_start = pdc_port_start,
169 .port_stop = pdc_port_stop,
170 .host_stop = pdc_host_stop,
173 static const struct ata_port_info pdc_port_info[] = {
177 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
178 .pio_mask = 0x1f, /* pio0-4 */
179 .mwdma_mask = 0x07, /* mwdma0-2 */
180 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
181 .port_ops = &pdc_sata_ops,
187 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
188 .pio_mask = 0x1f, /* pio0-4 */
189 .mwdma_mask = 0x07, /* mwdma0-2 */
190 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
191 .port_ops = &pdc_sata_ops,
197 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
198 .pio_mask = 0x1f, /* pio0-4 */
199 .mwdma_mask = 0x07, /* mwdma0-2 */
200 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
201 .port_ops = &pdc_pata_ops,
207 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
208 .pio_mask = 0x1f, /* pio0-4 */
209 .mwdma_mask = 0x07, /* mwdma0-2 */
210 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
211 .port_ops = &pdc_sata_ops,
217 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
218 .pio_mask = 0x1f, /* pio0-4 */
219 .mwdma_mask = 0x07, /* mwdma0-2 */
220 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
221 .port_ops = &pdc_sata_ops,
227 .host_flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
228 .pio_mask = 0x1f, /* pio0-4 */
229 .mwdma_mask = 0x07, /* mwdma0-2 */
230 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
231 .port_ops = &pdc_sata_ops,
235 static const struct pci_device_id pdc_ata_pci_tbl[] = {
236 { PCI_VENDOR_ID_PROMISE, 0x3371, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
238 { PCI_VENDOR_ID_PROMISE, 0x3570, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
240 { PCI_VENDOR_ID_PROMISE, 0x3571, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
242 { PCI_VENDOR_ID_PROMISE, 0x3373, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
244 { PCI_VENDOR_ID_PROMISE, 0x3375, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
246 { PCI_VENDOR_ID_PROMISE, 0x3376, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
248 { PCI_VENDOR_ID_PROMISE, 0x3574, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
250 { PCI_VENDOR_ID_PROMISE, 0x3d75, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
252 { PCI_VENDOR_ID_PROMISE, 0x3d73, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
255 { PCI_VENDOR_ID_PROMISE, 0x3318, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
257 { PCI_VENDOR_ID_PROMISE, 0x3319, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
259 { PCI_VENDOR_ID_PROMISE, 0x3515, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
261 { PCI_VENDOR_ID_PROMISE, 0x3519, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
263 { PCI_VENDOR_ID_PROMISE, 0x3d17, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
265 { PCI_VENDOR_ID_PROMISE, 0x3d18, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
268 { PCI_VENDOR_ID_PROMISE, 0x6629, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
271 { PCI_VENDOR_ID_PROMISE, 0x3570, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
273 { } /* terminate list */
277 static struct pci_driver pdc_ata_pci_driver = {
279 .id_table = pdc_ata_pci_tbl,
280 .probe = pdc_ata_init_one,
281 .remove = ata_pci_remove_one,
285 static int pdc_port_start(struct ata_port *ap)
287 struct device *dev = ap->host_set->dev;
288 struct pdc_port_priv *pp;
291 rc = ata_port_start(ap);
295 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
301 pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
307 ap->private_data = pp;
319 static void pdc_port_stop(struct ata_port *ap)
321 struct device *dev = ap->host_set->dev;
322 struct pdc_port_priv *pp = ap->private_data;
324 ap->private_data = NULL;
325 dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
331 static void pdc_host_stop(struct ata_host_set *host_set)
333 struct pdc_host_priv *hp = host_set->private_data;
335 ata_pci_host_stop(host_set);
341 static void pdc_reset_port(struct ata_port *ap)
343 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
347 for (i = 11; i > 0; i--) {
360 readl(mmio); /* flush */
363 static void pdc_sata_phy_reset(struct ata_port *ap)
369 static void pdc_pata_cbl_detect(struct ata_port *ap)
372 void __iomem *mmio = (void *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
377 ap->cbl = ATA_CBL_PATA40;
378 ap->udma_mask &= ATA_UDMA_MASK_40C;
380 ap->cbl = ATA_CBL_PATA80;
383 static void pdc_pata_phy_reset(struct ata_port *ap)
385 pdc_pata_cbl_detect(ap);
391 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
393 if (sc_reg > SCR_CONTROL)
395 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
399 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
402 if (sc_reg > SCR_CONTROL)
404 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
407 static void pdc_qc_prep(struct ata_queued_cmd *qc)
409 struct pdc_port_priv *pp = qc->ap->private_data;
414 switch (qc->tf.protocol) {
419 case ATA_PROT_NODATA:
420 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
421 qc->dev->devno, pp->pkt);
423 if (qc->tf.flags & ATA_TFLAG_LBA48)
424 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
426 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
428 pdc_pkt_footer(&qc->tf, pp->pkt, i);
436 static void pdc_eng_timeout(struct ata_port *ap)
438 struct ata_host_set *host_set = ap->host_set;
440 struct ata_queued_cmd *qc;
445 spin_lock_irqsave(&host_set->lock, flags);
447 qc = ata_qc_from_tag(ap, ap->active_tag);
449 switch (qc->tf.protocol) {
451 case ATA_PROT_NODATA:
452 ata_port_printk(ap, KERN_ERR, "command timeout\n");
453 drv_stat = ata_wait_idle(ap);
454 qc->err_mask |= __ac_err_mask(drv_stat);
458 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
460 ata_port_printk(ap, KERN_ERR,
461 "unknown timeout, cmd 0x%x stat 0x%x\n",
462 qc->tf.command, drv_stat);
464 qc->err_mask |= ac_err_mask(drv_stat);
468 spin_unlock_irqrestore(&host_set->lock, flags);
469 ata_eh_qc_complete(qc);
473 static inline unsigned int pdc_host_intr( struct ata_port *ap,
474 struct ata_queued_cmd *qc)
476 unsigned int handled = 0;
478 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
481 if (tmp & PDC_ERR_MASK) {
482 qc->err_mask |= AC_ERR_DEV;
486 switch (qc->tf.protocol) {
488 case ATA_PROT_NODATA:
489 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
495 ap->stats.idle_irq++;
502 static void pdc_irq_clear(struct ata_port *ap)
504 struct ata_host_set *host_set = ap->host_set;
505 void __iomem *mmio = host_set->mmio_base;
507 readl(mmio + PDC_INT_SEQMASK);
510 static irqreturn_t pdc_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
512 struct ata_host_set *host_set = dev_instance;
516 unsigned int handled = 0;
517 void __iomem *mmio_base;
521 if (!host_set || !host_set->mmio_base) {
522 VPRINTK("QUICK EXIT\n");
526 mmio_base = host_set->mmio_base;
528 /* reading should also clear interrupts */
529 mask = readl(mmio_base + PDC_INT_SEQMASK);
531 if (mask == 0xffffffff) {
532 VPRINTK("QUICK EXIT 2\n");
536 spin_lock(&host_set->lock);
538 mask &= 0xffff; /* only 16 tags possible */
540 VPRINTK("QUICK EXIT 3\n");
544 writel(mask, mmio_base + PDC_INT_SEQMASK);
546 for (i = 0; i < host_set->n_ports; i++) {
547 VPRINTK("port %u\n", i);
548 ap = host_set->ports[i];
549 tmp = mask & (1 << (i + 1));
551 !(ap->flags & ATA_FLAG_DISABLED)) {
552 struct ata_queued_cmd *qc;
554 qc = ata_qc_from_tag(ap, ap->active_tag);
555 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
556 handled += pdc_host_intr(ap, qc);
563 spin_unlock(&host_set->lock);
564 return IRQ_RETVAL(handled);
567 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
569 struct ata_port *ap = qc->ap;
570 struct pdc_port_priv *pp = ap->private_data;
571 unsigned int port_no = ap->port_no;
572 u8 seq = (u8) (port_no + 1);
574 VPRINTK("ENTER, ap %p\n", ap);
576 writel(0x00000001, ap->host_set->mmio_base + (seq * 4));
577 readl(ap->host_set->mmio_base + (seq * 4)); /* flush */
580 wmb(); /* flush PRD, pkt writes */
581 writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
582 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
585 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
587 switch (qc->tf.protocol) {
589 case ATA_PROT_NODATA:
590 pdc_packet_start(qc);
593 case ATA_PROT_ATAPI_DMA:
601 return ata_qc_issue_prot(qc);
604 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
606 WARN_ON (tf->protocol == ATA_PROT_DMA ||
607 tf->protocol == ATA_PROT_NODATA);
612 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
614 WARN_ON (tf->protocol == ATA_PROT_DMA ||
615 tf->protocol == ATA_PROT_NODATA);
616 ata_exec_command(ap, tf);
620 static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
622 port->cmd_addr = base;
623 port->data_addr = base;
625 port->error_addr = base + 0x4;
626 port->nsect_addr = base + 0x8;
627 port->lbal_addr = base + 0xc;
628 port->lbam_addr = base + 0x10;
629 port->lbah_addr = base + 0x14;
630 port->device_addr = base + 0x18;
632 port->status_addr = base + 0x1c;
633 port->altstatus_addr =
634 port->ctl_addr = base + 0x38;
638 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
640 void __iomem *mmio = pe->mmio_base;
641 struct pdc_host_priv *hp = pe->private_data;
642 int hotplug_offset = hp->hotplug_offset;
646 * Except for the hotplug stuff, this is voodoo from the
647 * Promise driver. Label this entire section
648 * "TODO: figure out why we do this"
651 /* change FIFO_SHD to 8 dwords, enable BMR_BURST */
652 tmp = readl(mmio + PDC_FLASH_CTL);
653 tmp |= 0x12000; /* bit 16 (fifo 8 dw) and 13 (bmr burst?) */
654 writel(tmp, mmio + PDC_FLASH_CTL);
656 /* clear plug/unplug flags for all ports */
657 tmp = readl(mmio + hotplug_offset);
658 writel(tmp | 0xff, mmio + hotplug_offset);
660 /* mask plug/unplug ints */
661 tmp = readl(mmio + hotplug_offset);
662 writel(tmp | 0xff0000, mmio + hotplug_offset);
664 /* reduce TBG clock to 133 Mhz. */
665 tmp = readl(mmio + PDC_TBG_MODE);
666 tmp &= ~0x30000; /* clear bit 17, 16*/
667 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
668 writel(tmp, mmio + PDC_TBG_MODE);
670 readl(mmio + PDC_TBG_MODE); /* flush */
673 /* adjust slew rate control register. */
674 tmp = readl(mmio + PDC_SLEW_CTL);
675 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
676 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
677 writel(tmp, mmio + PDC_SLEW_CTL);
680 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
682 static int printed_version;
683 struct ata_probe_ent *probe_ent = NULL;
684 struct pdc_host_priv *hp;
686 void __iomem *mmio_base;
687 unsigned int board_idx = (unsigned int) ent->driver_data;
688 int pci_dev_busy = 0;
691 if (!printed_version++)
692 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
694 rc = pci_enable_device(pdev);
698 rc = pci_request_regions(pdev, DRV_NAME);
704 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
706 goto err_out_regions;
707 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
709 goto err_out_regions;
711 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
712 if (probe_ent == NULL) {
714 goto err_out_regions;
717 probe_ent->dev = pci_dev_to_dev(pdev);
718 INIT_LIST_HEAD(&probe_ent->node);
720 mmio_base = pci_iomap(pdev, 3, 0);
721 if (mmio_base == NULL) {
723 goto err_out_free_ent;
725 base = (unsigned long) mmio_base;
727 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
730 goto err_out_free_ent;
733 /* Set default hotplug offset */
734 hp->hotplug_offset = PDC_SATA_PLUG_CSR;
735 probe_ent->private_data = hp;
737 probe_ent->sht = pdc_port_info[board_idx].sht;
738 probe_ent->host_flags = pdc_port_info[board_idx].host_flags;
739 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
740 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
741 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
742 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
744 probe_ent->irq = pdev->irq;
745 probe_ent->irq_flags = SA_SHIRQ;
746 probe_ent->mmio_base = mmio_base;
748 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
749 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
751 probe_ent->port[0].scr_addr = base + 0x400;
752 probe_ent->port[1].scr_addr = base + 0x500;
754 /* notice 4-port boards */
757 /* Override hotplug offset for SATAII150 */
758 hp->hotplug_offset = PDC2_SATA_PLUG_CSR;
761 probe_ent->n_ports = 4;
763 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
764 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
766 probe_ent->port[2].scr_addr = base + 0x600;
767 probe_ent->port[3].scr_addr = base + 0x700;
770 /* Override hotplug offset for SATAII150 */
771 hp->hotplug_offset = PDC2_SATA_PLUG_CSR;
774 probe_ent->n_ports = 2;
777 probe_ent->n_ports = 2;
780 probe_ent->n_ports = 4;
782 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
783 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
785 probe_ent->port[2].scr_addr = base + 0x600;
786 probe_ent->port[3].scr_addr = base + 0x700;
793 pci_set_master(pdev);
795 /* initialize adapter */
796 pdc_host_init(board_idx, probe_ent);
798 /* FIXME: Need any other frees than hp? */
799 if (!ata_device_add(probe_ent))
809 pci_release_regions(pdev);
812 pci_disable_device(pdev);
817 static int __init pdc_ata_init(void)
819 return pci_module_init(&pdc_ata_pci_driver);
823 static void __exit pdc_ata_exit(void)
825 pci_unregister_driver(&pdc_ata_pci_driver);
829 MODULE_AUTHOR("Jeff Garzik");
830 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
831 MODULE_LICENSE("GPL");
832 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
833 MODULE_VERSION(DRV_VERSION);
835 module_init(pdc_ata_init);
836 module_exit(pdc_ata_exit);