2 * sata_nv.c - NVIDIA nForce SATA
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
26 * No hardware documentation available outside of NVIDIA.
27 * This driver programs the NVIDIA SATA controller in a similar
28 * fashion as with other PCI IDE BMDMA controllers, with a few
29 * NV-specific details such as register offsets, SATA phy location,
34 #include <linux/config.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/device.h>
43 #include <scsi/scsi_host.h>
44 #include <linux/libata.h>
46 #define DRV_NAME "sata_nv"
47 #define DRV_VERSION "0.9"
54 NV_PORT0_SCR_REG_OFFSET = 0x00,
55 NV_PORT1_SCR_REG_OFFSET = 0x40,
57 /* INT_STATUS/ENABLE */
60 NV_INT_STATUS_CK804 = 0x440,
61 NV_INT_ENABLE_CK804 = 0x441,
63 /* INT_STATUS/ENABLE bits */
67 NV_INT_REMOVED = 0x08,
69 NV_INT_PORT_SHIFT = 4, /* each port occupies 4 bits */
72 NV_INT_MASK = NV_INT_DEV |
73 NV_INT_ADDED | NV_INT_REMOVED,
77 NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI
79 // For PCI config register 20
80 NV_MCP_SATA_CFG_20 = 0x50,
81 NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
84 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
85 static void nv_ck804_host_stop(struct ata_host_set *host_set);
86 static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance,
87 struct pt_regs *regs);
88 static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance,
89 struct pt_regs *regs);
90 static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance,
91 struct pt_regs *regs);
92 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
93 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
95 static void nv_nf2_freeze(struct ata_port *ap);
96 static void nv_nf2_thaw(struct ata_port *ap);
97 static void nv_ck804_freeze(struct ata_port *ap);
98 static void nv_ck804_thaw(struct ata_port *ap);
99 static void nv_error_handler(struct ata_port *ap);
105 NFORCE3 = NFORCE2, /* NF2 == NF3 as far as sata_nv is concerned */
109 static const struct pci_device_id nv_pci_tbl[] = {
110 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA,
111 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE2 },
112 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA,
113 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
114 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2,
115 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
116 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA,
117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
118 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
120 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
122 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
124 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
126 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2,
127 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
128 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
130 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
132 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA,
133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
134 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2,
135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
136 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3,
137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
138 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
139 PCI_ANY_ID, PCI_ANY_ID,
140 PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC },
141 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
142 PCI_ANY_ID, PCI_ANY_ID,
143 PCI_CLASS_STORAGE_RAID<<8, 0xffff00, GENERIC },
144 { 0, } /* terminate list */
147 static struct pci_driver nv_pci_driver = {
149 .id_table = nv_pci_tbl,
150 .probe = nv_init_one,
151 .remove = ata_pci_remove_one,
154 static struct scsi_host_template nv_sht = {
155 .module = THIS_MODULE,
157 .ioctl = ata_scsi_ioctl,
158 .queuecommand = ata_scsi_queuecmd,
159 .can_queue = ATA_DEF_QUEUE,
160 .this_id = ATA_SHT_THIS_ID,
161 .sg_tablesize = LIBATA_MAX_PRD,
162 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
163 .emulated = ATA_SHT_EMULATED,
164 .use_clustering = ATA_SHT_USE_CLUSTERING,
165 .proc_name = DRV_NAME,
166 .dma_boundary = ATA_DMA_BOUNDARY,
167 .slave_configure = ata_scsi_slave_config,
168 .slave_destroy = ata_scsi_slave_destroy,
169 .bios_param = ata_std_bios_param,
172 static const struct ata_port_operations nv_generic_ops = {
173 .port_disable = ata_port_disable,
174 .tf_load = ata_tf_load,
175 .tf_read = ata_tf_read,
176 .exec_command = ata_exec_command,
177 .check_status = ata_check_status,
178 .dev_select = ata_std_dev_select,
179 .bmdma_setup = ata_bmdma_setup,
180 .bmdma_start = ata_bmdma_start,
181 .bmdma_stop = ata_bmdma_stop,
182 .bmdma_status = ata_bmdma_status,
183 .qc_prep = ata_qc_prep,
184 .qc_issue = ata_qc_issue_prot,
185 .freeze = ata_bmdma_freeze,
186 .thaw = ata_bmdma_thaw,
187 .error_handler = nv_error_handler,
188 .post_internal_cmd = ata_bmdma_post_internal_cmd,
189 .data_xfer = ata_pio_data_xfer,
190 .irq_handler = nv_generic_interrupt,
191 .irq_clear = ata_bmdma_irq_clear,
192 .scr_read = nv_scr_read,
193 .scr_write = nv_scr_write,
194 .port_start = ata_port_start,
195 .port_stop = ata_port_stop,
196 .host_stop = ata_pci_host_stop,
199 static const struct ata_port_operations nv_nf2_ops = {
200 .port_disable = ata_port_disable,
201 .tf_load = ata_tf_load,
202 .tf_read = ata_tf_read,
203 .exec_command = ata_exec_command,
204 .check_status = ata_check_status,
205 .dev_select = ata_std_dev_select,
206 .bmdma_setup = ata_bmdma_setup,
207 .bmdma_start = ata_bmdma_start,
208 .bmdma_stop = ata_bmdma_stop,
209 .bmdma_status = ata_bmdma_status,
210 .qc_prep = ata_qc_prep,
211 .qc_issue = ata_qc_issue_prot,
212 .freeze = nv_nf2_freeze,
214 .error_handler = nv_error_handler,
215 .post_internal_cmd = ata_bmdma_post_internal_cmd,
216 .data_xfer = ata_pio_data_xfer,
217 .irq_handler = nv_nf2_interrupt,
218 .irq_clear = ata_bmdma_irq_clear,
219 .scr_read = nv_scr_read,
220 .scr_write = nv_scr_write,
221 .port_start = ata_port_start,
222 .port_stop = ata_port_stop,
223 .host_stop = ata_pci_host_stop,
226 static const struct ata_port_operations nv_ck804_ops = {
227 .port_disable = ata_port_disable,
228 .tf_load = ata_tf_load,
229 .tf_read = ata_tf_read,
230 .exec_command = ata_exec_command,
231 .check_status = ata_check_status,
232 .dev_select = ata_std_dev_select,
233 .bmdma_setup = ata_bmdma_setup,
234 .bmdma_start = ata_bmdma_start,
235 .bmdma_stop = ata_bmdma_stop,
236 .bmdma_status = ata_bmdma_status,
237 .qc_prep = ata_qc_prep,
238 .qc_issue = ata_qc_issue_prot,
239 .freeze = nv_ck804_freeze,
240 .thaw = nv_ck804_thaw,
241 .error_handler = nv_error_handler,
242 .post_internal_cmd = ata_bmdma_post_internal_cmd,
243 .data_xfer = ata_pio_data_xfer,
244 .irq_handler = nv_ck804_interrupt,
245 .irq_clear = ata_bmdma_irq_clear,
246 .scr_read = nv_scr_read,
247 .scr_write = nv_scr_write,
248 .port_start = ata_port_start,
249 .port_stop = ata_port_stop,
250 .host_stop = nv_ck804_host_stop,
253 static struct ata_port_info nv_port_info[] = {
257 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
258 .pio_mask = NV_PIO_MASK,
259 .mwdma_mask = NV_MWDMA_MASK,
260 .udma_mask = NV_UDMA_MASK,
261 .port_ops = &nv_generic_ops,
266 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
267 .pio_mask = NV_PIO_MASK,
268 .mwdma_mask = NV_MWDMA_MASK,
269 .udma_mask = NV_UDMA_MASK,
270 .port_ops = &nv_nf2_ops,
275 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY,
276 .pio_mask = NV_PIO_MASK,
277 .mwdma_mask = NV_MWDMA_MASK,
278 .udma_mask = NV_UDMA_MASK,
279 .port_ops = &nv_ck804_ops,
283 MODULE_AUTHOR("NVIDIA");
284 MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
285 MODULE_LICENSE("GPL");
286 MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
287 MODULE_VERSION(DRV_VERSION);
289 static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance,
290 struct pt_regs *regs)
292 struct ata_host_set *host_set = dev_instance;
294 unsigned int handled = 0;
297 spin_lock_irqsave(&host_set->lock, flags);
299 for (i = 0; i < host_set->n_ports; i++) {
302 ap = host_set->ports[i];
304 !(ap->flags & ATA_FLAG_DISABLED)) {
305 struct ata_queued_cmd *qc;
307 qc = ata_qc_from_tag(ap, ap->active_tag);
308 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
309 handled += ata_host_intr(ap, qc);
311 // No request pending? Clear interrupt status
312 // anyway, in case there's one pending.
313 ap->ops->check_status(ap);
318 spin_unlock_irqrestore(&host_set->lock, flags);
320 return IRQ_RETVAL(handled);
323 static int nv_host_intr(struct ata_port *ap, u8 irq_stat)
325 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag);
328 /* freeze if hotplugged */
329 if (unlikely(irq_stat & (NV_INT_ADDED | NV_INT_REMOVED))) {
334 /* bail out if not our interrupt */
335 if (!(irq_stat & NV_INT_DEV))
338 /* DEV interrupt w/ no active qc? */
339 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
340 ata_check_status(ap);
344 /* handle interrupt */
345 handled = ata_host_intr(ap, qc);
346 if (unlikely(!handled)) {
347 /* spurious, clear it */
348 ata_check_status(ap);
354 static irqreturn_t nv_do_interrupt(struct ata_host_set *host_set, u8 irq_stat)
358 for (i = 0; i < host_set->n_ports; i++) {
359 struct ata_port *ap = host_set->ports[i];
361 if (ap && !(ap->flags & ATA_FLAG_DISABLED))
362 handled += nv_host_intr(ap, irq_stat);
364 irq_stat >>= NV_INT_PORT_SHIFT;
367 return IRQ_RETVAL(handled);
370 static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance,
371 struct pt_regs *regs)
373 struct ata_host_set *host_set = dev_instance;
378 spin_lock_irqsave(&host_set->lock, flags);
379 irq_stat = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
380 ret = nv_do_interrupt(host_set, irq_stat);
381 spin_unlock_irqrestore(&host_set->lock, flags);
386 static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance,
387 struct pt_regs *regs)
389 struct ata_host_set *host_set = dev_instance;
394 spin_lock_irqsave(&host_set->lock, flags);
395 irq_stat = readb(host_set->mmio_base + NV_INT_STATUS_CK804);
396 ret = nv_do_interrupt(host_set, irq_stat);
397 spin_unlock_irqrestore(&host_set->lock, flags);
402 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
404 if (sc_reg > SCR_CONTROL)
407 return ioread32((void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
410 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
412 if (sc_reg > SCR_CONTROL)
415 iowrite32(val, (void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
418 static void nv_nf2_freeze(struct ata_port *ap)
420 unsigned long scr_addr = ap->host_set->ports[0]->ioaddr.scr_addr;
421 int shift = ap->port_no * NV_INT_PORT_SHIFT;
424 mask = inb(scr_addr + NV_INT_ENABLE);
425 mask &= ~(NV_INT_ALL << shift);
426 outb(mask, scr_addr + NV_INT_ENABLE);
429 static void nv_nf2_thaw(struct ata_port *ap)
431 unsigned long scr_addr = ap->host_set->ports[0]->ioaddr.scr_addr;
432 int shift = ap->port_no * NV_INT_PORT_SHIFT;
435 outb(NV_INT_ALL << shift, scr_addr + NV_INT_STATUS);
437 mask = inb(scr_addr + NV_INT_ENABLE);
438 mask |= (NV_INT_MASK << shift);
439 outb(mask, scr_addr + NV_INT_ENABLE);
442 static void nv_ck804_freeze(struct ata_port *ap)
444 void __iomem *mmio_base = ap->host_set->mmio_base;
445 int shift = ap->port_no * NV_INT_PORT_SHIFT;
448 mask = readb(mmio_base + NV_INT_ENABLE_CK804);
449 mask &= ~(NV_INT_ALL << shift);
450 writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
453 static void nv_ck804_thaw(struct ata_port *ap)
455 void __iomem *mmio_base = ap->host_set->mmio_base;
456 int shift = ap->port_no * NV_INT_PORT_SHIFT;
459 writeb(NV_INT_ALL << shift, mmio_base + NV_INT_STATUS_CK804);
461 mask = readb(mmio_base + NV_INT_ENABLE_CK804);
462 mask |= (NV_INT_MASK << shift);
463 writeb(mask, mmio_base + NV_INT_ENABLE_CK804);
466 static int nv_hardreset(struct ata_port *ap, unsigned int *class)
470 /* SATA hardreset fails to retrieve proper device signature on
471 * some controllers. Don't classify on hardreset. For more
472 * info, see http://bugme.osdl.org/show_bug.cgi?id=3352
474 return sata_std_hardreset(ap, &dummy);
477 static void nv_error_handler(struct ata_port *ap)
479 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
480 nv_hardreset, ata_std_postreset);
483 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
485 static int printed_version = 0;
486 struct ata_port_info *ppi;
487 struct ata_probe_ent *probe_ent;
488 int pci_dev_busy = 0;
493 // Make sure this is a SATA controller by counting the number of bars
494 // (NVIDIA SATA controllers will always have six bars). Otherwise,
495 // it's an IDE controller and we ignore it.
496 for (bar=0; bar<6; bar++)
497 if (pci_resource_start(pdev, bar) == 0)
500 if (!printed_version++)
501 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
503 rc = pci_enable_device(pdev);
507 rc = pci_request_regions(pdev, DRV_NAME);
510 goto err_out_disable;
513 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
515 goto err_out_regions;
516 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
518 goto err_out_regions;
522 ppi = &nv_port_info[ent->driver_data];
523 probe_ent = ata_pci_init_native_mode(pdev, &ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
525 goto err_out_regions;
527 probe_ent->mmio_base = pci_iomap(pdev, 5, 0);
528 if (!probe_ent->mmio_base) {
530 goto err_out_free_ent;
533 base = (unsigned long)probe_ent->mmio_base;
535 probe_ent->port[0].scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
536 probe_ent->port[1].scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
538 /* enable SATA space for CK804 */
539 if (ent->driver_data == CK804) {
542 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val);
543 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
544 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
547 pci_set_master(pdev);
549 rc = ata_device_add(probe_ent);
551 goto err_out_iounmap;
558 pci_iounmap(pdev, probe_ent->mmio_base);
562 pci_release_regions(pdev);
565 pci_disable_device(pdev);
570 static void nv_ck804_host_stop(struct ata_host_set *host_set)
572 struct pci_dev *pdev = to_pci_dev(host_set->dev);
575 /* disable SATA space for CK804 */
576 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val);
577 regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
578 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
580 ata_pci_host_stop(host_set);
583 static int __init nv_init(void)
585 return pci_module_init(&nv_pci_driver);
588 static void __exit nv_exit(void)
590 pci_unregister_driver(&nv_pci_driver);
593 module_init(nv_init);
594 module_exit(nv_exit);