2 * sata_nv.c - NVIDIA nForce SATA
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
26 * No hardware documentation available outside of NVIDIA.
27 * This driver programs the NVIDIA SATA controller in a similar
28 * fashion as with other PCI IDE BMDMA controllers, with a few
29 * NV-specific details such as register offsets, SATA phy location,
34 #include <linux/config.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/device.h>
43 #include <scsi/scsi_host.h>
44 #include <linux/libata.h>
46 #define DRV_NAME "sata_nv"
47 #define DRV_VERSION "0.9"
54 NV_PORT0_SCR_REG_OFFSET = 0x00,
55 NV_PORT1_SCR_REG_OFFSET = 0x40,
58 NV_INT_STATUS_CK804 = 0x440,
59 NV_INT_STATUS_PDEV_INT = 0x01,
60 NV_INT_STATUS_PDEV_PM = 0x02,
61 NV_INT_STATUS_PDEV_ADDED = 0x04,
62 NV_INT_STATUS_PDEV_REMOVED = 0x08,
63 NV_INT_STATUS_SDEV_INT = 0x10,
64 NV_INT_STATUS_SDEV_PM = 0x20,
65 NV_INT_STATUS_SDEV_ADDED = 0x40,
66 NV_INT_STATUS_SDEV_REMOVED = 0x80,
67 NV_INT_STATUS_PDEV_HOTPLUG = (NV_INT_STATUS_PDEV_ADDED |
68 NV_INT_STATUS_PDEV_REMOVED),
69 NV_INT_STATUS_SDEV_HOTPLUG = (NV_INT_STATUS_SDEV_ADDED |
70 NV_INT_STATUS_SDEV_REMOVED),
71 NV_INT_STATUS_HOTPLUG = (NV_INT_STATUS_PDEV_HOTPLUG |
72 NV_INT_STATUS_SDEV_HOTPLUG),
75 NV_INT_ENABLE_CK804 = 0x441,
76 NV_INT_ENABLE_PDEV_MASK = 0x01,
77 NV_INT_ENABLE_PDEV_PM = 0x02,
78 NV_INT_ENABLE_PDEV_ADDED = 0x04,
79 NV_INT_ENABLE_PDEV_REMOVED = 0x08,
80 NV_INT_ENABLE_SDEV_MASK = 0x10,
81 NV_INT_ENABLE_SDEV_PM = 0x20,
82 NV_INT_ENABLE_SDEV_ADDED = 0x40,
83 NV_INT_ENABLE_SDEV_REMOVED = 0x80,
84 NV_INT_ENABLE_PDEV_HOTPLUG = (NV_INT_ENABLE_PDEV_ADDED |
85 NV_INT_ENABLE_PDEV_REMOVED),
86 NV_INT_ENABLE_SDEV_HOTPLUG = (NV_INT_ENABLE_SDEV_ADDED |
87 NV_INT_ENABLE_SDEV_REMOVED),
88 NV_INT_ENABLE_HOTPLUG = (NV_INT_ENABLE_PDEV_HOTPLUG |
89 NV_INT_ENABLE_SDEV_HOTPLUG),
92 NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI
94 // For PCI config register 20
95 NV_MCP_SATA_CFG_20 = 0x50,
96 NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04,
99 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
100 static irqreturn_t nv_interrupt (int irq, void *dev_instance,
101 struct pt_regs *regs);
102 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg);
103 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
104 static void nv_host_stop (struct ata_host_set *host_set);
105 static void nv_enable_hotplug(struct ata_probe_ent *probe_ent);
106 static void nv_disable_hotplug(struct ata_host_set *host_set);
107 static int nv_check_hotplug(struct ata_host_set *host_set);
108 static void nv_enable_hotplug_ck804(struct ata_probe_ent *probe_ent);
109 static void nv_disable_hotplug_ck804(struct ata_host_set *host_set);
110 static int nv_check_hotplug_ck804(struct ata_host_set *host_set);
120 static const struct pci_device_id nv_pci_tbl[] = {
121 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA,
122 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE2 },
123 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA,
124 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
125 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2,
126 PCI_ANY_ID, PCI_ANY_ID, 0, 0, NFORCE3 },
127 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA,
128 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
129 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2,
130 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
131 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA,
132 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
133 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2,
134 PCI_ANY_ID, PCI_ANY_ID, 0, 0, CK804 },
135 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA,
136 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
137 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2,
138 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
139 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA,
140 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
141 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2,
142 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
143 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA,
144 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
145 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2,
146 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
147 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3,
148 PCI_ANY_ID, PCI_ANY_ID, 0, 0, GENERIC },
149 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
150 PCI_ANY_ID, PCI_ANY_ID,
151 PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC },
152 { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
153 PCI_ANY_ID, PCI_ANY_ID,
154 PCI_CLASS_STORAGE_RAID<<8, 0xffff00, GENERIC },
155 { 0, } /* terminate list */
160 enum nv_host_type host_type;
161 void (*enable_hotplug)(struct ata_probe_ent *probe_ent);
162 void (*disable_hotplug)(struct ata_host_set *host_set);
163 int (*check_hotplug)(struct ata_host_set *host_set);
166 static struct nv_host_desc nv_device_tbl[] = {
168 .host_type = GENERIC,
169 .enable_hotplug = NULL,
170 .disable_hotplug= NULL,
171 .check_hotplug = NULL,
174 .host_type = NFORCE2,
175 .enable_hotplug = nv_enable_hotplug,
176 .disable_hotplug= nv_disable_hotplug,
177 .check_hotplug = nv_check_hotplug,
180 .host_type = NFORCE3,
181 .enable_hotplug = nv_enable_hotplug,
182 .disable_hotplug= nv_disable_hotplug,
183 .check_hotplug = nv_check_hotplug,
185 { .host_type = CK804,
186 .enable_hotplug = nv_enable_hotplug_ck804,
187 .disable_hotplug= nv_disable_hotplug_ck804,
188 .check_hotplug = nv_check_hotplug_ck804,
194 struct nv_host_desc *host_desc;
195 unsigned long host_flags;
198 static struct pci_driver nv_pci_driver = {
200 .id_table = nv_pci_tbl,
201 .probe = nv_init_one,
202 .remove = ata_pci_remove_one,
205 static struct scsi_host_template nv_sht = {
206 .module = THIS_MODULE,
208 .ioctl = ata_scsi_ioctl,
209 .queuecommand = ata_scsi_queuecmd,
210 .can_queue = ATA_DEF_QUEUE,
211 .this_id = ATA_SHT_THIS_ID,
212 .sg_tablesize = LIBATA_MAX_PRD,
213 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
214 .emulated = ATA_SHT_EMULATED,
215 .use_clustering = ATA_SHT_USE_CLUSTERING,
216 .proc_name = DRV_NAME,
217 .dma_boundary = ATA_DMA_BOUNDARY,
218 .slave_configure = ata_scsi_slave_config,
219 .bios_param = ata_std_bios_param,
222 static const struct ata_port_operations nv_ops = {
223 .port_disable = ata_port_disable,
224 .tf_load = ata_tf_load,
225 .tf_read = ata_tf_read,
226 .exec_command = ata_exec_command,
227 .check_status = ata_check_status,
228 .dev_select = ata_std_dev_select,
229 .phy_reset = sata_phy_reset,
230 .bmdma_setup = ata_bmdma_setup,
231 .bmdma_start = ata_bmdma_start,
232 .bmdma_stop = ata_bmdma_stop,
233 .bmdma_status = ata_bmdma_status,
234 .qc_prep = ata_qc_prep,
235 .qc_issue = ata_qc_issue_prot,
236 .eng_timeout = ata_eng_timeout,
237 .irq_handler = nv_interrupt,
238 .irq_clear = ata_bmdma_irq_clear,
239 .scr_read = nv_scr_read,
240 .scr_write = nv_scr_write,
241 .port_start = ata_port_start,
242 .port_stop = ata_port_stop,
243 .host_stop = nv_host_stop,
246 /* FIXME: The hardware provides the necessary SATA PHY controls
247 * to support ATA_FLAG_SATA_RESET. However, it is currently
248 * necessary to disable that flag, to solve misdetection problems.
249 * See http://bugme.osdl.org/show_bug.cgi?id=3352 for more info.
251 * This problem really needs to be investigated further. But in the
252 * meantime, we avoid ATA_FLAG_SATA_RESET to get people working.
254 static struct ata_port_info nv_port_info = {
256 .host_flags = ATA_FLAG_SATA |
257 /* ATA_FLAG_SATA_RESET | */
260 .pio_mask = NV_PIO_MASK,
261 .mwdma_mask = NV_MWDMA_MASK,
262 .udma_mask = NV_UDMA_MASK,
266 MODULE_AUTHOR("NVIDIA");
267 MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
268 MODULE_LICENSE("GPL");
269 MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
270 MODULE_VERSION(DRV_VERSION);
272 static irqreturn_t nv_interrupt (int irq, void *dev_instance,
273 struct pt_regs *regs)
275 struct ata_host_set *host_set = dev_instance;
276 struct nv_host *host = host_set->private_data;
278 unsigned int handled = 0;
281 spin_lock_irqsave(&host_set->lock, flags);
283 for (i = 0; i < host_set->n_ports; i++) {
286 ap = host_set->ports[i];
288 !(ap->flags & ATA_FLAG_DISABLED)) {
289 struct ata_queued_cmd *qc;
291 qc = ata_qc_from_tag(ap, ap->active_tag);
292 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
293 handled += ata_host_intr(ap, qc);
295 // No request pending? Clear interrupt status
296 // anyway, in case there's one pending.
297 ap->ops->check_status(ap);
302 if (host->host_desc->check_hotplug)
303 handled += host->host_desc->check_hotplug(host_set);
305 spin_unlock_irqrestore(&host_set->lock, flags);
307 return IRQ_RETVAL(handled);
310 static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg)
312 if (sc_reg > SCR_CONTROL)
315 return ioread32((void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
318 static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
320 if (sc_reg > SCR_CONTROL)
323 iowrite32(val, (void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4));
326 static void nv_host_stop (struct ata_host_set *host_set)
328 struct nv_host *host = host_set->private_data;
330 // Disable hotplug event interrupts.
331 if (host->host_desc->disable_hotplug)
332 host->host_desc->disable_hotplug(host_set);
336 ata_pci_host_stop(host_set);
339 static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
341 static int printed_version = 0;
342 struct nv_host *host;
343 struct ata_port_info *ppi;
344 struct ata_probe_ent *probe_ent;
345 int pci_dev_busy = 0;
350 // Make sure this is a SATA controller by counting the number of bars
351 // (NVIDIA SATA controllers will always have six bars). Otherwise,
352 // it's an IDE controller and we ignore it.
353 for (bar=0; bar<6; bar++)
354 if (pci_resource_start(pdev, bar) == 0)
357 if (!printed_version++)
358 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
360 rc = pci_enable_device(pdev);
364 rc = pci_request_regions(pdev, DRV_NAME);
367 goto err_out_disable;
370 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
372 goto err_out_regions;
373 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
375 goto err_out_regions;
380 probe_ent = ata_pci_init_native_mode(pdev, &ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
382 goto err_out_regions;
384 host = kmalloc(sizeof(struct nv_host), GFP_KERNEL);
386 goto err_out_free_ent;
388 memset(host, 0, sizeof(struct nv_host));
389 host->host_desc = &nv_device_tbl[ent->driver_data];
391 probe_ent->private_data = host;
393 probe_ent->mmio_base = pci_iomap(pdev, 5, 0);
394 if (!probe_ent->mmio_base) {
396 goto err_out_free_host;
399 base = (unsigned long)probe_ent->mmio_base;
401 probe_ent->port[0].scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
402 probe_ent->port[1].scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
404 pci_set_master(pdev);
406 rc = ata_device_add(probe_ent);
408 goto err_out_iounmap;
410 // Enable hotplug event interrupts.
411 if (host->host_desc->enable_hotplug)
412 host->host_desc->enable_hotplug(probe_ent);
419 pci_iounmap(pdev, probe_ent->mmio_base);
425 pci_release_regions(pdev);
428 pci_disable_device(pdev);
433 static void nv_enable_hotplug(struct ata_probe_ent *probe_ent)
437 outb(NV_INT_STATUS_HOTPLUG,
438 probe_ent->port[0].scr_addr + NV_INT_STATUS);
440 intr_mask = inb(probe_ent->port[0].scr_addr + NV_INT_ENABLE);
441 intr_mask |= NV_INT_ENABLE_HOTPLUG;
443 outb(intr_mask, probe_ent->port[0].scr_addr + NV_INT_ENABLE);
446 static void nv_disable_hotplug(struct ata_host_set *host_set)
450 intr_mask = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_ENABLE);
452 intr_mask &= ~(NV_INT_ENABLE_HOTPLUG);
454 outb(intr_mask, host_set->ports[0]->ioaddr.scr_addr + NV_INT_ENABLE);
457 static int nv_check_hotplug(struct ata_host_set *host_set)
461 intr_status = inb(host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
463 // Clear interrupt status.
464 outb(0xff, host_set->ports[0]->ioaddr.scr_addr + NV_INT_STATUS);
466 if (intr_status & NV_INT_STATUS_HOTPLUG) {
467 if (intr_status & NV_INT_STATUS_PDEV_ADDED)
468 printk(KERN_WARNING "nv_sata: "
469 "Primary device added\n");
471 if (intr_status & NV_INT_STATUS_PDEV_REMOVED)
472 printk(KERN_WARNING "nv_sata: "
473 "Primary device removed\n");
475 if (intr_status & NV_INT_STATUS_SDEV_ADDED)
476 printk(KERN_WARNING "nv_sata: "
477 "Secondary device added\n");
479 if (intr_status & NV_INT_STATUS_SDEV_REMOVED)
480 printk(KERN_WARNING "nv_sata: "
481 "Secondary device removed\n");
489 static void nv_enable_hotplug_ck804(struct ata_probe_ent *probe_ent)
491 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
495 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val);
496 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
497 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
499 writeb(NV_INT_STATUS_HOTPLUG, probe_ent->mmio_base + NV_INT_STATUS_CK804);
501 intr_mask = readb(probe_ent->mmio_base + NV_INT_ENABLE_CK804);
502 intr_mask |= NV_INT_ENABLE_HOTPLUG;
504 writeb(intr_mask, probe_ent->mmio_base + NV_INT_ENABLE_CK804);
507 static void nv_disable_hotplug_ck804(struct ata_host_set *host_set)
509 struct pci_dev *pdev = to_pci_dev(host_set->dev);
513 intr_mask = readb(host_set->mmio_base + NV_INT_ENABLE_CK804);
515 intr_mask &= ~(NV_INT_ENABLE_HOTPLUG);
517 writeb(intr_mask, host_set->mmio_base + NV_INT_ENABLE_CK804);
519 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val);
520 regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
521 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
524 static int nv_check_hotplug_ck804(struct ata_host_set *host_set)
528 intr_status = readb(host_set->mmio_base + NV_INT_STATUS_CK804);
530 // Clear interrupt status.
531 writeb(0xff, host_set->mmio_base + NV_INT_STATUS_CK804);
533 if (intr_status & NV_INT_STATUS_HOTPLUG) {
534 if (intr_status & NV_INT_STATUS_PDEV_ADDED)
535 printk(KERN_WARNING "nv_sata: "
536 "Primary device added\n");
538 if (intr_status & NV_INT_STATUS_PDEV_REMOVED)
539 printk(KERN_WARNING "nv_sata: "
540 "Primary device removed\n");
542 if (intr_status & NV_INT_STATUS_SDEV_ADDED)
543 printk(KERN_WARNING "nv_sata: "
544 "Secondary device added\n");
546 if (intr_status & NV_INT_STATUS_SDEV_REMOVED)
547 printk(KERN_WARNING "nv_sata: "
548 "Secondary device removed\n");
556 static int __init nv_init(void)
558 return pci_module_init(&nv_pci_driver);
561 static void __exit nv_exit(void)
563 pci_unregister_driver(&nv_pci_driver);
566 module_init(nv_init);
567 module_exit(nv_exit);