2 * sata_mv.c - Marvell SATA support
4 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; version 2 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #include <linux/kernel.h>
24 #include <linux/module.h>
25 #include <linux/pci.h>
26 #include <linux/init.h>
27 #include <linux/blkdev.h>
28 #include <linux/delay.h>
29 #include <linux/interrupt.h>
30 #include <linux/sched.h>
31 #include <linux/dma-mapping.h>
33 #include <scsi/scsi_host.h>
34 #include <linux/libata.h>
37 #define DRV_NAME "sata_mv"
38 #define DRV_VERSION "0.25"
41 /* BAR's are enumerated in terms of pci_resource_start() terms */
42 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
43 MV_IO_BAR = 2, /* offset 0x18: IO space */
44 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
46 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
47 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
50 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
51 MV_SATAHC0_REG_BASE = 0x20000,
53 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
54 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
55 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
56 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
58 MV_USE_Q_DEPTH = ATA_DEF_QUEUE,
61 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
63 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
64 * CRPB needs alignment on a 256B boundary. Size == 256B
65 * SG count of 176 leads to MV_PORT_PRIV_DMA_SZ == 4KB
66 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
68 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
69 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
71 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
72 MV_PORT_PRIV_DMA_SZ = (MV_CRQB_Q_SZ + MV_CRPB_Q_SZ + MV_SG_TBL_SZ),
74 /* Our DMA boundary is determined by an ePRD being unable to handle
75 * anything larger than 64KB
77 MV_DMA_BOUNDARY = 0xffffU,
80 /* == (port / MV_PORTS_PER_HC) to determine HC from 0-7 port */
82 /* == (port % MV_PORTS_PER_HC) to determine hard port from 0-7 port */
86 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
87 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
88 MV_FLAG_GLBL_SFT_RST = (1 << 28), /* Global Soft Reset support */
89 MV_COMMON_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
90 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO),
91 MV_6XXX_FLAGS = (MV_FLAG_IRQ_COALESCE |
92 MV_FLAG_GLBL_SFT_RST),
99 CRQB_FLAG_READ = (1 << 0),
101 CRQB_CMD_ADDR_SHIFT = 8,
102 CRQB_CMD_CS = (0x2 << 11),
103 CRQB_CMD_LAST = (1 << 15),
105 CRPB_FLAG_STATUS_SHIFT = 8,
107 EPRD_FLAG_END_OF_TBL = (1 << 31),
109 /* PCI interface registers */
111 PCI_COMMAND_OFS = 0xc00,
113 PCI_MAIN_CMD_STS_OFS = 0xd30,
114 STOP_PCI_MASTER = (1 << 2),
115 PCI_MASTER_EMPTY = (1 << 3),
116 GLOB_SFT_RST = (1 << 4),
118 PCI_IRQ_CAUSE_OFS = 0x1d58,
119 PCI_IRQ_MASK_OFS = 0x1d5c,
120 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
122 HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
123 HC_MAIN_IRQ_MASK_OFS = 0x1d64,
124 PORT0_ERR = (1 << 0), /* shift by port # */
125 PORT0_DONE = (1 << 1), /* shift by port # */
126 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
127 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
129 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
130 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
131 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
132 GPIO_INT = (1 << 22),
133 SELF_INT = (1 << 23),
134 TWSI_INT = (1 << 24),
135 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
136 HC_MAIN_MASKED_IRQS = (TRAN_LO_DONE | TRAN_HI_DONE |
137 PORTS_0_7_COAL_DONE | GPIO_INT | TWSI_INT |
140 /* SATAHC registers */
143 HC_IRQ_CAUSE_OFS = 0x14,
144 CRPB_DMA_DONE = (1 << 0), /* shift by port # */
145 HC_IRQ_COAL = (1 << 4), /* IRQ coalescing */
146 DEV_IRQ = (1 << 8), /* shift by port # */
148 /* Shadow block registers */
150 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
153 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
154 SATA_ACTIVE_OFS = 0x350,
158 EDMA_CFG_Q_DEPTH = 0, /* queueing disabled */
159 EDMA_CFG_NCQ = (1 << 5),
160 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
161 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
162 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
164 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
165 EDMA_ERR_IRQ_MASK_OFS = 0xc,
166 EDMA_ERR_D_PAR = (1 << 0),
167 EDMA_ERR_PRD_PAR = (1 << 1),
168 EDMA_ERR_DEV = (1 << 2),
169 EDMA_ERR_DEV_DCON = (1 << 3),
170 EDMA_ERR_DEV_CON = (1 << 4),
171 EDMA_ERR_SERR = (1 << 5),
172 EDMA_ERR_SELF_DIS = (1 << 7),
173 EDMA_ERR_BIST_ASYNC = (1 << 8),
174 EDMA_ERR_CRBQ_PAR = (1 << 9),
175 EDMA_ERR_CRPB_PAR = (1 << 10),
176 EDMA_ERR_INTRL_PAR = (1 << 11),
177 EDMA_ERR_IORDY = (1 << 12),
178 EDMA_ERR_LNK_CTRL_RX = (0xf << 13),
179 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15),
180 EDMA_ERR_LNK_DATA_RX = (0xf << 17),
181 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21),
182 EDMA_ERR_LNK_DATA_TX = (0x1f << 26),
183 EDMA_ERR_TRANS_PROTO = (1 << 31),
184 EDMA_ERR_FATAL = (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
185 EDMA_ERR_DEV_DCON | EDMA_ERR_CRBQ_PAR |
186 EDMA_ERR_CRPB_PAR | EDMA_ERR_INTRL_PAR |
187 EDMA_ERR_IORDY | EDMA_ERR_LNK_CTRL_RX_2 |
188 EDMA_ERR_LNK_DATA_RX |
189 EDMA_ERR_LNK_DATA_TX |
190 EDMA_ERR_TRANS_PROTO),
192 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
193 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
194 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
196 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
197 EDMA_REQ_Q_PTR_SHIFT = 5,
199 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
200 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
201 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
202 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
203 EDMA_RSP_Q_PTR_SHIFT = 3,
210 /* Host private flags (hp_flags) */
211 MV_HP_FLAG_MSI = (1 << 0),
213 /* Port private flags (pp_flags) */
214 MV_PP_FLAG_EDMA_EN = (1 << 0),
215 MV_PP_FLAG_EDMA_DS_ACT = (1 << 1),
218 /* Command ReQuest Block: 32B */
226 /* Command ResPonse Block: 8B */
233 /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
241 struct mv_port_priv {
242 struct mv_crqb *crqb;
244 struct mv_crpb *crpb;
246 struct mv_sg *sg_tbl;
247 dma_addr_t sg_tbl_dma;
249 unsigned req_producer; /* cp of req_in_ptr */
250 unsigned rsp_consumer; /* cp of rsp_out_ptr */
254 struct mv_host_priv {
258 static void mv_irq_clear(struct ata_port *ap);
259 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in);
260 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
261 static void mv_phy_reset(struct ata_port *ap);
262 static void mv_host_stop(struct ata_host_set *host_set);
263 static int mv_port_start(struct ata_port *ap);
264 static void mv_port_stop(struct ata_port *ap);
265 static void mv_qc_prep(struct ata_queued_cmd *qc);
266 static int mv_qc_issue(struct ata_queued_cmd *qc);
267 static irqreturn_t mv_interrupt(int irq, void *dev_instance,
268 struct pt_regs *regs);
269 static void mv_eng_timeout(struct ata_port *ap);
270 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
272 static Scsi_Host_Template mv_sht = {
273 .module = THIS_MODULE,
275 .ioctl = ata_scsi_ioctl,
276 .queuecommand = ata_scsi_queuecmd,
277 .eh_strategy_handler = ata_scsi_error,
278 .can_queue = MV_USE_Q_DEPTH,
279 .this_id = ATA_SHT_THIS_ID,
280 .sg_tablesize = MV_MAX_SG_CT,
281 .max_sectors = ATA_MAX_SECTORS,
282 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
283 .emulated = ATA_SHT_EMULATED,
284 .use_clustering = ATA_SHT_USE_CLUSTERING,
285 .proc_name = DRV_NAME,
286 .dma_boundary = MV_DMA_BOUNDARY,
287 .slave_configure = ata_scsi_slave_config,
288 .bios_param = ata_std_bios_param,
292 static const struct ata_port_operations mv_ops = {
293 .port_disable = ata_port_disable,
295 .tf_load = ata_tf_load,
296 .tf_read = ata_tf_read,
297 .check_status = ata_check_status,
298 .exec_command = ata_exec_command,
299 .dev_select = ata_std_dev_select,
301 .phy_reset = mv_phy_reset,
303 .qc_prep = mv_qc_prep,
304 .qc_issue = mv_qc_issue,
306 .eng_timeout = mv_eng_timeout,
308 .irq_handler = mv_interrupt,
309 .irq_clear = mv_irq_clear,
311 .scr_read = mv_scr_read,
312 .scr_write = mv_scr_write,
314 .port_start = mv_port_start,
315 .port_stop = mv_port_stop,
316 .host_stop = mv_host_stop,
319 static struct ata_port_info mv_port_info[] = {
322 .host_flags = MV_COMMON_FLAGS,
323 .pio_mask = 0x1f, /* pio0-4 */
324 .udma_mask = 0, /* 0x7f (udma0-6 disabled for now) */
329 .host_flags = (MV_COMMON_FLAGS | MV_FLAG_DUAL_HC),
330 .pio_mask = 0x1f, /* pio0-4 */
331 .udma_mask = 0, /* 0x7f (udma0-6 disabled for now) */
336 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS),
337 .pio_mask = 0x1f, /* pio0-4 */
338 .udma_mask = 0x7f, /* udma0-6 */
343 .host_flags = (MV_COMMON_FLAGS | MV_6XXX_FLAGS |
345 .pio_mask = 0x1f, /* pio0-4 */
346 .udma_mask = 0x7f, /* udma0-6 */
351 static struct pci_device_id mv_pci_tbl[] = {
352 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5040), 0, 0, chip_504x},
353 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5041), 0, 0, chip_504x},
354 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5080), 0, 0, chip_508x},
355 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5081), 0, 0, chip_508x},
357 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6040), 0, 0, chip_604x},
358 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6041), 0, 0, chip_604x},
359 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6080), 0, 0, chip_608x},
360 {PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x6081), 0, 0, chip_608x},
361 {} /* terminate list */
364 static struct pci_driver mv_pci_driver = {
366 .id_table = mv_pci_tbl,
367 .probe = mv_init_one,
368 .remove = ata_pci_remove_one,
375 static inline void writelfl(unsigned long data, void __iomem *addr)
378 (void) readl(addr); /* flush to avoid PCI posted write */
381 static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
383 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
386 static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
388 return (mv_hc_base(base, port >> MV_PORT_HC_SHIFT) +
389 MV_SATAHC_ARBTR_REG_SZ +
390 ((port & MV_PORT_MASK) * MV_PORT_REG_SZ));
393 static inline void __iomem *mv_ap_base(struct ata_port *ap)
395 return mv_port_base(ap->host_set->mmio_base, ap->port_no);
398 static inline int mv_get_hc_count(unsigned long hp_flags)
400 return ((hp_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
403 static void mv_irq_clear(struct ata_port *ap)
408 * mv_start_dma - Enable eDMA engine
409 * @base: port base address
410 * @pp: port private data
412 * Verify the local cache of the eDMA state is accurate with an
416 * Inherited from caller.
418 static void mv_start_dma(void __iomem *base, struct mv_port_priv *pp)
420 if (!(MV_PP_FLAG_EDMA_EN & pp->pp_flags)) {
421 writelfl(EDMA_EN, base + EDMA_CMD_OFS);
422 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
424 assert(EDMA_EN & readl(base + EDMA_CMD_OFS));
428 * mv_stop_dma - Disable eDMA engine
429 * @ap: ATA channel to manipulate
431 * Verify the local cache of the eDMA state is accurate with an
435 * Inherited from caller.
437 static void mv_stop_dma(struct ata_port *ap)
439 void __iomem *port_mmio = mv_ap_base(ap);
440 struct mv_port_priv *pp = ap->private_data;
444 if (MV_PP_FLAG_EDMA_EN & pp->pp_flags) {
445 /* Disable EDMA if active. The disable bit auto clears.
447 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
448 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
450 assert(!(EDMA_EN & readl(port_mmio + EDMA_CMD_OFS)));
453 /* now properly wait for the eDMA to stop */
454 for (i = 1000; i > 0; i--) {
455 reg = readl(port_mmio + EDMA_CMD_OFS);
456 if (!(EDMA_EN & reg)) {
463 printk(KERN_ERR "ata%u: Unable to stop eDMA\n", ap->id);
464 /* FIXME: Consider doing a reset here to recover */
469 static void mv_dump_mem(void __iomem *start, unsigned bytes)
472 for (b = 0; b < bytes; ) {
473 DPRINTK("%p: ", start + b);
474 for (w = 0; b < bytes && w < 4; w++) {
475 printk("%08x ",readl(start + b));
483 static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
488 for (b = 0; b < bytes; ) {
489 DPRINTK("%02x: ", b);
490 for (w = 0; b < bytes && w < 4; w++) {
491 (void) pci_read_config_dword(pdev,b,&dw);
499 static void mv_dump_all_regs(void __iomem *mmio_base, int port,
500 struct pci_dev *pdev)
503 void __iomem *hc_base = mv_hc_base(mmio_base,
504 port >> MV_PORT_HC_SHIFT);
505 void __iomem *port_base;
506 int start_port, num_ports, p, start_hc, num_hcs, hc;
509 start_hc = start_port = 0;
510 num_ports = 8; /* shld be benign for 4 port devs */
513 start_hc = port >> MV_PORT_HC_SHIFT;
515 num_ports = num_hcs = 1;
517 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
518 num_ports > 1 ? num_ports - 1 : start_port);
521 DPRINTK("PCI config space regs:\n");
522 mv_dump_pci_cfg(pdev, 0x68);
524 DPRINTK("PCI regs:\n");
525 mv_dump_mem(mmio_base+0xc00, 0x3c);
526 mv_dump_mem(mmio_base+0xd00, 0x34);
527 mv_dump_mem(mmio_base+0xf00, 0x4);
528 mv_dump_mem(mmio_base+0x1d00, 0x6c);
529 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
530 hc_base = mv_hc_base(mmio_base, port >> MV_PORT_HC_SHIFT);
531 DPRINTK("HC regs (HC %i):\n", hc);
532 mv_dump_mem(hc_base, 0x1c);
534 for (p = start_port; p < start_port + num_ports; p++) {
535 port_base = mv_port_base(mmio_base, p);
536 DPRINTK("EDMA regs (port %i):\n",p);
537 mv_dump_mem(port_base, 0x54);
538 DPRINTK("SATA regs (port %i):\n",p);
539 mv_dump_mem(port_base+0x300, 0x60);
544 static unsigned int mv_scr_offset(unsigned int sc_reg_in)
552 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
555 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
564 static u32 mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in)
566 unsigned int ofs = mv_scr_offset(sc_reg_in);
568 if (0xffffffffU != ofs) {
569 return readl(mv_ap_base(ap) + ofs);
575 static void mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
577 unsigned int ofs = mv_scr_offset(sc_reg_in);
579 if (0xffffffffU != ofs) {
580 writelfl(val, mv_ap_base(ap) + ofs);
585 * mv_global_soft_reset - Perform the 6xxx global soft reset
586 * @mmio_base: base address of the HBA
588 * This routine only applies to 6xxx parts.
591 * Inherited from caller.
593 static int mv_global_soft_reset(void __iomem *mmio_base)
595 void __iomem *reg = mmio_base + PCI_MAIN_CMD_STS_OFS;
599 /* Following procedure defined in PCI "main command and status
603 writel(t | STOP_PCI_MASTER, reg);
605 for (i = 0; i < 1000; i++) {
608 if (PCI_MASTER_EMPTY & t) {
612 if (!(PCI_MASTER_EMPTY & t)) {
613 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
621 writel(t | GLOB_SFT_RST, reg);
624 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
626 if (!(GLOB_SFT_RST & t)) {
627 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
632 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
635 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
638 } while ((GLOB_SFT_RST & t) && (i-- > 0));
640 if (GLOB_SFT_RST & t) {
641 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
649 * mv_host_stop - Host specific cleanup/stop routine.
650 * @host_set: host data structure
652 * Disable ints, cleanup host memory, call general purpose
656 * Inherited from caller.
658 static void mv_host_stop(struct ata_host_set *host_set)
660 struct mv_host_priv *hpriv = host_set->private_data;
661 struct pci_dev *pdev = to_pci_dev(host_set->dev);
663 if (hpriv->hp_flags & MV_HP_FLAG_MSI) {
664 pci_disable_msi(pdev);
669 ata_host_stop(host_set);
673 * mv_port_start - Port specific init/start routine.
674 * @ap: ATA channel to manipulate
676 * Allocate and point to DMA memory, init port private memory,
680 * Inherited from caller.
682 static int mv_port_start(struct ata_port *ap)
684 struct device *dev = ap->host_set->dev;
685 struct mv_port_priv *pp;
686 void __iomem *port_mmio = mv_ap_base(ap);
690 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
694 memset(pp, 0, sizeof(*pp));
696 mem = dma_alloc_coherent(dev, MV_PORT_PRIV_DMA_SZ, &mem_dma,
702 memset(mem, 0, MV_PORT_PRIV_DMA_SZ);
704 /* First item in chunk of DMA memory:
705 * 32-slot command request table (CRQB), 32 bytes each in size
708 pp->crqb_dma = mem_dma;
710 mem_dma += MV_CRQB_Q_SZ;
713 * 32-slot command response table (CRPB), 8 bytes each in size
716 pp->crpb_dma = mem_dma;
718 mem_dma += MV_CRPB_Q_SZ;
721 * Table of scatter-gather descriptors (ePRD), 16 bytes each
724 pp->sg_tbl_dma = mem_dma;
726 writelfl(EDMA_CFG_Q_DEPTH | EDMA_CFG_RD_BRST_EXT |
727 EDMA_CFG_WR_BUFF_LEN, port_mmio + EDMA_CFG_OFS);
729 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
730 writelfl(pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK,
731 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
733 writelfl(0, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
734 writelfl(0, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
736 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
737 writelfl(pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK,
738 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
740 pp->req_producer = pp->rsp_consumer = 0;
742 /* Don't turn on EDMA here...do it before DMA commands only. Else
743 * we'll be unable to send non-data, PIO, etc due to restricted access
746 ap->private_data = pp;
751 * mv_port_stop - Port specific cleanup/stop routine.
752 * @ap: ATA channel to manipulate
754 * Stop DMA, cleanup port memory.
757 * This routine uses the host_set lock to protect the DMA stop.
759 static void mv_port_stop(struct ata_port *ap)
761 struct device *dev = ap->host_set->dev;
762 struct mv_port_priv *pp = ap->private_data;
765 spin_lock_irqsave(&ap->host_set->lock, flags);
767 spin_unlock_irqrestore(&ap->host_set->lock, flags);
769 ap->private_data = NULL;
770 dma_free_coherent(dev, MV_PORT_PRIV_DMA_SZ, pp->crpb, pp->crpb_dma);
775 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
776 * @qc: queued command whose SG list to source from
778 * Populate the SG list and mark the last entry.
781 * Inherited from caller.
783 static void mv_fill_sg(struct ata_queued_cmd *qc)
785 struct mv_port_priv *pp = qc->ap->private_data;
788 for (i = 0; i < qc->n_elem; i++) {
792 addr = sg_dma_address(&qc->sg[i]);
793 sg_len = sg_dma_len(&qc->sg[i]);
795 pp->sg_tbl[i].addr = cpu_to_le32(addr & 0xffffffff);
796 pp->sg_tbl[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
797 assert(0 == (sg_len & ~MV_DMA_BOUNDARY));
798 pp->sg_tbl[i].flags_size = cpu_to_le32(sg_len);
800 if (0 < qc->n_elem) {
801 pp->sg_tbl[qc->n_elem - 1].flags_size |=
802 cpu_to_le32(EPRD_FLAG_END_OF_TBL);
806 static inline unsigned mv_inc_q_index(unsigned *index)
808 *index = (*index + 1) & MV_MAX_Q_DEPTH_MASK;
812 static inline void mv_crqb_pack_cmd(u16 *cmdw, u8 data, u8 addr, unsigned last)
814 *cmdw = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
815 (last ? CRQB_CMD_LAST : 0);
819 * mv_qc_prep - Host specific command preparation.
820 * @qc: queued command to prepare
822 * This routine simply redirects to the general purpose routine
823 * if command is not DMA. Else, it handles prep of the CRQB
824 * (command request block), does some sanity checking, and calls
825 * the SG load routine.
828 * Inherited from caller.
830 static void mv_qc_prep(struct ata_queued_cmd *qc)
832 struct ata_port *ap = qc->ap;
833 struct mv_port_priv *pp = ap->private_data;
835 struct ata_taskfile *tf;
838 if (ATA_PROT_DMA != qc->tf.protocol) {
842 /* the req producer index should be the same as we remember it */
843 assert(((readl(mv_ap_base(qc->ap) + EDMA_REQ_Q_IN_PTR_OFS) >>
844 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
847 /* Fill in command request block
849 if (!(qc->tf.flags & ATA_TFLAG_WRITE)) {
850 flags |= CRQB_FLAG_READ;
852 assert(MV_MAX_Q_DEPTH > qc->tag);
853 flags |= qc->tag << CRQB_TAG_SHIFT;
855 pp->crqb[pp->req_producer].sg_addr =
856 cpu_to_le32(pp->sg_tbl_dma & 0xffffffff);
857 pp->crqb[pp->req_producer].sg_addr_hi =
858 cpu_to_le32((pp->sg_tbl_dma >> 16) >> 16);
859 pp->crqb[pp->req_producer].ctrl_flags = cpu_to_le16(flags);
861 cw = &pp->crqb[pp->req_producer].ata_cmd[0];
864 /* Sadly, the CRQB cannot accomodate all registers--there are
865 * only 11 bytes...so we must pick and choose required
866 * registers based on the command. So, we drop feature and
867 * hob_feature for [RW] DMA commands, but they are needed for
868 * NCQ. NCQ will drop hob_nsect.
870 switch (tf->command) {
872 case ATA_CMD_READ_EXT:
874 case ATA_CMD_WRITE_EXT:
875 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
877 #ifdef LIBATA_NCQ /* FIXME: remove this line when NCQ added */
878 case ATA_CMD_FPDMA_READ:
879 case ATA_CMD_FPDMA_WRITE:
880 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
881 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
883 #endif /* FIXME: remove this line when NCQ added */
885 /* The only other commands EDMA supports in non-queued and
886 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
887 * of which are defined/used by Linux. If we get here, this
890 * FIXME: modify libata to give qc_prep a return value and
896 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
897 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
898 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
899 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
900 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
901 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
902 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
903 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
904 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
906 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) {
913 * mv_qc_issue - Initiate a command to the host
914 * @qc: queued command to start
916 * This routine simply redirects to the general purpose routine
917 * if command is not DMA. Else, it sanity checks our local
918 * caches of the request producer/consumer indices then enables
919 * DMA and bumps the request producer index.
922 * Inherited from caller.
924 static int mv_qc_issue(struct ata_queued_cmd *qc)
926 void __iomem *port_mmio = mv_ap_base(qc->ap);
927 struct mv_port_priv *pp = qc->ap->private_data;
930 if (ATA_PROT_DMA != qc->tf.protocol) {
931 /* We're about to send a non-EDMA capable command to the
932 * port. Turn off EDMA so there won't be problems accessing
933 * shadow block, etc registers.
936 return ata_qc_issue_prot(qc);
939 in_ptr = readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
941 /* the req producer index should be the same as we remember it */
942 assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
944 /* until we do queuing, the queue should be empty at this point */
945 assert(((in_ptr >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
946 ((readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS) >>
947 EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK));
949 mv_inc_q_index(&pp->req_producer); /* now incr producer index */
951 mv_start_dma(port_mmio, pp);
953 /* and write the request in pointer to kick the EDMA to life */
954 in_ptr &= EDMA_REQ_Q_BASE_LO_MASK;
955 in_ptr |= pp->req_producer << EDMA_REQ_Q_PTR_SHIFT;
956 writelfl(in_ptr, port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
962 * mv_get_crpb_status - get status from most recently completed cmd
963 * @ap: ATA channel to manipulate
965 * This routine is for use when the port is in DMA mode, when it
966 * will be using the CRPB (command response block) method of
967 * returning command completion information. We assert indices
968 * are good, grab status, and bump the response consumer index to
969 * prove that we're up to date.
972 * Inherited from caller.
974 static u8 mv_get_crpb_status(struct ata_port *ap)
976 void __iomem *port_mmio = mv_ap_base(ap);
977 struct mv_port_priv *pp = ap->private_data;
980 out_ptr = readl(port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
982 /* the response consumer index should be the same as we remember it */
983 assert(((out_ptr >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
986 /* increment our consumer index... */
987 pp->rsp_consumer = mv_inc_q_index(&pp->rsp_consumer);
989 /* and, until we do NCQ, there should only be 1 CRPB waiting */
990 assert(((readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS) >>
991 EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK) ==
994 /* write out our inc'd consumer index so EDMA knows we're caught up */
995 out_ptr &= EDMA_RSP_Q_BASE_LO_MASK;
996 out_ptr |= pp->rsp_consumer << EDMA_RSP_Q_PTR_SHIFT;
997 writelfl(out_ptr, port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
999 /* Return ATA status register for completed CRPB */
1000 return (pp->crpb[pp->rsp_consumer].flags >> CRPB_FLAG_STATUS_SHIFT);
1004 * mv_err_intr - Handle error interrupts on the port
1005 * @ap: ATA channel to manipulate
1007 * In most cases, just clear the interrupt and move on. However,
1008 * some cases require an eDMA reset, which is done right before
1009 * the COMRESET in mv_phy_reset(). The SERR case requires a
1010 * clear of pending errors in the SATA SERROR register. Finally,
1011 * if the port disabled DMA, update our cached copy to match.
1014 * Inherited from caller.
1016 static void mv_err_intr(struct ata_port *ap)
1018 void __iomem *port_mmio = mv_ap_base(ap);
1019 u32 edma_err_cause, serr = 0;
1021 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1023 if (EDMA_ERR_SERR & edma_err_cause) {
1024 serr = scr_read(ap, SCR_ERROR);
1025 scr_write_flush(ap, SCR_ERROR, serr);
1027 if (EDMA_ERR_SELF_DIS & edma_err_cause) {
1028 struct mv_port_priv *pp = ap->private_data;
1029 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
1031 DPRINTK(KERN_ERR "ata%u: port error; EDMA err cause: 0x%08x "
1032 "SERR: 0x%08x\n", ap->id, edma_err_cause, serr);
1034 /* Clear EDMA now that SERR cleanup done */
1035 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1037 /* check for fatal here and recover if needed */
1038 if (EDMA_ERR_FATAL & edma_err_cause) {
1044 * mv_host_intr - Handle all interrupts on the given host controller
1045 * @host_set: host specific structure
1046 * @relevant: port error bits relevant to this host controller
1047 * @hc: which host controller we're to look at
1049 * Read then write clear the HC interrupt status then walk each
1050 * port connected to the HC and see if it needs servicing. Port
1051 * success ints are reported in the HC interrupt status reg, the
1052 * port error ints are reported in the higher level main
1053 * interrupt status register and thus are passed in via the
1054 * 'relevant' argument.
1057 * Inherited from caller.
1059 static void mv_host_intr(struct ata_host_set *host_set, u32 relevant,
1062 void __iomem *mmio = host_set->mmio_base;
1063 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1064 struct ata_port *ap;
1065 struct ata_queued_cmd *qc;
1067 int shift, port, port0, hard_port, handled;
1073 port0 = MV_PORTS_PER_HC;
1076 /* we'll need the HC success int register in most cases */
1077 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1079 writelfl(~hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
1082 VPRINTK("ENTER, hc%u relevant=0x%08x HC IRQ cause=0x%08x\n",
1083 hc,relevant,hc_irq_cause);
1085 for (port = port0; port < port0 + MV_PORTS_PER_HC; port++) {
1086 ap = host_set->ports[port];
1087 hard_port = port & MV_PORT_MASK; /* range 0-3 */
1088 handled = 0; /* ensure ata_status is set if handled++ */
1090 if ((CRPB_DMA_DONE << hard_port) & hc_irq_cause) {
1091 /* new CRPB on the queue; just one at a time until NCQ
1093 ata_status = mv_get_crpb_status(ap);
1095 } else if ((DEV_IRQ << hard_port) & hc_irq_cause) {
1096 /* received ATA IRQ; read the status reg to clear INTRQ
1098 ata_status = readb((void __iomem *)
1099 ap->ioaddr.status_addr);
1103 shift = port << 1; /* (port * 2) */
1104 if (port >= MV_PORTS_PER_HC) {
1105 shift++; /* skip bit 8 in the HC Main IRQ reg */
1107 if ((PORT0_ERR << shift) & relevant) {
1109 /* OR in ATA_ERR to ensure libata knows we took one */
1110 ata_status = readb((void __iomem *)
1111 ap->ioaddr.status_addr) | ATA_ERR;
1115 if (handled && ap) {
1116 qc = ata_qc_from_tag(ap, ap->active_tag);
1118 VPRINTK("port %u IRQ found for qc, "
1119 "ata_status 0x%x\n", port,ata_status);
1120 /* mark qc status appropriately */
1121 ata_qc_complete(qc, ata_status);
1131 * @dev_instance: private data; in this case the host structure
1134 * Read the read only register to determine if any host
1135 * controllers have pending interrupts. If so, call lower level
1136 * routine to handle. Also check for PCI errors which are only
1140 * This routine holds the host_set lock while processing pending
1143 static irqreturn_t mv_interrupt(int irq, void *dev_instance,
1144 struct pt_regs *regs)
1146 struct ata_host_set *host_set = dev_instance;
1147 unsigned int hc, handled = 0, n_hcs;
1148 void __iomem *mmio = host_set->mmio_base;
1151 irq_stat = readl(mmio + HC_MAIN_IRQ_CAUSE_OFS);
1153 /* check the cases where we either have nothing pending or have read
1154 * a bogus register value which can indicate HW removal or PCI fault
1156 if (!irq_stat || (0xffffffffU == irq_stat)) {
1160 n_hcs = mv_get_hc_count(host_set->ports[0]->flags);
1161 spin_lock(&host_set->lock);
1163 for (hc = 0; hc < n_hcs; hc++) {
1164 u32 relevant = irq_stat & (HC0_IRQ_PEND << (hc * HC_SHIFT));
1166 mv_host_intr(host_set, relevant, hc);
1170 if (PCI_ERR & irq_stat) {
1171 printk(KERN_ERR DRV_NAME ": PCI ERROR; PCI IRQ cause=0x%08x\n",
1172 readl(mmio + PCI_IRQ_CAUSE_OFS));
1174 DPRINTK("All regs @ PCI error\n");
1175 mv_dump_all_regs(mmio, -1, to_pci_dev(host_set->dev));
1177 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1180 spin_unlock(&host_set->lock);
1182 return IRQ_RETVAL(handled);
1186 * mv_phy_reset - Perform eDMA reset followed by COMRESET
1187 * @ap: ATA channel to manipulate
1189 * Part of this is taken from __sata_phy_reset and modified to
1190 * not sleep since this routine gets called from interrupt level.
1193 * Inherited from caller. This is coded to safe to call at
1194 * interrupt level, i.e. it does not sleep.
1196 static void mv_phy_reset(struct ata_port *ap)
1198 void __iomem *port_mmio = mv_ap_base(ap);
1199 struct ata_taskfile tf;
1200 struct ata_device *dev = &ap->device[0];
1201 unsigned long timeout;
1203 VPRINTK("ENTER, port %u, mmio 0x%p\n", ap->port_no, port_mmio);
1207 writelfl(ATA_RST, port_mmio + EDMA_CMD_OFS);
1208 udelay(25); /* allow reset propagation */
1210 /* Spec never mentions clearing the bit. Marvell's driver does
1211 * clear the bit, however.
1213 writelfl(0, port_mmio + EDMA_CMD_OFS);
1215 VPRINTK("S-regs after ATA_RST: SStat 0x%08x SErr 0x%08x "
1216 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1217 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1219 /* proceed to init communications via the scr_control reg */
1220 scr_write_flush(ap, SCR_CONTROL, 0x301);
1222 scr_write_flush(ap, SCR_CONTROL, 0x300);
1223 timeout = jiffies + (HZ * 1);
1226 if ((scr_read(ap, SCR_STATUS) & 0xf) != 1)
1228 } while (time_before(jiffies, timeout));
1230 VPRINTK("S-regs after PHY wake: SStat 0x%08x SErr 0x%08x "
1231 "SCtrl 0x%08x\n", mv_scr_read(ap, SCR_STATUS),
1232 mv_scr_read(ap, SCR_ERROR), mv_scr_read(ap, SCR_CONTROL));
1234 if (sata_dev_present(ap)) {
1237 printk(KERN_INFO "ata%u: no device found (phy stat %08x)\n",
1238 ap->id, scr_read(ap, SCR_STATUS));
1239 ata_port_disable(ap);
1242 ap->cbl = ATA_CBL_SATA;
1244 tf.lbah = readb((void __iomem *) ap->ioaddr.lbah_addr);
1245 tf.lbam = readb((void __iomem *) ap->ioaddr.lbam_addr);
1246 tf.lbal = readb((void __iomem *) ap->ioaddr.lbal_addr);
1247 tf.nsect = readb((void __iomem *) ap->ioaddr.nsect_addr);
1249 dev->class = ata_dev_classify(&tf);
1250 if (!ata_dev_present(dev)) {
1251 VPRINTK("Port disabled post-sig: No device present.\n");
1252 ata_port_disable(ap);
1258 * mv_eng_timeout - Routine called by libata when SCSI times out I/O
1259 * @ap: ATA channel to manipulate
1261 * Intent is to clear all pending error conditions, reset the
1262 * chip/bus, fail the command, and move on.
1265 * This routine holds the host_set lock while failing the command.
1267 static void mv_eng_timeout(struct ata_port *ap)
1269 struct ata_queued_cmd *qc;
1270 unsigned long flags;
1272 printk(KERN_ERR "ata%u: Entering mv_eng_timeout\n",ap->id);
1273 DPRINTK("All regs @ start of eng_timeout\n");
1274 mv_dump_all_regs(ap->host_set->mmio_base, ap->port_no,
1275 to_pci_dev(ap->host_set->dev));
1277 qc = ata_qc_from_tag(ap, ap->active_tag);
1278 printk(KERN_ERR "mmio_base %p ap %p qc %p scsi_cmnd %p &cmnd %p\n",
1279 ap->host_set->mmio_base, ap, qc, qc->scsicmd,
1280 &qc->scsicmd->cmnd);
1286 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
1289 /* hack alert! We cannot use the supplied completion
1290 * function from inside the ->eh_strategy_handler() thread.
1291 * libata is the only user of ->eh_strategy_handler() in
1292 * any kernel, so the default scsi_done() assumes it is
1293 * not being called from the SCSI EH.
1295 spin_lock_irqsave(&ap->host_set->lock, flags);
1296 qc->scsidone = scsi_finish_command;
1297 ata_qc_complete(qc, ATA_ERR);
1298 spin_unlock_irqrestore(&ap->host_set->lock, flags);
1303 * mv_port_init - Perform some early initialization on a single port.
1304 * @port: libata data structure storing shadow register addresses
1305 * @port_mmio: base address of the port
1307 * Initialize shadow register mmio addresses, clear outstanding
1308 * interrupts on the port, and unmask interrupts for the future
1309 * start of the port.
1312 * Inherited from caller.
1314 static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
1316 unsigned long shd_base = (unsigned long) port_mmio + SHD_BLK_OFS;
1319 /* PIO related setup
1321 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
1323 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
1324 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
1325 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
1326 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
1327 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
1328 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
1330 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
1331 /* special case: control/altstatus doesn't have ATA_REG_ address */
1332 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
1335 port->cmd_addr = port->bmdma_addr = port->scr_addr = 0;
1337 /* Clear any currently outstanding port interrupt conditions */
1338 serr_ofs = mv_scr_offset(SCR_ERROR);
1339 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
1340 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1342 /* unmask all EDMA error interrupts */
1343 writelfl(~0, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
1345 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
1346 readl(port_mmio + EDMA_CFG_OFS),
1347 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
1348 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
1352 * mv_host_init - Perform some early initialization of the host.
1353 * @probe_ent: early data struct representing the host
1355 * If possible, do an early global reset of the host. Then do
1356 * our port init and clear/unmask all/relevant host interrupts.
1359 * Inherited from caller.
1361 static int mv_host_init(struct ata_probe_ent *probe_ent)
1363 int rc = 0, n_hc, port, hc;
1364 void __iomem *mmio = probe_ent->mmio_base;
1365 void __iomem *port_mmio;
1367 if ((MV_FLAG_GLBL_SFT_RST & probe_ent->host_flags) &&
1368 mv_global_soft_reset(probe_ent->mmio_base)) {
1373 n_hc = mv_get_hc_count(probe_ent->host_flags);
1374 probe_ent->n_ports = MV_PORTS_PER_HC * n_hc;
1376 for (port = 0; port < probe_ent->n_ports; port++) {
1377 port_mmio = mv_port_base(mmio, port);
1378 mv_port_init(&probe_ent->port[port], port_mmio);
1381 for (hc = 0; hc < n_hc; hc++) {
1382 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
1384 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
1385 "(before clear)=0x%08x\n", hc,
1386 readl(hc_mmio + HC_CFG_OFS),
1387 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
1389 /* Clear any currently outstanding hc interrupt conditions */
1390 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
1393 /* Clear any currently outstanding host interrupt conditions */
1394 writelfl(0, mmio + PCI_IRQ_CAUSE_OFS);
1396 /* and unmask interrupt generation for host regs */
1397 writelfl(PCI_UNMASK_ALL_IRQS, mmio + PCI_IRQ_MASK_OFS);
1398 writelfl(~HC_MAIN_MASKED_IRQS, mmio + HC_MAIN_IRQ_MASK_OFS);
1400 VPRINTK("HC MAIN IRQ cause/mask=0x%08x/0x%08x "
1401 "PCI int cause/mask=0x%08x/0x%08x\n",
1402 readl(mmio + HC_MAIN_IRQ_CAUSE_OFS),
1403 readl(mmio + HC_MAIN_IRQ_MASK_OFS),
1404 readl(mmio + PCI_IRQ_CAUSE_OFS),
1405 readl(mmio + PCI_IRQ_MASK_OFS));
1411 * mv_print_info - Dump key info to kernel log for perusal.
1412 * @probe_ent: early data struct representing the host
1414 * FIXME: complete this.
1417 * Inherited from caller.
1419 static void mv_print_info(struct ata_probe_ent *probe_ent)
1421 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1422 struct mv_host_priv *hpriv = probe_ent->private_data;
1426 /* Use this to determine the HW stepping of the chip so we know
1427 * what errata to workaround
1429 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
1431 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
1434 else if (scc == 0x01)
1439 printk(KERN_INFO DRV_NAME
1440 "(%s) %u slots %u ports %s mode IRQ via %s\n",
1441 pci_name(pdev), (unsigned)MV_MAX_Q_DEPTH, probe_ent->n_ports,
1442 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
1446 * mv_init_one - handle a positive probe of a Marvell host
1447 * @pdev: PCI device found
1448 * @ent: PCI device ID entry for the matched host
1451 * Inherited from caller.
1453 static int mv_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1455 static int printed_version = 0;
1456 struct ata_probe_ent *probe_ent = NULL;
1457 struct mv_host_priv *hpriv;
1458 unsigned int board_idx = (unsigned int)ent->driver_data;
1459 void __iomem *mmio_base;
1460 int pci_dev_busy = 0, rc;
1462 if (!printed_version++) {
1463 printk(KERN_INFO DRV_NAME " version " DRV_VERSION "\n");
1466 rc = pci_enable_device(pdev);
1471 rc = pci_request_regions(pdev, DRV_NAME);
1477 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1478 if (probe_ent == NULL) {
1480 goto err_out_regions;
1483 memset(probe_ent, 0, sizeof(*probe_ent));
1484 probe_ent->dev = pci_dev_to_dev(pdev);
1485 INIT_LIST_HEAD(&probe_ent->node);
1487 mmio_base = pci_iomap(pdev, MV_PRIMARY_BAR, 0);
1488 if (mmio_base == NULL) {
1490 goto err_out_free_ent;
1493 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1496 goto err_out_iounmap;
1498 memset(hpriv, 0, sizeof(*hpriv));
1500 probe_ent->sht = mv_port_info[board_idx].sht;
1501 probe_ent->host_flags = mv_port_info[board_idx].host_flags;
1502 probe_ent->pio_mask = mv_port_info[board_idx].pio_mask;
1503 probe_ent->udma_mask = mv_port_info[board_idx].udma_mask;
1504 probe_ent->port_ops = mv_port_info[board_idx].port_ops;
1506 probe_ent->irq = pdev->irq;
1507 probe_ent->irq_flags = SA_SHIRQ;
1508 probe_ent->mmio_base = mmio_base;
1509 probe_ent->private_data = hpriv;
1511 /* initialize adapter */
1512 rc = mv_host_init(probe_ent);
1517 /* Enable interrupts */
1518 if (pci_enable_msi(pdev) == 0) {
1519 hpriv->hp_flags |= MV_HP_FLAG_MSI;
1524 mv_dump_pci_cfg(pdev, 0x68);
1525 mv_print_info(probe_ent);
1527 if (ata_device_add(probe_ent) == 0) {
1528 rc = -ENODEV; /* No devices discovered */
1529 goto err_out_dev_add;
1536 if (MV_HP_FLAG_MSI & hpriv->hp_flags) {
1537 pci_disable_msi(pdev);
1544 pci_iounmap(pdev, mmio_base);
1548 pci_release_regions(pdev);
1550 if (!pci_dev_busy) {
1551 pci_disable_device(pdev);
1557 static int __init mv_init(void)
1559 return pci_module_init(&mv_pci_driver);
1562 static void __exit mv_exit(void)
1564 pci_unregister_driver(&mv_pci_driver);
1567 MODULE_AUTHOR("Brett Russ");
1568 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
1569 MODULE_LICENSE("GPL");
1570 MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
1571 MODULE_VERSION(DRV_VERSION);
1573 module_init(mv_init);
1574 module_exit(mv_exit);