err.no Git - linux-2.6/blob - drivers/scsi/qla2xxx/qla_sup.c

   1 /*
   2  * QLogic Fibre Channel HBA Driver
   3  * Copyright (c)  2003-2008 QLogic Corporation
   4  *
   5  * See LICENSE.qla2xxx for copyright and licensing details.
   6  */
   7 #include "qla_def.h"
   8
   9 #include <linux/delay.h>
  10 #include <linux/vmalloc.h>
  11 #include <asm/uaccess.h>
  12
  13 static uint16_t qla2x00_nvram_request(scsi_qla_host_t *, uint32_t);
  14 static void qla2x00_nv_deselect(scsi_qla_host_t *);
  15 static void qla2x00_nv_write(scsi_qla_host_t *, uint16_t);
  16
  17 /*
  18  * NVRAM support routines
  19  */
  20
  21 /**
  22  * qla2x00_lock_nvram_access() -
  23  * @ha: HA context
  24  */
  25 static void
  26 qla2x00_lock_nvram_access(scsi_qla_host_t *ha)
  27 {
  28         uint16_t data;
  29         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  30
  31         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  32                 data = RD_REG_WORD(&reg->nvram);
  33                 while (data & NVR_BUSY) {
  34                         udelay(100);
  35                         data = RD_REG_WORD(&reg->nvram);
  36                 }
  37
  38                 /* Lock resource */
  39                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  40                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  41                 udelay(5);
  42                 data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  43                 while ((data & BIT_0) == 0) {
  44                         /* Lock failed */
  45                         udelay(100);
  46                         WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0x1);
  47                         RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  48                         udelay(5);
  49                         data = RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  50                 }
  51         }
  52 }
  53
  54 /**
  55  * qla2x00_unlock_nvram_access() -
  56  * @ha: HA context
  57  */
  58 static void
  59 qla2x00_unlock_nvram_access(scsi_qla_host_t *ha)
  60 {
  61         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
  62
  63         if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
  64                 WRT_REG_WORD(&reg->u.isp2300.host_semaphore, 0);
  65                 RD_REG_WORD(&reg->u.isp2300.host_semaphore);
  66         }
  67 }
  68
  69 /**
  70  * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
  71  *      request routine to get the word from NVRAM.
  72  * @ha: HA context
  73  * @addr: Address in NVRAM to read
  74  *
  75  * Returns the word read from nvram @addr.
  76  */
  77 static uint16_t
  78 qla2x00_get_nvram_word(scsi_qla_host_t *ha, uint32_t addr)
  79 {
  80         uint16_t        data;
  81         uint32_t        nv_cmd;
  82
  83         nv_cmd = addr << 16;
  84         nv_cmd |= NV_READ_OP;
  85         data = qla2x00_nvram_request(ha, nv_cmd);
  86
  87         return (data);
  88 }
  89
  90 /**
  91  * qla2x00_write_nvram_word() - Write NVRAM data.
  92  * @ha: HA context
  93  * @addr: Address in NVRAM to write
  94  * @data: word to program
  95  */
  96 static void
  97 qla2x00_write_nvram_word(scsi_qla_host_t *ha, uint32_t addr, uint16_t data)
  98 {
  99         int count;
 100         uint16_t word;
 101         uint32_t nv_cmd, wait_cnt;
 102         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 103
 104         qla2x00_nv_write(ha, NVR_DATA_OUT);
 105         qla2x00_nv_write(ha, 0);
 106         qla2x00_nv_write(ha, 0);
 107
 108         for (word = 0; word < 8; word++)
 109                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 110
 111         qla2x00_nv_deselect(ha);
 112
 113         /* Write data */
 114         nv_cmd = (addr << 16) | NV_WRITE_OP;
 115         nv_cmd |= data;
 116         nv_cmd <<= 5;
 117         for (count = 0; count < 27; count++) {
 118                 if (nv_cmd & BIT_31)
 119                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 120                 else
 121                         qla2x00_nv_write(ha, 0);
 122
 123                 nv_cmd <<= 1;
 124         }
 125
 126         qla2x00_nv_deselect(ha);
 127
 128         /* Wait for NVRAM to become ready */
 129         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 130         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 131         wait_cnt = NVR_WAIT_CNT;
 132         do {
 133                 if (!--wait_cnt) {
 134                         DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
 135                             __func__, ha->host_no));
 136                         break;
 137                 }
 138                 NVRAM_DELAY();
 139                 word = RD_REG_WORD(&reg->nvram);
 140         } while ((word & NVR_DATA_IN) == 0);
 141
 142         qla2x00_nv_deselect(ha);
 143
 144         /* Disable writes */
 145         qla2x00_nv_write(ha, NVR_DATA_OUT);
 146         for (count = 0; count < 10; count++)
 147                 qla2x00_nv_write(ha, 0);
 148
 149         qla2x00_nv_deselect(ha);
 150 }
 151
 152 static int
 153 qla2x00_write_nvram_word_tmo(scsi_qla_host_t *ha, uint32_t addr, uint16_t data,
 154     uint32_t tmo)
 155 {
 156         int ret, count;
 157         uint16_t word;
 158         uint32_t nv_cmd;
 159         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 160
 161         ret = QLA_SUCCESS;
 162
 163         qla2x00_nv_write(ha, NVR_DATA_OUT);
 164         qla2x00_nv_write(ha, 0);
 165         qla2x00_nv_write(ha, 0);
 166
 167         for (word = 0; word < 8; word++)
 168                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 169
 170         qla2x00_nv_deselect(ha);
 171
 172         /* Write data */
 173         nv_cmd = (addr << 16) | NV_WRITE_OP;
 174         nv_cmd |= data;
 175         nv_cmd <<= 5;
 176         for (count = 0; count < 27; count++) {
 177                 if (nv_cmd & BIT_31)
 178                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 179                 else
 180                         qla2x00_nv_write(ha, 0);
 181
 182                 nv_cmd <<= 1;
 183         }
 184
 185         qla2x00_nv_deselect(ha);
 186
 187         /* Wait for NVRAM to become ready */
 188         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 189         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 190         do {
 191                 NVRAM_DELAY();
 192                 word = RD_REG_WORD(&reg->nvram);
 193                 if (!--tmo) {
 194                         ret = QLA_FUNCTION_FAILED;
 195                         break;
 196                 }
 197         } while ((word & NVR_DATA_IN) == 0);
 198
 199         qla2x00_nv_deselect(ha);
 200
 201         /* Disable writes */
 202         qla2x00_nv_write(ha, NVR_DATA_OUT);
 203         for (count = 0; count < 10; count++)
 204                 qla2x00_nv_write(ha, 0);
 205
 206         qla2x00_nv_deselect(ha);
 207
 208         return ret;
 209 }
 210
 211 /**
 212  * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
 213  *      NVRAM.
 214  * @ha: HA context
 215  * @nv_cmd: NVRAM command
 216  *
 217  * Bit definitions for NVRAM command:
 218  *
 219  *      Bit 26     = start bit
 220  *      Bit 25, 24 = opcode
 221  *      Bit 23-16  = address
 222  *      Bit 15-0   = write data
 223  *
 224  * Returns the word read from nvram @addr.
 225  */
 226 static uint16_t
 227 qla2x00_nvram_request(scsi_qla_host_t *ha, uint32_t nv_cmd)
 228 {
 229         uint8_t         cnt;
 230         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 231         uint16_t        data = 0;
 232         uint16_t        reg_data;
 233
 234         /* Send command to NVRAM. */
 235         nv_cmd <<= 5;
 236         for (cnt = 0; cnt < 11; cnt++) {
 237                 if (nv_cmd & BIT_31)
 238                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 239                 else
 240                         qla2x00_nv_write(ha, 0);
 241                 nv_cmd <<= 1;
 242         }
 243
 244         /* Read data from NVRAM. */
 245         for (cnt = 0; cnt < 16; cnt++) {
 246                 WRT_REG_WORD(&reg->nvram, NVR_SELECT | NVR_CLOCK);
 247                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 248                 NVRAM_DELAY();
 249                 data <<= 1;
 250                 reg_data = RD_REG_WORD(&reg->nvram);
 251                 if (reg_data & NVR_DATA_IN)
 252                         data |= BIT_0;
 253                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 254                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 255                 NVRAM_DELAY();
 256         }
 257
 258         /* Deselect chip. */
 259         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
 260         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 261         NVRAM_DELAY();
 262
 263         return (data);
 264 }
 265
 266 /**
 267  * qla2x00_nv_write() - Clean NVRAM operations.
 268  * @ha: HA context
 269  */
 270 static void
 271 qla2x00_nv_deselect(scsi_qla_host_t *ha)
 272 {
 273         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 274
 275         WRT_REG_WORD(&reg->nvram, NVR_DESELECT);
 276         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 277         NVRAM_DELAY();
 278 }
 279
 280 /**
 281  * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
 282  * @ha: HA context
 283  * @data: Serial interface selector
 284  */
 285 static void
 286 qla2x00_nv_write(scsi_qla_host_t *ha, uint16_t data)
 287 {
 288         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 289
 290         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
 291         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 292         NVRAM_DELAY();
 293         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT| NVR_CLOCK |
 294             NVR_WRT_ENABLE);
 295         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 296         NVRAM_DELAY();
 297         WRT_REG_WORD(&reg->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
 298         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 299         NVRAM_DELAY();
 300 }
 301
 302 /**
 303  * qla2x00_clear_nvram_protection() -
 304  * @ha: HA context
 305  */
 306 static int
 307 qla2x00_clear_nvram_protection(scsi_qla_host_t *ha)
 308 {
 309         int ret, stat;
 310         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 311         uint32_t word, wait_cnt;
 312         uint16_t wprot, wprot_old;
 313
 314         /* Clear NVRAM write protection. */
 315         ret = QLA_FUNCTION_FAILED;
 316
 317         wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
 318         stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base,
 319             __constant_cpu_to_le16(0x1234), 100000);
 320         wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base));
 321         if (stat != QLA_SUCCESS || wprot != 0x1234) {
 322                 /* Write enable. */
 323                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 324                 qla2x00_nv_write(ha, 0);
 325                 qla2x00_nv_write(ha, 0);
 326                 for (word = 0; word < 8; word++)
 327                         qla2x00_nv_write(ha, NVR_DATA_OUT);
 328
 329                 qla2x00_nv_deselect(ha);
 330
 331                 /* Enable protection register. */
 332                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 333                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 334                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 335                 for (word = 0; word < 8; word++)
 336                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 337
 338                 qla2x00_nv_deselect(ha);
 339
 340                 /* Clear protection register (ffff is cleared). */
 341                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 342                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 343                 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 344                 for (word = 0; word < 8; word++)
 345                         qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 346
 347                 qla2x00_nv_deselect(ha);
 348
 349                 /* Wait for NVRAM to become ready. */
 350                 WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 351                 RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
 352                 wait_cnt = NVR_WAIT_CNT;
 353                 do {
 354                         if (!--wait_cnt) {
 355                                 DEBUG9_10(printk("%s(%ld): NVRAM didn't go "
 356                                     "ready...\n", __func__,
 357                                     ha->host_no));
 358                                 break;
 359                         }
 360                         NVRAM_DELAY();
 361                         word = RD_REG_WORD(&reg->nvram);
 362                 } while ((word & NVR_DATA_IN) == 0);
 363
 364                 if (wait_cnt)
 365                         ret = QLA_SUCCESS;
 366         } else
 367                 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old);
 368
 369         return ret;
 370 }
 371
 372 static void
 373 qla2x00_set_nvram_protection(scsi_qla_host_t *ha, int stat)
 374 {
 375         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 376         uint32_t word, wait_cnt;
 377
 378         if (stat != QLA_SUCCESS)
 379                 return;
 380
 381         /* Set NVRAM write protection. */
 382         /* Write enable. */
 383         qla2x00_nv_write(ha, NVR_DATA_OUT);
 384         qla2x00_nv_write(ha, 0);
 385         qla2x00_nv_write(ha, 0);
 386         for (word = 0; word < 8; word++)
 387                 qla2x00_nv_write(ha, NVR_DATA_OUT);
 388
 389         qla2x00_nv_deselect(ha);
 390
 391         /* Enable protection register. */
 392         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 393         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 394         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 395         for (word = 0; word < 8; word++)
 396                 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
 397
 398         qla2x00_nv_deselect(ha);
 399
 400         /* Enable protection register. */
 401         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 402         qla2x00_nv_write(ha, NVR_PR_ENABLE);
 403         qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
 404         for (word = 0; word < 8; word++)
 405                 qla2x00_nv_write(ha, NVR_PR_ENABLE);
 406
 407         qla2x00_nv_deselect(ha);
 408
 409         /* Wait for NVRAM to become ready. */
 410         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
 411         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
 412         wait_cnt = NVR_WAIT_CNT;
 413         do {
 414                 if (!--wait_cnt) {
 415                         DEBUG9_10(printk("%s(%ld): NVRAM didn't go ready...\n",
 416                             __func__, ha->host_no));
 417                         break;
 418                 }
 419                 NVRAM_DELAY();
 420                 word = RD_REG_WORD(&reg->nvram);
 421         } while ((word & NVR_DATA_IN) == 0);
 422 }
 423
 424
 425 /*****************************************************************************/
 426 /* Flash Manipulation Routines                                               */
 427 /*****************************************************************************/
 428
 429 #define OPTROM_BURST_SIZE       0x1000
 430 #define OPTROM_BURST_DWORDS     (OPTROM_BURST_SIZE / 4)
 431
 432 static inline uint32_t
 433 flash_conf_to_access_addr(uint32_t faddr)
 434 {
 435         return FARX_ACCESS_FLASH_CONF | faddr;
 436 }
 437
 438 static inline uint32_t
 439 flash_data_to_access_addr(uint32_t faddr)
 440 {
 441         return FARX_ACCESS_FLASH_DATA | faddr;
 442 }
 443
 444 static inline uint32_t
 445 nvram_conf_to_access_addr(uint32_t naddr)
 446 {
 447         return FARX_ACCESS_NVRAM_CONF | naddr;
 448 }
 449
 450 static inline uint32_t
 451 nvram_data_to_access_addr(uint32_t naddr)
 452 {
 453         return FARX_ACCESS_NVRAM_DATA | naddr;
 454 }
 455
 456 static uint32_t
 457 qla24xx_read_flash_dword(scsi_qla_host_t *ha, uint32_t addr)
 458 {
 459         int rval;
 460         uint32_t cnt, data;
 461         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 462
 463         WRT_REG_DWORD(&reg->flash_addr, addr & ~FARX_DATA_FLAG);
 464         /* Wait for READ cycle to complete. */
 465         rval = QLA_SUCCESS;
 466         for (cnt = 3000;
 467             (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) == 0 &&
 468             rval == QLA_SUCCESS; cnt--) {
 469                 if (cnt)
 470                         udelay(10);
 471                 else
 472                         rval = QLA_FUNCTION_TIMEOUT;
 473                 cond_resched();
 474         }
 475
 476         /* TODO: What happens if we time out? */
 477         data = 0xDEADDEAD;
 478         if (rval == QLA_SUCCESS)
 479                 data = RD_REG_DWORD(&reg->flash_data);
 480
 481         return data;
 482 }
 483
 484 uint32_t *
 485 qla24xx_read_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
 486     uint32_t dwords)
 487 {
 488         uint32_t i;
 489
 490         /* Dword reads to flash. */
 491         for (i = 0; i < dwords; i++, faddr++)
 492                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
 493                     flash_data_to_access_addr(faddr)));
 494
 495         return dwptr;
 496 }
 497
 498 static int
 499 qla24xx_write_flash_dword(scsi_qla_host_t *ha, uint32_t addr, uint32_t data)
 500 {
 501         int rval;
 502         uint32_t cnt;
 503         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 504
 505         WRT_REG_DWORD(&reg->flash_data, data);
 506         RD_REG_DWORD(&reg->flash_data);         /* PCI Posting. */
 507         WRT_REG_DWORD(&reg->flash_addr, addr | FARX_DATA_FLAG);
 508         /* Wait for Write cycle to complete. */
 509         rval = QLA_SUCCESS;
 510         for (cnt = 500000; (RD_REG_DWORD(&reg->flash_addr) & FARX_DATA_FLAG) &&
 511             rval == QLA_SUCCESS; cnt--) {
 512                 if (cnt)
 513                         udelay(10);
 514                 else
 515                         rval = QLA_FUNCTION_TIMEOUT;
 516                 cond_resched();
 517         }
 518         return rval;
 519 }
 520
 521 static void
 522 qla24xx_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
 523     uint8_t *flash_id)
 524 {
 525         uint32_t ids;
 526
 527         ids = qla24xx_read_flash_dword(ha, flash_data_to_access_addr(0xd03ab));
 528         *man_id = LSB(ids);
 529         *flash_id = MSB(ids);
 530
 531         /* Check if man_id and flash_id are valid. */
 532         if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) {
 533                 /* Read information using 0x9f opcode
 534                  * Device ID, Mfg ID would be read in the format:
 535                  *   <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID>
 536                  * Example: ATMEL 0x00 01 45 1F
 537                  * Extract MFG and Dev ID from last two bytes.
 538                  */
 539                 ids = qla24xx_read_flash_dword(ha,
 540                     flash_data_to_access_addr(0xd009f));
 541                 *man_id = LSB(ids);
 542                 *flash_id = MSB(ids);
 543         }
 544 }
 545
 546 static void
 547 qla24xx_unprotect_flash(scsi_qla_host_t *ha)
 548 {
 549         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 550
 551         /* Enable flash write. */
 552         WRT_REG_DWORD(&reg->ctrl_status,
 553             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
 554         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
 555
 556         /* Disable flash write-protection. */
 557         qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
 558         /* Some flash parts need an additional zero-write to clear bits.*/
 559         qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
 560 }
 561
 562 static void
 563 qla24xx_protect_flash(scsi_qla_host_t *ha)
 564 {
 565         uint32_t cnt;
 566         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 567
 568         /* Enable flash write-protection and wait for completion. */
 569         qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0x9c);
 570         for (cnt = 300; cnt &&
 571             qla24xx_read_flash_dword(ha,
 572                     flash_conf_to_access_addr(0x005)) & BIT_0;
 573             cnt--) {
 574                 udelay(10);
 575         }
 576
 577         /* Disable flash write. */
 578         WRT_REG_DWORD(&reg->ctrl_status,
 579             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
 580         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
 581 }
 582
 583 static int
 584 qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
 585     uint32_t dwords)
 586 {
 587         int ret;
 588         uint32_t liter, miter;
 589         uint32_t sec_mask, rest_addr, conf_addr;
 590         uint32_t fdata, findex;
 591         uint8_t man_id, flash_id;
 592         dma_addr_t optrom_dma;
 593         void *optrom = NULL;
 594         uint32_t *s, *d;
 595
 596         ret = QLA_SUCCESS;
 597
 598         /* Prepare burst-capable write on supported ISPs. */
 599         if (IS_QLA25XX(ha) && !(faddr & 0xfff) &&
 600             dwords > OPTROM_BURST_DWORDS) {
 601                 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
 602                     &optrom_dma, GFP_KERNEL);
 603                 if (!optrom) {
 604                         qla_printk(KERN_DEBUG, ha,
 605                             "Unable to allocate memory for optrom burst write "
 606                             "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
 607                 }
 608         }
 609
 610         qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
 611         DEBUG9(printk("%s(%ld): Flash man_id=%d flash_id=%d\n", __func__,
 612             ha->host_no, man_id, flash_id));
 613
 614         conf_addr = flash_conf_to_access_addr(0x03d8);
 615         switch (man_id) {
 616         case 0xbf: /* STT flash. */
 617                 if (flash_id == 0x8e) {
 618                         rest_addr = 0x3fff;
 619                         sec_mask = 0x7c000;
 620                 } else {
 621                         rest_addr = 0x1fff;
 622                         sec_mask = 0x7e000;
 623                 }
 624                 if (flash_id == 0x80)
 625                         conf_addr = flash_conf_to_access_addr(0x0352);
 626                 break;
 627         case 0x13: /* ST M25P80. */
 628                 rest_addr = 0x3fff;
 629                 sec_mask = 0x7c000;
 630                 break;
 631         case 0x1f: // Atmel 26DF081A
 632                 rest_addr = 0x3fff;
 633                 sec_mask = 0x7c000;
 634                 conf_addr = flash_conf_to_access_addr(0x0320);
 635                 break;
 636         default:
 637                 /* Default to 64 kb sector size. */
 638                 rest_addr = 0x3fff;
 639                 sec_mask = 0x7c000;
 640                 break;
 641         }
 642
 643         qla24xx_unprotect_flash(ha);
 644
 645         for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
 646                 if (man_id == 0x1f) {
 647                         findex = faddr << 2;
 648                         fdata = findex & sec_mask;
 649                 } else {
 650                         findex = faddr;
 651                         fdata = (findex & sec_mask) << 2;
 652                 }
 653
 654                 /* Are we at the beginning of a sector? */
 655                 if ((findex & rest_addr) == 0) {
 656                         /* Do sector unprotect at 4K boundry for Atmel part. */
 657                         if (man_id == 0x1f)
 658                                 qla24xx_write_flash_dword(ha,
 659                                     flash_conf_to_access_addr(0x0339),
 660                                     (fdata & 0xff00) | ((fdata << 16) &
 661                                     0xff0000) | ((fdata >> 16) & 0xff));
 662                         ret = qla24xx_write_flash_dword(ha, conf_addr,
 663                             (fdata & 0xff00) |((fdata << 16) &
 664                             0xff0000) | ((fdata >> 16) & 0xff));
 665                         if (ret != QLA_SUCCESS) {
 666                                 DEBUG9(printk("%s(%ld) Unable to flash "
 667                                     "sector: address=%x.\n", __func__,
 668                                     ha->host_no, faddr));
 669                                 break;
 670                         }
 671                 }
 672
 673                 /* Go with burst-write. */
 674                 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
 675                         /* Copy data to DMA'ble buffer. */
 676                         for (miter = 0, s = optrom, d = dwptr;
 677                             miter < OPTROM_BURST_DWORDS; miter++, s++, d++)
 678                                 *s = cpu_to_le32(*d);
 679
 680                         ret = qla2x00_load_ram(ha, optrom_dma,
 681                             flash_data_to_access_addr(faddr),
 682                             OPTROM_BURST_DWORDS);
 683                         if (ret != QLA_SUCCESS) {
 684                                 qla_printk(KERN_WARNING, ha,
 685                                     "Unable to burst-write optrom segment "
 686                                     "(%x/%x/%llx).\n", ret,
 687                                     flash_data_to_access_addr(faddr),
 688                                     (unsigned long long)optrom_dma);
 689                                 qla_printk(KERN_WARNING, ha,
 690                                     "Reverting to slow-write.\n");
 691
 692                                 dma_free_coherent(&ha->pdev->dev,
 693                                     OPTROM_BURST_SIZE, optrom, optrom_dma);
 694                                 optrom = NULL;
 695                         } else {
 696                                 liter += OPTROM_BURST_DWORDS - 1;
 697                                 faddr += OPTROM_BURST_DWORDS - 1;
 698                                 dwptr += OPTROM_BURST_DWORDS - 1;
 699                                 continue;
 700                         }
 701                 }
 702
 703                 ret = qla24xx_write_flash_dword(ha,
 704                     flash_data_to_access_addr(faddr), cpu_to_le32(*dwptr));
 705                 if (ret != QLA_SUCCESS) {
 706                         DEBUG9(printk("%s(%ld) Unable to program flash "
 707                             "address=%x data=%x.\n", __func__,
 708                             ha->host_no, faddr, *dwptr));
 709                         break;
 710                 }
 711
 712                 /* Do sector protect at 4K boundry for Atmel part. */
 713                 if (man_id == 0x1f &&
 714                     ((faddr & rest_addr) == rest_addr))
 715                         qla24xx_write_flash_dword(ha,
 716                             flash_conf_to_access_addr(0x0336),
 717                             (fdata & 0xff00) | ((fdata << 16) &
 718                             0xff0000) | ((fdata >> 16) & 0xff));
 719         }
 720
 721         qla24xx_protect_flash(ha);
 722
 723         if (optrom)
 724                 dma_free_coherent(&ha->pdev->dev,
 725                     OPTROM_BURST_SIZE, optrom, optrom_dma);
 726
 727         return ret;
 728 }
 729
 730 uint8_t *
 731 qla2x00_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
 732     uint32_t bytes)
 733 {
 734         uint32_t i;
 735         uint16_t *wptr;
 736
 737         /* Word reads to NVRAM via registers. */
 738         wptr = (uint16_t *)buf;
 739         qla2x00_lock_nvram_access(ha);
 740         for (i = 0; i < bytes >> 1; i++, naddr++)
 741                 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
 742                     naddr));
 743         qla2x00_unlock_nvram_access(ha);
 744
 745         return buf;
 746 }
 747
 748 uint8_t *
 749 qla24xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
 750     uint32_t bytes)
 751 {
 752         uint32_t i;
 753         uint32_t *dwptr;
 754
 755         /* Dword reads to flash. */
 756         dwptr = (uint32_t *)buf;
 757         for (i = 0; i < bytes >> 2; i++, naddr++)
 758                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
 759                     nvram_data_to_access_addr(naddr)));
 760
 761         return buf;
 762 }
 763
 764 int
 765 qla2x00_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
 766     uint32_t bytes)
 767 {
 768         int ret, stat;
 769         uint32_t i;
 770         uint16_t *wptr;
 771         unsigned long flags;
 772
 773         ret = QLA_SUCCESS;
 774
 775         spin_lock_irqsave(&ha->hardware_lock, flags);
 776         qla2x00_lock_nvram_access(ha);
 777
 778         /* Disable NVRAM write-protection. */
 779         stat = qla2x00_clear_nvram_protection(ha);
 780
 781         wptr = (uint16_t *)buf;
 782         for (i = 0; i < bytes >> 1; i++, naddr++) {
 783                 qla2x00_write_nvram_word(ha, naddr,
 784                     cpu_to_le16(*wptr));
 785                 wptr++;
 786         }
 787
 788         /* Enable NVRAM write-protection. */
 789         qla2x00_set_nvram_protection(ha, stat);
 790
 791         qla2x00_unlock_nvram_access(ha);
 792         spin_unlock_irqrestore(&ha->hardware_lock, flags);
 793
 794         return ret;
 795 }
 796
 797 int
 798 qla24xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
 799     uint32_t bytes)
 800 {
 801         int ret;
 802         uint32_t i;
 803         uint32_t *dwptr;
 804         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
 805         unsigned long flags;
 806
 807         ret = QLA_SUCCESS;
 808
 809         spin_lock_irqsave(&ha->hardware_lock, flags);
 810         /* Enable flash write. */
 811         WRT_REG_DWORD(&reg->ctrl_status,
 812             RD_REG_DWORD(&reg->ctrl_status) | CSRX_FLASH_ENABLE);
 813         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
 814
 815         /* Disable NVRAM write-protection. */
 816         qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
 817             0);
 818         qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
 819             0);
 820
 821         /* Dword writes to flash. */
 822         dwptr = (uint32_t *)buf;
 823         for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
 824                 ret = qla24xx_write_flash_dword(ha,
 825                     nvram_data_to_access_addr(naddr),
 826                     cpu_to_le32(*dwptr));
 827                 if (ret != QLA_SUCCESS) {
 828                         DEBUG9(printk("%s(%ld) Unable to program "
 829                             "nvram address=%x data=%x.\n", __func__,
 830                             ha->host_no, naddr, *dwptr));
 831                         break;
 832                 }
 833         }
 834
 835         /* Enable NVRAM write-protection. */
 836         qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
 837             0x8c);
 838
 839         /* Disable flash write. */
 840         WRT_REG_DWORD(&reg->ctrl_status,
 841             RD_REG_DWORD(&reg->ctrl_status) & ~CSRX_FLASH_ENABLE);
 842         RD_REG_DWORD(&reg->ctrl_status);        /* PCI Posting. */
 843         spin_unlock_irqrestore(&ha->hardware_lock, flags);
 844
 845         return ret;
 846 }
 847
 848 uint8_t *
 849 qla25xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
 850     uint32_t bytes)
 851 {
 852         uint32_t i;
 853         uint32_t *dwptr;
 854
 855         /* Dword reads to flash. */
 856         dwptr = (uint32_t *)buf;
 857         for (i = 0; i < bytes >> 2; i++, naddr++)
 858                 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
 859                     flash_data_to_access_addr(FA_VPD_NVRAM_ADDR | naddr)));
 860
 861         return buf;
 862 }
 863
 864 int
 865 qla25xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
 866     uint32_t bytes)
 867 {
 868 #define RMW_BUFFER_SIZE (64 * 1024)
 869         uint8_t *dbuf;
 870
 871         dbuf = vmalloc(RMW_BUFFER_SIZE);
 872         if (!dbuf)
 873                 return QLA_MEMORY_ALLOC_FAILED;
 874         ha->isp_ops->read_optrom(ha, dbuf, FA_VPD_NVRAM_ADDR << 2,
 875             RMW_BUFFER_SIZE);
 876         memcpy(dbuf + (naddr << 2), buf, bytes);
 877         ha->isp_ops->write_optrom(ha, dbuf, FA_VPD_NVRAM_ADDR << 2,
 878             RMW_BUFFER_SIZE);
 879         vfree(dbuf);
 880
 881         return QLA_SUCCESS;
 882 }
 883
 884 static inline void
 885 qla2x00_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags)
 886 {
 887         if (IS_QLA2322(ha)) {
 888                 /* Flip all colors. */
 889                 if (ha->beacon_color_state == QLA_LED_ALL_ON) {
 890                         /* Turn off. */
 891                         ha->beacon_color_state = 0;
 892                         *pflags = GPIO_LED_ALL_OFF;
 893                 } else {
 894                         /* Turn on. */
 895                         ha->beacon_color_state = QLA_LED_ALL_ON;
 896                         *pflags = GPIO_LED_RGA_ON;
 897                 }
 898         } else {
 899                 /* Flip green led only. */
 900                 if (ha->beacon_color_state == QLA_LED_GRN_ON) {
 901                         /* Turn off. */
 902                         ha->beacon_color_state = 0;
 903                         *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF;
 904                 } else {
 905                         /* Turn on. */
 906                         ha->beacon_color_state = QLA_LED_GRN_ON;
 907                         *pflags = GPIO_LED_GREEN_ON_AMBER_OFF;
 908                 }
 909         }
 910 }
 911
 912 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r))
 913
 914 void
 915 qla2x00_beacon_blink(struct scsi_qla_host *ha)
 916 {
 917         uint16_t gpio_enable;
 918         uint16_t gpio_data;
 919         uint16_t led_color = 0;
 920         unsigned long flags;
 921         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 922
 923         spin_lock_irqsave(&ha->hardware_lock, flags);
 924
 925         /* Save the Original GPIOE. */
 926         if (ha->pio_address) {
 927                 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
 928                 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
 929         } else {
 930                 gpio_enable = RD_REG_WORD(&reg->gpioe);
 931                 gpio_data = RD_REG_WORD(&reg->gpiod);
 932         }
 933
 934         /* Set the modified gpio_enable values */
 935         gpio_enable |= GPIO_LED_MASK;
 936
 937         if (ha->pio_address) {
 938                 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
 939         } else {
 940                 WRT_REG_WORD(&reg->gpioe, gpio_enable);
 941                 RD_REG_WORD(&reg->gpioe);
 942         }
 943
 944         qla2x00_flip_colors(ha, &led_color);
 945
 946         /* Clear out any previously set LED color. */
 947         gpio_data &= ~GPIO_LED_MASK;
 948
 949         /* Set the new input LED color to GPIOD. */
 950         gpio_data |= led_color;
 951
 952         /* Set the modified gpio_data values */
 953         if (ha->pio_address) {
 954                 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
 955         } else {
 956                 WRT_REG_WORD(&reg->gpiod, gpio_data);
 957                 RD_REG_WORD(&reg->gpiod);
 958         }
 959
 960         spin_unlock_irqrestore(&ha->hardware_lock, flags);
 961 }
 962
 963 int
 964 qla2x00_beacon_on(struct scsi_qla_host *ha)
 965 {
 966         uint16_t gpio_enable;
 967         uint16_t gpio_data;
 968         unsigned long flags;
 969         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
 970
 971         ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
 972         ha->fw_options[1] |= FO1_DISABLE_GPIO6_7;
 973
 974         if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
 975                 qla_printk(KERN_WARNING, ha,
 976                     "Unable to update fw options (beacon on).\n");
 977                 return QLA_FUNCTION_FAILED;
 978         }
 979
 980         /* Turn off LEDs. */
 981         spin_lock_irqsave(&ha->hardware_lock, flags);
 982         if (ha->pio_address) {
 983                 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe));
 984                 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod));
 985         } else {
 986                 gpio_enable = RD_REG_WORD(&reg->gpioe);
 987                 gpio_data = RD_REG_WORD(&reg->gpiod);
 988         }
 989         gpio_enable |= GPIO_LED_MASK;
 990
 991         /* Set the modified gpio_enable values. */
 992         if (ha->pio_address) {
 993                 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable);
 994         } else {
 995                 WRT_REG_WORD(&reg->gpioe, gpio_enable);
 996                 RD_REG_WORD(&reg->gpioe);
 997         }
 998
 999         /* Clear out previously set LED colour. */
1000         gpio_data &= ~GPIO_LED_MASK;
1001         if (ha->pio_address) {
1002                 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data);
1003         } else {
1004                 WRT_REG_WORD(&reg->gpiod, gpio_data);
1005                 RD_REG_WORD(&reg->gpiod);
1006         }
1007         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1008
1009         /*
1010          * Let the per HBA timer kick off the blinking process based on
1011          * the following flags. No need to do anything else now.
1012          */
1013         ha->beacon_blink_led = 1;
1014         ha->beacon_color_state = 0;
1015
1016         return QLA_SUCCESS;
1017 }
1018
1019 int
1020 qla2x00_beacon_off(struct scsi_qla_host *ha)
1021 {
1022         int rval = QLA_SUCCESS;
1023
1024         ha->beacon_blink_led = 0;
1025
1026         /* Set the on flag so when it gets flipped it will be off. */
1027         if (IS_QLA2322(ha))
1028                 ha->beacon_color_state = QLA_LED_ALL_ON;
1029         else
1030                 ha->beacon_color_state = QLA_LED_GRN_ON;
1031
1032         ha->isp_ops->beacon_blink(ha);  /* This turns green LED off */
1033
1034         ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
1035         ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7;
1036
1037         rval = qla2x00_set_fw_options(ha, ha->fw_options);
1038         if (rval != QLA_SUCCESS)
1039                 qla_printk(KERN_WARNING, ha,
1040                     "Unable to update fw options (beacon off).\n");
1041         return rval;
1042 }
1043
1044
1045 static inline void
1046 qla24xx_flip_colors(scsi_qla_host_t *ha, uint16_t *pflags)
1047 {
1048         /* Flip all colors. */
1049         if (ha->beacon_color_state == QLA_LED_ALL_ON) {
1050                 /* Turn off. */
1051                 ha->beacon_color_state = 0;
1052                 *pflags = 0;
1053         } else {
1054                 /* Turn on. */
1055                 ha->beacon_color_state = QLA_LED_ALL_ON;
1056                 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON;
1057         }
1058 }
1059
1060 void
1061 qla24xx_beacon_blink(struct scsi_qla_host *ha)
1062 {
1063         uint16_t led_color = 0;
1064         uint32_t gpio_data;
1065         unsigned long flags;
1066         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1067
1068         /* Save the Original GPIOD. */
1069         spin_lock_irqsave(&ha->hardware_lock, flags);
1070         gpio_data = RD_REG_DWORD(&reg->gpiod);
1071
1072         /* Enable the gpio_data reg for update. */
1073         gpio_data |= GPDX_LED_UPDATE_MASK;
1074
1075         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1076         gpio_data = RD_REG_DWORD(&reg->gpiod);
1077
1078         /* Set the color bits. */
1079         qla24xx_flip_colors(ha, &led_color);
1080
1081         /* Clear out any previously set LED color. */
1082         gpio_data &= ~GPDX_LED_COLOR_MASK;
1083
1084         /* Set the new input LED color to GPIOD. */
1085         gpio_data |= led_color;
1086
1087         /* Set the modified gpio_data values. */
1088         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1089         gpio_data = RD_REG_DWORD(&reg->gpiod);
1090         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1091 }
1092
1093 int
1094 qla24xx_beacon_on(struct scsi_qla_host *ha)
1095 {
1096         uint32_t gpio_data;
1097         unsigned long flags;
1098         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1099
1100         if (ha->beacon_blink_led == 0) {
1101                 /* Enable firmware for update */
1102                 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL;
1103
1104                 if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS)
1105                         return QLA_FUNCTION_FAILED;
1106
1107                 if (qla2x00_get_fw_options(ha, ha->fw_options) !=
1108                     QLA_SUCCESS) {
1109                         qla_printk(KERN_WARNING, ha,
1110                             "Unable to update fw options (beacon on).\n");
1111                         return QLA_FUNCTION_FAILED;
1112                 }
1113
1114                 spin_lock_irqsave(&ha->hardware_lock, flags);
1115                 gpio_data = RD_REG_DWORD(&reg->gpiod);
1116
1117                 /* Enable the gpio_data reg for update. */
1118                 gpio_data |= GPDX_LED_UPDATE_MASK;
1119                 WRT_REG_DWORD(&reg->gpiod, gpio_data);
1120                 RD_REG_DWORD(&reg->gpiod);
1121
1122                 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1123         }
1124
1125         /* So all colors blink together. */
1126         ha->beacon_color_state = 0;
1127
1128         /* Let the per HBA timer kick off the blinking process. */
1129         ha->beacon_blink_led = 1;
1130
1131         return QLA_SUCCESS;
1132 }
1133
1134 int
1135 qla24xx_beacon_off(struct scsi_qla_host *ha)
1136 {
1137         uint32_t gpio_data;
1138         unsigned long flags;
1139         struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1140
1141         ha->beacon_blink_led = 0;
1142         ha->beacon_color_state = QLA_LED_ALL_ON;
1143
1144         ha->isp_ops->beacon_blink(ha);  /* Will flip to all off. */
1145
1146         /* Give control back to firmware. */
1147         spin_lock_irqsave(&ha->hardware_lock, flags);
1148         gpio_data = RD_REG_DWORD(&reg->gpiod);
1149
1150         /* Disable the gpio_data reg for update. */
1151         gpio_data &= ~GPDX_LED_UPDATE_MASK;
1152         WRT_REG_DWORD(&reg->gpiod, gpio_data);
1153         RD_REG_DWORD(&reg->gpiod);
1154         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1155
1156         ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL;
1157
1158         if (qla2x00_set_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
1159                 qla_printk(KERN_WARNING, ha,
1160                     "Unable to update fw options (beacon off).\n");
1161                 return QLA_FUNCTION_FAILED;
1162         }
1163
1164         if (qla2x00_get_fw_options(ha, ha->fw_options) != QLA_SUCCESS) {
1165                 qla_printk(KERN_WARNING, ha,
1166                     "Unable to get fw options (beacon off).\n");
1167                 return QLA_FUNCTION_FAILED;
1168         }
1169
1170         return QLA_SUCCESS;
1171 }
1172
1173
1174 /*
1175  * Flash support routines
1176  */
1177
1178 /**
1179  * qla2x00_flash_enable() - Setup flash for reading and writing.
1180  * @ha: HA context
1181  */
1182 static void
1183 qla2x00_flash_enable(scsi_qla_host_t *ha)
1184 {
1185         uint16_t data;
1186         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1187
1188         data = RD_REG_WORD(&reg->ctrl_status);
1189         data |= CSR_FLASH_ENABLE;
1190         WRT_REG_WORD(&reg->ctrl_status, data);
1191         RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1192 }
1193
1194 /**
1195  * qla2x00_flash_disable() - Disable flash and allow RISC to run.
1196  * @ha: HA context
1197  */
1198 static void
1199 qla2x00_flash_disable(scsi_qla_host_t *ha)
1200 {
1201         uint16_t data;
1202         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1203
1204         data = RD_REG_WORD(&reg->ctrl_status);
1205         data &= ~(CSR_FLASH_ENABLE);
1206         WRT_REG_WORD(&reg->ctrl_status, data);
1207         RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1208 }
1209
1210 /**
1211  * qla2x00_read_flash_byte() - Reads a byte from flash
1212  * @ha: HA context
1213  * @addr: Address in flash to read
1214  *
1215  * A word is read from the chip, but, only the lower byte is valid.
1216  *
1217  * Returns the byte read from flash @addr.
1218  */
1219 static uint8_t
1220 qla2x00_read_flash_byte(scsi_qla_host_t *ha, uint32_t addr)
1221 {
1222         uint16_t data;
1223         uint16_t bank_select;
1224         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1225
1226         bank_select = RD_REG_WORD(&reg->ctrl_status);
1227
1228         if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1229                 /* Specify 64K address range: */
1230                 /*  clear out Module Select and Flash Address bits [19:16]. */
1231                 bank_select &= ~0xf8;
1232                 bank_select |= addr >> 12 & 0xf0;
1233                 bank_select |= CSR_FLASH_64K_BANK;
1234                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1235                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1236
1237                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1238                 data = RD_REG_WORD(&reg->flash_data);
1239
1240                 return (uint8_t)data;
1241         }
1242
1243         /* Setup bit 16 of flash address. */
1244         if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1245                 bank_select |= CSR_FLASH_64K_BANK;
1246                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1247                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1248         } else if (((addr & BIT_16) == 0) &&
1249             (bank_select & CSR_FLASH_64K_BANK)) {
1250                 bank_select &= ~(CSR_FLASH_64K_BANK);
1251                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1252                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1253         }
1254
1255         /* Always perform IO mapped accesses to the FLASH registers. */
1256         if (ha->pio_address) {
1257                 uint16_t data2;
1258
1259                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1260                 do {
1261                         data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1262                         barrier();
1263                         cpu_relax();
1264                         data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data));
1265                 } while (data != data2);
1266         } else {
1267                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1268                 data = qla2x00_debounce_register(&reg->flash_data);
1269         }
1270
1271         return (uint8_t)data;
1272 }
1273
1274 /**
1275  * qla2x00_write_flash_byte() - Write a byte to flash
1276  * @ha: HA context
1277  * @addr: Address in flash to write
1278  * @data: Data to write
1279  */
1280 static void
1281 qla2x00_write_flash_byte(scsi_qla_host_t *ha, uint32_t addr, uint8_t data)
1282 {
1283         uint16_t bank_select;
1284         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1285
1286         bank_select = RD_REG_WORD(&reg->ctrl_status);
1287         if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1288                 /* Specify 64K address range: */
1289                 /*  clear out Module Select and Flash Address bits [19:16]. */
1290                 bank_select &= ~0xf8;
1291                 bank_select |= addr >> 12 & 0xf0;
1292                 bank_select |= CSR_FLASH_64K_BANK;
1293                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1294                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1295
1296                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1297                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1298                 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1299                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1300
1301                 return;
1302         }
1303
1304         /* Setup bit 16 of flash address. */
1305         if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) {
1306                 bank_select |= CSR_FLASH_64K_BANK;
1307                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1308                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1309         } else if (((addr & BIT_16) == 0) &&
1310             (bank_select & CSR_FLASH_64K_BANK)) {
1311                 bank_select &= ~(CSR_FLASH_64K_BANK);
1312                 WRT_REG_WORD(&reg->ctrl_status, bank_select);
1313                 RD_REG_WORD(&reg->ctrl_status); /* PCI Posting. */
1314         }
1315
1316         /* Always perform IO mapped accesses to the FLASH registers. */
1317         if (ha->pio_address) {
1318                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr);
1319                 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data);
1320         } else {
1321                 WRT_REG_WORD(&reg->flash_address, (uint16_t)addr);
1322                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1323                 WRT_REG_WORD(&reg->flash_data, (uint16_t)data);
1324                 RD_REG_WORD(&reg->ctrl_status);         /* PCI Posting. */
1325         }
1326 }
1327
1328 /**
1329  * qla2x00_poll_flash() - Polls flash for completion.
1330  * @ha: HA context
1331  * @addr: Address in flash to poll
1332  * @poll_data: Data to be polled
1333  * @man_id: Flash manufacturer ID
1334  * @flash_id: Flash ID
1335  *
1336  * This function polls the device until bit 7 of what is read matches data
1337  * bit 7 or until data bit 5 becomes a 1.  If that hapens, the flash ROM timed
1338  * out (a fatal error).  The flash book recommeds reading bit 7 again after
1339  * reading bit 5 as a 1.
1340  *
1341  * Returns 0 on success, else non-zero.
1342  */
1343 static int
1344 qla2x00_poll_flash(scsi_qla_host_t *ha, uint32_t addr, uint8_t poll_data,
1345     uint8_t man_id, uint8_t flash_id)
1346 {
1347         int status;
1348         uint8_t flash_data;
1349         uint32_t cnt;
1350
1351         status = 1;
1352
1353         /* Wait for 30 seconds for command to finish. */
1354         poll_data &= BIT_7;
1355         for (cnt = 3000000; cnt; cnt--) {
1356                 flash_data = qla2x00_read_flash_byte(ha, addr);
1357                 if ((flash_data & BIT_7) == poll_data) {
1358                         status = 0;
1359                         break;
1360                 }
1361
1362                 if (man_id != 0x40 && man_id != 0xda) {
1363                         if ((flash_data & BIT_5) && cnt > 2)
1364                                 cnt = 2;
1365                 }
1366                 udelay(10);
1367                 barrier();
1368                 cond_resched();
1369         }
1370         return status;
1371 }
1372
1373 /**
1374  * qla2x00_program_flash_address() - Programs a flash address
1375  * @ha: HA context
1376  * @addr: Address in flash to program
1377  * @data: Data to be written in flash
1378  * @man_id: Flash manufacturer ID
1379  * @flash_id: Flash ID
1380  *
1381  * Returns 0 on success, else non-zero.
1382  */
1383 static int
1384 qla2x00_program_flash_address(scsi_qla_host_t *ha, uint32_t addr, uint8_t data,
1385     uint8_t man_id, uint8_t flash_id)
1386 {
1387         /* Write Program Command Sequence. */
1388         if (IS_OEM_001(ha)) {
1389                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1390                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1391                 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0);
1392                 qla2x00_write_flash_byte(ha, addr, data);
1393         } else {
1394                 if (man_id == 0xda && flash_id == 0xc1) {
1395                         qla2x00_write_flash_byte(ha, addr, data);
1396                         if (addr & 0x7e)
1397                                 return 0;
1398                 } else {
1399                         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1400                         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1401                         qla2x00_write_flash_byte(ha, 0x5555, 0xa0);
1402                         qla2x00_write_flash_byte(ha, addr, data);
1403                 }
1404         }
1405
1406         udelay(150);
1407
1408         /* Wait for write to complete. */
1409         return qla2x00_poll_flash(ha, addr, data, man_id, flash_id);
1410 }
1411
1412 /**
1413  * qla2x00_erase_flash() - Erase the flash.
1414  * @ha: HA context
1415  * @man_id: Flash manufacturer ID
1416  * @flash_id: Flash ID
1417  *
1418  * Returns 0 on success, else non-zero.
1419  */
1420 static int
1421 qla2x00_erase_flash(scsi_qla_host_t *ha, uint8_t man_id, uint8_t flash_id)
1422 {
1423         /* Individual Sector Erase Command Sequence */
1424         if (IS_OEM_001(ha)) {
1425                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1426                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1427                 qla2x00_write_flash_byte(ha, 0xaaa, 0x80);
1428                 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa);
1429                 qla2x00_write_flash_byte(ha, 0x555, 0x55);
1430                 qla2x00_write_flash_byte(ha, 0xaaa, 0x10);
1431         } else {
1432                 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1433                 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1434                 qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1435                 qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1436                 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1437                 qla2x00_write_flash_byte(ha, 0x5555, 0x10);
1438         }
1439
1440         udelay(150);
1441
1442         /* Wait for erase to complete. */
1443         return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id);
1444 }
1445
1446 /**
1447  * qla2x00_erase_flash_sector() - Erase a flash sector.
1448  * @ha: HA context
1449  * @addr: Flash sector to erase
1450  * @sec_mask: Sector address mask
1451  * @man_id: Flash manufacturer ID
1452  * @flash_id: Flash ID
1453  *
1454  * Returns 0 on success, else non-zero.
1455  */
1456 static int
1457 qla2x00_erase_flash_sector(scsi_qla_host_t *ha, uint32_t addr,
1458     uint32_t sec_mask, uint8_t man_id, uint8_t flash_id)
1459 {
1460         /* Individual Sector Erase Command Sequence */
1461         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1462         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1463         qla2x00_write_flash_byte(ha, 0x5555, 0x80);
1464         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1465         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1466         if (man_id == 0x1f && flash_id == 0x13)
1467                 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10);
1468         else
1469                 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30);
1470
1471         udelay(150);
1472
1473         /* Wait for erase to complete. */
1474         return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id);
1475 }
1476
1477 /**
1478  * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip.
1479  * @man_id: Flash manufacturer ID
1480  * @flash_id: Flash ID
1481  */
1482 static void
1483 qla2x00_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
1484     uint8_t *flash_id)
1485 {
1486         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1487         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1488         qla2x00_write_flash_byte(ha, 0x5555, 0x90);
1489         *man_id = qla2x00_read_flash_byte(ha, 0x0000);
1490         *flash_id = qla2x00_read_flash_byte(ha, 0x0001);
1491         qla2x00_write_flash_byte(ha, 0x5555, 0xaa);
1492         qla2x00_write_flash_byte(ha, 0x2aaa, 0x55);
1493         qla2x00_write_flash_byte(ha, 0x5555, 0xf0);
1494 }
1495
1496 static void
1497 qla2x00_read_flash_data(scsi_qla_host_t *ha, uint8_t *tmp_buf, uint32_t saddr,
1498         uint32_t length)
1499 {
1500         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1501         uint32_t midpoint, ilength;
1502         uint8_t data;
1503
1504         midpoint = length / 2;
1505
1506         WRT_REG_WORD(&reg->nvram, 0);
1507         RD_REG_WORD(&reg->nvram);
1508         for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) {
1509                 if (ilength == midpoint) {
1510                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1511                         RD_REG_WORD(&reg->nvram);
1512                 }
1513                 data = qla2x00_read_flash_byte(ha, saddr);
1514                 if (saddr % 100)
1515                         udelay(10);
1516                 *tmp_buf = data;
1517                 cond_resched();
1518         }
1519 }
1520
1521 static inline void
1522 qla2x00_suspend_hba(struct scsi_qla_host *ha)
1523 {
1524         int cnt;
1525         unsigned long flags;
1526         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1527
1528         /* Suspend HBA. */
1529         scsi_block_requests(ha->host);
1530         ha->isp_ops->disable_intrs(ha);
1531         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1532
1533         /* Pause RISC. */
1534         spin_lock_irqsave(&ha->hardware_lock, flags);
1535         WRT_REG_WORD(&reg->hccr, HCCR_PAUSE_RISC);
1536         RD_REG_WORD(&reg->hccr);
1537         if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
1538                 for (cnt = 0; cnt < 30000; cnt++) {
1539                         if ((RD_REG_WORD(&reg->hccr) & HCCR_RISC_PAUSE) != 0)
1540                                 break;
1541                         udelay(100);
1542                 }
1543         } else {
1544                 udelay(10);
1545         }
1546         spin_unlock_irqrestore(&ha->hardware_lock, flags);
1547 }
1548
1549 static inline void
1550 qla2x00_resume_hba(struct scsi_qla_host *ha)
1551 {
1552         /* Resume HBA. */
1553         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1554         set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags);
1555         qla2xxx_wake_dpc(ha);
1556         qla2x00_wait_for_hba_online(ha);
1557         scsi_unblock_requests(ha->host);
1558 }
1559
1560 uint8_t *
1561 qla2x00_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1562     uint32_t offset, uint32_t length)
1563 {
1564         uint32_t addr, midpoint;
1565         uint8_t *data;
1566         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1567
1568         /* Suspend HBA. */
1569         qla2x00_suspend_hba(ha);
1570
1571         /* Go with read. */
1572         midpoint = ha->optrom_size / 2;
1573
1574         qla2x00_flash_enable(ha);
1575         WRT_REG_WORD(&reg->nvram, 0);
1576         RD_REG_WORD(&reg->nvram);               /* PCI Posting. */
1577         for (addr = offset, data = buf; addr < length; addr++, data++) {
1578                 if (addr == midpoint) {
1579                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1580                         RD_REG_WORD(&reg->nvram);       /* PCI Posting. */
1581                 }
1582
1583                 *data = qla2x00_read_flash_byte(ha, addr);
1584         }
1585         qla2x00_flash_disable(ha);
1586
1587         /* Resume HBA. */
1588         qla2x00_resume_hba(ha);
1589
1590         return buf;
1591 }
1592
1593 int
1594 qla2x00_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1595     uint32_t offset, uint32_t length)
1596 {
1597
1598         int rval;
1599         uint8_t man_id, flash_id, sec_number, data;
1600         uint16_t wd;
1601         uint32_t addr, liter, sec_mask, rest_addr;
1602         struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1603
1604         /* Suspend HBA. */
1605         qla2x00_suspend_hba(ha);
1606
1607         rval = QLA_SUCCESS;
1608         sec_number = 0;
1609
1610         /* Reset ISP chip. */
1611         WRT_REG_WORD(&reg->ctrl_status, CSR_ISP_SOFT_RESET);
1612         pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
1613
1614         /* Go with write. */
1615         qla2x00_flash_enable(ha);
1616         do {    /* Loop once to provide quick error exit */
1617                 /* Structure of flash memory based on manufacturer */
1618                 if (IS_OEM_001(ha)) {
1619                         /* OEM variant with special flash part. */
1620                         man_id = flash_id = 0;
1621                         rest_addr = 0xffff;
1622                         sec_mask   = 0x10000;
1623                         goto update_flash;
1624                 }
1625                 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id);
1626                 switch (man_id) {
1627                 case 0x20: /* ST flash. */
1628                         if (flash_id == 0xd2 || flash_id == 0xe3) {
1629                                 /*
1630                                  * ST m29w008at part - 64kb sector size with
1631                                  * 32kb,8kb,8kb,16kb sectors at memory address
1632                                  * 0xf0000.
1633                                  */
1634                                 rest_addr = 0xffff;
1635                                 sec_mask = 0x10000;
1636                                 break;
1637                         }
1638                         /*
1639                          * ST m29w010b part - 16kb sector size
1640                          * Default to 16kb sectors
1641                          */
1642                         rest_addr = 0x3fff;
1643                         sec_mask = 0x1c000;
1644                         break;
1645                 case 0x40: /* Mostel flash. */
1646                         /* Mostel v29c51001 part - 512 byte sector size. */
1647                         rest_addr = 0x1ff;
1648                         sec_mask = 0x1fe00;
1649                         break;
1650                 case 0xbf: /* SST flash. */
1651                         /* SST39sf10 part - 4kb sector size. */
1652                         rest_addr = 0xfff;
1653                         sec_mask = 0x1f000;
1654                         break;
1655                 case 0xda: /* Winbond flash. */
1656                         /* Winbond W29EE011 part - 256 byte sector size. */
1657                         rest_addr = 0x7f;
1658                         sec_mask = 0x1ff80;
1659                         break;
1660                 case 0xc2: /* Macronix flash. */
1661                         /* 64k sector size. */
1662                         if (flash_id == 0x38 || flash_id == 0x4f) {
1663                                 rest_addr = 0xffff;
1664                                 sec_mask = 0x10000;
1665                                 break;
1666                         }
1667                         /* Fall through... */
1668
1669                 case 0x1f: /* Atmel flash. */
1670                         /* 512k sector size. */
1671                         if (flash_id == 0x13) {
1672                                 rest_addr = 0x7fffffff;
1673                                 sec_mask =   0x80000000;
1674                                 break;
1675                         }
1676                         /* Fall through... */
1677
1678                 case 0x01: /* AMD flash. */
1679                         if (flash_id == 0x38 || flash_id == 0x40 ||
1680                             flash_id == 0x4f) {
1681                                 /* Am29LV081 part - 64kb sector size. */
1682                                 /* Am29LV002BT part - 64kb sector size. */
1683                                 rest_addr = 0xffff;
1684                                 sec_mask = 0x10000;
1685                                 break;
1686                         } else if (flash_id == 0x3e) {
1687                                 /*
1688                                  * Am29LV008b part - 64kb sector size with
1689                                  * 32kb,8kb,8kb,16kb sector at memory address
1690                                  * h0xf0000.
1691                                  */
1692                                 rest_addr = 0xffff;
1693                                 sec_mask = 0x10000;
1694                                 break;
1695                         } else if (flash_id == 0x20 || flash_id == 0x6e) {
1696                                 /*
1697                                  * Am29LV010 part or AM29f010 - 16kb sector
1698                                  * size.
1699                                  */
1700                                 rest_addr = 0x3fff;
1701                                 sec_mask = 0x1c000;
1702                                 break;
1703                         } else if (flash_id == 0x6d) {
1704                                 /* Am29LV001 part - 8kb sector size. */
1705                                 rest_addr = 0x1fff;
1706                                 sec_mask = 0x1e000;
1707                                 break;
1708                         }
1709                 default:
1710                         /* Default to 16 kb sector size. */
1711                         rest_addr = 0x3fff;
1712                         sec_mask = 0x1c000;
1713                         break;
1714                 }
1715
1716 update_flash:
1717                 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1718                         if (qla2x00_erase_flash(ha, man_id, flash_id)) {
1719                                 rval = QLA_FUNCTION_FAILED;
1720                                 break;
1721                         }
1722                 }
1723
1724                 for (addr = offset, liter = 0; liter < length; liter++,
1725                     addr++) {
1726                         data = buf[liter];
1727                         /* Are we at the beginning of a sector? */
1728                         if ((addr & rest_addr) == 0) {
1729                                 if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
1730                                         if (addr >= 0x10000UL) {
1731                                                 if (((addr >> 12) & 0xf0) &&
1732                                                     ((man_id == 0x01 &&
1733                                                         flash_id == 0x3e) ||
1734                                                      (man_id == 0x20 &&
1735                                                          flash_id == 0xd2))) {
1736                                                         sec_number++;
1737                                                         if (sec_number == 1) {
1738                                                                 rest_addr =
1739                                                                     0x7fff;
1740                                                                 sec_mask =
1741                                                                     0x18000;
1742                                                         } else if (
1743                                                             sec_number == 2 ||
1744                                                             sec_number == 3) {
1745                                                                 rest_addr =
1746                                                                     0x1fff;
1747                                                                 sec_mask =
1748                                                                     0x1e000;
1749                                                         } else if (
1750                                                             sec_number == 4) {
1751                                                                 rest_addr =
1752                                                                     0x3fff;
1753                                                                 sec_mask =
1754                                                                     0x1c000;
1755                                                         }
1756                                                 }
1757                                         }
1758                                 } else if (addr == ha->optrom_size / 2) {
1759                                         WRT_REG_WORD(&reg->nvram, NVR_SELECT);
1760                                         RD_REG_WORD(&reg->nvram);
1761                                 }
1762
1763                                 if (flash_id == 0xda && man_id == 0xc1) {
1764                                         qla2x00_write_flash_byte(ha, 0x5555,
1765                                             0xaa);
1766                                         qla2x00_write_flash_byte(ha, 0x2aaa,
1767                                             0x55);
1768                                         qla2x00_write_flash_byte(ha, 0x5555,
1769                                             0xa0);
1770                                 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) {
1771                                         /* Then erase it */
1772                                         if (qla2x00_erase_flash_sector(ha,
1773                                             addr, sec_mask, man_id,
1774                                             flash_id)) {
1775                                                 rval = QLA_FUNCTION_FAILED;
1776                                                 break;
1777                                         }
1778                                         if (man_id == 0x01 && flash_id == 0x6d)
1779                                                 sec_number++;
1780                                 }
1781                         }
1782
1783                         if (man_id == 0x01 && flash_id == 0x6d) {
1784                                 if (sec_number == 1 &&
1785                                     addr == (rest_addr - 1)) {
1786                                         rest_addr = 0x0fff;
1787                                         sec_mask   = 0x1f000;
1788                                 } else if (sec_number == 3 && (addr & 0x7ffe)) {
1789                                         rest_addr = 0x3fff;
1790                                         sec_mask   = 0x1c000;
1791                                 }
1792                         }
1793
1794                         if (qla2x00_program_flash_address(ha, addr, data,
1795                             man_id, flash_id)) {
1796                                 rval = QLA_FUNCTION_FAILED;
1797                                 break;
1798                         }
1799                         cond_resched();
1800                 }
1801         } while (0);
1802         qla2x00_flash_disable(ha);
1803
1804         /* Resume HBA. */
1805         qla2x00_resume_hba(ha);
1806
1807         return rval;
1808 }
1809
1810 uint8_t *
1811 qla24xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1812     uint32_t offset, uint32_t length)
1813 {
1814         /* Suspend HBA. */
1815         scsi_block_requests(ha->host);
1816         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1817
1818         /* Go with read. */
1819         qla24xx_read_flash_data(ha, (uint32_t *)buf, offset >> 2, length >> 2);
1820
1821         /* Resume HBA. */
1822         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1823         scsi_unblock_requests(ha->host);
1824
1825         return buf;
1826 }
1827
1828 int
1829 qla24xx_write_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1830     uint32_t offset, uint32_t length)
1831 {
1832         int rval;
1833
1834         /* Suspend HBA. */
1835         scsi_block_requests(ha->host);
1836         set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1837
1838         /* Go with write. */
1839         rval = qla24xx_write_flash_data(ha, (uint32_t *)buf, offset >> 2,
1840             length >> 2);
1841
1842         /* Resume HBA -- RISC reset needed. */
1843         clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags);
1844         set_bit(ISP_ABORT_NEEDED, &ha->dpc_flags);
1845         qla2xxx_wake_dpc(ha);
1846         qla2x00_wait_for_hba_online(ha);
1847         scsi_unblock_requests(ha->host);
1848
1849         return rval;
1850 }
1851
1852 uint8_t *
1853 qla25xx_read_optrom_data(struct scsi_qla_host *ha, uint8_t *buf,
1854     uint32_t offset, uint32_t length)
1855 {
1856         int rval;
1857         dma_addr_t optrom_dma;
1858         void *optrom;
1859         uint8_t *pbuf;
1860         uint32_t faddr, left, burst;
1861
1862         if (offset & 0xfff)
1863                 goto slow_read;
1864         if (length < OPTROM_BURST_SIZE)
1865                 goto slow_read;
1866
1867         optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1868             &optrom_dma, GFP_KERNEL);
1869         if (!optrom) {
1870                 qla_printk(KERN_DEBUG, ha,
1871                     "Unable to allocate memory for optrom burst read "
1872                     "(%x KB).\n", OPTROM_BURST_SIZE / 1024);
1873
1874                 goto slow_read;
1875         }
1876
1877         pbuf = buf;
1878         faddr = offset >> 2;
1879         left = length >> 2;
1880         burst = OPTROM_BURST_DWORDS;
1881         while (left != 0) {
1882                 if (burst > left)
1883                         burst = left;
1884
1885                 rval = qla2x00_dump_ram(ha, optrom_dma,
1886                     flash_data_to_access_addr(faddr), burst);
1887                 if (rval) {
1888                         qla_printk(KERN_WARNING, ha,
1889                             "Unable to burst-read optrom segment "
1890                             "(%x/%x/%llx).\n", rval,
1891                             flash_data_to_access_addr(faddr),
1892                             (unsigned long long)optrom_dma);
1893                         qla_printk(KERN_WARNING, ha,
1894                             "Reverting to slow-read.\n");
1895
1896                         dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
1897                             optrom, optrom_dma);
1898                         goto slow_read;
1899                 }
1900
1901                 memcpy(pbuf, optrom, burst * 4);
1902
1903                 left -= burst;
1904                 faddr += burst;
1905                 pbuf += burst * 4;
1906         }
1907
1908         dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom,
1909             optrom_dma);
1910
1911         return buf;
1912
1913 slow_read:
1914     return qla24xx_read_optrom_data(ha, buf, offset, length);
1915 }
1916
1917 /**
1918  * qla2x00_get_fcode_version() - Determine an FCODE image's version.
1919  * @ha: HA context
1920  * @pcids: Pointer to the FCODE PCI data structure
1921  *
1922  * The process of retrieving the FCODE version information is at best
1923  * described as interesting.
1924  *
1925  * Within the first 100h bytes of the image an ASCII string is present
1926  * which contains several pieces of information including the FCODE
1927  * version.  Unfortunately it seems the only reliable way to retrieve
1928  * the version is by scanning for another sentinel within the string,
1929  * the FCODE build date:
1930  *
1931  *      ... 2.00.02 10/17/02 ...
1932  *
1933  * Returns QLA_SUCCESS on successful retrieval of version.
1934  */
1935 static void
1936 qla2x00_get_fcode_version(scsi_qla_host_t *ha, uint32_t pcids)
1937 {
1938         int ret = QLA_FUNCTION_FAILED;
1939         uint32_t istart, iend, iter, vend;
1940         uint8_t do_next, rbyte, *vbyte;
1941
1942         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
1943
1944         /* Skip the PCI data structure. */
1945         istart = pcids +
1946             ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) |
1947                 qla2x00_read_flash_byte(ha, pcids + 0x0A));
1948         iend = istart + 0x100;
1949         do {
1950                 /* Scan for the sentinel date string...eeewww. */
1951                 do_next = 0;
1952                 iter = istart;
1953                 while ((iter < iend) && !do_next) {
1954                         iter++;
1955                         if (qla2x00_read_flash_byte(ha, iter) == '/') {
1956                                 if (qla2x00_read_flash_byte(ha, iter + 2) ==
1957                                     '/')
1958                                         do_next++;
1959                                 else if (qla2x00_read_flash_byte(ha,
1960                                     iter + 3) == '/')
1961                                         do_next++;
1962                         }
1963                 }
1964                 if (!do_next)
1965                         break;
1966
1967                 /* Backtrack to previous ' ' (space). */
1968                 do_next = 0;
1969                 while ((iter > istart) && !do_next) {
1970                         iter--;
1971                         if (qla2x00_read_flash_byte(ha, iter) == ' ')
1972                                 do_next++;
1973                 }
1974                 if (!do_next)
1975                         break;
1976
1977                 /*
1978                  * Mark end of version tag, and find previous ' ' (space) or
1979                  * string length (recent FCODE images -- major hack ahead!!!).
1980                  */
1981                 vend = iter - 1;
1982                 do_next = 0;
1983                 while ((iter > istart) && !do_next) {
1984                         iter--;
1985                         rbyte = qla2x00_read_flash_byte(ha, iter);
1986                         if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10)
1987                                 do_next++;
1988                 }
1989                 if (!do_next)
1990                         break;
1991
1992                 /* Mark beginning of version tag, and copy data. */
1993                 iter++;
1994                 if ((vend - iter) &&
1995                     ((vend - iter) < sizeof(ha->fcode_revision))) {
1996                         vbyte = ha->fcode_revision;
1997                         while (iter <= vend) {
1998                                 *vbyte++ = qla2x00_read_flash_byte(ha, iter);
1999                                 iter++;
2000                         }
2001                         ret = QLA_SUCCESS;
2002                 }
2003         } while (0);
2004
2005         if (ret != QLA_SUCCESS)
2006                 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2007 }
2008
2009 int
2010 qla2x00_get_flash_version(scsi_qla_host_t *ha, void *mbuf)
2011 {
2012         int ret = QLA_SUCCESS;
2013         uint8_t code_type, last_image;
2014         uint32_t pcihdr, pcids;
2015         uint8_t *dbyte;
2016         uint16_t *dcode;
2017
2018         if (!ha->pio_address || !mbuf)
2019                 return QLA_FUNCTION_FAILED;
2020
2021         memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2022         memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2023         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2024         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2025
2026         qla2x00_flash_enable(ha);
2027
2028         /* Begin with first PCI expansion ROM header. */
2029         pcihdr = 0;
2030         last_image = 1;
2031         do {
2032                 /* Verify PCI expansion ROM header. */
2033                 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 ||
2034                     qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) {
2035                         /* No signature */
2036                         DEBUG2(printk("scsi(%ld): No matching ROM "
2037                             "signature.\n", ha->host_no));
2038                         ret = QLA_FUNCTION_FAILED;
2039                         break;
2040                 }
2041
2042                 /* Locate PCI data structure. */
2043                 pcids = pcihdr +
2044                     ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) |
2045                         qla2x00_read_flash_byte(ha, pcihdr + 0x18));
2046
2047                 /* Validate signature of PCI data structure. */
2048                 if (qla2x00_read_flash_byte(ha, pcids) != 'P' ||
2049                     qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' ||
2050                     qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' ||
2051                     qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') {
2052                         /* Incorrect header. */
2053                         DEBUG2(printk("%s(): PCI data struct not found "
2054                             "pcir_adr=%x.\n", __func__, pcids));
2055                         ret = QLA_FUNCTION_FAILED;
2056                         break;
2057                 }
2058
2059                 /* Read version */
2060                 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14);
2061                 switch (code_type) {
2062                 case ROM_CODE_TYPE_BIOS:
2063                         /* Intel x86, PC-AT compatible. */
2064                         ha->bios_revision[0] =
2065                             qla2x00_read_flash_byte(ha, pcids + 0x12);
2066                         ha->bios_revision[1] =
2067                             qla2x00_read_flash_byte(ha, pcids + 0x13);
2068                         DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__,
2069                             ha->bios_revision[1], ha->bios_revision[0]));
2070                         break;
2071                 case ROM_CODE_TYPE_FCODE:
2072                         /* Open Firmware standard for PCI (FCode). */
2073                         /* Eeeewww... */
2074                         qla2x00_get_fcode_version(ha, pcids);
2075                         break;
2076                 case ROM_CODE_TYPE_EFI:
2077                         /* Extensible Firmware Interface (EFI). */
2078                         ha->efi_revision[0] =
2079                             qla2x00_read_flash_byte(ha, pcids + 0x12);
2080                         ha->efi_revision[1] =
2081                             qla2x00_read_flash_byte(ha, pcids + 0x13);
2082                         DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__,
2083                             ha->efi_revision[1], ha->efi_revision[0]));
2084                         break;
2085                 default:
2086                         DEBUG2(printk("%s(): Unrecognized code type %x at "
2087                             "pcids %x.\n", __func__, code_type, pcids));
2088                         break;
2089                 }
2090
2091                 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7;
2092
2093                 /* Locate next PCI expansion ROM. */
2094                 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) |
2095                     qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512;
2096         } while (!last_image);
2097
2098         if (IS_QLA2322(ha)) {
2099                 /* Read firmware image information. */
2100                 memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2101                 dbyte = mbuf;
2102                 memset(dbyte, 0, 8);
2103                 dcode = (uint16_t *)dbyte;
2104
2105                 qla2x00_read_flash_data(ha, dbyte, FA_RISC_CODE_ADDR * 4 + 10,
2106                     8);
2107                 DEBUG3(printk("%s(%ld): dumping fw ver from flash:\n",
2108                     __func__, ha->host_no));
2109                 DEBUG3(qla2x00_dump_buffer((uint8_t *)dbyte, 8));
2110
2111                 if ((dcode[0] == 0xffff && dcode[1] == 0xffff &&
2112                     dcode[2] == 0xffff && dcode[3] == 0xffff) ||
2113                     (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2114                     dcode[3] == 0)) {
2115                         DEBUG2(printk("%s(): Unrecognized fw revision at "
2116                             "%x.\n", __func__, FA_RISC_CODE_ADDR * 4));
2117                 } else {
2118                         /* values are in big endian */
2119                         ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1];
2120                         ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3];
2121                         ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5];
2122                 }
2123         }
2124
2125         qla2x00_flash_disable(ha);
2126
2127         return ret;
2128 }
2129
2130 int
2131 qla24xx_get_flash_version(scsi_qla_host_t *ha, void *mbuf)
2132 {
2133         int ret = QLA_SUCCESS;
2134         uint32_t pcihdr, pcids;
2135         uint32_t *dcode;
2136         uint8_t *bcode;
2137         uint8_t code_type, last_image;
2138         int i;
2139
2140         if (!mbuf)
2141                 return QLA_FUNCTION_FAILED;
2142
2143         memset(ha->bios_revision, 0, sizeof(ha->bios_revision));
2144         memset(ha->efi_revision, 0, sizeof(ha->efi_revision));
2145         memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision));
2146         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2147
2148         dcode = mbuf;
2149
2150         /* Begin with first PCI expansion ROM header. */
2151         pcihdr = 0;
2152         last_image = 1;
2153         do {
2154                 /* Verify PCI expansion ROM header. */
2155                 qla24xx_read_flash_data(ha, dcode, pcihdr >> 2, 0x20);
2156                 bcode = mbuf + (pcihdr % 4);
2157                 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) {
2158                         /* No signature */
2159                         DEBUG2(printk("scsi(%ld): No matching ROM "
2160                             "signature.\n", ha->host_no));
2161                         ret = QLA_FUNCTION_FAILED;
2162                         break;
2163                 }
2164
2165                 /* Locate PCI data structure. */
2166                 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]);
2167
2168                 qla24xx_read_flash_data(ha, dcode, pcids >> 2, 0x20);
2169                 bcode = mbuf + (pcihdr % 4);
2170
2171                 /* Validate signature of PCI data structure. */
2172                 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' ||
2173                     bcode[0x2] != 'I' || bcode[0x3] != 'R') {
2174                         /* Incorrect header. */
2175                         DEBUG2(printk("%s(): PCI data struct not found "
2176                             "pcir_adr=%x.\n", __func__, pcids));
2177                         ret = QLA_FUNCTION_FAILED;
2178                         break;
2179                 }
2180
2181                 /* Read version */
2182                 code_type = bcode[0x14];
2183                 switch (code_type) {
2184                 case ROM_CODE_TYPE_BIOS:
2185                         /* Intel x86, PC-AT compatible. */
2186                         ha->bios_revision[0] = bcode[0x12];
2187                         ha->bios_revision[1] = bcode[0x13];
2188                         DEBUG3(printk("%s(): read BIOS %d.%d.\n", __func__,
2189                             ha->bios_revision[1], ha->bios_revision[0]));
2190                         break;
2191                 case ROM_CODE_TYPE_FCODE:
2192                         /* Open Firmware standard for PCI (FCode). */
2193                         ha->fcode_revision[0] = bcode[0x12];
2194                         ha->fcode_revision[1] = bcode[0x13];
2195                         DEBUG3(printk("%s(): read FCODE %d.%d.\n", __func__,
2196                             ha->fcode_revision[1], ha->fcode_revision[0]));
2197                         break;
2198                 case ROM_CODE_TYPE_EFI:
2199                         /* Extensible Firmware Interface (EFI). */
2200                         ha->efi_revision[0] = bcode[0x12];
2201                         ha->efi_revision[1] = bcode[0x13];
2202                         DEBUG3(printk("%s(): read EFI %d.%d.\n", __func__,
2203                             ha->efi_revision[1], ha->efi_revision[0]));
2204                         break;
2205                 default:
2206                         DEBUG2(printk("%s(): Unrecognized code type %x at "
2207                             "pcids %x.\n", __func__, code_type, pcids));
2208                         break;
2209                 }
2210
2211                 last_image = bcode[0x15] & BIT_7;
2212
2213                 /* Locate next PCI expansion ROM. */
2214                 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512;
2215         } while (!last_image);
2216
2217         /* Read firmware image information. */
2218         memset(ha->fw_revision, 0, sizeof(ha->fw_revision));
2219         dcode = mbuf;
2220
2221         qla24xx_read_flash_data(ha, dcode, FA_RISC_CODE_ADDR + 4, 4);
2222         for (i = 0; i < 4; i++)
2223                 dcode[i] = be32_to_cpu(dcode[i]);
2224
2225         if ((dcode[0] == 0xffffffff && dcode[1] == 0xffffffff &&
2226             dcode[2] == 0xffffffff && dcode[3] == 0xffffffff) ||
2227             (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 &&
2228             dcode[3] == 0)) {
2229                 DEBUG2(printk("%s(): Unrecognized fw version at %x.\n",
2230                     __func__, FA_RISC_CODE_ADDR));
2231         } else {
2232                 ha->fw_revision[0] = dcode[0];
2233                 ha->fw_revision[1] = dcode[1];
2234                 ha->fw_revision[2] = dcode[2];
2235                 ha->fw_revision[3] = dcode[3];
2236         }
2237
2238         return ret;
2239 }
2240
2241 static int
2242 qla2xxx_hw_event_store(scsi_qla_host_t *ha, uint32_t *fdata)
2243 {
2244         uint32_t d[2], faddr;
2245
2246         /* Locate first empty entry. */
2247         for (;;) {
2248                 if (ha->hw_event_ptr >=
2249                     ha->hw_event_start + FA_HW_EVENT_SIZE) {
2250                         DEBUG2(qla_printk(KERN_WARNING, ha,
2251                             "HW event -- Log Full!\n"));
2252                         return QLA_MEMORY_ALLOC_FAILED;
2253                 }
2254
2255                 qla24xx_read_flash_data(ha, d, ha->hw_event_ptr, 2);
2256                 faddr = flash_data_to_access_addr(ha->hw_event_ptr);
2257                 ha->hw_event_ptr += FA_HW_EVENT_ENTRY_SIZE;
2258                 if (d[0] == __constant_cpu_to_le32(0xffffffff) &&
2259                     d[1] == __constant_cpu_to_le32(0xffffffff)) {
2260                         qla24xx_unprotect_flash(ha);
2261
2262                         qla24xx_write_flash_dword(ha, faddr++,
2263                             cpu_to_le32(jiffies));
2264                         qla24xx_write_flash_dword(ha, faddr++, 0);
2265                         qla24xx_write_flash_dword(ha, faddr++, *fdata++);
2266                         qla24xx_write_flash_dword(ha, faddr++, *fdata);
2267
2268                         qla24xx_protect_flash(ha);
2269                         break;
2270                 }
2271         }
2272         return QLA_SUCCESS;
2273 }
2274
2275 int
2276 qla2xxx_hw_event_log(scsi_qla_host_t *ha, uint16_t code, uint16_t d1,
2277     uint16_t d2, uint16_t d3)
2278 {
2279 #define QMARK(a, b, c, d) \
2280     cpu_to_le32(LSB(a) << 24 | LSB(b) << 16 | LSB(c) << 8 | LSB(d))
2281
2282         int rval;
2283         uint32_t marker[2], fdata[4];
2284
2285         if (ha->hw_event_start == 0)
2286                 return QLA_FUNCTION_FAILED;
2287
2288         DEBUG2(qla_printk(KERN_WARNING, ha,
2289             "HW event -- code=%x, d1=%x, d2=%x, d3=%x.\n", code, d1, d2, d3));
2290
2291         /* If marker not already found, locate or write.  */
2292         if (!ha->flags.hw_event_marker_found) {
2293                 /* Create marker. */
2294                 marker[0] = QMARK('L', ha->fw_major_version,
2295                     ha->fw_minor_version, ha->fw_subminor_version);
2296                 marker[1] = QMARK(QLA_DRIVER_MAJOR_VER, QLA_DRIVER_MINOR_VER,
2297                     QLA_DRIVER_PATCH_VER, QLA_DRIVER_BETA_VER);
2298
2299                 /* Locate marker. */
2300                 ha->hw_event_ptr = ha->hw_event_start;
2301                 for (;;) {
2302                         qla24xx_read_flash_data(ha, fdata, ha->hw_event_ptr,
2303                             4);
2304                         if (fdata[0] == __constant_cpu_to_le32(0xffffffff) &&
2305                             fdata[1] == __constant_cpu_to_le32(0xffffffff))
2306                                 break;
2307                         ha->hw_event_ptr += FA_HW_EVENT_ENTRY_SIZE;
2308                         if (ha->hw_event_ptr >=
2309                             ha->hw_event_start + FA_HW_EVENT_SIZE) {
2310                                 DEBUG2(qla_printk(KERN_WARNING, ha,
2311                                     "HW event -- Log Full!\n"));
2312                                 return QLA_MEMORY_ALLOC_FAILED;
2313                         }
2314                         if (fdata[2] == marker[0] && fdata[3] == marker[1]) {
2315                                 ha->flags.hw_event_marker_found = 1;
2316                                 break;
2317                         }
2318                 }
2319                 /* No marker, write it. */
2320                 if (!ha->flags.hw_event_marker_found) {
2321                         rval = qla2xxx_hw_event_store(ha, marker);
2322                         if (rval != QLA_SUCCESS) {
2323                                 DEBUG2(qla_printk(KERN_WARNING, ha,
2324                                     "HW event -- Failed marker write=%x.!\n",
2325                                     rval));
2326                                 return rval;
2327                         }
2328                         ha->flags.hw_event_marker_found = 1;
2329                 }
2330         }
2331
2332         /* Store error.  */
2333         fdata[0] = cpu_to_le32(code << 16 | d1);
2334         fdata[1] = cpu_to_le32(d2 << 16 | d3);
2335         rval = qla2xxx_hw_event_store(ha, fdata);
2336         if (rval != QLA_SUCCESS) {
2337                 DEBUG2(qla_printk(KERN_WARNING, ha,
2338                     "HW event -- Failed error write=%x.!\n",
2339                     rval));
2340         }
2341
2342         return rval;
2343 }