2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2005 QLogic Corporation
5 * See LICENSE.qla2xxx for copyright and licensing details.
9 #include <linux/delay.h>
10 #include <asm/uaccess.h>
12 static uint16_t qla2x00_nvram_request(scsi_qla_host_t *, uint32_t);
13 static void qla2x00_nv_deselect(scsi_qla_host_t *);
14 static void qla2x00_nv_write(scsi_qla_host_t *, uint16_t);
17 * NVRAM support routines
21 * qla2x00_lock_nvram_access() -
25 qla2x00_lock_nvram_access(scsi_qla_host_t *ha)
28 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
30 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
31 data = RD_REG_WORD(®->nvram);
32 while (data & NVR_BUSY) {
34 data = RD_REG_WORD(®->nvram);
38 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1);
39 RD_REG_WORD(®->u.isp2300.host_semaphore);
41 data = RD_REG_WORD(®->u.isp2300.host_semaphore);
42 while ((data & BIT_0) == 0) {
45 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0x1);
46 RD_REG_WORD(®->u.isp2300.host_semaphore);
48 data = RD_REG_WORD(®->u.isp2300.host_semaphore);
54 * qla2x00_unlock_nvram_access() -
58 qla2x00_unlock_nvram_access(scsi_qla_host_t *ha)
60 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
62 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) {
63 WRT_REG_WORD(®->u.isp2300.host_semaphore, 0);
64 RD_REG_WORD(®->u.isp2300.host_semaphore);
69 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the
70 * request routine to get the word from NVRAM.
72 * @addr: Address in NVRAM to read
74 * Returns the word read from nvram @addr.
77 qla2x00_get_nvram_word(scsi_qla_host_t *ha, uint32_t addr)
84 data = qla2x00_nvram_request(ha, nv_cmd);
90 * qla2x00_write_nvram_word() - Write NVRAM data.
92 * @addr: Address in NVRAM to write
93 * @data: word to program
96 qla2x00_write_nvram_word(scsi_qla_host_t *ha, uint32_t addr, uint16_t data)
101 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
103 qla2x00_nv_write(ha, NVR_DATA_OUT);
104 qla2x00_nv_write(ha, 0);
105 qla2x00_nv_write(ha, 0);
107 for (word = 0; word < 8; word++)
108 qla2x00_nv_write(ha, NVR_DATA_OUT);
110 qla2x00_nv_deselect(ha);
113 nv_cmd = (addr << 16) | NV_WRITE_OP;
116 for (count = 0; count < 27; count++) {
118 qla2x00_nv_write(ha, NVR_DATA_OUT);
120 qla2x00_nv_write(ha, 0);
125 qla2x00_nv_deselect(ha);
127 /* Wait for NVRAM to become ready */
128 WRT_REG_WORD(®->nvram, NVR_SELECT);
129 RD_REG_WORD(®->nvram); /* PCI Posting. */
132 word = RD_REG_WORD(®->nvram);
133 } while ((word & NVR_DATA_IN) == 0);
135 qla2x00_nv_deselect(ha);
138 qla2x00_nv_write(ha, NVR_DATA_OUT);
139 for (count = 0; count < 10; count++)
140 qla2x00_nv_write(ha, 0);
142 qla2x00_nv_deselect(ha);
146 qla2x00_write_nvram_word_tmo(scsi_qla_host_t *ha, uint32_t addr, uint16_t data,
152 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
156 qla2x00_nv_write(ha, NVR_DATA_OUT);
157 qla2x00_nv_write(ha, 0);
158 qla2x00_nv_write(ha, 0);
160 for (word = 0; word < 8; word++)
161 qla2x00_nv_write(ha, NVR_DATA_OUT);
163 qla2x00_nv_deselect(ha);
166 nv_cmd = (addr << 16) | NV_WRITE_OP;
169 for (count = 0; count < 27; count++) {
171 qla2x00_nv_write(ha, NVR_DATA_OUT);
173 qla2x00_nv_write(ha, 0);
178 qla2x00_nv_deselect(ha);
180 /* Wait for NVRAM to become ready */
181 WRT_REG_WORD(®->nvram, NVR_SELECT);
182 RD_REG_WORD(®->nvram); /* PCI Posting. */
185 word = RD_REG_WORD(®->nvram);
187 ret = QLA_FUNCTION_FAILED;
190 } while ((word & NVR_DATA_IN) == 0);
192 qla2x00_nv_deselect(ha);
195 qla2x00_nv_write(ha, NVR_DATA_OUT);
196 for (count = 0; count < 10; count++)
197 qla2x00_nv_write(ha, 0);
199 qla2x00_nv_deselect(ha);
205 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from
208 * @nv_cmd: NVRAM command
210 * Bit definitions for NVRAM command:
213 * Bit 25, 24 = opcode
214 * Bit 23-16 = address
215 * Bit 15-0 = write data
217 * Returns the word read from nvram @addr.
220 qla2x00_nvram_request(scsi_qla_host_t *ha, uint32_t nv_cmd)
223 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
227 /* Send command to NVRAM. */
229 for (cnt = 0; cnt < 11; cnt++) {
231 qla2x00_nv_write(ha, NVR_DATA_OUT);
233 qla2x00_nv_write(ha, 0);
237 /* Read data from NVRAM. */
238 for (cnt = 0; cnt < 16; cnt++) {
239 WRT_REG_WORD(®->nvram, NVR_SELECT | NVR_CLOCK);
240 RD_REG_WORD(®->nvram); /* PCI Posting. */
243 reg_data = RD_REG_WORD(®->nvram);
244 if (reg_data & NVR_DATA_IN)
246 WRT_REG_WORD(®->nvram, NVR_SELECT);
247 RD_REG_WORD(®->nvram); /* PCI Posting. */
252 WRT_REG_WORD(®->nvram, NVR_DESELECT);
253 RD_REG_WORD(®->nvram); /* PCI Posting. */
260 * qla2x00_nv_write() - Clean NVRAM operations.
264 qla2x00_nv_deselect(scsi_qla_host_t *ha)
266 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
268 WRT_REG_WORD(®->nvram, NVR_DESELECT);
269 RD_REG_WORD(®->nvram); /* PCI Posting. */
274 * qla2x00_nv_write() - Prepare for NVRAM read/write operation.
276 * @data: Serial interface selector
279 qla2x00_nv_write(scsi_qla_host_t *ha, uint16_t data)
281 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
283 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
284 RD_REG_WORD(®->nvram); /* PCI Posting. */
286 WRT_REG_WORD(®->nvram, data | NVR_SELECT| NVR_CLOCK |
288 RD_REG_WORD(®->nvram); /* PCI Posting. */
290 WRT_REG_WORD(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE);
291 RD_REG_WORD(®->nvram); /* PCI Posting. */
296 * qla2x00_clear_nvram_protection() -
300 qla2x00_clear_nvram_protection(scsi_qla_host_t *ha)
303 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
305 uint16_t wprot, wprot_old;
307 /* Clear NVRAM write protection. */
308 ret = QLA_FUNCTION_FAILED;
309 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, 0));
310 stat = qla2x00_write_nvram_word_tmo(ha, 0,
311 __constant_cpu_to_le16(0x1234), 100000);
312 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, 0));
313 if (stat != QLA_SUCCESS || wprot != __constant_cpu_to_le16(0x1234)) {
315 qla2x00_nv_write(ha, NVR_DATA_OUT);
316 qla2x00_nv_write(ha, 0);
317 qla2x00_nv_write(ha, 0);
318 for (word = 0; word < 8; word++)
319 qla2x00_nv_write(ha, NVR_DATA_OUT);
321 qla2x00_nv_deselect(ha);
323 /* Enable protection register. */
324 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
325 qla2x00_nv_write(ha, NVR_PR_ENABLE);
326 qla2x00_nv_write(ha, NVR_PR_ENABLE);
327 for (word = 0; word < 8; word++)
328 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
330 qla2x00_nv_deselect(ha);
332 /* Clear protection register (ffff is cleared). */
333 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
334 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
335 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
336 for (word = 0; word < 8; word++)
337 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
339 qla2x00_nv_deselect(ha);
341 /* Wait for NVRAM to become ready. */
342 WRT_REG_WORD(®->nvram, NVR_SELECT);
343 RD_REG_WORD(®->nvram); /* PCI Posting. */
346 word = RD_REG_WORD(®->nvram);
347 } while ((word & NVR_DATA_IN) == 0);
351 qla2x00_write_nvram_word(ha, 0, wprot_old);
357 qla2x00_set_nvram_protection(scsi_qla_host_t *ha, int stat)
359 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
362 if (stat != QLA_SUCCESS)
365 /* Set NVRAM write protection. */
367 qla2x00_nv_write(ha, NVR_DATA_OUT);
368 qla2x00_nv_write(ha, 0);
369 qla2x00_nv_write(ha, 0);
370 for (word = 0; word < 8; word++)
371 qla2x00_nv_write(ha, NVR_DATA_OUT);
373 qla2x00_nv_deselect(ha);
375 /* Enable protection register. */
376 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
377 qla2x00_nv_write(ha, NVR_PR_ENABLE);
378 qla2x00_nv_write(ha, NVR_PR_ENABLE);
379 for (word = 0; word < 8; word++)
380 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE);
382 qla2x00_nv_deselect(ha);
384 /* Enable protection register. */
385 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
386 qla2x00_nv_write(ha, NVR_PR_ENABLE);
387 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT);
388 for (word = 0; word < 8; word++)
389 qla2x00_nv_write(ha, NVR_PR_ENABLE);
391 qla2x00_nv_deselect(ha);
393 /* Wait for NVRAM to become ready. */
394 WRT_REG_WORD(®->nvram, NVR_SELECT);
395 RD_REG_WORD(®->nvram); /* PCI Posting. */
398 word = RD_REG_WORD(®->nvram);
399 } while ((word & NVR_DATA_IN) == 0);
403 /*****************************************************************************/
404 /* Flash Manipulation Routines */
405 /*****************************************************************************/
407 static inline uint32_t
408 flash_conf_to_access_addr(uint32_t faddr)
410 return FARX_ACCESS_FLASH_CONF | faddr;
413 static inline uint32_t
414 flash_data_to_access_addr(uint32_t faddr)
416 return FARX_ACCESS_FLASH_DATA | faddr;
419 static inline uint32_t
420 nvram_conf_to_access_addr(uint32_t naddr)
422 return FARX_ACCESS_NVRAM_CONF | naddr;
425 static inline uint32_t
426 nvram_data_to_access_addr(uint32_t naddr)
428 return FARX_ACCESS_NVRAM_DATA | naddr;
432 qla24xx_read_flash_dword(scsi_qla_host_t *ha, uint32_t addr)
436 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
438 WRT_REG_DWORD(®->flash_addr, addr & ~FARX_DATA_FLAG);
439 /* Wait for READ cycle to complete. */
442 (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) == 0 &&
443 rval == QLA_SUCCESS; cnt--) {
447 rval = QLA_FUNCTION_TIMEOUT;
450 /* TODO: What happens if we time out? */
452 if (rval == QLA_SUCCESS)
453 data = RD_REG_DWORD(®->flash_data);
459 qla24xx_read_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
464 /* Dword reads to flash. */
465 for (i = 0; i < dwords; i++, faddr++)
466 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
467 flash_data_to_access_addr(faddr)));
473 qla24xx_write_flash_dword(scsi_qla_host_t *ha, uint32_t addr, uint32_t data)
477 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
479 WRT_REG_DWORD(®->flash_data, data);
480 RD_REG_DWORD(®->flash_data); /* PCI Posting. */
481 WRT_REG_DWORD(®->flash_addr, addr | FARX_DATA_FLAG);
482 /* Wait for Write cycle to complete. */
484 for (cnt = 500000; (RD_REG_DWORD(®->flash_addr) & FARX_DATA_FLAG) &&
485 rval == QLA_SUCCESS; cnt--) {
489 rval = QLA_FUNCTION_TIMEOUT;
495 qla24xx_get_flash_manufacturer(scsi_qla_host_t *ha, uint8_t *man_id,
500 ids = qla24xx_read_flash_dword(ha, flash_data_to_access_addr(0xd03ab));
502 *flash_id = MSB(ids);
506 qla24xx_write_flash_data(scsi_qla_host_t *ha, uint32_t *dwptr, uint32_t faddr,
511 uint32_t sec_mask, rest_addr, conf_addr;
513 uint8_t man_id, flash_id;
514 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
518 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id);
519 DEBUG9(printk("%s(%ld): Flash man_id=%d flash_id=%d\n", __func__,
520 ha->host_no, man_id, flash_id));
522 conf_addr = flash_conf_to_access_addr(0x03d8);
524 case 0xbf: /* STT flash. */
527 if (flash_id == 0x80)
528 conf_addr = flash_conf_to_access_addr(0x0352);
530 case 0x13: /* ST M25P80. */
535 /* Default to 64 kb sector size. */
541 /* Enable flash write. */
542 WRT_REG_DWORD(®->ctrl_status,
543 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE);
544 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */
546 /* Disable flash write-protection. */
547 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0);
549 do { /* Loop once to provide quick error exit. */
550 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) {
551 /* Are we at the beginning of a sector? */
552 if ((faddr & rest_addr) == 0) {
553 fdata = (faddr & sec_mask) << 2;
554 ret = qla24xx_write_flash_dword(ha, conf_addr,
555 (fdata & 0xff00) |((fdata << 16) &
556 0xff0000) | ((fdata >> 16) & 0xff));
557 if (ret != QLA_SUCCESS) {
558 DEBUG9(printk("%s(%ld) Unable to flash "
559 "sector: address=%x.\n", __func__,
560 ha->host_no, faddr));
564 ret = qla24xx_write_flash_dword(ha,
565 flash_data_to_access_addr(faddr),
566 cpu_to_le32(*dwptr));
567 if (ret != QLA_SUCCESS) {
568 DEBUG9(printk("%s(%ld) Unable to program flash "
569 "address=%x data=%x.\n", __func__,
570 ha->host_no, faddr, *dwptr));
576 /* Enable flash write-protection. */
577 qla24xx_write_flash_dword(ha, flash_conf_to_access_addr(0x101), 0x9c);
579 /* Disable flash write. */
580 WRT_REG_DWORD(®->ctrl_status,
581 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE);
582 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */
588 qla2x00_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
594 /* Word reads to NVRAM via registers. */
595 wptr = (uint16_t *)buf;
596 qla2x00_lock_nvram_access(ha);
597 for (i = 0; i < bytes >> 1; i++, naddr++)
598 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha,
600 qla2x00_unlock_nvram_access(ha);
606 qla24xx_read_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
612 /* Dword reads to flash. */
613 dwptr = (uint32_t *)buf;
614 for (i = 0; i < bytes >> 2; i++, naddr++)
615 dwptr[i] = cpu_to_le32(qla24xx_read_flash_dword(ha,
616 nvram_data_to_access_addr(naddr)));
622 qla2x00_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
631 qla2x00_lock_nvram_access(ha);
633 /* Disable NVRAM write-protection. */
634 stat = qla2x00_clear_nvram_protection(ha);
636 wptr = (uint16_t *)buf;
637 for (i = 0; i < bytes >> 1; i++, naddr++) {
638 qla2x00_write_nvram_word(ha, naddr,
643 /* Enable NVRAM write-protection. */
644 qla2x00_set_nvram_protection(ha, stat);
646 qla2x00_unlock_nvram_access(ha);
652 qla24xx_write_nvram_data(scsi_qla_host_t *ha, uint8_t *buf, uint32_t naddr,
658 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
662 /* Enable flash write. */
663 WRT_REG_DWORD(®->ctrl_status,
664 RD_REG_DWORD(®->ctrl_status) | CSRX_FLASH_ENABLE);
665 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */
667 /* Disable NVRAM write-protection. */
668 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
670 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
673 /* Dword writes to flash. */
674 dwptr = (uint32_t *)buf;
675 for (i = 0; i < bytes >> 2; i++, naddr++, dwptr++) {
676 ret = qla24xx_write_flash_dword(ha,
677 nvram_data_to_access_addr(naddr),
678 cpu_to_le32(*dwptr));
679 if (ret != QLA_SUCCESS) {
680 DEBUG9(printk("%s(%ld) Unable to program "
681 "nvram address=%x data=%x.\n", __func__,
682 ha->host_no, naddr, *dwptr));
687 /* Enable NVRAM write-protection. */
688 qla24xx_write_flash_dword(ha, nvram_conf_to_access_addr(0x101),
691 /* Disable flash write. */
692 WRT_REG_DWORD(®->ctrl_status,
693 RD_REG_DWORD(®->ctrl_status) & ~CSRX_FLASH_ENABLE);
694 RD_REG_DWORD(®->ctrl_status); /* PCI Posting. */