2 mvsas.c - Marvell 88SE6440 SAS/SATA support
4 Copyright 2007 Red Hat, Inc.
5 Copyright 2008 Marvell. <kewei@marvell.com>
7 This program is free software; you can redistribute it and/or
8 modify it under the terms of the GNU General Public License as
9 published by the Free Software Foundation; either version 2,
10 or (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty
14 of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
15 See the GNU General Public License for more details.
17 You should have received a copy of the GNU General Public
18 License along with this program; see the file COPYING. If not,
19 write to the Free Software Foundation, 675 Mass Ave, Cambridge,
22 ---------------------------------------------------------------
25 * hardware supports controlling the endian-ness of data
26 structures. this permits elimination of all the le32_to_cpu()
27 and cpu_to_le32() conversions.
31 #include <linux/kernel.h>
32 #include <linux/module.h>
33 #include <linux/pci.h>
34 #include <linux/interrupt.h>
35 #include <linux/spinlock.h>
36 #include <linux/delay.h>
37 #include <linux/dma-mapping.h>
38 #include <linux/ctype.h>
39 #include <scsi/libsas.h>
40 #include <scsi/scsi_tcq.h>
41 #include <scsi/sas_ata.h>
44 #define DRV_NAME "mvsas"
45 #define DRV_VERSION "0.5.2"
47 #define MVS_DISABLE_NVRAM
48 #define MVS_DISABLE_MSI
50 #define mr32(reg) readl(regs + MVS_##reg)
51 #define mw32(reg,val) writel((val), regs + MVS_##reg)
52 #define mw32_f(reg,val) do { \
53 writel((val), regs + MVS_##reg); \
54 readl(regs + MVS_##reg); \
57 #define MVS_ID_NOT_MAPPED 0x7f
58 #define MVS_CHIP_SLOT_SZ (1U << mvi->chip->slot_width)
60 /* offset for D2H FIS in the Received FIS List Structure */
61 #define SATA_RECEIVED_D2H_FIS(reg_set) \
62 ((void *) mvi->rx_fis + 0x400 + 0x100 * reg_set + 0x40)
63 #define SATA_RECEIVED_PIO_FIS(reg_set) \
64 ((void *) mvi->rx_fis + 0x400 + 0x100 * reg_set + 0x20)
65 #define UNASSOC_D2H_FIS(id) \
66 ((void *) mvi->rx_fis + 0x100 * id)
68 #define for_each_phy(__lseq_mask, __mc, __lseq, __rest) \
69 for ((__mc) = (__lseq_mask), (__lseq) = 0; \
70 (__mc) != 0 && __rest; \
71 (++__lseq), (__mc) >>= 1)
73 /* driver compile-time configuration */
74 enum driver_configuration {
75 MVS_TX_RING_SZ = 1024, /* TX ring size (12-bit) */
76 MVS_RX_RING_SZ = 1024, /* RX ring size (12-bit) */
77 /* software requires power-of-2
80 MVS_SLOTS = 512, /* command slots */
81 MVS_SLOT_BUF_SZ = 8192, /* cmd tbl + IU + status + PRD */
82 MVS_SSP_CMD_SZ = 64, /* SSP command table buffer size */
83 MVS_ATA_CMD_SZ = 96, /* SATA command table buffer size */
84 MVS_OAF_SZ = 64, /* Open address frame buffer size */
86 MVS_RX_FIS_COUNT = 17, /* Optional rx'd FISs (max 17) */
88 MVS_QUEUE_SIZE = 30, /* Support Queue depth */
89 MVS_CAN_QUEUE = MVS_SLOTS - 1, /* SCSI Queue depth */
92 /* unchangeable hardware details */
93 enum hardware_details {
94 MVS_MAX_PHYS = 8, /* max. possible phys */
95 MVS_MAX_PORTS = 8, /* max. possible ports */
96 MVS_RX_FISL_SZ = 0x400 + (MVS_RX_FIS_COUNT * 0x100),
99 /* peripheral registers (BAR2) */
100 enum peripheral_registers {
101 SPI_CTL = 0x10, /* EEPROM control */
102 SPI_CMD = 0x14, /* EEPROM command */
103 SPI_DATA = 0x18, /* EEPROM data */
106 enum peripheral_register_bits {
107 TWSI_RDY = (1U << 7), /* EEPROM interface ready */
108 TWSI_RD = (1U << 4), /* EEPROM read access */
110 SPI_ADDR_MASK = 0x3ffff, /* bits 17:0 */
113 /* enhanced mode registers (BAR4) */
115 MVS_GBL_CTL = 0x04, /* global control */
116 MVS_GBL_INT_STAT = 0x08, /* global irq status */
117 MVS_GBL_PI = 0x0C, /* ports implemented bitmask */
118 MVS_GBL_PORT_TYPE = 0xa0, /* port type */
120 MVS_CTL = 0x100, /* SAS/SATA port configuration */
121 MVS_PCS = 0x104, /* SAS/SATA port control/status */
122 MVS_CMD_LIST_LO = 0x108, /* cmd list addr */
123 MVS_CMD_LIST_HI = 0x10C,
124 MVS_RX_FIS_LO = 0x110, /* RX FIS list addr */
125 MVS_RX_FIS_HI = 0x114,
127 MVS_TX_CFG = 0x120, /* TX configuration */
128 MVS_TX_LO = 0x124, /* TX (delivery) ring addr */
131 MVS_TX_PROD_IDX = 0x12C, /* TX producer pointer */
132 MVS_TX_CONS_IDX = 0x130, /* TX consumer pointer (RO) */
133 MVS_RX_CFG = 0x134, /* RX configuration */
134 MVS_RX_LO = 0x138, /* RX (completion) ring addr */
136 MVS_RX_CONS_IDX = 0x140, /* RX consumer pointer (RO) */
138 MVS_INT_COAL = 0x148, /* Int coalescing config */
139 MVS_INT_COAL_TMOUT = 0x14C, /* Int coalescing timeout */
140 MVS_INT_STAT = 0x150, /* Central int status */
141 MVS_INT_MASK = 0x154, /* Central int enable */
142 MVS_INT_STAT_SRS = 0x158, /* SATA register set status */
143 MVS_INT_MASK_SRS = 0x15C,
145 /* ports 1-3 follow after this */
146 MVS_P0_INT_STAT = 0x160, /* port0 interrupt status */
147 MVS_P0_INT_MASK = 0x164, /* port0 interrupt mask */
148 MVS_P4_INT_STAT = 0x200, /* Port 4 interrupt status */
149 MVS_P4_INT_MASK = 0x204, /* Port 4 interrupt enable mask */
151 /* ports 1-3 follow after this */
152 MVS_P0_SER_CTLSTAT = 0x180, /* port0 serial control/status */
153 MVS_P4_SER_CTLSTAT = 0x220, /* port4 serial control/status */
155 MVS_CMD_ADDR = 0x1B8, /* Command register port (addr) */
156 MVS_CMD_DATA = 0x1BC, /* Command register port (data) */
158 /* ports 1-3 follow after this */
159 MVS_P0_CFG_ADDR = 0x1C0, /* port0 phy register address */
160 MVS_P0_CFG_DATA = 0x1C4, /* port0 phy register data */
161 MVS_P4_CFG_ADDR = 0x230, /* Port 4 config address */
162 MVS_P4_CFG_DATA = 0x234, /* Port 4 config data */
164 /* ports 1-3 follow after this */
165 MVS_P0_VSR_ADDR = 0x1E0, /* port0 VSR address */
166 MVS_P0_VSR_DATA = 0x1E4, /* port0 VSR data */
167 MVS_P4_VSR_ADDR = 0x250, /* port 4 VSR addr */
168 MVS_P4_VSR_DATA = 0x254, /* port 4 VSR data */
171 enum hw_register_bits {
173 INT_EN = (1U << 1), /* Global int enable */
174 HBA_RST = (1U << 0), /* HBA reset */
176 /* MVS_GBL_INT_STAT */
177 INT_XOR = (1U << 4), /* XOR engine event */
178 INT_SAS_SATA = (1U << 0), /* SAS/SATA event */
180 /* MVS_GBL_PORT_TYPE */ /* shl for ports 1-3 */
181 SATA_TARGET = (1U << 16), /* port0 SATA target enable */
182 MODE_AUTO_DET_PORT7 = (1U << 15), /* port0 SAS/SATA autodetect */
183 MODE_AUTO_DET_PORT6 = (1U << 14),
184 MODE_AUTO_DET_PORT5 = (1U << 13),
185 MODE_AUTO_DET_PORT4 = (1U << 12),
186 MODE_AUTO_DET_PORT3 = (1U << 11),
187 MODE_AUTO_DET_PORT2 = (1U << 10),
188 MODE_AUTO_DET_PORT1 = (1U << 9),
189 MODE_AUTO_DET_PORT0 = (1U << 8),
190 MODE_AUTO_DET_EN = MODE_AUTO_DET_PORT0 | MODE_AUTO_DET_PORT1 |
191 MODE_AUTO_DET_PORT2 | MODE_AUTO_DET_PORT3 |
192 MODE_AUTO_DET_PORT4 | MODE_AUTO_DET_PORT5 |
193 MODE_AUTO_DET_PORT6 | MODE_AUTO_DET_PORT7,
194 MODE_SAS_PORT7_MASK = (1U << 7), /* port0 SAS(1), SATA(0) mode */
195 MODE_SAS_PORT6_MASK = (1U << 6),
196 MODE_SAS_PORT5_MASK = (1U << 5),
197 MODE_SAS_PORT4_MASK = (1U << 4),
198 MODE_SAS_PORT3_MASK = (1U << 3),
199 MODE_SAS_PORT2_MASK = (1U << 2),
200 MODE_SAS_PORT1_MASK = (1U << 1),
201 MODE_SAS_PORT0_MASK = (1U << 0),
202 MODE_SAS_SATA = MODE_SAS_PORT0_MASK | MODE_SAS_PORT1_MASK |
203 MODE_SAS_PORT2_MASK | MODE_SAS_PORT3_MASK |
204 MODE_SAS_PORT4_MASK | MODE_SAS_PORT5_MASK |
205 MODE_SAS_PORT6_MASK | MODE_SAS_PORT7_MASK,
207 /* SAS_MODE value may be
208 * dictated (in hw) by values
209 * of SATA_TARGET & AUTO_DET
213 TX_EN = (1U << 16), /* Enable TX */
214 TX_RING_SZ_MASK = 0xfff, /* TX ring size, bits 11:0 */
217 RX_EN = (1U << 16), /* Enable RX */
218 RX_RING_SZ_MASK = 0xfff, /* RX ring size, bits 11:0 */
221 COAL_EN = (1U << 16), /* Enable int coalescing */
223 /* MVS_INT_STAT, MVS_INT_MASK */
224 CINT_I2C = (1U << 31), /* I2C event */
225 CINT_SW0 = (1U << 30), /* software event 0 */
226 CINT_SW1 = (1U << 29), /* software event 1 */
227 CINT_PRD_BC = (1U << 28), /* PRD BC err for read cmd */
228 CINT_DMA_PCIE = (1U << 27), /* DMA to PCIE timeout */
229 CINT_MEM = (1U << 26), /* int mem parity err */
230 CINT_I2C_SLAVE = (1U << 25), /* slave I2C event */
231 CINT_SRS = (1U << 3), /* SRS event */
232 CINT_CI_STOP = (1U << 1), /* cmd issue stopped */
233 CINT_DONE = (1U << 0), /* cmd completion */
235 /* shl for ports 1-3 */
236 CINT_PORT_STOPPED = (1U << 16), /* port0 stopped */
237 CINT_PORT = (1U << 8), /* port0 event */
238 CINT_PORT_MASK_OFFSET = 8,
239 CINT_PORT_MASK = (0xFF << CINT_PORT_MASK_OFFSET),
241 /* TX (delivery) ring bits */
243 TXQ_CMD_SSP = 1, /* SSP protocol */
244 TXQ_CMD_SMP = 2, /* SMP protocol */
245 TXQ_CMD_STP = 3, /* STP/SATA protocol */
246 TXQ_CMD_SSP_FREE_LIST = 4, /* add to SSP targ free list */
247 TXQ_CMD_SLOT_RESET = 7, /* reset command slot */
248 TXQ_MODE_I = (1U << 28), /* mode: 0=target,1=initiator */
249 TXQ_PRIO_HI = (1U << 27), /* priority: 0=normal, 1=high */
250 TXQ_SRS_SHIFT = 20, /* SATA register set */
252 TXQ_PHY_SHIFT = 12, /* PHY bitmap */
254 TXQ_SLOT_MASK = 0xfff, /* slot number */
256 /* RX (completion) ring bits */
257 RXQ_GOOD = (1U << 23), /* Response good */
258 RXQ_SLOT_RESET = (1U << 21), /* Slot reset complete */
259 RXQ_CMD_RX = (1U << 20), /* target cmd received */
260 RXQ_ATTN = (1U << 19), /* attention */
261 RXQ_RSP = (1U << 18), /* response frame xfer'd */
262 RXQ_ERR = (1U << 17), /* err info rec xfer'd */
263 RXQ_DONE = (1U << 16), /* cmd complete */
264 RXQ_SLOT_MASK = 0xfff, /* slot number */
266 /* mvs_cmd_hdr bits */
267 MCH_PRD_LEN_SHIFT = 16, /* 16-bit PRD table len */
268 MCH_SSP_FR_TYPE_SHIFT = 13, /* SSP frame type */
270 /* SSP initiator only */
271 MCH_SSP_FR_CMD = 0x0, /* COMMAND frame */
273 /* SSP initiator or target */
274 MCH_SSP_FR_TASK = 0x1, /* TASK frame */
276 /* SSP target only */
277 MCH_SSP_FR_XFER_RDY = 0x4, /* XFER_RDY frame */
278 MCH_SSP_FR_RESP = 0x5, /* RESPONSE frame */
279 MCH_SSP_FR_READ = 0x6, /* Read DATA frame(s) */
280 MCH_SSP_FR_READ_RESP = 0x7, /* ditto, plus RESPONSE */
282 MCH_PASSTHRU = (1U << 12), /* pass-through (SSP) */
283 MCH_FBURST = (1U << 11), /* first burst (SSP) */
284 MCH_CHK_LEN = (1U << 10), /* chk xfer len (SSP) */
285 MCH_RETRY = (1U << 9), /* tport layer retry (SSP) */
286 MCH_PROTECTION = (1U << 8), /* protection info rec (SSP) */
287 MCH_RESET = (1U << 7), /* Reset (STP/SATA) */
288 MCH_FPDMA = (1U << 6), /* First party DMA (STP/SATA) */
289 MCH_ATAPI = (1U << 5), /* ATAPI (STP/SATA) */
290 MCH_BIST = (1U << 4), /* BIST activate (STP/SATA) */
291 MCH_PMP_MASK = 0xf, /* PMP from cmd FIS (STP/SATA)*/
293 CCTL_RST = (1U << 5), /* port logic reset */
295 /* 0(LSB first), 1(MSB first) */
296 CCTL_ENDIAN_DATA = (1U << 3), /* PRD data */
297 CCTL_ENDIAN_RSP = (1U << 2), /* response frame */
298 CCTL_ENDIAN_OPEN = (1U << 1), /* open address frame */
299 CCTL_ENDIAN_CMD = (1U << 0), /* command table */
301 /* MVS_Px_SER_CTLSTAT (per-phy control) */
302 PHY_SSP_RST = (1U << 3), /* reset SSP link layer */
303 PHY_BCAST_CHG = (1U << 2), /* broadcast(change) notif */
304 PHY_RST_HARD = (1U << 1), /* hard reset + phy reset */
305 PHY_RST = (1U << 0), /* phy reset */
306 PHY_MIN_SPP_PHYS_LINK_RATE_MASK = (0xF << 8),
307 PHY_MAX_SPP_PHYS_LINK_RATE_MASK = (0xF << 12),
308 PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET = (16),
309 PHY_NEG_SPP_PHYS_LINK_RATE_MASK =
310 (0xF << PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET),
311 PHY_READY_MASK = (1U << 20),
313 /* MVS_Px_INT_STAT, MVS_Px_INT_MASK (per-phy events) */
314 PHYEV_DEC_ERR = (1U << 24), /* Phy Decoding Error */
315 PHYEV_UNASSOC_FIS = (1U << 19), /* unassociated FIS rx'd */
316 PHYEV_AN = (1U << 18), /* SATA async notification */
317 PHYEV_BIST_ACT = (1U << 17), /* BIST activate FIS */
318 PHYEV_SIG_FIS = (1U << 16), /* signature FIS */
319 PHYEV_POOF = (1U << 12), /* phy ready from 1 -> 0 */
320 PHYEV_IU_BIG = (1U << 11), /* IU too long err */
321 PHYEV_IU_SMALL = (1U << 10), /* IU too short err */
322 PHYEV_UNK_TAG = (1U << 9), /* unknown tag */
323 PHYEV_BROAD_CH = (1U << 8), /* broadcast(CHANGE) */
324 PHYEV_COMWAKE = (1U << 7), /* COMWAKE rx'd */
325 PHYEV_PORT_SEL = (1U << 6), /* port selector present */
326 PHYEV_HARD_RST = (1U << 5), /* hard reset rx'd */
327 PHYEV_ID_TMOUT = (1U << 4), /* identify timeout */
328 PHYEV_ID_FAIL = (1U << 3), /* identify failed */
329 PHYEV_ID_DONE = (1U << 2), /* identify done */
330 PHYEV_HARD_RST_DONE = (1U << 1), /* hard reset done */
331 PHYEV_RDY_CH = (1U << 0), /* phy ready changed state */
334 PCS_EN_SATA_REG_SHIFT = (16), /* Enable SATA Register Set */
335 PCS_EN_PORT_XMT_SHIFT = (12), /* Enable Port Transmit */
336 PCS_EN_PORT_XMT_SHIFT2 = (8), /* For 6480 */
337 PCS_SATA_RETRY = (1U << 8), /* retry ctl FIS on R_ERR */
338 PCS_RSP_RX_EN = (1U << 7), /* raw response rx */
339 PCS_SELF_CLEAR = (1U << 5), /* self-clearing int mode */
340 PCS_FIS_RX_EN = (1U << 4), /* FIS rx enable */
341 PCS_CMD_STOP_ERR = (1U << 3), /* cmd stop-on-err enable */
342 PCS_CMD_RST = (1U << 1), /* reset cmd issue */
343 PCS_CMD_EN = (1U << 0), /* enable cmd issue */
345 /* Port n Attached Device Info */
346 PORT_DEV_SSP_TRGT = (1U << 19),
347 PORT_DEV_SMP_TRGT = (1U << 18),
348 PORT_DEV_STP_TRGT = (1U << 17),
349 PORT_DEV_SSP_INIT = (1U << 11),
350 PORT_DEV_SMP_INIT = (1U << 10),
351 PORT_DEV_STP_INIT = (1U << 9),
352 PORT_PHY_ID_MASK = (0xFFU << 24),
353 PORT_DEV_TRGT_MASK = (0x7U << 17),
354 PORT_DEV_INIT_MASK = (0x7U << 9),
355 PORT_DEV_TYPE_MASK = (0x7U << 0),
357 /* Port n PHY Status */
359 PHY_DW_SYNC = (1U << 1),
360 PHY_OOB_DTCTD = (1U << 0),
363 /* PHYMODE 6 (CDB) */
364 PHY_MODE6_LATECLK = (1U << 29), /* Lock Clock */
365 PHY_MODE6_DTL_SPEED = (1U << 27), /* Digital Loop Speed */
366 PHY_MODE6_FC_ORDER = (1U << 26), /* Fibre Channel Mode Order*/
367 PHY_MODE6_MUCNT_EN = (1U << 24), /* u Count Enable */
368 PHY_MODE6_SEL_MUCNT_LEN = (1U << 22), /* Training Length Select */
369 PHY_MODE6_SELMUPI = (1U << 20), /* Phase Multi Select (init) */
370 PHY_MODE6_SELMUPF = (1U << 18), /* Phase Multi Select (final) */
371 PHY_MODE6_SELMUFF = (1U << 16), /* Freq Loop Multi Sel(final) */
372 PHY_MODE6_SELMUFI = (1U << 14), /* Freq Loop Multi Sel(init) */
373 PHY_MODE6_FREEZE_LOOP = (1U << 12), /* Freeze Rx CDR Loop */
374 PHY_MODE6_INT_RXFOFFS = (1U << 3), /* Rx CDR Freq Loop Enable */
375 PHY_MODE6_FRC_RXFOFFS = (1U << 2), /* Initial Rx CDR Offset */
376 PHY_MODE6_STAU_0D8 = (1U << 1), /* Rx CDR Freq Loop Saturate */
377 PHY_MODE6_RXSAT_DIS = (1U << 0), /* Saturate Ctl */
380 enum mvs_info_flags {
381 MVF_MSI = (1U << 0), /* MSI is enabled */
382 MVF_PHY_PWR_FIX = (1U << 1), /* bug workaround */
385 enum sas_cmd_port_registers {
386 CMD_CMRST_OOB_DET = 0x100, /* COMRESET OOB detect register */
387 CMD_CMWK_OOB_DET = 0x104, /* COMWAKE OOB detect register */
388 CMD_CMSAS_OOB_DET = 0x108, /* COMSAS OOB detect register */
389 CMD_BRST_OOB_DET = 0x10c, /* burst OOB detect register */
390 CMD_OOB_SPACE = 0x110, /* OOB space control register */
391 CMD_OOB_BURST = 0x114, /* OOB burst control register */
392 CMD_PHY_TIMER = 0x118, /* PHY timer control register */
393 CMD_PHY_CONFIG0 = 0x11c, /* PHY config register 0 */
394 CMD_PHY_CONFIG1 = 0x120, /* PHY config register 1 */
395 CMD_SAS_CTL0 = 0x124, /* SAS control register 0 */
396 CMD_SAS_CTL1 = 0x128, /* SAS control register 1 */
397 CMD_SAS_CTL2 = 0x12c, /* SAS control register 2 */
398 CMD_SAS_CTL3 = 0x130, /* SAS control register 3 */
399 CMD_ID_TEST = 0x134, /* ID test register */
400 CMD_PL_TIMER = 0x138, /* PL timer register */
401 CMD_WD_TIMER = 0x13c, /* WD timer register */
402 CMD_PORT_SEL_COUNT = 0x140, /* port selector count register */
403 CMD_APP_MEM_CTL = 0x144, /* Application Memory Control */
404 CMD_XOR_MEM_CTL = 0x148, /* XOR Block Memory Control */
405 CMD_DMA_MEM_CTL = 0x14c, /* DMA Block Memory Control */
406 CMD_PORT_MEM_CTL0 = 0x150, /* Port Memory Control 0 */
407 CMD_PORT_MEM_CTL1 = 0x154, /* Port Memory Control 1 */
408 CMD_SATA_PORT_MEM_CTL0 = 0x158, /* SATA Port Memory Control 0 */
409 CMD_SATA_PORT_MEM_CTL1 = 0x15c, /* SATA Port Memory Control 1 */
410 CMD_XOR_MEM_BIST_CTL = 0x160, /* XOR Memory BIST Control */
411 CMD_XOR_MEM_BIST_STAT = 0x164, /* XOR Memroy BIST Status */
412 CMD_DMA_MEM_BIST_CTL = 0x168, /* DMA Memory BIST Control */
413 CMD_DMA_MEM_BIST_STAT = 0x16c, /* DMA Memory BIST Status */
414 CMD_PORT_MEM_BIST_CTL = 0x170, /* Port Memory BIST Control */
415 CMD_PORT_MEM_BIST_STAT0 = 0x174, /* Port Memory BIST Status 0 */
416 CMD_PORT_MEM_BIST_STAT1 = 0x178, /* Port Memory BIST Status 1 */
417 CMD_STP_MEM_BIST_CTL = 0x17c, /* STP Memory BIST Control */
418 CMD_STP_MEM_BIST_STAT0 = 0x180, /* STP Memory BIST Status 0 */
419 CMD_STP_MEM_BIST_STAT1 = 0x184, /* STP Memory BIST Status 1 */
420 CMD_RESET_COUNT = 0x188, /* Reset Count */
421 CMD_MONTR_DATA_SEL = 0x18C, /* Monitor Data/Select */
422 CMD_PLL_PHY_CONFIG = 0x190, /* PLL/PHY Configuration */
423 CMD_PHY_CTL = 0x194, /* PHY Control and Status */
424 CMD_PHY_TEST_COUNT0 = 0x198, /* Phy Test Count 0 */
425 CMD_PHY_TEST_COUNT1 = 0x19C, /* Phy Test Count 1 */
426 CMD_PHY_TEST_COUNT2 = 0x1A0, /* Phy Test Count 2 */
427 CMD_APP_ERR_CONFIG = 0x1A4, /* Application Error Configuration */
428 CMD_PND_FIFO_CTL0 = 0x1A8, /* Pending FIFO Control 0 */
429 CMD_HOST_CTL = 0x1AC, /* Host Control Status */
430 CMD_HOST_WR_DATA = 0x1B0, /* Host Write Data */
431 CMD_HOST_RD_DATA = 0x1B4, /* Host Read Data */
432 CMD_PHY_MODE_21 = 0x1B8, /* Phy Mode 21 */
433 CMD_SL_MODE0 = 0x1BC, /* SL Mode 0 */
434 CMD_SL_MODE1 = 0x1C0, /* SL Mode 1 */
435 CMD_PND_FIFO_CTL1 = 0x1C4, /* Pending FIFO Control 1 */
438 /* SAS/SATA configuration port registers, aka phy registers */
439 enum sas_sata_config_port_regs {
440 PHYR_IDENTIFY = 0x00, /* info for IDENTIFY frame */
441 PHYR_ADDR_LO = 0x04, /* my SAS address (low) */
442 PHYR_ADDR_HI = 0x08, /* my SAS address (high) */
443 PHYR_ATT_DEV_INFO = 0x0C, /* attached device info */
444 PHYR_ATT_ADDR_LO = 0x10, /* attached dev SAS addr (low) */
445 PHYR_ATT_ADDR_HI = 0x14, /* attached dev SAS addr (high) */
446 PHYR_SATA_CTL = 0x18, /* SATA control */
447 PHYR_PHY_STAT = 0x1C, /* PHY status */
448 PHYR_SATA_SIG0 = 0x20, /*port SATA signature FIS(Byte 0-3) */
449 PHYR_SATA_SIG1 = 0x24, /*port SATA signature FIS(Byte 4-7) */
450 PHYR_SATA_SIG2 = 0x28, /*port SATA signature FIS(Byte 8-11) */
451 PHYR_SATA_SIG3 = 0x2c, /*port SATA signature FIS(Byte 12-15) */
452 PHYR_R_ERR_COUNT = 0x30, /* port R_ERR count register */
453 PHYR_CRC_ERR_COUNT = 0x34, /* port CRC error count register */
454 PHYR_WIDE_PORT = 0x38, /* wide port participating */
455 PHYR_CURRENT0 = 0x80, /* current connection info 0 */
456 PHYR_CURRENT1 = 0x84, /* current connection info 1 */
457 PHYR_CURRENT2 = 0x88, /* current connection info 2 */
460 /* SAS/SATA Vendor Specific Port Registers */
461 enum sas_sata_vsp_regs {
462 VSR_PHY_STAT = 0x00, /* Phy Status */
463 VSR_PHY_MODE1 = 0x01, /* phy tx */
464 VSR_PHY_MODE2 = 0x02, /* tx scc */
465 VSR_PHY_MODE3 = 0x03, /* pll */
466 VSR_PHY_MODE4 = 0x04, /* VCO */
467 VSR_PHY_MODE5 = 0x05, /* Rx */
468 VSR_PHY_MODE6 = 0x06, /* CDR */
469 VSR_PHY_MODE7 = 0x07, /* Impedance */
470 VSR_PHY_MODE8 = 0x08, /* Voltage */
471 VSR_PHY_MODE9 = 0x09, /* Test */
472 VSR_PHY_MODE10 = 0x0A, /* Power */
473 VSR_PHY_MODE11 = 0x0B, /* Phy Mode */
474 VSR_PHY_VS0 = 0x0C, /* Vednor Specific 0 */
475 VSR_PHY_VS1 = 0x0D, /* Vednor Specific 1 */
478 enum pci_cfg_registers {
484 enum pci_cfg_register_bits {
485 PCTL_PWR_ON = (0xFU << 24),
486 PCTL_OFF = (0xFU << 12),
487 PRD_REQ_SIZE = (0x4000),
488 PRD_REQ_MASK = (0x00007000),
491 enum nvram_layout_offsets {
492 NVR_SIG = 0x00, /* 0xAA, 0x55 */
493 NVR_SAS_ADDR = 0x02, /* 8-byte SAS address */
503 PORT_TYPE_SAS = (1L << 1),
504 PORT_TYPE_SATA = (1L << 0),
507 /* Command Table Format */
515 STP_ATAPI_CMD = 0x40,
524 SB_EIR_OFF = 0x00, /* Error Information Record */
525 SB_RFB_OFF = 0x08, /* Response Frame Buffer */
526 SB_RFB_MAX = 0x400, /* RFB size*/
529 enum error_info_rec {
530 CMD_ISS_STPD = (1U << 31), /* Cmd Issue Stopped */
531 CMD_PI_ERR = (1U << 30), /* Protection info error. see flags2 */
532 RSP_OVER = (1U << 29), /* rsp buffer overflow */
533 RETRY_LIM = (1U << 28), /* FIS/frame retry limit exceeded */
534 UNK_FIS = (1U << 27), /* unknown FIS */
535 DMA_TERM = (1U << 26), /* DMA terminate primitive rx'd */
536 SYNC_ERR = (1U << 25), /* SYNC rx'd during frame xmit */
537 TFILE_ERR = (1U << 24), /* SATA taskfile Error bit set */
538 R_ERR = (1U << 23), /* SATA returned R_ERR prim */
539 RD_OFS = (1U << 20), /* Read DATA frame invalid offset */
540 XFER_RDY_OFS = (1U << 19), /* XFER_RDY offset error */
541 UNEXP_XFER_RDY = (1U << 18), /* unexpected XFER_RDY error */
542 DATA_OVER_UNDER = (1U << 16), /* data overflow/underflow */
543 INTERLOCK = (1U << 15), /* interlock error */
544 NAK = (1U << 14), /* NAK rx'd */
545 ACK_NAK_TO = (1U << 13), /* ACK/NAK timeout */
546 CXN_CLOSED = (1U << 12), /* cxn closed w/out ack/nak */
547 OPEN_TO = (1U << 11), /* I_T nexus lost, open cxn timeout */
548 PATH_BLOCKED = (1U << 10), /* I_T nexus lost, pathway blocked */
549 NO_DEST = (1U << 9), /* I_T nexus lost, no destination */
550 STP_RES_BSY = (1U << 8), /* STP resources busy */
551 BREAK = (1U << 7), /* break received */
552 BAD_DEST = (1U << 6), /* bad destination */
553 BAD_PROTO = (1U << 5), /* protocol not supported */
554 BAD_RATE = (1U << 4), /* cxn rate not supported */
555 WRONG_DEST = (1U << 3), /* wrong destination error */
556 CREDIT_TO = (1U << 2), /* credit timeout */
557 WDOG_TO = (1U << 1), /* watchdog timeout */
558 BUF_PAR = (1U << 0), /* buffer parity error */
561 enum error_info_rec_2 {
562 SLOT_BSY_ERR = (1U << 31), /* Slot Busy Error */
563 GRD_CHK_ERR = (1U << 14), /* Guard Check Error */
564 APP_CHK_ERR = (1U << 13), /* Application Check error */
565 REF_CHK_ERR = (1U << 12), /* Reference Check Error */
566 USR_BLK_NM = (1U << 0), /* User Block Number */
569 struct mvs_chip_info {
575 struct mvs_err_info {
581 __le64 addr; /* 64-bit buffer address */
583 __le32 len; /* 16-bit length */
587 __le32 flags; /* PRD tbl len; SAS, SATA ctl */
588 __le32 lens; /* cmd, max resp frame len */
589 __le32 tags; /* targ port xfer tag; tag */
590 __le32 data_len; /* data xfer len */
591 __le64 cmd_tbl; /* command table address */
592 __le64 open_frame; /* open addr frame address */
593 __le64 status_buf; /* status buffer address */
594 __le64 prd_tbl; /* PRD tbl address */
599 struct asd_sas_port sas_port;
603 struct list_head list;
607 struct mvs_port *port;
608 struct asd_sas_phy sas_phy;
609 struct sas_identify identify;
610 struct scsi_device *sdev;
612 u64 att_dev_sas_addr;
621 enum sas_linkrate minimum_linkrate;
622 enum sas_linkrate maximum_linkrate;
625 struct mvs_slot_info {
626 struct list_head list;
627 struct sas_task *task;
631 /* DMA buffer for storing cmd tbl, open addr frame, status buffer,
641 struct mvs_port *port;
647 spinlock_t lock; /* host-wide lock */
648 struct pci_dev *pdev; /* our device */
649 void __iomem *regs; /* enhanced mode registers */
650 void __iomem *peri_regs; /* peripheral registers */
652 u8 sas_addr[SAS_ADDR_SIZE];
653 struct sas_ha_struct sas; /* SCSI/SAS glue */
654 struct Scsi_Host *shost;
656 __le32 *tx; /* TX (delivery) DMA ring */
658 u32 tx_prod; /* cached next-producer idx */
660 __le32 *rx; /* RX (completion) DMA ring */
662 u32 rx_cons; /* RX consumer idx */
664 __le32 *rx_fis; /* RX'd FIS area */
665 dma_addr_t rx_fis_dma;
667 struct mvs_cmd_hdr *slot; /* DMA command header slots */
670 const struct mvs_chip_info *chip;
673 struct mvs_slot_info slot_info[MVS_SLOTS];
674 /* further per-slot information */
675 struct mvs_phy phy[MVS_MAX_PHYS];
676 struct mvs_port port[MVS_MAX_PHYS];
677 #ifdef MVS_USE_TASKLET
678 struct tasklet_struct tasklet;
682 static int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
684 static u32 mvs_read_phy_ctl(struct mvs_info *mvi, u32 port);
685 static void mvs_write_phy_ctl(struct mvs_info *mvi, u32 port, u32 val);
686 static u32 mvs_read_port_irq_stat(struct mvs_info *mvi, u32 port);
687 static void mvs_write_port_irq_stat(struct mvs_info *mvi, u32 port, u32 val);
688 static void mvs_write_port_irq_mask(struct mvs_info *mvi, u32 port, u32 val);
689 static u32 mvs_read_port_irq_mask(struct mvs_info *mvi, u32 port);
691 static u32 mvs_is_phy_ready(struct mvs_info *mvi, int i);
692 static void mvs_detect_porttype(struct mvs_info *mvi, int i);
693 static void mvs_update_phyinfo(struct mvs_info *mvi, int i, int get_st);
694 static void mvs_release_task(struct mvs_info *mvi, int phy_no);
696 static int mvs_scan_finished(struct Scsi_Host *, unsigned long);
697 static void mvs_scan_start(struct Scsi_Host *);
698 static int mvs_slave_configure(struct scsi_device *sdev);
700 static struct scsi_transport_template *mvs_stt;
702 static const struct mvs_chip_info mvs_chips[] = {
703 [chip_6320] = { 2, 16, 9 },
704 [chip_6440] = { 4, 16, 9 },
705 [chip_6480] = { 8, 32, 10 },
708 static struct scsi_host_template mvs_sht = {
709 .module = THIS_MODULE,
711 .queuecommand = sas_queuecommand,
712 .target_alloc = sas_target_alloc,
713 .slave_configure = mvs_slave_configure,
714 .slave_destroy = sas_slave_destroy,
715 .scan_finished = mvs_scan_finished,
716 .scan_start = mvs_scan_start,
717 .change_queue_depth = sas_change_queue_depth,
718 .change_queue_type = sas_change_queue_type,
719 .bios_param = sas_bios_param,
723 .sg_tablesize = SG_ALL,
724 .max_sectors = SCSI_DEFAULT_MAX_SECTORS,
725 .use_clustering = ENABLE_CLUSTERING,
726 .eh_device_reset_handler = sas_eh_device_reset_handler,
727 .eh_bus_reset_handler = sas_eh_bus_reset_handler,
728 .slave_alloc = sas_slave_alloc,
729 .target_destroy = sas_target_destroy,
733 static void mvs_hexdump(u32 size, u8 *data, u32 baseaddr)
741 printk("%08X : ", baseaddr + offset);
747 for (i = 0; i < 16; i++) {
749 printk("%02X ", (u32)data[i]);
754 for (i = 0; i < run; i++)
755 printk("%c", isalnum(data[i]) ? data[i] : '.');
764 static void mvs_hba_sb_dump(struct mvs_info *mvi, u32 tag,
765 enum sas_protocol proto)
768 struct pci_dev *pdev = mvi->pdev;
769 struct mvs_slot_info *slot = &mvi->slot_info[tag];
771 offset = slot->cmd_size + MVS_OAF_SZ +
772 sizeof(struct mvs_prd) * slot->n_elem;
773 dev_printk(KERN_DEBUG, &pdev->dev, "+---->Status buffer[%d] :\n",
775 mvs_hexdump(32, (u8 *) slot->response,
776 (u32) slot->buf_dma + offset);
780 static void mvs_hba_memory_dump(struct mvs_info *mvi, u32 tag,
781 enum sas_protocol proto)
786 void __iomem *regs = mvi->regs;
787 struct pci_dev *pdev = mvi->pdev;
788 struct mvs_slot_info *slot = &mvi->slot_info[tag];
791 sz = mr32(TX_CFG) & TX_RING_SZ_MASK;
793 addr = mr32(TX_HI) << 16 << 16 | mr32(TX_LO);
794 dev_printk(KERN_DEBUG, &pdev->dev,
795 "Delivery Queue Size=%04d , WRT_PTR=%04X\n", sz, w_ptr);
796 dev_printk(KERN_DEBUG, &pdev->dev,
797 "Delivery Queue Base Address=0x%llX (PA)"
798 "(tx_dma=0x%llX), Entry=%04d\n",
799 addr, mvi->tx_dma, w_ptr);
800 mvs_hexdump(sizeof(u32), (u8 *)(&mvi->tx[mvi->tx_prod]),
801 (u32) mvi->tx_dma + sizeof(u32) * w_ptr);
803 addr = mvi->slot_dma;
804 dev_printk(KERN_DEBUG, &pdev->dev,
805 "Command List Base Address=0x%llX (PA)"
806 "(slot_dma=0x%llX), Header=%03d\n",
807 addr, slot->buf_dma, tag);
808 dev_printk(KERN_DEBUG, &pdev->dev, "Command Header[%03d]:\n", tag);
810 mvs_hexdump(sizeof(struct mvs_cmd_hdr), (u8 *)(&mvi->slot[tag]),
811 (u32) mvi->slot_dma + tag * sizeof(struct mvs_cmd_hdr));
812 /*1.command table area */
813 dev_printk(KERN_DEBUG, &pdev->dev, "+---->Command Table :\n");
814 mvs_hexdump(slot->cmd_size, (u8 *) slot->buf, (u32) slot->buf_dma);
815 /*2.open address frame area */
816 dev_printk(KERN_DEBUG, &pdev->dev, "+---->Open Address Frame :\n");
817 mvs_hexdump(MVS_OAF_SZ, (u8 *) slot->buf + slot->cmd_size,
818 (u32) slot->buf_dma + slot->cmd_size);
820 mvs_hba_sb_dump(mvi, tag, proto);
822 dev_printk(KERN_DEBUG, &pdev->dev, "+---->PRD table :\n");
823 mvs_hexdump(sizeof(struct mvs_prd) * slot->n_elem,
824 (u8 *) slot->buf + slot->cmd_size + MVS_OAF_SZ,
825 (u32) slot->buf_dma + slot->cmd_size + MVS_OAF_SZ);
829 static void mvs_hba_cq_dump(struct mvs_info *mvi)
833 void __iomem *regs = mvi->regs;
834 struct pci_dev *pdev = mvi->pdev;
835 u32 entry = mvi->rx_cons + 1;
836 u32 rx_desc = le32_to_cpu(mvi->rx[entry]);
838 /*Completion Queue */
839 addr = mr32(RX_HI) << 16 << 16 | mr32(RX_LO);
840 dev_printk(KERN_DEBUG, &pdev->dev, "Completion Task = 0x%p\n",
841 mvi->slot_info[rx_desc & RXQ_SLOT_MASK].task);
842 dev_printk(KERN_DEBUG, &pdev->dev,
843 "Completion List Base Address=0x%llX (PA), "
844 "CQ_Entry=%04d, CQ_WP=0x%08X\n",
845 addr, entry - 1, mvi->rx[0]);
846 mvs_hexdump(sizeof(u32), (u8 *)(&rx_desc),
847 mvi->rx_dma + sizeof(u32) * entry);
851 static void mvs_hba_interrupt_enable(struct mvs_info *mvi)
853 void __iomem *regs = mvi->regs;
858 mw32(GBL_CTL, tmp | INT_EN);
861 static void mvs_hba_interrupt_disable(struct mvs_info *mvi)
863 void __iomem *regs = mvi->regs;
868 mw32(GBL_CTL, tmp & ~INT_EN);
871 static int mvs_int_rx(struct mvs_info *mvi, bool self_clear);
873 /* move to PCI layer or libata core? */
874 static int pci_go_64(struct pci_dev *pdev)
878 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
879 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
881 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
883 dev_printk(KERN_ERR, &pdev->dev,
884 "64-bit DMA enable failed\n");
889 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
891 dev_printk(KERN_ERR, &pdev->dev,
892 "32-bit DMA enable failed\n");
895 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
897 dev_printk(KERN_ERR, &pdev->dev,
898 "32-bit consistent DMA enable failed\n");
906 static int mvs_find_tag(struct mvs_info *mvi, struct sas_task *task, u32 *tag)
908 if (task->lldd_task) {
909 struct mvs_slot_info *slot;
910 slot = (struct mvs_slot_info *) task->lldd_task;
911 *tag = slot - mvi->slot_info;
917 static void mvs_tag_clear(struct mvs_info *mvi, u32 tag)
919 void *bitmap = (void *) &mvi->tags;
920 clear_bit(tag, bitmap);
923 static void mvs_tag_free(struct mvs_info *mvi, u32 tag)
925 mvs_tag_clear(mvi, tag);
928 static void mvs_tag_set(struct mvs_info *mvi, unsigned int tag)
930 void *bitmap = (void *) &mvi->tags;
931 set_bit(tag, bitmap);
934 static int mvs_tag_alloc(struct mvs_info *mvi, u32 *tag_out)
936 unsigned int index, tag;
937 void *bitmap = (void *) &mvi->tags;
939 index = find_first_zero_bit(bitmap, MVS_SLOTS);
941 if (tag >= MVS_SLOTS)
942 return -SAS_QUEUE_FULL;
943 mvs_tag_set(mvi, tag);
948 static void mvs_tag_init(struct mvs_info *mvi)
951 for (i = 0; i < MVS_SLOTS; ++i)
952 mvs_tag_clear(mvi, i);
955 #ifndef MVS_DISABLE_NVRAM
956 static int mvs_eep_read(void __iomem *regs, u32 addr, u32 *data)
960 if (addr & ~SPI_ADDR_MASK)
963 writel(addr, regs + SPI_CMD);
964 writel(TWSI_RD, regs + SPI_CTL);
966 while (timeout-- > 0) {
967 if (readl(regs + SPI_CTL) & TWSI_RDY) {
968 *data = readl(regs + SPI_DATA);
978 static int mvs_eep_read_buf(void __iomem *regs, u32 addr,
979 void *buf, u32 buflen)
981 u32 addr_end, tmp_addr, i, j;
984 u8 *tmp8, *buf8 = buf;
986 addr_end = addr + buflen;
987 tmp_addr = ALIGN(addr, 4);
993 rc = mvs_eep_read(regs, tmp_addr, &tmp);
998 for (i = j; i < 4; i++)
1004 for (j = ALIGN(addr_end, 4); tmp_addr < j; tmp_addr += 4) {
1005 rc = mvs_eep_read(regs, tmp_addr, &tmp);
1009 memcpy(buf8, &tmp, 4);
1013 if (tmp_addr < addr_end) {
1014 rc = mvs_eep_read(regs, tmp_addr, &tmp);
1019 j = addr_end - tmp_addr;
1020 for (i = 0; i < j; i++)
1030 static int mvs_nvram_read(struct mvs_info *mvi, u32 addr,
1031 void *buf, u32 buflen)
1033 #ifndef MVS_DISABLE_NVRAM
1034 void __iomem *regs = mvi->regs;
1040 rc = mvs_eep_read_buf(regs, addr, &hdr, 2);
1042 msg = "nvram hdr read failed";
1045 rc = mvs_eep_read_buf(regs, addr + 2, buf, buflen);
1047 msg = "nvram read failed";
1051 if (hdr[0] != 0x5A) {
1053 msg = "invalid nvram entry id";
1059 sum = ((u32)hdr[0]) + ((u32)hdr[1]);
1060 for (i = 0; i < buflen; i++)
1061 sum += ((u32)tmp[i]);
1064 msg = "nvram checksum failure";
1072 dev_printk(KERN_ERR, &mvi->pdev->dev, "%s", msg);
1075 /* FIXME , For SAS target mode */
1076 memcpy(buf, "\x50\x05\x04\x30\x11\xab\x00\x00", 8);
1081 static void mvs_bytes_dmaed(struct mvs_info *mvi, int i)
1083 struct mvs_phy *phy = &mvi->phy[i];
1084 struct asd_sas_phy *sas_phy = mvi->sas.sas_phy[i];
1086 if (!phy->phy_attached)
1090 struct sas_phy *sphy = sas_phy->phy;
1092 sphy->negotiated_linkrate = sas_phy->linkrate;
1093 sphy->minimum_linkrate = phy->minimum_linkrate;
1094 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
1095 sphy->maximum_linkrate = phy->maximum_linkrate;
1096 sphy->maximum_linkrate_hw = SAS_LINK_RATE_3_0_GBPS;
1099 if (phy->phy_type & PORT_TYPE_SAS) {
1100 struct sas_identify_frame *id;
1102 id = (struct sas_identify_frame *)phy->frame_rcvd;
1103 id->dev_type = phy->identify.device_type;
1104 id->initiator_bits = SAS_PROTOCOL_ALL;
1105 id->target_bits = phy->identify.target_port_protocols;
1106 } else if (phy->phy_type & PORT_TYPE_SATA) {
1109 mvi->sas.sas_phy[i]->frame_rcvd_size = phy->frame_rcvd_size;
1110 mvi->sas.notify_port_event(mvi->sas.sas_phy[i],
1114 static int mvs_scan_finished(struct Scsi_Host *shost, unsigned long time)
1116 /* give the phy enabling interrupt event time to come in (1s
1117 * is empirically about all it takes) */
1120 /* Wait for discovery to finish */
1121 scsi_flush_work(shost);
1125 static void mvs_scan_start(struct Scsi_Host *shost)
1128 struct mvs_info *mvi = SHOST_TO_SAS_HA(shost)->lldd_ha;
1130 for (i = 0; i < mvi->chip->n_phy; ++i) {
1131 mvs_bytes_dmaed(mvi, i);
1135 static int mvs_slave_configure(struct scsi_device *sdev)
1137 struct domain_device *dev = sdev_to_domain_dev(sdev);
1138 int ret = sas_slave_configure(sdev);
1143 if (dev_is_sata(dev)) {
1144 /* struct ata_port *ap = dev->sata_dev.ap; */
1145 /* struct ata_device *adev = ap->link.device; */
1147 /* clamp at no NCQ for the time being */
1148 /* adev->flags |= ATA_DFLAG_NCQ_OFF; */
1149 scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, 1);
1154 static void mvs_int_port(struct mvs_info *mvi, int phy_no, u32 events)
1156 struct pci_dev *pdev = mvi->pdev;
1157 struct sas_ha_struct *sas_ha = &mvi->sas;
1158 struct mvs_phy *phy = &mvi->phy[phy_no];
1159 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1161 phy->irq_status = mvs_read_port_irq_stat(mvi, phy_no);
1163 * events is port event now ,
1164 * we need check the interrupt status which belongs to per port.
1166 dev_printk(KERN_DEBUG, &pdev->dev,
1167 "Port %d Event = %X\n",
1168 phy_no, phy->irq_status);
1170 if (phy->irq_status & (PHYEV_POOF | PHYEV_DEC_ERR)) {
1171 mvs_release_task(mvi, phy_no);
1172 if (!mvs_is_phy_ready(mvi, phy_no)) {
1173 sas_phy_disconnected(sas_phy);
1174 sas_ha->notify_phy_event(sas_phy, PHYE_LOSS_OF_SIGNAL);
1175 dev_printk(KERN_INFO, &pdev->dev,
1176 "Port %d Unplug Notice\n", phy_no);
1179 mvs_phy_control(sas_phy, PHY_FUNC_LINK_RESET, NULL);
1181 if (!(phy->irq_status & PHYEV_DEC_ERR)) {
1182 if (phy->irq_status & PHYEV_COMWAKE) {
1183 u32 tmp = mvs_read_port_irq_mask(mvi, phy_no);
1184 mvs_write_port_irq_mask(mvi, phy_no,
1185 tmp | PHYEV_SIG_FIS);
1187 if (phy->irq_status & (PHYEV_SIG_FIS | PHYEV_ID_DONE)) {
1188 phy->phy_status = mvs_is_phy_ready(mvi, phy_no);
1189 if (phy->phy_status) {
1190 mvs_detect_porttype(mvi, phy_no);
1192 if (phy->phy_type & PORT_TYPE_SATA) {
1193 u32 tmp = mvs_read_port_irq_mask(mvi,
1195 tmp &= ~PHYEV_SIG_FIS;
1196 mvs_write_port_irq_mask(mvi,
1200 mvs_update_phyinfo(mvi, phy_no, 0);
1201 sas_ha->notify_phy_event(sas_phy,
1203 mvs_bytes_dmaed(mvi, phy_no);
1205 dev_printk(KERN_DEBUG, &pdev->dev,
1206 "plugin interrupt but phy is gone\n");
1207 mvs_phy_control(sas_phy, PHY_FUNC_LINK_RESET,
1210 } else if (phy->irq_status & PHYEV_BROAD_CH) {
1211 mvs_release_task(mvi, phy_no);
1212 sas_ha->notify_port_event(sas_phy,
1213 PORTE_BROADCAST_RCVD);
1216 mvs_write_port_irq_stat(mvi, phy_no, phy->irq_status);
1219 static void mvs_int_sata(struct mvs_info *mvi)
1224 static void mvs_slot_free(struct mvs_info *mvi, struct sas_task *task,
1225 struct mvs_slot_info *slot, u32 slot_idx)
1227 if (!sas_protocol_ata(task->task_proto))
1229 pci_unmap_sg(mvi->pdev, task->scatter,
1230 slot->n_elem, task->data_dir);
1232 switch (task->task_proto) {
1233 case SAS_PROTOCOL_SMP:
1234 pci_unmap_sg(mvi->pdev, &task->smp_task.smp_resp, 1,
1235 PCI_DMA_FROMDEVICE);
1236 pci_unmap_sg(mvi->pdev, &task->smp_task.smp_req, 1,
1240 case SAS_PROTOCOL_SATA:
1241 case SAS_PROTOCOL_STP:
1242 case SAS_PROTOCOL_SSP:
1249 mvs_tag_clear(mvi, slot_idx);
1252 static void mvs_slot_err(struct mvs_info *mvi, struct sas_task *task,
1255 struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
1256 u64 err_dw0 = *(u32 *) slot->response;
1257 void __iomem *regs = mvi->regs;
1260 if (err_dw0 & CMD_ISS_STPD)
1261 if (sas_protocol_ata(task->task_proto)) {
1262 tmp = mr32(INT_STAT_SRS);
1263 mw32(INT_STAT_SRS, tmp & 0xFFFF);
1266 mvs_hba_sb_dump(mvi, slot_idx, task->task_proto);
1269 static int mvs_slot_complete(struct mvs_info *mvi, u32 rx_desc)
1271 u32 slot_idx = rx_desc & RXQ_SLOT_MASK;
1272 struct mvs_slot_info *slot = &mvi->slot_info[slot_idx];
1273 struct sas_task *task = slot->task;
1274 struct task_status_struct *tstat = &task->task_status;
1275 struct mvs_port *port = &mvi->port[task->dev->port->id];
1279 spin_lock(&task->task_state_lock);
1280 aborted = task->task_state_flags & SAS_TASK_STATE_ABORTED;
1282 task->task_state_flags &=
1283 ~(SAS_TASK_STATE_PENDING | SAS_TASK_AT_INITIATOR);
1284 task->task_state_flags |= SAS_TASK_STATE_DONE;
1286 spin_unlock(&task->task_state_lock);
1291 memset(tstat, 0, sizeof(*tstat));
1292 tstat->resp = SAS_TASK_COMPLETE;
1295 if (unlikely(!port->port_attached)) {
1296 tstat->stat = SAS_PHY_DOWN;
1300 /* error info record present */
1301 if ((rx_desc & RXQ_ERR) && (*(u64 *) slot->response)) {
1302 tstat->stat = SAM_CHECK_COND;
1303 mvs_slot_err(mvi, task, slot_idx);
1307 switch (task->task_proto) {
1308 case SAS_PROTOCOL_SSP:
1309 /* hw says status == 0, datapres == 0 */
1310 if (rx_desc & RXQ_GOOD) {
1311 tstat->stat = SAM_GOOD;
1312 tstat->resp = SAS_TASK_COMPLETE;
1314 /* response frame present */
1315 else if (rx_desc & RXQ_RSP) {
1316 struct ssp_response_iu *iu =
1317 slot->response + sizeof(struct mvs_err_info);
1318 sas_ssp_task_response(&mvi->pdev->dev, task, iu);
1321 /* should never happen? */
1323 tstat->stat = SAM_CHECK_COND;
1326 case SAS_PROTOCOL_SMP: {
1327 struct scatterlist *sg_resp = &task->smp_task.smp_resp;
1328 tstat->stat = SAM_GOOD;
1329 to = kmap_atomic(sg_page(sg_resp), KM_IRQ0);
1330 memcpy(to + sg_resp->offset,
1331 slot->response + sizeof(struct mvs_err_info),
1332 sg_dma_len(sg_resp));
1333 kunmap_atomic(to, KM_IRQ0);
1337 case SAS_PROTOCOL_SATA:
1338 case SAS_PROTOCOL_STP:
1339 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP: {
1340 struct ata_task_resp *resp =
1341 (struct ata_task_resp *)tstat->buf;
1343 if ((rx_desc & (RXQ_DONE | RXQ_ERR | RXQ_ATTN)) ==
1345 tstat->stat = SAM_GOOD;
1347 tstat->stat = SAM_CHECK_COND;
1349 resp->frame_len = sizeof(struct dev_to_host_fis);
1350 memcpy(&resp->ending_fis[0],
1351 SATA_RECEIVED_D2H_FIS(port->taskfileset),
1352 sizeof(struct dev_to_host_fis));
1353 if (resp->ending_fis[2] & ATA_ERR)
1354 mvs_hexdump(16, resp->ending_fis, 0);
1359 tstat->stat = SAM_CHECK_COND;
1364 mvs_slot_free(mvi, task, slot, slot_idx);
1365 task->task_done(task);
1369 static void mvs_int_full(struct mvs_info *mvi)
1371 void __iomem *regs = mvi->regs;
1375 stat = mr32(INT_STAT);
1377 mvs_int_rx(mvi, false);
1379 for (i = 0; i < MVS_MAX_PORTS; i++) {
1380 tmp = (stat >> i) & (CINT_PORT | CINT_PORT_STOPPED);
1382 mvs_int_port(mvi, i, tmp);
1385 if (stat & CINT_SRS)
1388 mw32(INT_STAT, stat);
1391 static int mvs_int_rx(struct mvs_info *mvi, bool self_clear)
1393 void __iomem *regs = mvi->regs;
1394 u32 rx_prod_idx, rx_desc;
1396 struct pci_dev *pdev = mvi->pdev;
1398 /* the first dword in the RX ring is special: it contains
1399 * a mirror of the hardware's RX producer index, so that
1400 * we don't have to stall the CPU reading that register.
1401 * The actual RX ring is offset by one dword, due to this.
1403 rx_prod_idx = mr32(RX_CONS_IDX) & RX_RING_SZ_MASK;
1404 if (rx_prod_idx == 0xfff) { /* h/w hasn't touched RX ring yet */
1405 mvi->rx_cons = 0xfff;
1409 /* The CMPL_Q may come late, read from register and try again
1410 * note: if coalescing is enabled,
1411 * it will need to read from register every time for sure
1413 if (mvi->rx_cons == rx_prod_idx)
1416 if (mvi->rx_cons == 0xfff)
1417 mvi->rx_cons = MVS_RX_RING_SZ - 1;
1419 while (mvi->rx_cons != rx_prod_idx) {
1421 /* increment our internal RX consumer pointer */
1422 mvi->rx_cons = (mvi->rx_cons + 1) & (MVS_RX_RING_SZ - 1);
1424 rx_desc = le32_to_cpu(mvi->rx[mvi->rx_cons + 1]);
1426 mvs_hba_cq_dump(mvi);
1428 if (likely(rx_desc & RXQ_DONE))
1429 mvs_slot_complete(mvi, rx_desc);
1430 if (rx_desc & RXQ_ATTN) {
1432 dev_printk(KERN_DEBUG, &pdev->dev, "ATTN %X\n",
1434 } else if (rx_desc & RXQ_ERR) {
1435 dev_printk(KERN_DEBUG, &pdev->dev, "RXQ_ERR %X\n",
1440 if (attn && self_clear)
1446 static irqreturn_t mvs_interrupt(int irq, void *opaque)
1448 struct mvs_info *mvi = opaque;
1449 void __iomem *regs = mvi->regs;
1452 stat = mr32(GBL_INT_STAT);
1454 /* clear CMD_CMPLT ASAP */
1455 mw32_f(INT_STAT, CINT_DONE);
1457 if (stat == 0 || stat == 0xffffffff)
1460 spin_lock(&mvi->lock);
1464 spin_unlock(&mvi->lock);
1469 #ifndef MVS_DISABLE_MSI
1470 static irqreturn_t mvs_msi_interrupt(int irq, void *opaque)
1472 struct mvs_info *mvi = opaque;
1474 spin_lock(&mvi->lock);
1476 mvs_int_rx(mvi, true);
1478 spin_unlock(&mvi->lock);
1484 struct mvs_task_exec_info {
1485 struct sas_task *task;
1486 struct mvs_cmd_hdr *hdr;
1487 struct mvs_port *port;
1492 static int mvs_task_prep_smp(struct mvs_info *mvi,
1493 struct mvs_task_exec_info *tei)
1496 struct sas_task *task = tei->task;
1497 struct mvs_cmd_hdr *hdr = tei->hdr;
1498 struct scatterlist *sg_req, *sg_resp;
1499 u32 req_len, resp_len, tag = tei->tag;
1502 dma_addr_t buf_tmp_dma;
1503 struct mvs_prd *buf_prd;
1504 struct scatterlist *sg;
1505 struct mvs_slot_info *slot = &mvi->slot_info[tag];
1506 struct asd_sas_port *sas_port = task->dev->port;
1507 u32 flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
1513 * DMA-map SMP request, response buffers
1515 sg_req = &task->smp_task.smp_req;
1516 elem = pci_map_sg(mvi->pdev, sg_req, 1, PCI_DMA_TODEVICE);
1519 req_len = sg_dma_len(sg_req);
1521 sg_resp = &task->smp_task.smp_resp;
1522 elem = pci_map_sg(mvi->pdev, sg_resp, 1, PCI_DMA_FROMDEVICE);
1527 resp_len = sg_dma_len(sg_resp);
1529 /* must be in dwords */
1530 if ((req_len & 0x3) || (resp_len & 0x3)) {
1536 * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
1539 /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ************** */
1540 buf_tmp = slot->buf;
1541 buf_tmp_dma = slot->buf_dma;
1545 hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
1547 buf_tmp_dma += req_len;
1548 slot->cmd_size = req_len;
1550 hdr->cmd_tbl = cpu_to_le64(sg_dma_address(sg_req));
1553 /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
1555 hdr->open_frame = cpu_to_le64(buf_tmp_dma);
1557 buf_tmp += MVS_OAF_SZ;
1558 buf_tmp_dma += MVS_OAF_SZ;
1560 /* region 3: PRD table ********************************************* */
1563 hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
1567 i = sizeof(struct mvs_prd) * tei->n_elem;
1571 /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
1572 slot->response = buf_tmp;
1573 hdr->status_buf = cpu_to_le64(buf_tmp_dma);
1576 * Fill in TX ring and command slot header
1578 slot->tx = mvi->tx_prod;
1579 mvi->tx[mvi->tx_prod] = cpu_to_le32((TXQ_CMD_SMP << TXQ_CMD_SHIFT) |
1581 (sas_port->phy_mask << TXQ_PHY_SHIFT));
1583 hdr->flags |= flags;
1584 hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | ((req_len - 4) / 4));
1585 hdr->tags = cpu_to_le32(tag);
1588 /* generate open address frame hdr (first 12 bytes) */
1589 buf_oaf[0] = (1 << 7) | (0 << 4) | 0x01; /* initiator, SMP, ftype 1h */
1590 buf_oaf[1] = task->dev->linkrate & 0xf;
1591 *(u16 *)(buf_oaf + 2) = 0xFFFF; /* SAS SPEC */
1592 memcpy(buf_oaf + 4, task->dev->sas_addr, SAS_ADDR_SIZE);
1594 /* fill in PRD (scatter/gather) table, if any */
1595 for_each_sg(task->scatter, sg, tei->n_elem, i) {
1596 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
1597 buf_prd->len = cpu_to_le32(sg_dma_len(sg));
1602 /* copy cmd table */
1603 from = kmap_atomic(sg_page(sg_req), KM_IRQ0);
1604 memcpy(buf_cmd, from + sg_req->offset, req_len);
1605 kunmap_atomic(from, KM_IRQ0);
1610 pci_unmap_sg(mvi->pdev, &tei->task->smp_task.smp_resp, 1,
1611 PCI_DMA_FROMDEVICE);
1613 pci_unmap_sg(mvi->pdev, &tei->task->smp_task.smp_req, 1,
1618 static void mvs_free_reg_set(struct mvs_info *mvi, struct mvs_port *port)
1620 void __iomem *regs = mvi->regs;
1622 u8 *tfs = &port->taskfileset;
1624 if (*tfs == MVS_ID_NOT_MAPPED)
1627 offs = 1U << ((*tfs & 0x0f) + PCS_EN_SATA_REG_SHIFT);
1630 mw32(PCS, tmp & ~offs);
1633 mw32(CTL, tmp & ~offs);
1636 tmp = mr32(INT_STAT_SRS) & (1U << *tfs);
1638 mw32(INT_STAT_SRS, tmp);
1640 *tfs = MVS_ID_NOT_MAPPED;
1643 static u8 mvs_assign_reg_set(struct mvs_info *mvi, struct mvs_port *port)
1647 void __iomem *regs = mvi->regs;
1649 if (port->taskfileset != MVS_ID_NOT_MAPPED)
1654 for (i = 0; i < mvi->chip->srs_sz; i++) {
1657 offs = 1U << ((i & 0x0f) + PCS_EN_SATA_REG_SHIFT);
1658 if (!(tmp & offs)) {
1659 port->taskfileset = i;
1662 mw32(PCS, tmp | offs);
1664 mw32(CTL, tmp | offs);
1665 tmp = mr32(INT_STAT_SRS) & (1U << i);
1667 mw32(INT_STAT_SRS, tmp);
1671 return MVS_ID_NOT_MAPPED;
1674 static u32 mvs_get_ncq_tag(struct sas_task *task)
1677 struct ata_queued_cmd *qc = task->uldd_task;
1685 static int mvs_task_prep_ata(struct mvs_info *mvi,
1686 struct mvs_task_exec_info *tei)
1688 struct sas_task *task = tei->task;
1689 struct domain_device *dev = task->dev;
1690 struct mvs_cmd_hdr *hdr = tei->hdr;
1691 struct asd_sas_port *sas_port = dev->port;
1692 struct mvs_slot_info *slot;
1693 struct scatterlist *sg;
1694 struct mvs_prd *buf_prd;
1695 struct mvs_port *port = tei->port;
1697 u32 flags = (tei->n_elem << MCH_PRD_LEN_SHIFT);
1699 u8 *buf_cmd, *buf_oaf;
1700 dma_addr_t buf_tmp_dma;
1701 u32 i, req_len, resp_len;
1702 const u32 max_resp_len = SB_RFB_MAX;
1704 if (mvs_assign_reg_set(mvi, port) == MVS_ID_NOT_MAPPED)
1707 slot = &mvi->slot_info[tag];
1708 slot->tx = mvi->tx_prod;
1709 mvi->tx[mvi->tx_prod] = cpu_to_le32(TXQ_MODE_I | tag |
1710 (TXQ_CMD_STP << TXQ_CMD_SHIFT) |
1711 (sas_port->phy_mask << TXQ_PHY_SHIFT) |
1712 (port->taskfileset << TXQ_SRS_SHIFT));
1714 if (task->ata_task.use_ncq)
1716 if (dev->sata_dev.command_set == ATAPI_COMMAND_SET) {
1717 if (task->ata_task.fis.command != ATA_CMD_ID_ATAPI)
1721 /* FIXME: fill in port multiplier number */
1723 hdr->flags = cpu_to_le32(flags);
1725 /* FIXME: the low order order 5 bits for the TAG if enable NCQ */
1726 if (task->ata_task.use_ncq) {
1727 hdr->tags = cpu_to_le32(mvs_get_ncq_tag(task));
1728 /*Fill in task file */
1729 task->ata_task.fis.sector_count = hdr->tags << 3;
1731 hdr->tags = cpu_to_le32(tag);
1732 hdr->data_len = cpu_to_le32(task->total_xfer_len);
1735 * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
1738 /* region 1: command table area (MVS_ATA_CMD_SZ bytes) ************** */
1739 buf_cmd = buf_tmp = slot->buf;
1740 buf_tmp_dma = slot->buf_dma;
1742 hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
1744 buf_tmp += MVS_ATA_CMD_SZ;
1745 buf_tmp_dma += MVS_ATA_CMD_SZ;
1747 slot->cmd_size = MVS_ATA_CMD_SZ;
1750 /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
1751 /* used for STP. unused for SATA? */
1753 hdr->open_frame = cpu_to_le64(buf_tmp_dma);
1755 buf_tmp += MVS_OAF_SZ;
1756 buf_tmp_dma += MVS_OAF_SZ;
1758 /* region 3: PRD table ********************************************* */
1761 hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
1765 i = sizeof(struct mvs_prd) * tei->n_elem;
1769 /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
1770 /* FIXME: probably unused, for SATA. kept here just in case
1771 * we get a STP/SATA error information record
1773 slot->response = buf_tmp;
1774 hdr->status_buf = cpu_to_le64(buf_tmp_dma);
1776 req_len = sizeof(struct host_to_dev_fis);
1777 resp_len = MVS_SLOT_BUF_SZ - MVS_ATA_CMD_SZ -
1778 sizeof(struct mvs_err_info) - i;
1780 /* request, response lengths */
1781 resp_len = min(resp_len, max_resp_len);
1782 hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
1784 task->ata_task.fis.flags |= 0x80; /* C=1: update ATA cmd reg */
1785 /* fill in command FIS and ATAPI CDB */
1786 memcpy(buf_cmd, &task->ata_task.fis, sizeof(struct host_to_dev_fis));
1787 if (dev->sata_dev.command_set == ATAPI_COMMAND_SET)
1788 memcpy(buf_cmd + STP_ATAPI_CMD,
1789 task->ata_task.atapi_packet, 16);
1791 /* generate open address frame hdr (first 12 bytes) */
1792 buf_oaf[0] = (1 << 7) | (2 << 4) | 0x1; /* initiator, STP, ftype 1h */
1793 buf_oaf[1] = task->dev->linkrate & 0xf;
1794 *(u16 *)(buf_oaf + 2) = cpu_to_be16(tag);
1795 memcpy(buf_oaf + 4, task->dev->sas_addr, SAS_ADDR_SIZE);
1797 /* fill in PRD (scatter/gather) table, if any */
1798 for_each_sg(task->scatter, sg, tei->n_elem, i) {
1799 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
1800 buf_prd->len = cpu_to_le32(sg_dma_len(sg));
1807 static int mvs_task_prep_ssp(struct mvs_info *mvi,
1808 struct mvs_task_exec_info *tei)
1810 struct sas_task *task = tei->task;
1811 struct mvs_cmd_hdr *hdr = tei->hdr;
1812 struct mvs_port *port = tei->port;
1813 struct mvs_slot_info *slot;
1814 struct scatterlist *sg;
1815 struct mvs_prd *buf_prd;
1816 struct ssp_frame_hdr *ssp_hdr;
1818 u8 *buf_cmd, *buf_oaf, fburst = 0;
1819 dma_addr_t buf_tmp_dma;
1821 u32 resp_len, req_len, i, tag = tei->tag;
1822 const u32 max_resp_len = SB_RFB_MAX;
1824 slot = &mvi->slot_info[tag];
1826 slot->tx = mvi->tx_prod;
1827 mvi->tx[mvi->tx_prod] = cpu_to_le32(TXQ_MODE_I | tag |
1828 (TXQ_CMD_SSP << TXQ_CMD_SHIFT) |
1829 (port->wide_port_phymap << TXQ_PHY_SHIFT));
1832 if (task->ssp_task.enable_first_burst) {
1833 flags |= MCH_FBURST;
1836 hdr->flags = cpu_to_le32(flags |
1837 (tei->n_elem << MCH_PRD_LEN_SHIFT) |
1838 (MCH_SSP_FR_CMD << MCH_SSP_FR_TYPE_SHIFT));
1840 hdr->tags = cpu_to_le32(tag);
1841 hdr->data_len = cpu_to_le32(task->total_xfer_len);
1844 * arrange MVS_SLOT_BUF_SZ-sized DMA buffer according to our needs
1847 /* region 1: command table area (MVS_SSP_CMD_SZ bytes) ************** */
1848 buf_cmd = buf_tmp = slot->buf;
1849 buf_tmp_dma = slot->buf_dma;
1851 hdr->cmd_tbl = cpu_to_le64(buf_tmp_dma);
1853 buf_tmp += MVS_SSP_CMD_SZ;
1854 buf_tmp_dma += MVS_SSP_CMD_SZ;
1856 slot->cmd_size = MVS_SSP_CMD_SZ;
1859 /* region 2: open address frame area (MVS_OAF_SZ bytes) ********* */
1861 hdr->open_frame = cpu_to_le64(buf_tmp_dma);
1863 buf_tmp += MVS_OAF_SZ;
1864 buf_tmp_dma += MVS_OAF_SZ;
1866 /* region 3: PRD table ********************************************* */
1869 hdr->prd_tbl = cpu_to_le64(buf_tmp_dma);
1873 i = sizeof(struct mvs_prd) * tei->n_elem;
1877 /* region 4: status buffer (larger the PRD, smaller this buf) ****** */
1878 slot->response = buf_tmp;
1879 hdr->status_buf = cpu_to_le64(buf_tmp_dma);
1881 resp_len = MVS_SLOT_BUF_SZ - MVS_SSP_CMD_SZ - MVS_OAF_SZ -
1882 sizeof(struct mvs_err_info) - i;
1883 resp_len = min(resp_len, max_resp_len);
1885 req_len = sizeof(struct ssp_frame_hdr) + 28;
1887 /* request, response lengths */
1888 hdr->lens = cpu_to_le32(((resp_len / 4) << 16) | (req_len / 4));
1890 /* generate open address frame hdr (first 12 bytes) */
1891 buf_oaf[0] = (1 << 7) | (1 << 4) | 0x1; /* initiator, SSP, ftype 1h */
1892 buf_oaf[1] = task->dev->linkrate & 0xf;
1893 *(u16 *)(buf_oaf + 2) = cpu_to_be16(tag);
1894 memcpy(buf_oaf + 4, task->dev->sas_addr, SAS_ADDR_SIZE);
1896 /* fill in SSP frame header (Command Table.SSP frame header) */
1897 ssp_hdr = (struct ssp_frame_hdr *)buf_cmd;
1898 ssp_hdr->frame_type = SSP_COMMAND;
1899 memcpy(ssp_hdr->hashed_dest_addr, task->dev->hashed_sas_addr,
1900 HASHED_SAS_ADDR_SIZE);
1901 memcpy(ssp_hdr->hashed_src_addr,
1902 task->dev->port->ha->hashed_sas_addr, HASHED_SAS_ADDR_SIZE);
1903 ssp_hdr->tag = cpu_to_be16(tag);
1905 /* fill in command frame IU */
1906 buf_cmd += sizeof(*ssp_hdr);
1907 memcpy(buf_cmd, &task->ssp_task.LUN, 8);
1908 buf_cmd[9] = fburst | task->ssp_task.task_attr |
1909 (task->ssp_task.task_prio << 3);
1910 memcpy(buf_cmd + 12, &task->ssp_task.cdb, 16);
1912 /* fill in PRD (scatter/gather) table, if any */
1913 for_each_sg(task->scatter, sg, tei->n_elem, i) {
1914 buf_prd->addr = cpu_to_le64(sg_dma_address(sg));
1915 buf_prd->len = cpu_to_le32(sg_dma_len(sg));
1922 static int mvs_task_exec(struct sas_task *task, const int num, gfp_t gfp_flags)
1924 struct domain_device *dev = task->dev;
1925 struct mvs_info *mvi = dev->port->ha->lldd_ha;
1926 struct pci_dev *pdev = mvi->pdev;
1927 void __iomem *regs = mvi->regs;
1928 struct mvs_task_exec_info tei;
1929 struct sas_task *t = task;
1930 u32 tag = 0xdeadbeef, rc, n_elem = 0;
1931 unsigned long flags;
1932 u32 n = num, pass = 0;
1934 spin_lock_irqsave(&mvi->lock, flags);
1937 tei.port = &mvi->port[dev->port->id];
1939 if (!tei.port->port_attached) {
1940 struct task_status_struct *ts = &t->task_status;
1941 ts->stat = SAS_PHY_DOWN;
1946 if (!sas_protocol_ata(t->task_proto)) {
1947 if (t->num_scatter) {
1948 n_elem = pci_map_sg(mvi->pdev, t->scatter,
1957 n_elem = t->num_scatter;
1960 rc = mvs_tag_alloc(mvi, &tag);
1964 mvi->slot_info[tag].task = t;
1965 mvi->slot_info[tag].n_elem = n_elem;
1966 memset(mvi->slot_info[tag].buf, 0, MVS_SLOT_BUF_SZ);
1968 tei.hdr = &mvi->slot[tag];
1970 tei.n_elem = n_elem;
1972 switch (t->task_proto) {
1973 case SAS_PROTOCOL_SMP:
1974 rc = mvs_task_prep_smp(mvi, &tei);
1976 case SAS_PROTOCOL_SSP:
1977 rc = mvs_task_prep_ssp(mvi, &tei);
1979 case SAS_PROTOCOL_SATA:
1980 case SAS_PROTOCOL_STP:
1981 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:
1982 rc = mvs_task_prep_ata(mvi, &tei);
1985 dev_printk(KERN_ERR, &pdev->dev,
1986 "unknown sas_task proto: 0x%x\n",
1995 /* TODO: select normal or high priority */
1997 spin_lock(&t->task_state_lock);
1998 t->task_state_flags |= SAS_TASK_AT_INITIATOR;
1999 spin_unlock(&t->task_state_lock);
2002 spin_unlock_irqrestore(&mvi->lock, flags);
2003 mw32(TX_PROD_IDX, mvi->tx_prod);
2005 mvs_hba_memory_dump(mvi, tag, t->task_proto);
2008 mvi->tx_prod = (mvi->tx_prod + 1) & (MVS_CHIP_SLOT_SZ - 1);
2013 t = list_entry(t->list.next, struct sas_task, list);
2019 mvs_tag_free(mvi, tag);
2021 dev_printk(KERN_ERR, &pdev->dev, "mvsas exec failed[%d]!\n", rc);
2022 if (!sas_protocol_ata(t->task_proto))
2024 pci_unmap_sg(mvi->pdev, t->scatter, n_elem,
2028 mw32(TX_PROD_IDX, (mvi->tx_prod - 1) & (MVS_CHIP_SLOT_SZ - 1));
2029 spin_unlock_irqrestore(&mvi->lock, flags);
2033 static int mvs_task_abort(struct sas_task *task)
2036 unsigned long flags;
2037 struct mvs_info *mvi = task->dev->port->ha->lldd_ha;
2038 struct pci_dev *pdev = mvi->pdev;
2040 spin_lock_irqsave(&task->task_state_lock, flags);
2041 if (task->task_state_flags & SAS_TASK_STATE_DONE) {
2042 rc = TMF_RESP_FUNC_COMPLETE;
2045 spin_unlock_irqrestore(&task->task_state_lock, flags);
2048 rc = TMF_RESP_FUNC_COMPLETE;
2050 switch (task->task_proto) {
2051 case SAS_PROTOCOL_SMP:
2052 dev_printk(KERN_DEBUG, &pdev->dev, "SMP Abort! ");
2054 case SAS_PROTOCOL_SSP:
2055 dev_printk(KERN_DEBUG, &pdev->dev, "SSP Abort! ");
2057 case SAS_PROTOCOL_SATA:
2058 case SAS_PROTOCOL_STP:
2059 case SAS_PROTOCOL_SATA | SAS_PROTOCOL_STP:{
2060 dev_printk(KERN_DEBUG, &pdev->dev, "STP Abort! "
2061 "Dump D2H FIS: \n");
2062 mvs_hexdump(sizeof(struct host_to_dev_fis),
2063 (void *)&task->ata_task.fis, 0);
2064 dev_printk(KERN_DEBUG, &pdev->dev, "Dump ATAPI Cmd : \n");
2065 mvs_hexdump(16, task->ata_task.atapi_packet, 0);
2075 static void mvs_free(struct mvs_info *mvi)
2082 for (i = 0; i < MVS_SLOTS; i++) {
2083 struct mvs_slot_info *slot = &mvi->slot_info[i];
2086 dma_free_coherent(&mvi->pdev->dev, MVS_SLOT_BUF_SZ,
2087 slot->buf, slot->buf_dma);
2091 dma_free_coherent(&mvi->pdev->dev,
2092 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
2093 mvi->tx, mvi->tx_dma);
2095 dma_free_coherent(&mvi->pdev->dev, MVS_RX_FISL_SZ,
2096 mvi->rx_fis, mvi->rx_fis_dma);
2098 dma_free_coherent(&mvi->pdev->dev,
2099 sizeof(*mvi->rx) * MVS_RX_RING_SZ,
2100 mvi->rx, mvi->rx_dma);
2102 dma_free_coherent(&mvi->pdev->dev,
2103 sizeof(*mvi->slot) * MVS_SLOTS,
2104 mvi->slot, mvi->slot_dma);
2105 #ifdef MVS_ENABLE_PERI
2107 iounmap(mvi->peri_regs);
2112 scsi_host_put(mvi->shost);
2113 kfree(mvi->sas.sas_port);
2114 kfree(mvi->sas.sas_phy);
2118 /* FIXME: locking? */
2119 static int mvs_phy_control(struct asd_sas_phy *sas_phy, enum phy_func func,
2122 struct mvs_info *mvi = sas_phy->ha->lldd_ha;
2123 int rc = 0, phy_id = sas_phy->id;
2126 tmp = mvs_read_phy_ctl(mvi, phy_id);
2129 case PHY_FUNC_SET_LINK_RATE:{
2130 struct sas_phy_linkrates *rates = funcdata;
2131 u32 lrmin = 0, lrmax = 0;
2133 lrmin = (rates->minimum_linkrate << 8);
2134 lrmax = (rates->maximum_linkrate << 12);
2141 tmp &= ~(0xf << 12);
2144 mvs_write_phy_ctl(mvi, phy_id, tmp);
2148 case PHY_FUNC_HARD_RESET:
2149 if (tmp & PHY_RST_HARD)
2151 mvs_write_phy_ctl(mvi, phy_id, tmp | PHY_RST_HARD);
2154 case PHY_FUNC_LINK_RESET:
2155 mvs_write_phy_ctl(mvi, phy_id, tmp | PHY_RST);
2158 case PHY_FUNC_DISABLE:
2159 case PHY_FUNC_RELEASE_SPINUP_HOLD:
2167 static void __devinit mvs_phy_init(struct mvs_info *mvi, int phy_id)
2169 struct mvs_phy *phy = &mvi->phy[phy_id];
2170 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2172 sas_phy->enabled = (phy_id < mvi->chip->n_phy) ? 1 : 0;
2173 sas_phy->class = SAS;
2174 sas_phy->iproto = SAS_PROTOCOL_ALL;
2175 sas_phy->tproto = 0;
2176 sas_phy->type = PHY_TYPE_PHYSICAL;
2177 sas_phy->role = PHY_ROLE_INITIATOR;
2178 sas_phy->oob_mode = OOB_NOT_CONNECTED;
2179 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
2181 sas_phy->id = phy_id;
2182 sas_phy->sas_addr = &mvi->sas_addr[0];
2183 sas_phy->frame_rcvd = &phy->frame_rcvd[0];
2184 sas_phy->ha = &mvi->sas;
2185 sas_phy->lldd_phy = phy;
2188 static struct mvs_info *__devinit mvs_alloc(struct pci_dev *pdev,
2189 const struct pci_device_id *ent)
2191 struct mvs_info *mvi;
2192 unsigned long res_start, res_len, res_flag;
2193 struct asd_sas_phy **arr_phy;
2194 struct asd_sas_port **arr_port;
2195 const struct mvs_chip_info *chip = &mvs_chips[ent->driver_data];
2199 * alloc and init our per-HBA mvs_info struct
2202 mvi = kzalloc(sizeof(*mvi), GFP_KERNEL);
2206 spin_lock_init(&mvi->lock);
2210 if (pdev->device == 0x6440 && pdev->revision == 0)
2211 mvi->flags |= MVF_PHY_PWR_FIX;
2214 * alloc and init SCSI, SAS glue
2217 mvi->shost = scsi_host_alloc(&mvs_sht, sizeof(void *));
2221 arr_phy = kcalloc(MVS_MAX_PHYS, sizeof(void *), GFP_KERNEL);
2222 arr_port = kcalloc(MVS_MAX_PHYS, sizeof(void *), GFP_KERNEL);
2223 if (!arr_phy || !arr_port)
2226 for (i = 0; i < MVS_MAX_PHYS; i++) {
2227 mvs_phy_init(mvi, i);
2228 arr_phy[i] = &mvi->phy[i].sas_phy;
2229 arr_port[i] = &mvi->port[i].sas_port;
2232 SHOST_TO_SAS_HA(mvi->shost) = &mvi->sas;
2233 mvi->shost->transportt = mvs_stt;
2234 mvi->shost->max_id = 21;
2235 mvi->shost->max_lun = ~0;
2236 mvi->shost->max_channel = 0;
2237 mvi->shost->max_cmd_len = 16;
2239 mvi->sas.sas_ha_name = DRV_NAME;
2240 mvi->sas.dev = &pdev->dev;
2241 mvi->sas.lldd_module = THIS_MODULE;
2242 mvi->sas.sas_addr = &mvi->sas_addr[0];
2243 mvi->sas.sas_phy = arr_phy;
2244 mvi->sas.sas_port = arr_port;
2245 mvi->sas.num_phys = chip->n_phy;
2246 mvi->sas.lldd_max_execute_num = MVS_CHIP_SLOT_SZ - 1;
2247 mvi->sas.lldd_queue_size = MVS_QUEUE_SIZE;
2248 mvi->can_queue = (MVS_CHIP_SLOT_SZ >> 1) - 1;
2249 mvi->sas.lldd_ha = mvi;
2250 mvi->sas.core.shost = mvi->shost;
2255 * ioremap main and peripheral registers
2258 #ifdef MVS_ENABLE_PERI
2259 res_start = pci_resource_start(pdev, 2);
2260 res_len = pci_resource_len(pdev, 2);
2261 if (!res_start || !res_len)
2264 mvi->peri_regs = ioremap_nocache(res_start, res_len);
2265 if (!mvi->peri_regs)
2269 res_start = pci_resource_start(pdev, 4);
2270 res_len = pci_resource_len(pdev, 4);
2271 if (!res_start || !res_len)
2274 res_flag = pci_resource_flags(pdev, 4);
2275 if (res_flag & IORESOURCE_CACHEABLE)
2276 mvi->regs = ioremap(res_start, res_len);
2278 mvi->regs = ioremap_nocache(res_start, res_len);
2284 * alloc and init our DMA areas
2287 mvi->tx = dma_alloc_coherent(&pdev->dev,
2288 sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ,
2289 &mvi->tx_dma, GFP_KERNEL);
2292 memset(mvi->tx, 0, sizeof(*mvi->tx) * MVS_CHIP_SLOT_SZ);
2294 mvi->rx_fis = dma_alloc_coherent(&pdev->dev, MVS_RX_FISL_SZ,
2295 &mvi->rx_fis_dma, GFP_KERNEL);
2298 memset(mvi->rx_fis, 0, MVS_RX_FISL_SZ);
2300 mvi->rx = dma_alloc_coherent(&pdev->dev,
2301 sizeof(*mvi->rx) * MVS_RX_RING_SZ,
2302 &mvi->rx_dma, GFP_KERNEL);
2305 memset(mvi->rx, 0, sizeof(*mvi->rx) * MVS_RX_RING_SZ);
2307 mvi->rx[0] = cpu_to_le32(0xfff);
2308 mvi->rx_cons = 0xfff;
2310 mvi->slot = dma_alloc_coherent(&pdev->dev,
2311 sizeof(*mvi->slot) * MVS_SLOTS,
2312 &mvi->slot_dma, GFP_KERNEL);
2315 memset(mvi->slot, 0, sizeof(*mvi->slot) * MVS_SLOTS);
2317 for (i = 0; i < MVS_SLOTS; i++) {
2318 struct mvs_slot_info *slot = &mvi->slot_info[i];
2320 slot->buf = dma_alloc_coherent(&pdev->dev, MVS_SLOT_BUF_SZ,
2321 &slot->buf_dma, GFP_KERNEL);
2324 memset(slot->buf, 0, MVS_SLOT_BUF_SZ);
2327 /* finally, read NVRAM to get our SAS address */
2328 if (mvs_nvram_read(mvi, NVR_SAS_ADDR, &mvi->sas_addr, 8))
2337 static u32 mvs_cr32(void __iomem *regs, u32 addr)
2339 mw32(CMD_ADDR, addr);
2340 return mr32(CMD_DATA);
2343 static void mvs_cw32(void __iomem *regs, u32 addr, u32 val)
2345 mw32(CMD_ADDR, addr);
2346 mw32(CMD_DATA, val);
2349 static u32 mvs_read_phy_ctl(struct mvs_info *mvi, u32 port)
2351 void __iomem *regs = mvi->regs;
2352 return (port < 4)?mr32(P0_SER_CTLSTAT + port * 4):
2353 mr32(P4_SER_CTLSTAT + (port - 4) * 4);
2356 static void mvs_write_phy_ctl(struct mvs_info *mvi, u32 port, u32 val)
2358 void __iomem *regs = mvi->regs;
2360 mw32(P0_SER_CTLSTAT + port * 4, val);
2362 mw32(P4_SER_CTLSTAT + (port - 4) * 4, val);
2365 static u32 mvs_read_port(struct mvs_info *mvi, u32 off, u32 off2, u32 port)
2367 void __iomem *regs = mvi->regs + off;
2368 void __iomem *regs2 = mvi->regs + off2;
2369 return (port < 4)?readl(regs + port * 8):
2370 readl(regs2 + (port - 4) * 8);
2373 static void mvs_write_port(struct mvs_info *mvi, u32 off, u32 off2,
2376 void __iomem *regs = mvi->regs + off;
2377 void __iomem *regs2 = mvi->regs + off2;
2379 writel(val, regs + port * 8);
2381 writel(val, regs2 + (port - 4) * 8);
2384 static u32 mvs_read_port_cfg_data(struct mvs_info *mvi, u32 port)
2386 return mvs_read_port(mvi, MVS_P0_CFG_DATA, MVS_P4_CFG_DATA, port);
2389 static void mvs_write_port_cfg_data(struct mvs_info *mvi, u32 port, u32 val)
2391 mvs_write_port(mvi, MVS_P0_CFG_DATA, MVS_P4_CFG_DATA, port, val);
2394 static void mvs_write_port_cfg_addr(struct mvs_info *mvi, u32 port, u32 addr)
2396 mvs_write_port(mvi, MVS_P0_CFG_ADDR, MVS_P4_CFG_ADDR, port, addr);
2399 static u32 mvs_read_port_vsr_data(struct mvs_info *mvi, u32 port)
2401 return mvs_read_port(mvi, MVS_P0_VSR_DATA, MVS_P4_VSR_DATA, port);
2404 static void mvs_write_port_vsr_data(struct mvs_info *mvi, u32 port, u32 val)
2406 mvs_write_port(mvi, MVS_P0_VSR_DATA, MVS_P4_VSR_DATA, port, val);
2409 static void mvs_write_port_vsr_addr(struct mvs_info *mvi, u32 port, u32 addr)
2411 mvs_write_port(mvi, MVS_P0_VSR_ADDR, MVS_P4_VSR_ADDR, port, addr);
2414 static u32 mvs_read_port_irq_stat(struct mvs_info *mvi, u32 port)
2416 return mvs_read_port(mvi, MVS_P0_INT_STAT, MVS_P4_INT_STAT, port);
2419 static void mvs_write_port_irq_stat(struct mvs_info *mvi, u32 port, u32 val)
2421 mvs_write_port(mvi, MVS_P0_INT_STAT, MVS_P4_INT_STAT, port, val);
2424 static u32 mvs_read_port_irq_mask(struct mvs_info *mvi, u32 port)
2426 return mvs_read_port(mvi, MVS_P0_INT_MASK, MVS_P4_INT_MASK, port);
2429 static void mvs_write_port_irq_mask(struct mvs_info *mvi, u32 port, u32 val)
2431 mvs_write_port(mvi, MVS_P0_INT_MASK, MVS_P4_INT_MASK, port, val);
2434 static void __devinit mvs_phy_hacks(struct mvs_info *mvi)
2436 void __iomem *regs = mvi->regs;
2439 /* workaround for SATA R-ERR, to ignore phy glitch */
2440 tmp = mvs_cr32(regs, CMD_PHY_TIMER);
2443 mvs_cw32(regs, CMD_PHY_TIMER, tmp);
2445 /* enable retry 127 times */
2446 mvs_cw32(regs, CMD_SAS_CTL1, 0x7f7f);
2448 /* extend open frame timeout to max */
2449 tmp = mvs_cr32(regs, CMD_SAS_CTL0);
2452 mvs_cw32(regs, CMD_SAS_CTL0, tmp);
2454 /* workaround for WDTIMEOUT , set to 550 ms */
2455 mvs_cw32(regs, CMD_WD_TIMER, 0xffffff);
2457 /* not to halt for different port op during wideport link change */
2458 mvs_cw32(regs, CMD_APP_ERR_CONFIG, 0xffefbf7d);
2460 /* workaround for Seagate disk not-found OOB sequence, recv
2461 * COMINIT before sending out COMWAKE */
2462 tmp = mvs_cr32(regs, CMD_PHY_MODE_21);
2465 mvs_cw32(regs, CMD_PHY_MODE_21, tmp);
2467 tmp = mvs_cr32(regs, CMD_PHY_TIMER);
2469 tmp |= (2U << 29); /* 8 ms retry */
2470 mvs_cw32(regs, CMD_PHY_TIMER, tmp);
2472 /* TEST - for phy decoding error, adjust voltage levels */
2473 mw32(P0_VSR_ADDR + 0, 0x8);
2474 mw32(P0_VSR_DATA + 0, 0x2F0);
2476 mw32(P0_VSR_ADDR + 8, 0x8);
2477 mw32(P0_VSR_DATA + 8, 0x2F0);
2479 mw32(P0_VSR_ADDR + 16, 0x8);
2480 mw32(P0_VSR_DATA + 16, 0x2F0);
2482 mw32(P0_VSR_ADDR + 24, 0x8);
2483 mw32(P0_VSR_DATA + 24, 0x2F0);
2487 static void mvs_enable_xmt(struct mvs_info *mvi, int PhyId)
2489 void __iomem *regs = mvi->regs;
2493 if (mvi->chip->n_phy <= 4)
2494 tmp |= 1 << (PhyId + PCS_EN_PORT_XMT_SHIFT);
2496 tmp |= 1 << (PhyId + PCS_EN_PORT_XMT_SHIFT2);
2500 static void mvs_detect_porttype(struct mvs_info *mvi, int i)
2502 void __iomem *regs = mvi->regs;
2504 struct mvs_phy *phy = &mvi->phy[i];
2506 /* TODO check & save device type */
2507 reg = mr32(GBL_PORT_TYPE);
2509 if (reg & MODE_SAS_SATA & (1 << i))
2510 phy->phy_type |= PORT_TYPE_SAS;
2512 phy->phy_type |= PORT_TYPE_SATA;
2515 static void *mvs_get_d2h_reg(struct mvs_info *mvi, int i, void *buf)
2517 u32 *s = (u32 *) buf;
2522 mvs_write_port_cfg_addr(mvi, i, PHYR_SATA_SIG3);
2523 s[3] = mvs_read_port_cfg_data(mvi, i);
2525 mvs_write_port_cfg_addr(mvi, i, PHYR_SATA_SIG2);
2526 s[2] = mvs_read_port_cfg_data(mvi, i);
2528 mvs_write_port_cfg_addr(mvi, i, PHYR_SATA_SIG1);
2529 s[1] = mvs_read_port_cfg_data(mvi, i);
2531 mvs_write_port_cfg_addr(mvi, i, PHYR_SATA_SIG0);
2532 s[0] = mvs_read_port_cfg_data(mvi, i);
2537 static u32 mvs_is_sig_fis_received(u32 irq_status)
2539 return irq_status & PHYEV_SIG_FIS;
2542 static void mvs_update_wideport(struct mvs_info *mvi, int i)
2544 struct mvs_phy *phy = &mvi->phy[i];
2545 struct mvs_port *port = phy->port;
2548 for_each_phy(port->wide_port_phymap, no, j, mvi->chip->n_phy)
2550 mvs_write_port_cfg_addr(mvi, no, PHYR_WIDE_PORT);
2551 mvs_write_port_cfg_data(mvi, no,
2552 port->wide_port_phymap);
2554 mvs_write_port_cfg_addr(mvi, no, PHYR_WIDE_PORT);
2555 mvs_write_port_cfg_data(mvi, no, 0);
2559 static u32 mvs_is_phy_ready(struct mvs_info *mvi, int i)
2562 struct mvs_phy *phy = &mvi->phy[i];
2563 struct mvs_port *port;
2565 tmp = mvs_read_phy_ctl(mvi, i);
2567 if ((tmp & PHY_READY_MASK) && !(phy->irq_status & PHYEV_POOF)) {
2569 phy->phy_attached = 1;
2575 if (phy->phy_type & PORT_TYPE_SAS) {
2576 port->wide_port_phymap &= ~(1U << i);
2577 if (!port->wide_port_phymap)
2578 port->port_attached = 0;
2579 mvs_update_wideport(mvi, i);
2580 } else if (phy->phy_type & PORT_TYPE_SATA)
2581 port->port_attached = 0;
2582 mvs_free_reg_set(mvi, phy->port);
2584 phy->phy_attached = 0;
2585 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
2590 static void mvs_update_phyinfo(struct mvs_info *mvi, int i,
2593 struct mvs_phy *phy = &mvi->phy[i];
2594 struct pci_dev *pdev = mvi->pdev;
2598 mvs_write_port_cfg_addr(mvi, i, PHYR_IDENTIFY);
2599 phy->dev_info = mvs_read_port_cfg_data(mvi, i);
2601 mvs_write_port_cfg_addr(mvi, i, PHYR_ADDR_HI);
2602 phy->dev_sas_addr = (u64) mvs_read_port_cfg_data(mvi, i) << 32;
2604 mvs_write_port_cfg_addr(mvi, i, PHYR_ADDR_LO);
2605 phy->dev_sas_addr |= mvs_read_port_cfg_data(mvi, i);
2608 phy->irq_status = mvs_read_port_irq_stat(mvi, i);
2609 phy->phy_status = mvs_is_phy_ready(mvi, i);
2612 if (phy->phy_status) {
2614 struct asd_sas_phy *sas_phy = mvi->sas.sas_phy[i];
2616 mvs_write_port_cfg_addr(mvi, i, PHYR_PHY_STAT);
2617 phy_st = mvs_read_port_cfg_data(mvi, i);
2620 (phy->phy_status & PHY_NEG_SPP_PHYS_LINK_RATE_MASK) >>
2621 PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET;
2623 /* Updated attached_sas_addr */
2624 mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_ADDR_HI);
2625 phy->att_dev_sas_addr =
2626 (u64) mvs_read_port_cfg_data(mvi, i) << 32;
2628 mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_ADDR_LO);
2629 phy->att_dev_sas_addr |= mvs_read_port_cfg_data(mvi, i);
2631 dev_printk(KERN_DEBUG, &pdev->dev,
2632 "phy[%d] Get Attached Address 0x%llX ,"
2633 " SAS Address 0x%llX\n",
2634 i, phy->att_dev_sas_addr, phy->dev_sas_addr);
2635 dev_printk(KERN_DEBUG, &pdev->dev,
2636 "Rate = %x , type = %d\n",
2637 sas_phy->linkrate, phy->phy_type);
2641 * If the device is capable of supporting a wide port
2642 * on its phys, it may configure the phys as a wide port.
2644 if (phy->phy_type & PORT_TYPE_SAS)
2645 for (j = 0; j < mvi->chip->n_phy && j != i; ++j) {
2646 if ((mvi->phy[j].phy_attached) &&
2647 (mvi->phy[j].phy_type & PORT_TYPE_SAS))
2648 if (phy->att_dev_sas_addr ==
2649 mvi->phy[j].att_dev_sas_addr - 1) {
2650 phy->att_dev_sas_addr =
2651 mvi->phy[j].att_dev_sas_addr;
2658 tmp64 = cpu_to_be64(phy->att_dev_sas_addr);
2659 memcpy(sas_phy->attached_sas_addr, &tmp64, SAS_ADDR_SIZE);
2661 if (phy->phy_type & PORT_TYPE_SAS) {
2662 mvs_write_port_cfg_addr(mvi, i, PHYR_ATT_DEV_INFO);
2663 phy->att_dev_info = mvs_read_port_cfg_data(mvi, i);
2664 phy->identify.device_type =
2665 phy->att_dev_info & PORT_DEV_TYPE_MASK;
2667 if (phy->identify.device_type == SAS_END_DEV)
2668 phy->identify.target_port_protocols =
2670 else if (phy->identify.device_type != NO_DEVICE)
2671 phy->identify.target_port_protocols =
2673 if (phy_st & PHY_OOB_DTCTD)
2674 sas_phy->oob_mode = SAS_OOB_MODE;
2675 phy->frame_rcvd_size =
2676 sizeof(struct sas_identify_frame);
2677 } else if (phy->phy_type & PORT_TYPE_SATA) {
2678 phy->identify.target_port_protocols = SAS_PROTOCOL_STP;
2679 if (mvs_is_sig_fis_received(phy->irq_status)) {
2680 if (phy_st & PHY_OOB_DTCTD)
2681 sas_phy->oob_mode = SATA_OOB_MODE;
2682 phy->frame_rcvd_size =
2683 sizeof(struct dev_to_host_fis);
2684 mvs_get_d2h_reg(mvi, i,
2685 (void *)sas_phy->frame_rcvd);
2687 dev_printk(KERN_DEBUG, &pdev->dev,
2691 /* workaround for HW phy decoding error on 1.5g disk drive */
2692 mvs_write_port_vsr_addr(mvi, i, VSR_PHY_MODE6);
2693 tmp = mvs_read_port_vsr_data(mvi, i);
2694 if (((phy->phy_status & PHY_NEG_SPP_PHYS_LINK_RATE_MASK) >>
2695 PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET) ==
2696 SAS_LINK_RATE_1_5_GBPS)
2697 tmp &= ~PHY_MODE6_DTL_SPEED;
2699 tmp |= PHY_MODE6_DTL_SPEED;
2700 mvs_write_port_vsr_data(mvi, i, tmp);
2704 mvs_write_port_irq_stat(mvi, i, phy->irq_status);
2707 static void mvs_port_formed(struct asd_sas_phy *sas_phy)
2709 struct sas_ha_struct *sas_ha = sas_phy->ha;
2710 struct mvs_info *mvi = sas_ha->lldd_ha;
2711 struct asd_sas_port *sas_port = sas_phy->port;
2712 struct mvs_phy *phy = sas_phy->lldd_phy;
2713 struct mvs_port *port = &mvi->port[sas_port->id];
2714 unsigned long flags;
2716 spin_lock_irqsave(&mvi->lock, flags);
2717 port->port_attached = 1;
2719 port->taskfileset = MVS_ID_NOT_MAPPED;
2720 if (phy->phy_type & PORT_TYPE_SAS) {
2721 port->wide_port_phymap = sas_port->phy_mask;
2722 mvs_update_wideport(mvi, sas_phy->id);
2724 spin_unlock_irqrestore(&mvi->lock, flags);
2727 static int __devinit mvs_hw_init(struct mvs_info *mvi)
2729 void __iomem *regs = mvi->regs;
2733 /* make sure interrupts are masked immediately (paranoia) */
2735 tmp = mr32(GBL_CTL);
2737 /* Reset Controller */
2738 if (!(tmp & HBA_RST)) {
2739 if (mvi->flags & MVF_PHY_PWR_FIX) {
2740 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp);
2741 tmp &= ~PCTL_PWR_ON;
2743 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);
2745 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp);
2746 tmp &= ~PCTL_PWR_ON;
2748 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp);
2751 /* global reset, incl. COMRESET/H_RESET_N (self-clearing) */
2752 mw32_f(GBL_CTL, HBA_RST);
2755 /* wait for reset to finish; timeout is just a guess */
2760 if (!(mr32(GBL_CTL) & HBA_RST))
2763 if (mr32(GBL_CTL) & HBA_RST) {
2764 dev_printk(KERN_ERR, &mvi->pdev->dev, "HBA reset failed\n");
2769 /* make sure RST is set; HBA_RST /should/ have done that for us */
2771 if (cctl & CCTL_RST)
2774 mw32_f(CTL, cctl | CCTL_RST);
2776 /* write to device control _AND_ device status register? - A.C. */
2777 pci_read_config_dword(mvi->pdev, PCR_DEV_CTRL, &tmp);
2778 tmp &= ~PRD_REQ_MASK;
2779 tmp |= PRD_REQ_SIZE;
2780 pci_write_config_dword(mvi->pdev, PCR_DEV_CTRL, tmp);
2782 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL, &tmp);
2785 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL, tmp);
2787 pci_read_config_dword(mvi->pdev, PCR_PHY_CTL2, &tmp);
2790 pci_write_config_dword(mvi->pdev, PCR_PHY_CTL2, tmp);
2795 mw32(PCS, 0); /*MVS_PCS */
2799 mw32(CMD_LIST_LO, mvi->slot_dma);
2800 mw32(CMD_LIST_HI, (mvi->slot_dma >> 16) >> 16);
2802 mw32(RX_FIS_LO, mvi->rx_fis_dma);
2803 mw32(RX_FIS_HI, (mvi->rx_fis_dma >> 16) >> 16);
2805 mw32(TX_CFG, MVS_CHIP_SLOT_SZ);
2806 mw32(TX_LO, mvi->tx_dma);
2807 mw32(TX_HI, (mvi->tx_dma >> 16) >> 16);
2809 mw32(RX_CFG, MVS_RX_RING_SZ);
2810 mw32(RX_LO, mvi->rx_dma);
2811 mw32(RX_HI, (mvi->rx_dma >> 16) >> 16);
2813 /* enable auto port detection */
2814 mw32(GBL_PORT_TYPE, MODE_AUTO_DET_EN);
2816 /* init and reset phys */
2817 for (i = 0; i < mvi->chip->n_phy; i++) {
2818 u32 lo = be32_to_cpu(*(u32 *)&mvi->sas_addr[4]);
2819 u32 hi = be32_to_cpu(*(u32 *)&mvi->sas_addr[0]);
2821 mvs_detect_porttype(mvi, i);
2823 /* set phy local SAS address */
2824 mvs_write_port_cfg_addr(mvi, i, PHYR_ADDR_LO);
2825 mvs_write_port_cfg_data(mvi, i, lo);
2826 mvs_write_port_cfg_addr(mvi, i, PHYR_ADDR_HI);
2827 mvs_write_port_cfg_data(mvi, i, hi);
2830 tmp = mvs_read_phy_ctl(mvi, i);
2832 mvs_write_phy_ctl(mvi, i, tmp);
2837 for (i = 0; i < mvi->chip->n_phy; i++) {
2838 /* clear phy int status */
2839 tmp = mvs_read_port_irq_stat(mvi, i);
2840 tmp &= ~PHYEV_SIG_FIS;
2841 mvs_write_port_irq_stat(mvi, i, tmp);
2843 /* set phy int mask */
2844 tmp = PHYEV_RDY_CH | PHYEV_BROAD_CH | PHYEV_UNASSOC_FIS |
2845 PHYEV_ID_DONE | PHYEV_DEC_ERR;
2846 mvs_write_port_irq_mask(mvi, i, tmp);
2849 mvs_update_phyinfo(mvi, i, 1);
2850 mvs_enable_xmt(mvi, i);
2853 /* FIXME: update wide port bitmaps */
2855 /* little endian for open address and command table, etc. */
2857 * it seems that ( from the spec ) turning on big-endian won't
2858 * do us any good on big-endian machines, need further confirmation
2861 cctl |= CCTL_ENDIAN_CMD;
2862 cctl |= CCTL_ENDIAN_DATA;
2863 cctl &= ~CCTL_ENDIAN_OPEN;
2864 cctl |= CCTL_ENDIAN_RSP;
2867 /* reset CMD queue */
2871 /* interrupt coalescing may cause missing HW interrput in some case,
2872 * and the max count is 0x1ff, while our max slot is 0x200,
2873 * it will make count 0.
2876 mw32(INT_COAL, tmp);
2879 mw32(INT_COAL_TMOUT, tmp);
2881 /* ladies and gentlemen, start your engines */
2883 mw32(TX_CFG, MVS_CHIP_SLOT_SZ | TX_EN);
2884 mw32(RX_CFG, MVS_RX_RING_SZ | RX_EN);
2885 /* enable CMD/CMPL_Q/RESP mode */
2886 mw32(PCS, PCS_SATA_RETRY | PCS_FIS_RX_EN | PCS_CMD_EN);
2888 /* re-enable interrupts globally */
2889 mvs_hba_interrupt_enable(mvi);
2891 /* enable completion queue interrupt */
2892 tmp = (CINT_PORT_MASK | CINT_DONE | CINT_MEM);
2893 mw32(INT_MASK, tmp);
2898 static void __devinit mvs_print_info(struct mvs_info *mvi)
2900 struct pci_dev *pdev = mvi->pdev;
2901 static int printed_version;
2903 if (!printed_version++)
2904 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
2906 dev_printk(KERN_INFO, &pdev->dev, "%u phys, addr %llx\n",
2907 mvi->chip->n_phy, SAS_ADDR(mvi->sas_addr));
2910 static int __devinit mvs_pci_init(struct pci_dev *pdev,
2911 const struct pci_device_id *ent)
2914 struct mvs_info *mvi;
2915 irq_handler_t irq_handler = mvs_interrupt;
2917 rc = pci_enable_device(pdev);
2921 pci_set_master(pdev);
2923 rc = pci_request_regions(pdev, DRV_NAME);
2925 goto err_out_disable;
2927 rc = pci_go_64(pdev);
2929 goto err_out_regions;
2931 mvi = mvs_alloc(pdev, ent);
2934 goto err_out_regions;
2937 rc = mvs_hw_init(mvi);
2941 #ifndef MVS_DISABLE_MSI
2942 if (!pci_enable_msi(pdev)) {
2944 void __iomem *regs = mvi->regs;
2945 mvi->flags |= MVF_MSI;
2946 irq_handler = mvs_msi_interrupt;
2948 mw32(PCS, tmp | PCS_SELF_CLEAR);
2952 rc = request_irq(pdev->irq, irq_handler, IRQF_SHARED, DRV_NAME, mvi);
2956 rc = scsi_add_host(mvi->shost, &pdev->dev);
2960 rc = sas_register_ha(&mvi->sas);
2964 pci_set_drvdata(pdev, mvi);
2966 mvs_print_info(mvi);
2968 scsi_scan_host(mvi->shost);
2973 scsi_remove_host(mvi->shost);
2975 free_irq(pdev->irq, mvi);
2977 if (mvi->flags |= MVF_MSI)
2978 pci_disable_msi(pdev);
2982 pci_release_regions(pdev);
2984 pci_disable_device(pdev);
2988 static void __devexit mvs_pci_remove(struct pci_dev *pdev)
2990 struct mvs_info *mvi = pci_get_drvdata(pdev);
2992 pci_set_drvdata(pdev, NULL);
2995 sas_unregister_ha(&mvi->sas);
2996 mvs_hba_interrupt_disable(mvi);
2997 sas_remove_host(mvi->shost);
2998 scsi_remove_host(mvi->shost);
3000 free_irq(pdev->irq, mvi);
3001 if (mvi->flags & MVF_MSI)
3002 pci_disable_msi(pdev);
3004 pci_release_regions(pdev);
3006 pci_disable_device(pdev);
3009 static struct sas_domain_function_template mvs_transport_ops = {
3010 .lldd_execute_task = mvs_task_exec,
3011 .lldd_control_phy = mvs_phy_control,
3012 .lldd_abort_task = mvs_task_abort,
3013 .lldd_port_formed = mvs_port_formed
3016 static struct pci_device_id __devinitdata mvs_pci_table[] = {
3017 { PCI_VDEVICE(MARVELL, 0x6320), chip_6320 },
3018 { PCI_VDEVICE(MARVELL, 0x6340), chip_6440 },
3019 { PCI_VDEVICE(MARVELL, 0x6440), chip_6440 },
3020 { PCI_VDEVICE(MARVELL, 0x6480), chip_6480 },
3022 { } /* terminate list */
3025 static struct pci_driver mvs_pci_driver = {
3027 .id_table = mvs_pci_table,
3028 .probe = mvs_pci_init,
3029 .remove = __devexit_p(mvs_pci_remove),
3032 static int __init mvs_init(void)
3036 mvs_stt = sas_domain_attach_transport(&mvs_transport_ops);
3040 rc = pci_register_driver(&mvs_pci_driver);
3047 sas_release_transport(mvs_stt);
3051 static void __exit mvs_exit(void)
3053 pci_unregister_driver(&mvs_pci_driver);
3054 sas_release_transport(mvs_stt);
3057 module_init(mvs_init);
3058 module_exit(mvs_exit);
3060 MODULE_AUTHOR("Jeff Garzik <jgarzik@pobox.com>");
3061 MODULE_DESCRIPTION("Marvell 88SE6440 SAS/SATA controller driver");
3062 MODULE_VERSION(DRV_VERSION);
3063 MODULE_LICENSE("GPL");
3064 MODULE_DEVICE_TABLE(pci, mvs_pci_table);