err.no Git - linux-2.6/blob - drivers/scsi/lpfc/lpfc_mbox.c

   1 /*******************************************************************
   2  * This file is part of the Emulex Linux Device Driver for         *
   3  * Fibre Channel Host Bus Adapters.                                *
   4  * Copyright (C) 2004-2007 Emulex.  All rights reserved.           *
   5  * EMULEX and SLI are trademarks of Emulex.                        *
   6  * www.emulex.com                                                  *
   7  * Portions Copyright (C) 2004-2005 Christoph Hellwig              *
   8  *                                                                 *
   9  * This program is free software; you can redistribute it and/or   *
  10  * modify it under the terms of version 2 of the GNU General       *
  11  * Public License as published by the Free Software Foundation.    *
  12  * This program is distributed in the hope that it will be useful. *
  13  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
  14  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
  15  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
  16  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
  17  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
  18  * more details, a copy of which can be found in the file COPYING  *
  19  * included with this package.                                     *
  20  *******************************************************************/
  21
  22 #include <linux/blkdev.h>
  23 #include <linux/pci.h>
  24 #include <linux/interrupt.h>
  25
  26 #include <scsi/scsi_device.h>
  27 #include <scsi/scsi_transport_fc.h>
  28
  29 #include <scsi/scsi.h>
  30
  31 #include "lpfc_hw.h"
  32 #include "lpfc_sli.h"
  33 #include "lpfc_disc.h"
  34 #include "lpfc_scsi.h"
  35 #include "lpfc.h"
  36 #include "lpfc_logmsg.h"
  37 #include "lpfc_crtn.h"
  38 #include "lpfc_compat.h"
  39
  40 /**********************************************/
  41
  42 /*                mailbox command             */
  43 /**********************************************/
  44 void
  45 lpfc_dump_mem(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb, uint16_t offset)
  46 {
  47         MAILBOX_t *mb;
  48         void *ctx;
  49
  50         mb = &pmb->mb;
  51         ctx = pmb->context2;
  52
  53         /* Setup to dump VPD region */
  54         memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
  55         mb->mbxCommand = MBX_DUMP_MEMORY;
  56         mb->un.varDmp.cv = 1;
  57         mb->un.varDmp.type = DMP_NV_PARAMS;
  58         mb->un.varDmp.entry_index = offset;
  59         mb->un.varDmp.region_id = DMP_REGION_VPD;
  60         mb->un.varDmp.word_cnt = (DMP_RSP_SIZE / sizeof (uint32_t));
  61         mb->un.varDmp.co = 0;
  62         mb->un.varDmp.resp_offset = 0;
  63         pmb->context2 = ctx;
  64         mb->mbxOwner = OWN_HOST;
  65         return;
  66 }
  67
  68 /**********************************************/
  69 /*  lpfc_read_nv  Issue a READ NVPARAM        */
  70 /*                mailbox command             */
  71 /**********************************************/
  72 void
  73 lpfc_read_nv(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb)
  74 {
  75         MAILBOX_t *mb;
  76
  77         mb = &pmb->mb;
  78         memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
  79         mb->mbxCommand = MBX_READ_NV;
  80         mb->mbxOwner = OWN_HOST;
  81         return;
  82 }
  83
  84 /**********************************************/
  85 /*  lpfc_read_la  Issue a READ LA             */
  86 /*                mailbox command             */
  87 /**********************************************/
  88 int
  89 lpfc_read_la(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb, struct lpfc_dmabuf *mp)
  90 {
  91         MAILBOX_t *mb;
  92         struct lpfc_sli *psli;
  93
  94         psli = &phba->sli;
  95         mb = &pmb->mb;
  96         memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
  97
  98         INIT_LIST_HEAD(&mp->list);
  99         mb->mbxCommand = MBX_READ_LA64;
 100         mb->un.varReadLA.un.lilpBde64.tus.f.bdeSize = 128;
 101         mb->un.varReadLA.un.lilpBde64.addrHigh = putPaddrHigh(mp->phys);
 102         mb->un.varReadLA.un.lilpBde64.addrLow = putPaddrLow(mp->phys);
 103
 104         /* Save address for later completion and set the owner to host so that
 105          * the FW knows this mailbox is available for processing.
 106          */
 107         pmb->context1 = (uint8_t *) mp;
 108         mb->mbxOwner = OWN_HOST;
 109         return (0);
 110 }
 111
 112 /**********************************************/
 113 /*  lpfc_clear_la  Issue a CLEAR LA           */
 114 /*                 mailbox command            */
 115 /**********************************************/
 116 void
 117 lpfc_clear_la(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb)
 118 {
 119         MAILBOX_t *mb;
 120
 121         mb = &pmb->mb;
 122         memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
 123
 124         mb->un.varClearLA.eventTag = phba->fc_eventTag;
 125         mb->mbxCommand = MBX_CLEAR_LA;
 126         mb->mbxOwner = OWN_HOST;
 127         return;
 128 }
 129
 130 /**************************************************/
 131 /*  lpfc_config_link  Issue a CONFIG LINK         */
 132 /*                    mailbox command             */
 133 /**************************************************/
 134 void
 135 lpfc_config_link(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb)
 136 {
 137         struct lpfc_vport  *vport = phba->pport;
 138         MAILBOX_t *mb = &pmb->mb;
 139         memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
 140
 141         /* NEW_FEATURE
 142          * SLI-2, Coalescing Response Feature.
 143          */
 144         if (phba->cfg_cr_delay) {
 145                 mb->un.varCfgLnk.cr = 1;
 146                 mb->un.varCfgLnk.ci = 1;
 147                 mb->un.varCfgLnk.cr_delay = phba->cfg_cr_delay;
 148                 mb->un.varCfgLnk.cr_count = phba->cfg_cr_count;
 149         }
 150
 151         mb->un.varCfgLnk.myId = vport->fc_myDID;
 152         mb->un.varCfgLnk.edtov = phba->fc_edtov;
 153         mb->un.varCfgLnk.arbtov = phba->fc_arbtov;
 154         mb->un.varCfgLnk.ratov = phba->fc_ratov;
 155         mb->un.varCfgLnk.rttov = phba->fc_rttov;
 156         mb->un.varCfgLnk.altov = phba->fc_altov;
 157         mb->un.varCfgLnk.crtov = phba->fc_crtov;
 158         mb->un.varCfgLnk.citov = phba->fc_citov;
 159
 160         if (phba->cfg_ack0)
 161                 mb->un.varCfgLnk.ack0_enable = 1;
 162
 163         mb->mbxCommand = MBX_CONFIG_LINK;
 164         mb->mbxOwner = OWN_HOST;
 165         return;
 166 }
 167
 168 /**********************************************/
 169 /*  lpfc_init_link  Issue an INIT LINK        */
 170 /*                  mailbox command           */
 171 /**********************************************/
 172 void
 173 lpfc_init_link(struct lpfc_hba * phba,
 174                LPFC_MBOXQ_t * pmb, uint32_t topology, uint32_t linkspeed)
 175 {
 176         lpfc_vpd_t *vpd;
 177         struct lpfc_sli *psli;
 178         MAILBOX_t *mb;
 179
 180         mb = &pmb->mb;
 181         memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
 182
 183         psli = &phba->sli;
 184         switch (topology) {
 185         case FLAGS_TOPOLOGY_MODE_LOOP_PT:
 186                 mb->un.varInitLnk.link_flags = FLAGS_TOPOLOGY_MODE_LOOP;
 187                 mb->un.varInitLnk.link_flags |= FLAGS_TOPOLOGY_FAILOVER;
 188                 break;
 189         case FLAGS_TOPOLOGY_MODE_PT_PT:
 190                 mb->un.varInitLnk.link_flags = FLAGS_TOPOLOGY_MODE_PT_PT;
 191                 break;
 192         case FLAGS_TOPOLOGY_MODE_LOOP:
 193                 mb->un.varInitLnk.link_flags = FLAGS_TOPOLOGY_MODE_LOOP;
 194                 break;
 195         case FLAGS_TOPOLOGY_MODE_PT_LOOP:
 196                 mb->un.varInitLnk.link_flags = FLAGS_TOPOLOGY_MODE_PT_PT;
 197                 mb->un.varInitLnk.link_flags |= FLAGS_TOPOLOGY_FAILOVER;
 198                 break;
 199         case FLAGS_LOCAL_LB:
 200                 mb->un.varInitLnk.link_flags = FLAGS_LOCAL_LB;
 201                 break;
 202         }
 203
 204         /* Enable asynchronous ABTS responses from firmware */
 205         mb->un.varInitLnk.link_flags |= FLAGS_IMED_ABORT;
 206
 207         /* NEW_FEATURE
 208          * Setting up the link speed
 209          */
 210         vpd = &phba->vpd;
 211         if (vpd->rev.feaLevelHigh >= 0x02){
 212                 switch(linkspeed){
 213                         case LINK_SPEED_1G:
 214                         case LINK_SPEED_2G:
 215                         case LINK_SPEED_4G:
 216                         case LINK_SPEED_8G:
 217                                 mb->un.varInitLnk.link_flags |=
 218                                                         FLAGS_LINK_SPEED;
 219                                 mb->un.varInitLnk.link_speed = linkspeed;
 220                         break;
 221                         case LINK_SPEED_AUTO:
 222                         default:
 223                                 mb->un.varInitLnk.link_speed =
 224                                                         LINK_SPEED_AUTO;
 225                         break;
 226                 }
 227
 228         }
 229         else
 230                 mb->un.varInitLnk.link_speed = LINK_SPEED_AUTO;
 231
 232         mb->mbxCommand = (volatile uint8_t)MBX_INIT_LINK;
 233         mb->mbxOwner = OWN_HOST;
 234         mb->un.varInitLnk.fabric_AL_PA = phba->fc_pref_ALPA;
 235         return;
 236 }
 237
 238 /**********************************************/
 239 /*  lpfc_read_sparam  Issue a READ SPARAM     */
 240 /*                    mailbox command         */
 241 /**********************************************/
 242 int
 243 lpfc_read_sparam(struct lpfc_hba *phba, LPFC_MBOXQ_t *pmb, int vpi)
 244 {
 245         struct lpfc_dmabuf *mp;
 246         MAILBOX_t *mb;
 247         struct lpfc_sli *psli;
 248
 249         psli = &phba->sli;
 250         mb = &pmb->mb;
 251         memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
 252
 253         mb->mbxOwner = OWN_HOST;
 254
 255         /* Get a buffer to hold the HBAs Service Parameters */
 256
 257         if (((mp = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL)) == 0) ||
 258             ((mp->virt = lpfc_mbuf_alloc(phba, 0, &(mp->phys))) == 0)) {
 259                 kfree(mp);
 260                 mb->mbxCommand = MBX_READ_SPARM64;
 261                 /* READ_SPARAM: no buffers */
 262                 lpfc_printf_log(phba,
 263                                 KERN_WARNING,
 264                                 LOG_MBOX,
 265                                 "%d:0301 READ_SPARAM: no buffers\n",
 266                                 phba->brd_no);
 267                 return (1);
 268         }
 269         INIT_LIST_HEAD(&mp->list);
 270         mb->mbxCommand = MBX_READ_SPARM64;
 271         mb->un.varRdSparm.un.sp64.tus.f.bdeSize = sizeof (struct serv_parm);
 272         mb->un.varRdSparm.un.sp64.addrHigh = putPaddrHigh(mp->phys);
 273         mb->un.varRdSparm.un.sp64.addrLow = putPaddrLow(mp->phys);
 274         mb->un.varRdSparm.vpi = vpi;
 275
 276         /* save address for completion */
 277         pmb->context1 = mp;
 278
 279         return (0);
 280 }
 281
 282 /********************************************/
 283 /*  lpfc_unreg_did  Issue a UNREG_DID       */
 284 /*                  mailbox command         */
 285 /********************************************/
 286 void
 287 lpfc_unreg_did(struct lpfc_hba * phba, uint16_t vpi, uint32_t did,
 288                LPFC_MBOXQ_t * pmb)
 289 {
 290         MAILBOX_t *mb;
 291
 292         mb = &pmb->mb;
 293         memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
 294
 295         mb->un.varUnregDID.did = did;
 296         mb->un.varUnregDID.vpi = vpi;
 297
 298         mb->mbxCommand = MBX_UNREG_D_ID;
 299         mb->mbxOwner = OWN_HOST;
 300         return;
 301 }
 302
 303 /**********************************************/
 304 /*  lpfc_read_nv  Issue a READ CONFIG         */
 305 /*                mailbox command             */
 306 /**********************************************/
 307 void
 308 lpfc_read_config(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb)
 309 {
 310         MAILBOX_t *mb;
 311
 312         mb = &pmb->mb;
 313         memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
 314
 315         mb->mbxCommand = MBX_READ_CONFIG;
 316         mb->mbxOwner = OWN_HOST;
 317         return;
 318 }
 319
 320 /*************************************************/
 321 /*  lpfc_read_lnk_stat  Issue a READ LINK STATUS */
 322 /*                mailbox command                */
 323 /*************************************************/
 324 void
 325 lpfc_read_lnk_stat(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb)
 326 {
 327         MAILBOX_t *mb;
 328
 329         mb = &pmb->mb;
 330         memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
 331
 332         mb->mbxCommand = MBX_READ_LNK_STAT;
 333         mb->mbxOwner = OWN_HOST;
 334         return;
 335 }
 336
 337 /********************************************/
 338 /*  lpfc_reg_login  Issue a REG_LOGIN       */
 339 /*                  mailbox command         */
 340 /********************************************/
 341 int
 342 lpfc_reg_login(struct lpfc_hba *phba, uint16_t vpi, uint32_t did,
 343                uint8_t *param, LPFC_MBOXQ_t *pmb, uint32_t flag)
 344 {
 345         MAILBOX_t *mb = &pmb->mb;
 346         uint8_t *sparam;
 347         struct lpfc_dmabuf *mp;
 348
 349         memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
 350
 351         mb->un.varRegLogin.rpi = 0;
 352         mb->un.varRegLogin.vpi = vpi;
 353         mb->un.varRegLogin.did = did;
 354         mb->un.varWords[30] = flag;     /* Set flag to issue action on cmpl */
 355
 356         mb->mbxOwner = OWN_HOST;
 357
 358         /* Get a buffer to hold NPorts Service Parameters */
 359         if (((mp = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL)) == NULL) ||
 360             ((mp->virt = lpfc_mbuf_alloc(phba, 0, &(mp->phys))) == 0)) {
 361                 kfree(mp);
 362                 mb->mbxCommand = MBX_REG_LOGIN64;
 363                 /* REG_LOGIN: no buffers */
 364                 lpfc_printf_log(phba, KERN_WARNING, LOG_MBOX,
 365                                 "%d (%d):0302 REG_LOGIN: no buffers, DID x%x, "
 366                                 "flag x%x\n",
 367                                 phba->brd_no, vpi, did, flag);
 368                 return (1);
 369         }
 370         INIT_LIST_HEAD(&mp->list);
 371         sparam = mp->virt;
 372
 373         /* Copy param's into a new buffer */
 374         memcpy(sparam, param, sizeof (struct serv_parm));
 375
 376         /* save address for completion */
 377         pmb->context1 = (uint8_t *) mp;
 378
 379         mb->mbxCommand = MBX_REG_LOGIN64;
 380         mb->un.varRegLogin.un.sp64.tus.f.bdeSize = sizeof (struct serv_parm);
 381         mb->un.varRegLogin.un.sp64.addrHigh = putPaddrHigh(mp->phys);
 382         mb->un.varRegLogin.un.sp64.addrLow = putPaddrLow(mp->phys);
 383
 384         return (0);
 385 }
 386
 387 /**********************************************/
 388 /*  lpfc_unreg_login  Issue a UNREG_LOGIN     */
 389 /*                    mailbox command         */
 390 /**********************************************/
 391 void
 392 lpfc_unreg_login(struct lpfc_hba *phba, uint16_t vpi, uint32_t rpi,
 393                  LPFC_MBOXQ_t * pmb)
 394 {
 395         MAILBOX_t *mb;
 396
 397         mb = &pmb->mb;
 398         memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
 399
 400         mb->un.varUnregLogin.rpi = (uint16_t) rpi;
 401         mb->un.varUnregLogin.rsvd1 = 0;
 402         mb->un.varUnregLogin.vpi = vpi;
 403
 404         mb->mbxCommand = MBX_UNREG_LOGIN;
 405         mb->mbxOwner = OWN_HOST;
 406         return;
 407 }
 408
 409 /**************************************************/
 410 /*  lpfc_reg_vpi   Issue a REG_VPI                */
 411 /*                    mailbox command             */
 412 /**************************************************/
 413 void
 414 lpfc_reg_vpi(struct lpfc_hba *phba, uint16_t vpi, uint32_t sid,
 415              LPFC_MBOXQ_t *pmb)
 416 {
 417         MAILBOX_t *mb = &pmb->mb;
 418
 419         memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
 420
 421         mb->un.varRegVpi.vpi = vpi;
 422         mb->un.varRegVpi.sid = sid;
 423
 424         mb->mbxCommand = MBX_REG_VPI;
 425         mb->mbxOwner = OWN_HOST;
 426         return;
 427
 428 }
 429
 430 /**************************************************/
 431 /*  lpfc_unreg_vpi   Issue a UNREG_VNPI           */
 432 /*                    mailbox command             */
 433 /**************************************************/
 434 void
 435 lpfc_unreg_vpi(struct lpfc_hba *phba, uint16_t vpi, LPFC_MBOXQ_t *pmb)
 436 {
 437         MAILBOX_t *mb = &pmb->mb;
 438         memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
 439
 440         mb->un.varUnregVpi.vpi = vpi;
 441
 442         mb->mbxCommand = MBX_UNREG_VPI;
 443         mb->mbxOwner = OWN_HOST;
 444         return;
 445
 446 }
 447
 448 static void
 449 lpfc_config_pcb_setup(struct lpfc_hba * phba)
 450 {
 451         struct lpfc_sli *psli = &phba->sli;
 452         struct lpfc_sli_ring *pring;
 453         PCB_t *pcbp = &phba->slim2p->pcb;
 454         dma_addr_t pdma_addr;
 455         uint32_t offset;
 456         uint32_t iocbCnt = 0;
 457         int i;
 458
 459         pcbp->maxRing = (psli->num_rings - 1);
 460
 461         for (i = 0; i < psli->num_rings; i++) {
 462                 pring = &psli->ring[i];
 463
 464                 pring->sizeCiocb = phba->sli_rev == 3 ? SLI3_IOCB_CMD_SIZE:
 465                                                         SLI2_IOCB_CMD_SIZE;
 466                 pring->sizeRiocb = phba->sli_rev == 3 ? SLI3_IOCB_RSP_SIZE:
 467                                                         SLI2_IOCB_RSP_SIZE;
 468                 /* A ring MUST have both cmd and rsp entries defined to be
 469                    valid */
 470                 if ((pring->numCiocb == 0) || (pring->numRiocb == 0)) {
 471                         pcbp->rdsc[i].cmdEntries = 0;
 472                         pcbp->rdsc[i].rspEntries = 0;
 473                         pcbp->rdsc[i].cmdAddrHigh = 0;
 474                         pcbp->rdsc[i].rspAddrHigh = 0;
 475                         pcbp->rdsc[i].cmdAddrLow = 0;
 476                         pcbp->rdsc[i].rspAddrLow = 0;
 477                         pring->cmdringaddr = NULL;
 478                         pring->rspringaddr = NULL;
 479                         continue;
 480                 }
 481                 /* Command ring setup for ring */
 482                 pring->cmdringaddr = (void *) &phba->slim2p->IOCBs[iocbCnt];
 483                 pcbp->rdsc[i].cmdEntries = pring->numCiocb;
 484
 485                 offset = (uint8_t *) &phba->slim2p->IOCBs[iocbCnt] -
 486                          (uint8_t *) phba->slim2p;
 487                 pdma_addr = phba->slim2p_mapping + offset;
 488                 pcbp->rdsc[i].cmdAddrHigh = putPaddrHigh(pdma_addr);
 489                 pcbp->rdsc[i].cmdAddrLow = putPaddrLow(pdma_addr);
 490                 iocbCnt += pring->numCiocb;
 491
 492                 /* Response ring setup for ring */
 493                 pring->rspringaddr = (void *) &phba->slim2p->IOCBs[iocbCnt];
 494
 495                 pcbp->rdsc[i].rspEntries = pring->numRiocb;
 496                 offset = (uint8_t *)&phba->slim2p->IOCBs[iocbCnt] -
 497                          (uint8_t *)phba->slim2p;
 498                 pdma_addr = phba->slim2p_mapping + offset;
 499                 pcbp->rdsc[i].rspAddrHigh = putPaddrHigh(pdma_addr);
 500                 pcbp->rdsc[i].rspAddrLow = putPaddrLow(pdma_addr);
 501                 iocbCnt += pring->numRiocb;
 502         }
 503 }
 504
 505 void
 506 lpfc_read_rev(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb)
 507 {
 508         MAILBOX_t *mb = &pmb->mb;
 509         memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
 510         mb->un.varRdRev.cv = 1;
 511         mb->un.varRdRev.v3req = 1; /* Request SLI3 info */
 512         mb->mbxCommand = MBX_READ_REV;
 513         mb->mbxOwner = OWN_HOST;
 514         return;
 515 }
 516
 517 static void
 518 lpfc_build_hbq_profile2(struct config_hbq_var *hbqmb,
 519                         struct lpfc_hbq_init  *hbq_desc)
 520 {
 521         hbqmb->profiles.profile2.seqlenbcnt = hbq_desc->seqlenbcnt;
 522         hbqmb->profiles.profile2.maxlen     = hbq_desc->maxlen;
 523         hbqmb->profiles.profile2.seqlenoff  = hbq_desc->seqlenoff;
 524 }
 525
 526 static void
 527 lpfc_build_hbq_profile3(struct config_hbq_var *hbqmb,
 528                         struct lpfc_hbq_init  *hbq_desc)
 529 {
 530         hbqmb->profiles.profile3.seqlenbcnt = hbq_desc->seqlenbcnt;
 531         hbqmb->profiles.profile3.maxlen     = hbq_desc->maxlen;
 532         hbqmb->profiles.profile3.cmdcodeoff = hbq_desc->cmdcodeoff;
 533         hbqmb->profiles.profile3.seqlenoff  = hbq_desc->seqlenoff;
 534         memcpy(&hbqmb->profiles.profile3.cmdmatch, hbq_desc->cmdmatch,
 535                sizeof(hbqmb->profiles.profile3.cmdmatch));
 536 }
 537
 538 static void
 539 lpfc_build_hbq_profile5(struct config_hbq_var *hbqmb,
 540                         struct lpfc_hbq_init  *hbq_desc)
 541 {
 542         hbqmb->profiles.profile5.seqlenbcnt = hbq_desc->seqlenbcnt;
 543         hbqmb->profiles.profile5.maxlen     = hbq_desc->maxlen;
 544         hbqmb->profiles.profile5.cmdcodeoff = hbq_desc->cmdcodeoff;
 545         hbqmb->profiles.profile5.seqlenoff  = hbq_desc->seqlenoff;
 546         memcpy(&hbqmb->profiles.profile5.cmdmatch, hbq_desc->cmdmatch,
 547                sizeof(hbqmb->profiles.profile5.cmdmatch));
 548 }
 549
 550 void
 551 lpfc_config_hbq(struct lpfc_hba *phba, struct lpfc_hbq_init *hbq_desc,
 552                 uint32_t hbq_entry_index, LPFC_MBOXQ_t *pmb)
 553 {
 554         int i;
 555         MAILBOX_t *mb = &pmb->mb;
 556         struct config_hbq_var *hbqmb = &mb->un.varCfgHbq;
 557
 558         memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
 559         hbqmb->entry_count = hbq_desc->entry_count;   /* # entries in HBQ */
 560         hbqmb->recvNotify = hbq_desc->rn;             /* Receive
 561                                                        * Notification */
 562         hbqmb->numMask    = hbq_desc->mask_count;     /* # R_CTL/TYPE masks
 563                                                        * # in words 0-19 */
 564         hbqmb->profile    = hbq_desc->profile;        /* Selection profile:
 565                                                        * 0 = all,
 566                                                        * 7 = logentry */
 567         hbqmb->ringMask   = hbq_desc->ring_mask;      /* Binds HBQ to a ring
 568                                                        * e.g. Ring0=b0001,
 569                                                        * ring2=b0100 */
 570         hbqmb->headerLen  = hbq_desc->headerLen;      /* 0 if not profile 4
 571                                                        * or 5 */
 572         hbqmb->logEntry   = hbq_desc->logEntry;       /* Set to 1 if this
 573                                                        * HBQ will be used
 574                                                        * for LogEntry
 575                                                        * buffers */
 576         hbqmb->hbqaddrLow = putPaddrLow(phba->hbqslimp.phys) +
 577                 hbq_entry_index * sizeof(struct lpfc_hbq_entry);
 578         hbqmb->hbqaddrHigh = putPaddrHigh(phba->hbqslimp.phys);
 579
 580         mb->mbxCommand = MBX_CONFIG_HBQ;
 581         mb->mbxOwner = OWN_HOST;
 582
 583                                 /* Copy info for profiles 2,3,5. Other
 584                                  * profiles this area is reserved
 585                                  */
 586         if (hbq_desc->profile == 2)
 587                 lpfc_build_hbq_profile2(hbqmb, hbq_desc);
 588         else if (hbq_desc->profile == 3)
 589                 lpfc_build_hbq_profile3(hbqmb, hbq_desc);
 590         else if (hbq_desc->profile == 5)
 591                 lpfc_build_hbq_profile5(hbqmb, hbq_desc);
 592
 593         /* Return if no rctl / type masks for this HBQ */
 594         if (!hbq_desc->mask_count)
 595                 return;
 596
 597         /* Otherwise we setup specific rctl / type masks for this HBQ */
 598         for (i = 0; i < hbq_desc->mask_count; i++) {
 599                 hbqmb->hbqMasks[i].tmatch = hbq_desc->hbqMasks[i].tmatch;
 600                 hbqmb->hbqMasks[i].tmask  = hbq_desc->hbqMasks[i].tmask;
 601                 hbqmb->hbqMasks[i].rctlmatch = hbq_desc->hbqMasks[i].rctlmatch;
 602                 hbqmb->hbqMasks[i].rctlmask  = hbq_desc->hbqMasks[i].rctlmask;
 603         }
 604
 605         return;
 606 }
 607
 608
 609
 610 void
 611 lpfc_config_ring(struct lpfc_hba * phba, int ring, LPFC_MBOXQ_t * pmb)
 612 {
 613         int i;
 614         MAILBOX_t *mb = &pmb->mb;
 615         struct lpfc_sli *psli;
 616         struct lpfc_sli_ring *pring;
 617
 618         memset(pmb, 0, sizeof (LPFC_MBOXQ_t));
 619
 620         mb->un.varCfgRing.ring = ring;
 621         mb->un.varCfgRing.maxOrigXchg = 0;
 622         mb->un.varCfgRing.maxRespXchg = 0;
 623         mb->un.varCfgRing.recvNotify = 1;
 624
 625         psli = &phba->sli;
 626         pring = &psli->ring[ring];
 627         mb->un.varCfgRing.numMask = pring->num_mask;
 628         mb->mbxCommand = MBX_CONFIG_RING;
 629         mb->mbxOwner = OWN_HOST;
 630
 631         /* Is this ring configured for a specific profile */
 632         if (pring->prt[0].profile) {
 633                 mb->un.varCfgRing.profile = pring->prt[0].profile;
 634                 return;
 635         }
 636
 637         /* Otherwise we setup specific rctl / type masks for this ring */
 638         for (i = 0; i < pring->num_mask; i++) {
 639                 mb->un.varCfgRing.rrRegs[i].rval = pring->prt[i].rctl;
 640                 if (mb->un.varCfgRing.rrRegs[i].rval != FC_ELS_REQ)
 641                         mb->un.varCfgRing.rrRegs[i].rmask = 0xff;
 642                 else
 643                         mb->un.varCfgRing.rrRegs[i].rmask = 0xfe;
 644                 mb->un.varCfgRing.rrRegs[i].tval = pring->prt[i].type;
 645                 mb->un.varCfgRing.rrRegs[i].tmask = 0xff;
 646         }
 647
 648         return;
 649 }
 650
 651 void
 652 lpfc_config_port(struct lpfc_hba *phba, LPFC_MBOXQ_t *pmb)
 653 {
 654         MAILBOX_t __iomem *mb_slim = (MAILBOX_t __iomem *) phba->MBslimaddr;
 655         MAILBOX_t *mb = &pmb->mb;
 656         dma_addr_t pdma_addr;
 657         uint32_t bar_low, bar_high;
 658         size_t offset;
 659         struct lpfc_hgp hgp;
 660         int i;
 661         uint32_t pgp_offset;
 662
 663         memset(pmb, 0, sizeof(LPFC_MBOXQ_t));
 664         mb->mbxCommand = MBX_CONFIG_PORT;
 665         mb->mbxOwner = OWN_HOST;
 666
 667         mb->un.varCfgPort.pcbLen = sizeof(PCB_t);
 668
 669         offset = (uint8_t *)&phba->slim2p->pcb - (uint8_t *)phba->slim2p;
 670         pdma_addr = phba->slim2p_mapping + offset;
 671         mb->un.varCfgPort.pcbLow = putPaddrLow(pdma_addr);
 672         mb->un.varCfgPort.pcbHigh = putPaddrHigh(pdma_addr);
 673
 674         /* If HBA supports SLI=3 ask for it */
 675
 676         if (phba->sli_rev == 3 && phba->vpd.sli3Feat.cerbm) {
 677                 mb->un.varCfgPort.cerbm = 1; /* Request HBQs */
 678                 mb->un.varCfgPort.max_hbq = 1; /* Requesting 2 HBQs */
 679                 if (phba->max_vpi && lpfc_npiv_enable &&
 680                     phba->vpd.sli3Feat.cmv) {
 681                         mb->un.varCfgPort.max_vpi = phba->max_vpi;
 682                         mb->un.varCfgPort.cmv = 1;
 683                         phba->sli3_options |= LPFC_SLI3_NPIV_ENABLED;
 684                 } else
 685                         mb->un.varCfgPort.max_vpi = phba->max_vpi = 0;
 686         } else
 687                 phba->sli_rev = 2;
 688         mb->un.varCfgPort.sli_mode = phba->sli_rev;
 689
 690         /* Now setup pcb */
 691         phba->slim2p->pcb.type = TYPE_NATIVE_SLI2;
 692         phba->slim2p->pcb.feature = FEATURE_INITIAL_SLI2;
 693
 694         /* Setup Mailbox pointers */
 695         phba->slim2p->pcb.mailBoxSize = offsetof(MAILBOX_t, us) +
 696                 sizeof(struct sli2_desc);
 697         offset = (uint8_t *)&phba->slim2p->mbx - (uint8_t *)phba->slim2p;
 698         pdma_addr = phba->slim2p_mapping + offset;
 699         phba->slim2p->pcb.mbAddrHigh = putPaddrHigh(pdma_addr);
 700         phba->slim2p->pcb.mbAddrLow = putPaddrLow(pdma_addr);
 701
 702         /*
 703          * Setup Host Group ring pointer.
 704          *
 705          * For efficiency reasons, the ring get/put pointers can be
 706          * placed in adapter memory (SLIM) rather than in host memory.
 707          * This allows firmware to avoid PCI reads/writes when updating
 708          * and checking pointers.
 709          *
 710          * The firmware recognizes the use of SLIM memory by comparing
 711          * the address of the get/put pointers structure with that of
 712          * the SLIM BAR (BAR0).
 713          *
 714          * Caution: be sure to use the PCI config space value of BAR0/BAR1
 715          * (the hardware's view of the base address), not the OS's
 716          * value of pci_resource_start() as the OS value may be a cookie
 717          * for ioremap/iomap.
 718          */
 719
 720
 721         pci_read_config_dword(phba->pcidev, PCI_BASE_ADDRESS_0, &bar_low);
 722         pci_read_config_dword(phba->pcidev, PCI_BASE_ADDRESS_1, &bar_high);
 723
 724         /*
 725          * Set up HGP - Port Memory
 726          *
 727          * The port expects the host get/put pointers to reside in memory
 728          * following the "non-diagnostic" mode mailbox (32 words, 0x80 bytes)
 729          * area of SLIM.  In SLI-2 mode, there's an additional 16 reserved
 730          * words (0x40 bytes).  This area is not reserved if HBQs are
 731          * configured in SLI-3.
 732          *
 733          * CR0Put    - SLI2(no HBQs) = 0xc0, With HBQs = 0x80
 734          * RR0Get                      0xc4              0x84
 735          * CR1Put                      0xc8              0x88
 736          * RR1Get                      0xcc              0x8c
 737          * CR2Put                      0xd0              0x90
 738          * RR2Get                      0xd4              0x94
 739          * CR3Put                      0xd8              0x98
 740          * RR3Get                      0xdc              0x9c
 741          *
 742          * Reserved                    0xa0-0xbf
 743          *    If HBQs configured:
 744          *                         HBQ 0 Put ptr  0xc0
 745          *                         HBQ 1 Put ptr  0xc4
 746          *                         HBQ 2 Put ptr  0xc8
 747          *                         ......
 748          *                         HBQ(M-1)Put Pointer 0xc0+(M-1)*4
 749          *
 750          */
 751
 752         if (phba->sli_rev == 3) {
 753                 phba->host_gp = &mb_slim->us.s3.host[0];
 754                 phba->hbq_put = &mb_slim->us.s3.hbq_put[0];
 755         } else {
 756                 phba->host_gp = &mb_slim->us.s2.host[0];
 757                 phba->hbq_put = NULL;
 758         }
 759
 760         /* mask off BAR0's flag bits 0 - 3 */
 761         phba->slim2p->pcb.hgpAddrLow = (bar_low & PCI_BASE_ADDRESS_MEM_MASK) +
 762                 (void __iomem *) phba->host_gp -
 763                 (void __iomem *)phba->MBslimaddr;
 764         if (bar_low & PCI_BASE_ADDRESS_MEM_TYPE_64)
 765                 phba->slim2p->pcb.hgpAddrHigh = bar_high;
 766         else
 767                 phba->slim2p->pcb.hgpAddrHigh = 0;
 768         /* write HGP data to SLIM at the required longword offset */
 769         memset(&hgp, 0, sizeof(struct lpfc_hgp));
 770
 771         for (i=0; i < phba->sli.num_rings; i++) {
 772                 lpfc_memcpy_to_slim(phba->host_gp + i, &hgp,
 773                                     sizeof(*phba->host_gp));
 774         }
 775
 776         /* Setup Port Group ring pointer */
 777         if (phba->sli_rev == 3)
 778                 pgp_offset = (uint8_t *)&phba->slim2p->mbx.us.s3_pgp.port -
 779                         (uint8_t *)phba->slim2p;
 780         else
 781                 pgp_offset = (uint8_t *)&phba->slim2p->mbx.us.s2.port -
 782                         (uint8_t *)phba->slim2p;
 783
 784         pdma_addr = phba->slim2p_mapping + pgp_offset;
 785         phba->slim2p->pcb.pgpAddrHigh = putPaddrHigh(pdma_addr);
 786         phba->slim2p->pcb.pgpAddrLow = putPaddrLow(pdma_addr);
 787         phba->hbq_get = &phba->slim2p->mbx.us.s3_pgp.hbq_get[0];
 788
 789         /* Use callback routine to setp rings in the pcb */
 790         lpfc_config_pcb_setup(phba);
 791
 792         /* special handling for LC HBAs */
 793         if (lpfc_is_LC_HBA(phba->pcidev->device)) {
 794                 uint32_t hbainit[5];
 795
 796                 lpfc_hba_init(phba, hbainit);
 797
 798                 memcpy(&mb->un.varCfgPort.hbainit, hbainit, 20);
 799         }
 800
 801         /* Swap PCB if needed */
 802         lpfc_sli_pcimem_bcopy(&phba->slim2p->pcb, &phba->slim2p->pcb,
 803                               sizeof(PCB_t));
 804 }
 805
 806 void
 807 lpfc_kill_board(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmb)
 808 {
 809         MAILBOX_t *mb = &pmb->mb;
 810
 811         memset(pmb, 0, sizeof(LPFC_MBOXQ_t));
 812         mb->mbxCommand = MBX_KILL_BOARD;
 813         mb->mbxOwner = OWN_HOST;
 814         return;
 815 }
 816
 817 void
 818 lpfc_mbox_put(struct lpfc_hba * phba, LPFC_MBOXQ_t * mbq)
 819 {
 820         struct lpfc_sli *psli;
 821
 822         psli = &phba->sli;
 823
 824         list_add_tail(&mbq->list, &psli->mboxq);
 825
 826         psli->mboxq_cnt++;
 827
 828         return;
 829 }
 830
 831 LPFC_MBOXQ_t *
 832 lpfc_mbox_get(struct lpfc_hba * phba)
 833 {
 834         LPFC_MBOXQ_t *mbq = NULL;
 835         struct lpfc_sli *psli = &phba->sli;
 836
 837         list_remove_head((&psli->mboxq), mbq, LPFC_MBOXQ_t, list);
 838         if (mbq)
 839                 psli->mboxq_cnt--;
 840
 841         return mbq;
 842 }
 843
 844 void
 845 lpfc_mbox_cmpl_put(struct lpfc_hba * phba, LPFC_MBOXQ_t * mbq)
 846 {
 847         /* This function expects to be called from interupt context */
 848         spin_lock(&phba->hbalock);
 849         list_add_tail(&mbq->list, &phba->sli.mboxq_cmpl);
 850         spin_unlock(&phba->hbalock);
 851         return;
 852 }
 853
 854 int
 855 lpfc_mbox_tmo_val(struct lpfc_hba *phba, int cmd)
 856 {
 857         switch (cmd) {
 858         case MBX_WRITE_NV:      /* 0x03 */
 859         case MBX_UPDATE_CFG:    /* 0x1B */
 860         case MBX_DOWN_LOAD:     /* 0x1C */
 861         case MBX_DEL_LD_ENTRY:  /* 0x1D */
 862         case MBX_LOAD_AREA:     /* 0x81 */
 863         case MBX_FLASH_WR_ULA:  /* 0x98 */
 864         case MBX_LOAD_EXP_ROM:  /* 0x9C */
 865                 return LPFC_MBOX_TMO_FLASH_CMD;
 866         }
 867         return LPFC_MBOX_TMO;
 868 }