1 /*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
3 * Fibre Channel Host Bus Adapters. *
4 * Copyright (C) 2004-2007 Emulex. All rights reserved. *
5 * EMULEX and SLI are trademarks of Emulex. *
8 * This program is free software; you can redistribute it and/or *
9 * modify it under the terms of version 2 of the GNU General *
10 * Public License as published by the Free Software Foundation. *
11 * This program is distributed in the hope that it will be useful. *
12 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
13 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
14 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
15 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
16 * TO BE LEGALLY INVALID. See the GNU General Public License for *
17 * more details, a copy of which can be found in the file COPYING *
18 * included with this package. *
19 *******************************************************************/
21 #define FDMI_DID 0xfffffaU
22 #define NameServer_DID 0xfffffcU
23 #define SCR_DID 0xfffffdU
24 #define Fabric_DID 0xfffffeU
25 #define Bcast_DID 0xffffffU
26 #define Mask_DID 0xffffffU
27 #define CT_DID_MASK 0xffff00U
28 #define Fabric_DID_MASK 0xfff000U
29 #define WELL_KNOWN_DID_MASK 0xfffff0U
31 #define PT2PT_LocalID 1
32 #define PT2PT_RemoteID 2
34 #define FF_DEF_EDTOV 2000 /* Default E_D_TOV (2000ms) */
35 #define FF_DEF_ALTOV 15 /* Default AL_TIME (15ms) */
36 #define FF_DEF_RATOV 2 /* Default RA_TOV (2s) */
37 #define FF_DEF_ARBTOV 1900 /* Default ARB_TOV (1900ms) */
39 #define LPFC_BUF_RING0 64 /* Number of buffers to post to RING
42 #define FCELSSIZE 1024 /* maximum ELS transfer size */
44 #define LPFC_FCP_RING 0 /* ring 0 for FCP initiator commands */
45 #define LPFC_EXTRA_RING 1 /* ring 1 for other protocols */
46 #define LPFC_ELS_RING 2 /* ring 2 for ELS commands */
47 #define LPFC_FCP_NEXT_RING 3
49 #define SLI2_IOCB_CMD_R0_ENTRIES 172 /* SLI-2 FCP command ring entries */
50 #define SLI2_IOCB_RSP_R0_ENTRIES 134 /* SLI-2 FCP response ring entries */
51 #define SLI2_IOCB_CMD_R1_ENTRIES 4 /* SLI-2 extra command ring entries */
52 #define SLI2_IOCB_RSP_R1_ENTRIES 4 /* SLI-2 extra response ring entries */
53 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36 /* SLI-2 extra FCP cmd ring entries */
54 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52 /* SLI-2 extra FCP rsp ring entries */
55 #define SLI2_IOCB_CMD_R2_ENTRIES 20 /* SLI-2 ELS command ring entries */
56 #define SLI2_IOCB_RSP_R2_ENTRIES 20 /* SLI-2 ELS response ring entries */
57 #define SLI2_IOCB_CMD_R3_ENTRIES 0
58 #define SLI2_IOCB_RSP_R3_ENTRIES 0
59 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
60 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
62 #define SLI2_IOCB_CMD_SIZE 32
63 #define SLI2_IOCB_RSP_SIZE 32
64 #define SLI3_IOCB_CMD_SIZE 128
65 #define SLI3_IOCB_RSP_SIZE 64
68 /* Common Transport structures and definitions */
71 /* Structure is in Big Endian format */
79 union CtCommandResponse {
80 /* Structure is in Big Endian format */
88 #define FC4_FEATURE_INIT 0x2
89 #define FC4_FEATURE_TARGET 0x1
91 struct lpfc_sli_ct_request {
92 /* Structure is in Big Endian format */
93 union CtRevisionId RevisionId;
98 union CtCommandResponse CommandResponse;
102 uint8_t VendorUnique;
107 uint8_t PortType; /* for GID_PT requests */
110 uint8_t Fc4Type; /* for GID_FT requests */
113 uint32_t PortId; /* For RFT_ID requests */
115 #ifdef __BIG_ENDIAN_BITFIELD
118 uint32_t fcpReg:1; /* Type 8 */
120 uint32_t ipReg:1; /* Type 5 */
122 #else /* __LITTLE_ENDIAN_BITFIELD */
124 uint32_t fcpReg:1; /* Type 8 */
127 uint32_t ipReg:1; /* Type 5 */
134 uint32_t PortId; /* For RNN_ID requests */
137 struct rsnn { /* For RSNN_ID requests */
140 uint8_t symbname[255];
142 struct rspn { /* For RSPN_ID requests */
145 uint8_t symbname[255];
153 #define FCP_TYPE_FEATURE_OFFSET 4
158 uint8_t type_code; /* type=8 for FCP */
163 #define SLI_CT_REVISION 1
164 #define GID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
166 #define GFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
168 #define RFT_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
170 #define RFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
172 #define RNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
174 #define RSNN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
176 #define RSPN_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
183 #define SLI_CT_MANAGEMENT_SERVICE 0xFA
184 #define SLI_CT_TIME_SERVICE 0xFB
185 #define SLI_CT_DIRECTORY_SERVICE 0xFC
186 #define SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
189 * Directory Service Subtypes
192 #define SLI_CT_DIRECTORY_NAME_SERVER 0x02
198 #define SLI_CT_RESPONSE_FS_RJT 0x8001
199 #define SLI_CT_RESPONSE_FS_ACC 0x8002
205 #define SLI_CT_NO_ADDITIONAL_EXPL 0x0
206 #define SLI_CT_INVALID_COMMAND 0x01
207 #define SLI_CT_INVALID_VERSION 0x02
208 #define SLI_CT_LOGICAL_ERROR 0x03
209 #define SLI_CT_INVALID_IU_SIZE 0x04
210 #define SLI_CT_LOGICAL_BUSY 0x05
211 #define SLI_CT_PROTOCOL_ERROR 0x07
212 #define SLI_CT_UNABLE_TO_PERFORM_REQ 0x09
213 #define SLI_CT_REQ_NOT_SUPPORTED 0x0b
214 #define SLI_CT_HBA_INFO_NOT_REGISTERED 0x10
215 #define SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE 0x11
216 #define SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN 0x12
217 #define SLI_CT_HBA_ATTR_NOT_PRESENT 0x13
218 #define SLI_CT_PORT_INFO_NOT_REGISTERED 0x20
219 #define SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
220 #define SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN 0x22
221 #define SLI_CT_VENDOR_UNIQUE 0xff
224 * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
227 #define SLI_CT_NO_PORT_ID 0x01
228 #define SLI_CT_NO_PORT_NAME 0x02
229 #define SLI_CT_NO_NODE_NAME 0x03
230 #define SLI_CT_NO_CLASS_OF_SERVICE 0x04
231 #define SLI_CT_NO_IP_ADDRESS 0x05
232 #define SLI_CT_NO_IPA 0x06
233 #define SLI_CT_NO_FC4_TYPES 0x07
234 #define SLI_CT_NO_SYMBOLIC_PORT_NAME 0x08
235 #define SLI_CT_NO_SYMBOLIC_NODE_NAME 0x09
236 #define SLI_CT_NO_PORT_TYPE 0x0A
237 #define SLI_CT_ACCESS_DENIED 0x10
238 #define SLI_CT_INVALID_PORT_ID 0x11
239 #define SLI_CT_DATABASE_EMPTY 0x12
242 * Name Server Command Codes
245 #define SLI_CTNS_GA_NXT 0x0100
246 #define SLI_CTNS_GPN_ID 0x0112
247 #define SLI_CTNS_GNN_ID 0x0113
248 #define SLI_CTNS_GCS_ID 0x0114
249 #define SLI_CTNS_GFT_ID 0x0117
250 #define SLI_CTNS_GSPN_ID 0x0118
251 #define SLI_CTNS_GPT_ID 0x011A
252 #define SLI_CTNS_GFF_ID 0x011F
253 #define SLI_CTNS_GID_PN 0x0121
254 #define SLI_CTNS_GID_NN 0x0131
255 #define SLI_CTNS_GIP_NN 0x0135
256 #define SLI_CTNS_GIPA_NN 0x0136
257 #define SLI_CTNS_GSNN_NN 0x0139
258 #define SLI_CTNS_GNN_IP 0x0153
259 #define SLI_CTNS_GIPA_IP 0x0156
260 #define SLI_CTNS_GID_FT 0x0171
261 #define SLI_CTNS_GID_PT 0x01A1
262 #define SLI_CTNS_RPN_ID 0x0212
263 #define SLI_CTNS_RNN_ID 0x0213
264 #define SLI_CTNS_RCS_ID 0x0214
265 #define SLI_CTNS_RFT_ID 0x0217
266 #define SLI_CTNS_RSPN_ID 0x0218
267 #define SLI_CTNS_RPT_ID 0x021A
268 #define SLI_CTNS_RFF_ID 0x021F
269 #define SLI_CTNS_RIP_NN 0x0235
270 #define SLI_CTNS_RIPA_NN 0x0236
271 #define SLI_CTNS_RSNN_NN 0x0239
272 #define SLI_CTNS_DA_ID 0x0300
278 #define SLI_CTPT_N_PORT 0x01
279 #define SLI_CTPT_NL_PORT 0x02
280 #define SLI_CTPT_FNL_PORT 0x03
281 #define SLI_CTPT_IP 0x04
282 #define SLI_CTPT_FCP 0x08
283 #define SLI_CTPT_NX_PORT 0x7F
284 #define SLI_CTPT_F_PORT 0x81
285 #define SLI_CTPT_FL_PORT 0x82
286 #define SLI_CTPT_E_PORT 0x84
288 #define SLI_CT_LAST_ENTRY 0x80000000
290 /* Fibre Channel Service Parameter definitions */
292 #define FC_PH_4_0 6 /* FC-PH version 4.0 */
293 #define FC_PH_4_1 7 /* FC-PH version 4.1 */
294 #define FC_PH_4_2 8 /* FC-PH version 4.2 */
295 #define FC_PH_4_3 9 /* FC-PH version 4.3 */
297 #define FC_PH_LOW 8 /* Lowest supported FC-PH version */
298 #define FC_PH_HIGH 9 /* Highest supported FC-PH version */
299 #define FC_PH3 0x20 /* FC-PH-3 version */
301 #define FF_FRAME_SIZE 2048
306 #ifdef __BIG_ENDIAN_BITFIELD
307 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
308 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
310 #else /* __LITTLE_ENDIAN_BITFIELD */
311 uint8_t IEEEextMsn:4; /* FC Word 0, bit 24:27, bit
313 uint8_t nameType:4; /* FC Word 0, bit 28:31 */
316 #define NAME_IEEE 0x1 /* IEEE name - nameType */
317 #define NAME_IEEE_EXT 0x2 /* IEEE extended name */
318 #define NAME_FC_TYPE 0x3 /* FC native name type */
319 #define NAME_IP_TYPE 0x4 /* IP address */
320 #define NAME_CCITT_TYPE 0xC
321 #define NAME_CCITT_GR_TYPE 0xE
322 uint8_t IEEEextLsb; /* FC Word 0, bit 16:23, IEEE
324 uint8_t IEEE[6]; /* FC IEEE address */
331 uint8_t fcphHigh; /* FC Word 0, byte 0 */
334 uint8_t bbCreditlsb; /* FC Word 0, byte 3 */
336 #ifdef __BIG_ENDIAN_BITFIELD
337 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
338 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
339 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
340 uint16_t fPort:1; /* FC Word 1, bit 28 */
341 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
342 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
343 uint16_t multicast:1; /* FC Word 1, bit 25 */
344 uint16_t broadcast:1; /* FC Word 1, bit 24 */
346 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
347 uint16_t simplex:1; /* FC Word 1, bit 22 */
348 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
349 uint16_t dhd:1; /* FC Word 1, bit 18 */
350 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
351 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
352 #else /* __LITTLE_ENDIAN_BITFIELD */
353 uint16_t broadcast:1; /* FC Word 1, bit 24 */
354 uint16_t multicast:1; /* FC Word 1, bit 25 */
355 uint16_t edtovResolution:1; /* FC Word 1, bit 26 */
356 uint16_t altBbCredit:1; /* FC Word 1, bit 27 */
357 uint16_t fPort:1; /* FC Word 1, bit 28 */
358 uint16_t response_multiple_NPort:1; /* FC Word 1, bit 29 */
359 uint16_t randomOffset:1; /* FC Word 1, bit 30 */
360 uint16_t request_multiple_Nport:1; /* FC Word 1, bit 31 */
362 uint16_t payloadlength:1; /* FC Word 1, bit 16 */
363 uint16_t contIncSeqCnt:1; /* FC Word 1, bit 17 */
364 uint16_t dhd:1; /* FC Word 1, bit 18 */
365 uint16_t word1Reserved1:3; /* FC Word 1, bit 21:19 */
366 uint16_t simplex:1; /* FC Word 1, bit 22 */
367 uint16_t huntgroup:1; /* FC Word 1, bit 23 */
370 uint8_t bbRcvSizeMsb; /* Upper nibble is reserved */
371 uint8_t bbRcvSizeLsb; /* FC Word 1, byte 3 */
374 uint8_t word2Reserved1; /* FC Word 2 byte 0 */
376 uint8_t totalConcurrSeq; /* FC Word 2 byte 1 */
377 uint8_t roByCategoryMsb; /* FC Word 2 byte 2 */
379 uint8_t roByCategoryLsb; /* FC Word 2 byte 3 */
381 uint32_t r_a_tov; /* R_A_TOV must be in B.E. format */
384 uint32_t e_d_tov; /* E_D_TOV must be in B.E. format */
388 #ifdef __BIG_ENDIAN_BITFIELD
389 uint8_t classValid:1; /* FC Word 0, bit 31 */
390 uint8_t intermix:1; /* FC Word 0, bit 30 */
391 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
392 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
393 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
394 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
395 #else /* __LITTLE_ENDIAN_BITFIELD */
396 uint8_t word0Reserved1:3; /* FC Word 0, bit 24:26 */
397 uint8_t seqDelivery:1; /* FC Word 0, bit 27 */
398 uint8_t stackedLockDown:1; /* FC Word 0, bit 28 */
399 uint8_t stackedXparent:1; /* FC Word 0, bit 29 */
400 uint8_t intermix:1; /* FC Word 0, bit 30 */
401 uint8_t classValid:1; /* FC Word 0, bit 31 */
405 uint8_t word0Reserved2; /* FC Word 0, bit 16:23 */
407 #ifdef __BIG_ENDIAN_BITFIELD
408 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
409 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
410 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
411 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
412 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
413 #else /* __LITTLE_ENDIAN_BITFIELD */
414 uint8_t word0Reserved3:2; /* FC Word 0, bit 8: 9 */
415 uint8_t iCtlAckNcapable:1; /* FC Word 0, bit 10 */
416 uint8_t iCtlAck0capable:1; /* FC Word 0, bit 11 */
417 uint8_t iCtlInitialPa:2; /* FC Word 0, bit 12:13 */
418 uint8_t iCtlXidReAssgn:2; /* FC Word 0, Bit 14:15 */
421 uint8_t word0Reserved4; /* FC Word 0, bit 0: 7 */
423 #ifdef __BIG_ENDIAN_BITFIELD
424 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
425 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
426 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
427 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
428 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
429 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
430 #else /* __LITTLE_ENDIAN_BITFIELD */
431 uint8_t rCtlCatPerSeq:2; /* FC Word 1, bit 24:25 */
432 uint8_t word1Reserved1:1; /* FC Word 1, bit 26 */
433 uint8_t rCtlErrorPolicy:2; /* FC Word 1, bit 27:28 */
434 uint8_t rCtlXidInterlck:1; /* FC Word 1, bit 29 */
435 uint8_t rCtlAckNcapable:1; /* FC Word 1, bit 30 */
436 uint8_t rCtlAck0capable:1; /* FC Word 1, bit 31 */
439 uint8_t word1Reserved2; /* FC Word 1, bit 16:23 */
440 uint8_t rcvDataSizeMsb; /* FC Word 1, bit 8:15 */
441 uint8_t rcvDataSizeLsb; /* FC Word 1, bit 0: 7 */
443 uint8_t concurrentSeqMsb; /* FC Word 2, bit 24:31 */
444 uint8_t concurrentSeqLsb; /* FC Word 2, bit 16:23 */
445 uint8_t EeCreditSeqMsb; /* FC Word 2, bit 8:15 */
446 uint8_t EeCreditSeqLsb; /* FC Word 2, bit 0: 7 */
448 uint8_t openSeqPerXchgMsb; /* FC Word 3, bit 24:31 */
449 uint8_t openSeqPerXchgLsb; /* FC Word 3, bit 16:23 */
450 uint8_t word3Reserved1; /* Fc Word 3, bit 8:15 */
451 uint8_t word3Reserved2; /* Fc Word 3, bit 0: 7 */
454 struct serv_parm { /* Structure is in Big Endian format */
456 struct lpfc_name portName;
457 struct lpfc_name nodeName;
458 struct class_parms cls1;
459 struct class_parms cls2;
460 struct class_parms cls3;
461 struct class_parms cls4;
462 uint8_t vendorVersion[16];
466 * Extended Link Service LS_COMMAND codes (Payload Word 0)
468 #ifdef __BIG_ENDIAN_BITFIELD
469 #define ELS_CMD_MASK 0xffff0000
470 #define ELS_RSP_MASK 0xff000000
471 #define ELS_CMD_LS_RJT 0x01000000
472 #define ELS_CMD_ACC 0x02000000
473 #define ELS_CMD_PLOGI 0x03000000
474 #define ELS_CMD_FLOGI 0x04000000
475 #define ELS_CMD_LOGO 0x05000000
476 #define ELS_CMD_ABTX 0x06000000
477 #define ELS_CMD_RCS 0x07000000
478 #define ELS_CMD_RES 0x08000000
479 #define ELS_CMD_RSS 0x09000000
480 #define ELS_CMD_RSI 0x0A000000
481 #define ELS_CMD_ESTS 0x0B000000
482 #define ELS_CMD_ESTC 0x0C000000
483 #define ELS_CMD_ADVC 0x0D000000
484 #define ELS_CMD_RTV 0x0E000000
485 #define ELS_CMD_RLS 0x0F000000
486 #define ELS_CMD_ECHO 0x10000000
487 #define ELS_CMD_TEST 0x11000000
488 #define ELS_CMD_RRQ 0x12000000
489 #define ELS_CMD_PRLI 0x20100014
490 #define ELS_CMD_PRLO 0x21100014
491 #define ELS_CMD_PRLO_ACC 0x02100014
492 #define ELS_CMD_PDISC 0x50000000
493 #define ELS_CMD_FDISC 0x51000000
494 #define ELS_CMD_ADISC 0x52000000
495 #define ELS_CMD_FARP 0x54000000
496 #define ELS_CMD_FARPR 0x55000000
497 #define ELS_CMD_RPS 0x56000000
498 #define ELS_CMD_RPL 0x57000000
499 #define ELS_CMD_FAN 0x60000000
500 #define ELS_CMD_RSCN 0x61040000
501 #define ELS_CMD_SCR 0x62000000
502 #define ELS_CMD_RNID 0x78000000
503 #define ELS_CMD_LIRR 0x7A000000
504 #else /* __LITTLE_ENDIAN_BITFIELD */
505 #define ELS_CMD_MASK 0xffff
506 #define ELS_RSP_MASK 0xff
507 #define ELS_CMD_LS_RJT 0x01
508 #define ELS_CMD_ACC 0x02
509 #define ELS_CMD_PLOGI 0x03
510 #define ELS_CMD_FLOGI 0x04
511 #define ELS_CMD_LOGO 0x05
512 #define ELS_CMD_ABTX 0x06
513 #define ELS_CMD_RCS 0x07
514 #define ELS_CMD_RES 0x08
515 #define ELS_CMD_RSS 0x09
516 #define ELS_CMD_RSI 0x0A
517 #define ELS_CMD_ESTS 0x0B
518 #define ELS_CMD_ESTC 0x0C
519 #define ELS_CMD_ADVC 0x0D
520 #define ELS_CMD_RTV 0x0E
521 #define ELS_CMD_RLS 0x0F
522 #define ELS_CMD_ECHO 0x10
523 #define ELS_CMD_TEST 0x11
524 #define ELS_CMD_RRQ 0x12
525 #define ELS_CMD_PRLI 0x14001020
526 #define ELS_CMD_PRLO 0x14001021
527 #define ELS_CMD_PRLO_ACC 0x14001002
528 #define ELS_CMD_PDISC 0x50
529 #define ELS_CMD_FDISC 0x51
530 #define ELS_CMD_ADISC 0x52
531 #define ELS_CMD_FARP 0x54
532 #define ELS_CMD_FARPR 0x55
533 #define ELS_CMD_RPS 0x56
534 #define ELS_CMD_RPL 0x57
535 #define ELS_CMD_FAN 0x60
536 #define ELS_CMD_RSCN 0x0461
537 #define ELS_CMD_SCR 0x62
538 #define ELS_CMD_RNID 0x78
539 #define ELS_CMD_LIRR 0x7A
543 * LS_RJT Payload Definition
546 struct ls_rjt { /* Structure is in Big Endian format */
550 uint8_t lsRjtRsvd0; /* FC Word 0, bit 24:31 */
552 uint8_t lsRjtRsnCode; /* FC Word 0, bit 16:23 */
553 /* LS_RJT reason codes */
554 #define LSRJT_INVALID_CMD 0x01
555 #define LSRJT_LOGICAL_ERR 0x03
556 #define LSRJT_LOGICAL_BSY 0x05
557 #define LSRJT_PROTOCOL_ERR 0x07
558 #define LSRJT_UNABLE_TPC 0x09 /* Unable to perform command */
559 #define LSRJT_CMD_UNSUPPORTED 0x0B
560 #define LSRJT_VENDOR_UNIQUE 0xFF /* See Byte 3 */
562 uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
563 /* LS_RJT reason explanation */
564 #define LSEXP_NOTHING_MORE 0x00
565 #define LSEXP_SPARM_OPTIONS 0x01
566 #define LSEXP_SPARM_ICTL 0x03
567 #define LSEXP_SPARM_RCTL 0x05
568 #define LSEXP_SPARM_RCV_SIZE 0x07
569 #define LSEXP_SPARM_CONCUR_SEQ 0x09
570 #define LSEXP_SPARM_CREDIT 0x0B
571 #define LSEXP_INVALID_PNAME 0x0D
572 #define LSEXP_INVALID_NNAME 0x0E
573 #define LSEXP_INVALID_CSP 0x0F
574 #define LSEXP_INVALID_ASSOC_HDR 0x11
575 #define LSEXP_ASSOC_HDR_REQ 0x13
576 #define LSEXP_INVALID_O_SID 0x15
577 #define LSEXP_INVALID_OX_RX 0x17
578 #define LSEXP_CMD_IN_PROGRESS 0x19
579 #define LSEXP_INVALID_NPORT_ID 0x1F
580 #define LSEXP_INVALID_SEQ_ID 0x21
581 #define LSEXP_INVALID_XCHG 0x23
582 #define LSEXP_INACTIVE_XCHG 0x25
583 #define LSEXP_RQ_REQUIRED 0x27
584 #define LSEXP_OUT_OF_RESOURCE 0x29
585 #define LSEXP_CANT_GIVE_DATA 0x2A
586 #define LSEXP_REQ_UNSUPPORTED 0x2C
587 uint8_t vendorUnique; /* FC Word 0, bit 0: 7 */
593 * N_Port Login (FLOGO/PLOGO Request) Payload Definition
596 typedef struct _LOGO { /* Structure is in Big Endian format */
598 uint32_t nPortId32; /* Access nPortId as a word */
600 uint8_t word1Reserved1; /* FC Word 1, bit 31:24 */
601 uint8_t nPortIdByte0; /* N_port ID bit 16:23 */
602 uint8_t nPortIdByte1; /* N_port ID bit 8:15 */
603 uint8_t nPortIdByte2; /* N_port ID bit 0: 7 */
606 struct lpfc_name portName; /* N_port name field */
610 * FCP Login (PRLI Request / ACC) Payload Definition
613 #define PRLX_PAGE_LEN 0x10
614 #define TPRLO_PAGE_LEN 0x14
616 typedef struct _PRLI { /* Structure is in Big Endian format */
617 uint8_t prliType; /* FC Parm Word 0, bit 24:31 */
619 #define PRLI_FCP_TYPE 0x08
620 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
622 #ifdef __BIG_ENDIAN_BITFIELD
623 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
624 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
625 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
627 /* ACC = imagePairEstablished */
628 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
629 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
630 #else /* __LITTLE_ENDIAN_BITFIELD */
631 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
632 uint8_t word0Reserved2:1; /* FC Parm Word 0, bit 12 */
633 uint8_t estabImagePair:1; /* FC Parm Word 0, bit 13 */
634 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
635 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
636 /* ACC = imagePairEstablished */
639 #define PRLI_REQ_EXECUTED 0x1 /* acceptRspCode */
640 #define PRLI_NO_RESOURCES 0x2
641 #define PRLI_INIT_INCOMPLETE 0x3
642 #define PRLI_NO_SUCH_PA 0x4
643 #define PRLI_PREDEF_CONFIG 0x5
644 #define PRLI_PARTIAL_SUCCESS 0x6
645 #define PRLI_INVALID_PAGE_CNT 0x7
646 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
648 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
650 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
652 uint8_t word3Reserved1; /* FC Parm Word 3, bit 24:31 */
653 uint8_t word3Reserved2; /* FC Parm Word 3, bit 16:23 */
655 #ifdef __BIG_ENDIAN_BITFIELD
656 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
657 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
658 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
659 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
660 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
661 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
662 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
663 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
664 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
665 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
666 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
667 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
668 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
669 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
670 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
671 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
672 #else /* __LITTLE_ENDIAN_BITFIELD */
673 uint16_t Retry:1; /* FC Parm Word 3, bit 8 */
674 uint16_t TaskRetryIdReq:1; /* FC Parm Word 3, bit 9 */
675 uint16_t Word3bit10Resved:1; /* FC Parm Word 3, bit 10 */
676 uint16_t Word3bit11Resved:1; /* FC Parm Word 3, bit 11 */
677 uint16_t Word3bit12Resved:1; /* FC Parm Word 3, bit 12 */
678 uint16_t Word3bit13Resved:1; /* FC Parm Word 3, bit 13 */
679 uint16_t Word3bit14Resved:1; /* FC Parm Word 3, bit 14 */
680 uint16_t Word3bit15Resved:1; /* FC Parm Word 3, bit 15 */
681 uint16_t writeXferRdyDis:1; /* FC Parm Word 3, bit 0 */
682 uint16_t readXferRdyDis:1; /* FC Parm Word 3, bit 1 */
683 uint16_t dataRspMixEna:1; /* FC Parm Word 3, bit 2 */
684 uint16_t cmdDataMixEna:1; /* FC Parm Word 3, bit 3 */
685 uint16_t targetFunc:1; /* FC Parm Word 3, bit 4 */
686 uint16_t initiatorFunc:1; /* FC Parm Word 3, bit 5 */
687 uint16_t dataOverLay:1; /* FC Parm Word 3, bit 6 */
688 uint16_t ConfmComplAllowed:1; /* FC Parm Word 3, bit 7 */
693 * FCP Logout (PRLO Request / ACC) Payload Definition
696 typedef struct _PRLO { /* Structure is in Big Endian format */
697 uint8_t prloType; /* FC Parm Word 0, bit 24:31 */
699 #define PRLO_FCP_TYPE 0x08
700 uint8_t word0Reserved1; /* FC Parm Word 0, bit 16:23 */
702 #ifdef __BIG_ENDIAN_BITFIELD
703 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
704 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
705 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
706 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
707 #else /* __LITTLE_ENDIAN_BITFIELD */
708 uint8_t acceptRspCode:4; /* FC Parm Word 0, bit 8:11, ACC ONLY */
709 uint8_t word0Reserved2:2; /* FC Parm Word 0, bit 12:13 */
710 uint8_t respProcAssocV:1; /* FC Parm Word 0, bit 14 */
711 uint8_t origProcAssocV:1; /* FC Parm Word 0, bit 15 */
714 #define PRLO_REQ_EXECUTED 0x1 /* acceptRspCode */
715 #define PRLO_NO_SUCH_IMAGE 0x4
716 #define PRLO_INVALID_PAGE_CNT 0x7
718 uint8_t word0Reserved3; /* FC Parm Word 0, bit 0:7 */
720 uint32_t origProcAssoc; /* FC Parm Word 1, bit 0:31 */
722 uint32_t respProcAssoc; /* FC Parm Word 2, bit 0:31 */
724 uint32_t word3Reserved1; /* FC Parm Word 3, bit 0:31 */
727 typedef struct _ADISC { /* Structure is in Big Endian format */
729 struct lpfc_name portName;
730 struct lpfc_name nodeName;
734 typedef struct _FARP { /* Structure is in Big Endian format */
737 #define FARP_NO_ACTION 0 /* FARP information enclosed, no
739 #define FARP_MATCH_PORT 0x1 /* Match on Responder Port Name */
740 #define FARP_MATCH_NODE 0x2 /* Match on Responder Node Name */
741 #define FARP_MATCH_IP 0x4 /* Match on IP address, not supported */
742 #define FARP_MATCH_IPV4 0x5 /* Match on IPV4 address, not
744 #define FARP_MATCH_IPV6 0x6 /* Match on IPV6 address, not
748 #define FARP_REQUEST_PLOGI 0x1 /* Request for PLOGI */
749 #define FARP_REQUEST_FARPR 0x2 /* Request for FARP Response */
750 struct lpfc_name OportName;
751 struct lpfc_name OnodeName;
752 struct lpfc_name RportName;
753 struct lpfc_name RnodeName;
758 typedef struct _FAN { /* Structure is in Big Endian format */
760 struct lpfc_name FportName;
761 struct lpfc_name FnodeName;
764 typedef struct _SCR { /* Structure is in Big Endian format */
769 #define SCR_FUNC_FABRIC 0x01
770 #define SCR_FUNC_NPORT 0x02
771 #define SCR_FUNC_FULL 0x03
772 #define SCR_CLEAR 0xff
775 typedef struct _RNID_TOP_DISC {
776 struct lpfc_name portName;
780 #define RNID_HOST 0xa
781 #define RNID_DRIVER 0xd
783 uint32_t attachedNodes;
785 #define RNID_IPV4 0x1
786 #define RNID_IPV6 0x2
791 #define RNID_TD_SUPPORT 0x1
792 #define RNID_LP_VALID 0x2
795 typedef struct _RNID { /* Structure is in Big Endian format */
797 #define RNID_TOPOLOGY_DISC 0xdf
801 struct lpfc_name portName;
802 struct lpfc_name nodeName;
804 RNID_TOP_DISC topologyDisc; /* topology disc (0xdf) */
808 typedef struct _RPS { /* Structure is in Big Endian format */
811 struct lpfc_name portName;
815 typedef struct _RPS_RSP { /* Structure is in Big Endian format */
818 uint32_t linkFailureCnt;
819 uint32_t lossSyncCnt;
820 uint32_t lossSignalCnt;
821 uint32_t primSeqErrCnt;
822 uint32_t invalidXmitWord;
826 typedef struct _RPL { /* Structure is in Big Endian format */
831 typedef struct _PORT_NUM_BLK {
834 struct lpfc_name portName;
837 typedef struct _RPL_RSP { /* Structure is in Big Endian format */
840 PORT_NUM_BLK port_num_blk;
843 /* This is used for RSCN command */
844 typedef struct _D_ID { /* Structure is in Big Endian format */
848 #ifdef __BIG_ENDIAN_BITFIELD
853 #else /* __LITTLE_ENDIAN_BITFIELD */
864 * Structure to define all ELS Payload types
867 typedef struct _ELS_PKT { /* Structure is in Big Endian format */
868 uint8_t elsCode; /* FC Word 0, bit 24:31 */
873 struct ls_rjt lsRjt; /* Payload for LS_RJT ELS response */
874 struct serv_parm logi; /* Payload for PLOGI/FLOGI/PDISC/ACC */
875 LOGO logo; /* Payload for PLOGO/FLOGO/ACC */
876 PRLI prli; /* Payload for PRLI/ACC */
877 PRLO prlo; /* Payload for PRLO/ACC */
878 ADISC adisc; /* Payload for ADISC/ACC */
879 FARP farp; /* Payload for FARP/ACC */
880 FAN fan; /* Payload for FAN */
881 SCR scr; /* Payload for SCR/ACC */
882 RNID rnid; /* Payload for RNID */
883 uint8_t pad[128 - 4]; /* Pad out to payload of 128 bytes */
889 * HBA MAnagement Operations Command Codes
891 #define SLI_MGMT_GRHL 0x100 /* Get registered HBA list */
892 #define SLI_MGMT_GHAT 0x101 /* Get HBA attributes */
893 #define SLI_MGMT_GRPL 0x102 /* Get registered Port list */
894 #define SLI_MGMT_GPAT 0x110 /* Get Port attributes */
895 #define SLI_MGMT_RHBA 0x200 /* Register HBA */
896 #define SLI_MGMT_RHAT 0x201 /* Register HBA atttributes */
897 #define SLI_MGMT_RPRT 0x210 /* Register Port */
898 #define SLI_MGMT_RPA 0x211 /* Register Port attributes */
899 #define SLI_MGMT_DHBA 0x300 /* De-register HBA */
900 #define SLI_MGMT_DPRT 0x310 /* De-register Port */
903 * Management Service Subtypes
905 #define SLI_CT_FDMI_Subtypes 0x10
908 * HBA Management Service Reject Code
910 #define REJECT_CODE 0x9 /* Unable to perform command request */
913 * HBA Management Service Reject Reason Code
914 * Please refer to the Reason Codes above
918 * HBA Attribute Types
920 #define NODE_NAME 0x1
921 #define MANUFACTURER 0x2
922 #define SERIAL_NUMBER 0x3
924 #define MODEL_DESCRIPTION 0x5
925 #define HARDWARE_VERSION 0x6
926 #define DRIVER_VERSION 0x7
927 #define OPTION_ROM_VERSION 0x8
928 #define FIRMWARE_VERSION 0x9
929 #define OS_NAME_VERSION 0xa
930 #define MAX_CT_PAYLOAD_LEN 0xb
933 * Port Attrubute Types
935 #define SUPPORTED_FC4_TYPES 0x1
936 #define SUPPORTED_SPEED 0x2
937 #define PORT_SPEED 0x3
938 #define MAX_FRAME_SIZE 0x4
939 #define OS_DEVICE_NAME 0x5
940 #define HOST_NAME 0x6
942 union AttributesDef {
943 /* Structure is in Big Endian format */
945 uint32_t AttrType:16;
953 * HBA Attribute Entry (8 - 260 bytes)
956 union AttributesDef ad;
958 uint32_t VendorSpecific;
959 uint8_t Manufacturer[64];
960 uint8_t SerialNumber[64];
962 uint8_t ModelDescription[256];
963 uint8_t HardwareVersion[256];
964 uint8_t DriverVersion[256];
965 uint8_t OptionROMVersion[256];
966 uint8_t FirmwareVersion[256];
967 struct lpfc_name NodeName;
968 uint8_t SupportFC4Types[32];
969 uint32_t SupportSpeed;
971 uint32_t MaxFrameSize;
972 uint8_t OsDeviceName[256];
973 uint8_t OsNameVersion[256];
974 uint32_t MaxCTPayloadLen;
975 uint8_t HostName[256];
980 * HBA Attribute Block
983 uint32_t EntryCnt; /* Number of HBA attribute entries */
984 ATTRIBUTE_ENTRY Entry; /* Variable-length array */
991 struct lpfc_name PortName;
998 struct lpfc_name PortName;
1002 * Registered Port List Format
1006 PORT_ENTRY pe; /* Variable-length array */
1010 * Register HBA(RHBA)
1014 REG_PORT_LIST rpl; /* variable-length array */
1015 /* ATTRIBUTE_BLOCK ab; */
1019 * Register HBA Attributes (RHAT)
1022 struct lpfc_name HBA_PortName;
1024 } REG_HBA_ATTRIBUTE;
1027 * Register Port Attributes (RPA)
1030 struct lpfc_name PortName;
1032 } REG_PORT_ATTRIBUTE;
1035 * Get Registered HBA List (GRHL) Accept Payload Format
1038 uint32_t HBA__Entry_Cnt; /* Number of Registered HBA Identifiers */
1039 struct lpfc_name HBA_PortName; /* Variable-length array */
1043 * Get Registered Port List (GRPL) Accept Payload Format
1046 uint32_t RPL_Entry_Cnt; /* Number of Registered Port Entries */
1047 PORT_ENTRY Reg_Port_Entry[1]; /* Variable-length array */
1051 * Get Port Attributes (GPAT) Accept Payload Format
1055 ATTRIBUTE_BLOCK pab;
1060 * Begin HBA configuration parameters.
1061 * The PCI configuration register BAR assignments are:
1062 * BAR0, offset 0x10 - SLIM base memory address
1063 * BAR1, offset 0x14 - SLIM base memory high address
1064 * BAR2, offset 0x18 - REGISTER base memory address
1065 * BAR3, offset 0x1c - REGISTER base memory high address
1066 * BAR4, offset 0x20 - BIU I/O registers
1067 * BAR5, offset 0x24 - REGISTER base io high address
1070 /* Number of rings currently used and available. */
1071 #define MAX_CONFIGURED_RINGS 3
1074 /* IOCB / Mailbox is owned by FireFly */
1077 /* IOCB / Mailbox is owned by Host */
1080 /* Number of 4-byte words in an IOCB. */
1081 #define IOCB_WORD_SZ 8
1083 /* defines for type field in fc header */
1084 #define FC_ELS_DATA 0x1
1085 #define FC_LLC_SNAP 0x5
1086 #define FC_FCP_DATA 0x8
1087 #define FC_COMMON_TRANSPORT_ULP 0x20
1089 /* defines for rctl field in fc header */
1090 #define FC_DEV_DATA 0x0
1091 #define FC_UNSOL_CTL 0x2
1092 #define FC_SOL_CTL 0x3
1093 #define FC_UNSOL_DATA 0x4
1094 #define FC_FCP_CMND 0x6
1095 #define FC_ELS_REQ 0x22
1096 #define FC_ELS_RSP 0x23
1098 /* network headers for Dfctl field */
1099 #define FC_NET_HDR 0x20
1101 /* Start FireFly Register definitions */
1102 #define PCI_VENDOR_ID_EMULEX 0x10df
1103 #define PCI_DEVICE_ID_FIREFLY 0x1ae5
1104 #define PCI_DEVICE_ID_SAT_SMB 0xf011
1105 #define PCI_DEVICE_ID_SAT_MID 0xf015
1106 #define PCI_DEVICE_ID_RFLY 0xf095
1107 #define PCI_DEVICE_ID_PFLY 0xf098
1108 #define PCI_DEVICE_ID_LP101 0xf0a1
1109 #define PCI_DEVICE_ID_TFLY 0xf0a5
1110 #define PCI_DEVICE_ID_BSMB 0xf0d1
1111 #define PCI_DEVICE_ID_BMID 0xf0d5
1112 #define PCI_DEVICE_ID_ZSMB 0xf0e1
1113 #define PCI_DEVICE_ID_ZMID 0xf0e5
1114 #define PCI_DEVICE_ID_NEPTUNE 0xf0f5
1115 #define PCI_DEVICE_ID_NEPTUNE_SCSP 0xf0f6
1116 #define PCI_DEVICE_ID_NEPTUNE_DCSP 0xf0f7
1117 #define PCI_DEVICE_ID_SAT 0xf100
1118 #define PCI_DEVICE_ID_SAT_SCSP 0xf111
1119 #define PCI_DEVICE_ID_SAT_DCSP 0xf112
1120 #define PCI_DEVICE_ID_SUPERFLY 0xf700
1121 #define PCI_DEVICE_ID_DRAGONFLY 0xf800
1122 #define PCI_DEVICE_ID_CENTAUR 0xf900
1123 #define PCI_DEVICE_ID_PEGASUS 0xf980
1124 #define PCI_DEVICE_ID_THOR 0xfa00
1125 #define PCI_DEVICE_ID_VIPER 0xfb00
1126 #define PCI_DEVICE_ID_LP10000S 0xfc00
1127 #define PCI_DEVICE_ID_LP11000S 0xfc10
1128 #define PCI_DEVICE_ID_LPE11000S 0xfc20
1129 #define PCI_DEVICE_ID_SAT_S 0xfc40
1130 #define PCI_DEVICE_ID_HELIOS 0xfd00
1131 #define PCI_DEVICE_ID_HELIOS_SCSP 0xfd11
1132 #define PCI_DEVICE_ID_HELIOS_DCSP 0xfd12
1133 #define PCI_DEVICE_ID_ZEPHYR 0xfe00
1134 #define PCI_DEVICE_ID_ZEPHYR_SCSP 0xfe11
1135 #define PCI_DEVICE_ID_ZEPHYR_DCSP 0xfe12
1137 #define JEDEC_ID_ADDRESS 0x0080001c
1138 #define FIREFLY_JEDEC_ID 0x1ACC
1139 #define SUPERFLY_JEDEC_ID 0x0020
1140 #define DRAGONFLY_JEDEC_ID 0x0021
1141 #define DRAGONFLY_V2_JEDEC_ID 0x0025
1142 #define CENTAUR_2G_JEDEC_ID 0x0026
1143 #define CENTAUR_1G_JEDEC_ID 0x0028
1144 #define PEGASUS_ORION_JEDEC_ID 0x0036
1145 #define PEGASUS_JEDEC_ID 0x0038
1146 #define THOR_JEDEC_ID 0x0012
1147 #define HELIOS_JEDEC_ID 0x0364
1148 #define ZEPHYR_JEDEC_ID 0x0577
1149 #define VIPER_JEDEC_ID 0x4838
1150 #define SATURN_JEDEC_ID 0x1004
1152 #define JEDEC_ID_MASK 0x0FFFF000
1153 #define JEDEC_ID_SHIFT 12
1154 #define FC_JEDEC_ID(id) ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1156 typedef struct { /* FireFly BIU registers */
1157 uint32_t hostAtt; /* See definitions for Host Attention
1159 uint32_t chipAtt; /* See definitions for Chip Attention
1161 uint32_t hostStatus; /* See definitions for Host Status register */
1162 uint32_t hostControl; /* See definitions for Host Control register */
1163 uint32_t buiConfig; /* See definitions for BIU configuration
1167 /* IO Register size in bytes */
1168 #define FF_REG_AREA_SIZE 256
1170 /* Host Attention Register */
1172 #define HA_REG_OFFSET 0 /* Byte offset from register base address */
1174 #define HA_R0RE_REQ 0x00000001 /* Bit 0 */
1175 #define HA_R0CE_RSP 0x00000002 /* Bit 1 */
1176 #define HA_R0ATT 0x00000008 /* Bit 3 */
1177 #define HA_R1RE_REQ 0x00000010 /* Bit 4 */
1178 #define HA_R1CE_RSP 0x00000020 /* Bit 5 */
1179 #define HA_R1ATT 0x00000080 /* Bit 7 */
1180 #define HA_R2RE_REQ 0x00000100 /* Bit 8 */
1181 #define HA_R2CE_RSP 0x00000200 /* Bit 9 */
1182 #define HA_R2ATT 0x00000800 /* Bit 11 */
1183 #define HA_R3RE_REQ 0x00001000 /* Bit 12 */
1184 #define HA_R3CE_RSP 0x00002000 /* Bit 13 */
1185 #define HA_R3ATT 0x00008000 /* Bit 15 */
1186 #define HA_LATT 0x20000000 /* Bit 29 */
1187 #define HA_MBATT 0x40000000 /* Bit 30 */
1188 #define HA_ERATT 0x80000000 /* Bit 31 */
1190 #define HA_RXRE_REQ 0x00000001 /* Bit 0 */
1191 #define HA_RXCE_RSP 0x00000002 /* Bit 1 */
1192 #define HA_RXATT 0x00000008 /* Bit 3 */
1193 #define HA_RXMASK 0x0000000f
1195 /* Chip Attention Register */
1197 #define CA_REG_OFFSET 4 /* Byte offset from register base address */
1199 #define CA_R0CE_REQ 0x00000001 /* Bit 0 */
1200 #define CA_R0RE_RSP 0x00000002 /* Bit 1 */
1201 #define CA_R0ATT 0x00000008 /* Bit 3 */
1202 #define CA_R1CE_REQ 0x00000010 /* Bit 4 */
1203 #define CA_R1RE_RSP 0x00000020 /* Bit 5 */
1204 #define CA_R1ATT 0x00000080 /* Bit 7 */
1205 #define CA_R2CE_REQ 0x00000100 /* Bit 8 */
1206 #define CA_R2RE_RSP 0x00000200 /* Bit 9 */
1207 #define CA_R2ATT 0x00000800 /* Bit 11 */
1208 #define CA_R3CE_REQ 0x00001000 /* Bit 12 */
1209 #define CA_R3RE_RSP 0x00002000 /* Bit 13 */
1210 #define CA_R3ATT 0x00008000 /* Bit 15 */
1211 #define CA_MBATT 0x40000000 /* Bit 30 */
1213 /* Host Status Register */
1215 #define HS_REG_OFFSET 8 /* Byte offset from register base address */
1217 #define HS_MBRDY 0x00400000 /* Bit 22 */
1218 #define HS_FFRDY 0x00800000 /* Bit 23 */
1219 #define HS_FFER8 0x01000000 /* Bit 24 */
1220 #define HS_FFER7 0x02000000 /* Bit 25 */
1221 #define HS_FFER6 0x04000000 /* Bit 26 */
1222 #define HS_FFER5 0x08000000 /* Bit 27 */
1223 #define HS_FFER4 0x10000000 /* Bit 28 */
1224 #define HS_FFER3 0x20000000 /* Bit 29 */
1225 #define HS_FFER2 0x40000000 /* Bit 30 */
1226 #define HS_FFER1 0x80000000 /* Bit 31 */
1227 #define HS_FFERM 0xFF000000 /* Mask for error bits 31:24 */
1229 /* Host Control Register */
1231 #define HC_REG_OFFSET 12 /* Word offset from register base address */
1233 #define HC_MBINT_ENA 0x00000001 /* Bit 0 */
1234 #define HC_R0INT_ENA 0x00000002 /* Bit 1 */
1235 #define HC_R1INT_ENA 0x00000004 /* Bit 2 */
1236 #define HC_R2INT_ENA 0x00000008 /* Bit 3 */
1237 #define HC_R3INT_ENA 0x00000010 /* Bit 4 */
1238 #define HC_INITHBI 0x02000000 /* Bit 25 */
1239 #define HC_INITMB 0x04000000 /* Bit 26 */
1240 #define HC_INITFF 0x08000000 /* Bit 27 */
1241 #define HC_LAINT_ENA 0x20000000 /* Bit 29 */
1242 #define HC_ERINT_ENA 0x80000000 /* Bit 31 */
1244 /* Mailbox Commands */
1245 #define MBX_SHUTDOWN 0x00 /* terminate testing */
1246 #define MBX_LOAD_SM 0x01
1247 #define MBX_READ_NV 0x02
1248 #define MBX_WRITE_NV 0x03
1249 #define MBX_RUN_BIU_DIAG 0x04
1250 #define MBX_INIT_LINK 0x05
1251 #define MBX_DOWN_LINK 0x06
1252 #define MBX_CONFIG_LINK 0x07
1253 #define MBX_CONFIG_RING 0x09
1254 #define MBX_RESET_RING 0x0A
1255 #define MBX_READ_CONFIG 0x0B
1256 #define MBX_READ_RCONFIG 0x0C
1257 #define MBX_READ_SPARM 0x0D
1258 #define MBX_READ_STATUS 0x0E
1259 #define MBX_READ_RPI 0x0F
1260 #define MBX_READ_XRI 0x10
1261 #define MBX_READ_REV 0x11
1262 #define MBX_READ_LNK_STAT 0x12
1263 #define MBX_REG_LOGIN 0x13
1264 #define MBX_UNREG_LOGIN 0x14
1265 #define MBX_READ_LA 0x15
1266 #define MBX_CLEAR_LA 0x16
1267 #define MBX_DUMP_MEMORY 0x17
1268 #define MBX_DUMP_CONTEXT 0x18
1269 #define MBX_RUN_DIAGS 0x19
1270 #define MBX_RESTART 0x1A
1271 #define MBX_UPDATE_CFG 0x1B
1272 #define MBX_DOWN_LOAD 0x1C
1273 #define MBX_DEL_LD_ENTRY 0x1D
1274 #define MBX_RUN_PROGRAM 0x1E
1275 #define MBX_SET_MASK 0x20
1276 #define MBX_SET_SLIM 0x21
1277 #define MBX_UNREG_D_ID 0x23
1278 #define MBX_KILL_BOARD 0x24
1279 #define MBX_CONFIG_FARP 0x25
1280 #define MBX_BEACON 0x2A
1281 #define MBX_HEARTBEAT 0x31
1283 #define MBX_CONFIG_HBQ 0x7C
1284 #define MBX_LOAD_AREA 0x81
1285 #define MBX_RUN_BIU_DIAG64 0x84
1286 #define MBX_CONFIG_PORT 0x88
1287 #define MBX_READ_SPARM64 0x8D
1288 #define MBX_READ_RPI64 0x8F
1289 #define MBX_REG_LOGIN64 0x93
1290 #define MBX_READ_LA64 0x95
1291 #define MBX_REG_VPI 0x96
1292 #define MBX_UNREG_VPI 0x97
1293 #define MBX_REG_VNPID 0x96
1294 #define MBX_UNREG_VNPID 0x97
1296 #define MBX_FLASH_WR_ULA 0x98
1297 #define MBX_SET_DEBUG 0x99
1298 #define MBX_LOAD_EXP_ROM 0x9C
1300 #define MBX_MAX_CMDS 0x9D
1301 #define MBX_SLI2_CMD_MASK 0x80
1305 #define CMD_RCV_SEQUENCE_CX 0x01
1306 #define CMD_XMIT_SEQUENCE_CR 0x02
1307 #define CMD_XMIT_SEQUENCE_CX 0x03
1308 #define CMD_XMIT_BCAST_CN 0x04
1309 #define CMD_XMIT_BCAST_CX 0x05
1310 #define CMD_QUE_RING_BUF_CN 0x06
1311 #define CMD_QUE_XRI_BUF_CX 0x07
1312 #define CMD_IOCB_CONTINUE_CN 0x08
1313 #define CMD_RET_XRI_BUF_CX 0x09
1314 #define CMD_ELS_REQUEST_CR 0x0A
1315 #define CMD_ELS_REQUEST_CX 0x0B
1316 #define CMD_RCV_ELS_REQ_CX 0x0D
1317 #define CMD_ABORT_XRI_CN 0x0E
1318 #define CMD_ABORT_XRI_CX 0x0F
1319 #define CMD_CLOSE_XRI_CN 0x10
1320 #define CMD_CLOSE_XRI_CX 0x11
1321 #define CMD_CREATE_XRI_CR 0x12
1322 #define CMD_CREATE_XRI_CX 0x13
1323 #define CMD_GET_RPI_CN 0x14
1324 #define CMD_XMIT_ELS_RSP_CX 0x15
1325 #define CMD_GET_RPI_CR 0x16
1326 #define CMD_XRI_ABORTED_CX 0x17
1327 #define CMD_FCP_IWRITE_CR 0x18
1328 #define CMD_FCP_IWRITE_CX 0x19
1329 #define CMD_FCP_IREAD_CR 0x1A
1330 #define CMD_FCP_IREAD_CX 0x1B
1331 #define CMD_FCP_ICMND_CR 0x1C
1332 #define CMD_FCP_ICMND_CX 0x1D
1333 #define CMD_FCP_TSEND_CX 0x1F
1334 #define CMD_FCP_TRECEIVE_CX 0x21
1335 #define CMD_FCP_TRSP_CX 0x23
1336 #define CMD_FCP_AUTO_TRSP_CX 0x29
1338 #define CMD_ADAPTER_MSG 0x20
1339 #define CMD_ADAPTER_DUMP 0x22
1341 /* SLI_2 IOCB Command Set */
1343 #define CMD_RCV_SEQUENCE64_CX 0x81
1344 #define CMD_XMIT_SEQUENCE64_CR 0x82
1345 #define CMD_XMIT_SEQUENCE64_CX 0x83
1346 #define CMD_XMIT_BCAST64_CN 0x84
1347 #define CMD_XMIT_BCAST64_CX 0x85
1348 #define CMD_QUE_RING_BUF64_CN 0x86
1349 #define CMD_QUE_XRI_BUF64_CX 0x87
1350 #define CMD_IOCB_CONTINUE64_CN 0x88
1351 #define CMD_RET_XRI_BUF64_CX 0x89
1352 #define CMD_ELS_REQUEST64_CR 0x8A
1353 #define CMD_ELS_REQUEST64_CX 0x8B
1354 #define CMD_ABORT_MXRI64_CN 0x8C
1355 #define CMD_RCV_ELS_REQ64_CX 0x8D
1356 #define CMD_XMIT_ELS_RSP64_CX 0x95
1357 #define CMD_FCP_IWRITE64_CR 0x98
1358 #define CMD_FCP_IWRITE64_CX 0x99
1359 #define CMD_FCP_IREAD64_CR 0x9A
1360 #define CMD_FCP_IREAD64_CX 0x9B
1361 #define CMD_FCP_ICMND64_CR 0x9C
1362 #define CMD_FCP_ICMND64_CX 0x9D
1363 #define CMD_FCP_TSEND64_CX 0x9F
1364 #define CMD_FCP_TRECEIVE64_CX 0xA1
1365 #define CMD_FCP_TRSP64_CX 0xA3
1367 #define CMD_IOCB_RCV_SEQ64_CX 0xB5
1368 #define CMD_IOCB_RCV_ELS64_CX 0xB7
1369 #define CMD_IOCB_RCV_CONT64_CX 0xBB
1371 #define CMD_GEN_REQUEST64_CR 0xC2
1372 #define CMD_GEN_REQUEST64_CX 0xC3
1374 #define CMD_MAX_IOCB_CMD 0xE6
1375 #define CMD_IOCB_MASK 0xff
1377 #define MAX_MSG_DATA 28 /* max msg data in CMD_ADAPTER_MSG
1379 #define LPFC_MAX_ADPTMSG 32 /* max msg data */
1383 #define MBX_SUCCESS 0
1384 #define MBXERR_NUM_RINGS 1
1385 #define MBXERR_NUM_IOCBS 2
1386 #define MBXERR_IOCBS_EXCEEDED 3
1387 #define MBXERR_BAD_RING_NUMBER 4
1388 #define MBXERR_MASK_ENTRIES_RANGE 5
1389 #define MBXERR_MASKS_EXCEEDED 6
1390 #define MBXERR_BAD_PROFILE 7
1391 #define MBXERR_BAD_DEF_CLASS 8
1392 #define MBXERR_BAD_MAX_RESPONDER 9
1393 #define MBXERR_BAD_MAX_ORIGINATOR 10
1394 #define MBXERR_RPI_REGISTERED 11
1395 #define MBXERR_RPI_FULL 12
1396 #define MBXERR_NO_RESOURCES 13
1397 #define MBXERR_BAD_RCV_LENGTH 14
1398 #define MBXERR_DMA_ERROR 15
1399 #define MBXERR_ERROR 16
1400 #define MBX_NOT_FINISHED 255
1402 #define MBX_BUSY 0xffffff /* Attempted cmd to busy Mailbox */
1403 #define MBX_TIMEOUT 0xfffffe /* time-out expired waiting for */
1406 * Begin Structure Definitions for Mailbox Commands
1410 #ifdef __BIG_ENDIAN_BITFIELD
1415 #else /* __LITTLE_ENDIAN_BITFIELD */
1424 uint32_t bdeAddress;
1425 #ifdef __BIG_ENDIAN_BITFIELD
1426 uint32_t bdeReserved:4;
1427 uint32_t bdeAddrHigh:4;
1428 uint32_t bdeSize:24;
1429 #else /* __LITTLE_ENDIAN_BITFIELD */
1430 uint32_t bdeSize:24;
1431 uint32_t bdeAddrHigh:4;
1432 uint32_t bdeReserved:4;
1436 struct ulp_bde64 { /* SLI-2 */
1440 #ifdef __BIG_ENDIAN_BITFIELD
1441 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
1443 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
1444 #else /* __LITTLE_ENDIAN_BITFIELD */
1445 uint32_t bdeSize:24; /* Size of buffer (in bytes) */
1446 uint32_t bdeFlags:8; /* BDE Flags 0 IS A SUPPORTED
1450 #define BUFF_USE_RSVD 0x01 /* bdeFlags */
1451 #define BUFF_USE_INTRPT 0x02 /* Not Implemented with LP6000 */
1452 #define BUFF_USE_CMND 0x04 /* Optional, 1=cmd/rsp 0=data buffer */
1453 #define BUFF_USE_RCV 0x08 /* "" "", 1=rcv buffer, 0=xmit
1455 #define BUFF_TYPE_32BIT 0x10 /* "" "", 1=32 bit addr 0=64 bit
1457 #define BUFF_TYPE_SPECIAL 0x20 /* Not Implemented with LP6000 */
1458 #define BUFF_TYPE_BDL 0x40 /* Optional, may be set in BDL */
1459 #define BUFF_TYPE_INVALID 0x80 /* "" "" */
1465 #define BDE64_SIZE_WORD 0
1466 #define BPL64_SIZE_WORD 0x40
1468 typedef struct ULP_BDL { /* SLI-2 */
1469 #ifdef __BIG_ENDIAN_BITFIELD
1470 uint32_t bdeFlags:8; /* BDL Flags */
1471 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1472 #else /* __LITTLE_ENDIAN_BITFIELD */
1473 uint32_t bdeSize:24; /* Size of BDL array in host memory (bytes) */
1474 uint32_t bdeFlags:8; /* BDL Flags */
1477 uint32_t addrLow; /* Address 0:31 */
1478 uint32_t addrHigh; /* Address 32:63 */
1479 uint32_t ulpIoTag32; /* Can be used for 32 bit I/O Tag */
1482 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
1485 #ifdef __BIG_ENDIAN_BITFIELD
1487 uint32_t acknowledgment:1;
1489 uint32_t erase_or_prog:1;
1490 uint32_t update_flash:1;
1491 uint32_t update_ram:1;
1493 uint32_t load_cmplt:1;
1494 #else /* __LITTLE_ENDIAN_BITFIELD */
1495 uint32_t load_cmplt:1;
1497 uint32_t update_ram:1;
1498 uint32_t update_flash:1;
1499 uint32_t erase_or_prog:1;
1501 uint32_t acknowledgment:1;
1505 uint32_t dl_to_adr_low;
1506 uint32_t dl_to_adr_high;
1509 uint32_t dl_from_mbx_offset;
1510 struct ulp_bde dl_from_bde;
1511 struct ulp_bde64 dl_from_bde64;
1516 /* Structure for MB Command READ_NVPARM (02) */
1519 uint32_t rsvd1[3]; /* Read as all one's */
1520 uint32_t rsvd2; /* Read as all zero's */
1521 uint32_t portname[2]; /* N_PORT name */
1522 uint32_t nodename[2]; /* NODE name */
1524 #ifdef __BIG_ENDIAN_BITFIELD
1525 uint32_t pref_DID:24;
1526 uint32_t hardAL_PA:8;
1527 #else /* __LITTLE_ENDIAN_BITFIELD */
1528 uint32_t hardAL_PA:8;
1529 uint32_t pref_DID:24;
1532 uint32_t rsvd3[21]; /* Read as all one's */
1535 /* Structure for MB Command WRITE_NVPARMS (03) */
1538 uint32_t rsvd1[3]; /* Must be all one's */
1539 uint32_t rsvd2; /* Must be all zero's */
1540 uint32_t portname[2]; /* N_PORT name */
1541 uint32_t nodename[2]; /* NODE name */
1543 #ifdef __BIG_ENDIAN_BITFIELD
1544 uint32_t pref_DID:24;
1545 uint32_t hardAL_PA:8;
1546 #else /* __LITTLE_ENDIAN_BITFIELD */
1547 uint32_t hardAL_PA:8;
1548 uint32_t pref_DID:24;
1551 uint32_t rsvd3[21]; /* Must be all one's */
1554 /* Structure for MB Command RUN_BIU_DIAG (04) */
1555 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
1561 struct ulp_bde xmit_bde;
1562 struct ulp_bde rcv_bde;
1565 struct ulp_bde64 xmit_bde64;
1566 struct ulp_bde64 rcv_bde64;
1571 /* Structure for MB Command INIT_LINK (05) */
1574 #ifdef __BIG_ENDIAN_BITFIELD
1576 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1577 #else /* __LITTLE_ENDIAN_BITFIELD */
1578 uint32_t lipsr_AL_PA:8; /* AL_PA to issue Lip Selective Reset to */
1582 #ifdef __BIG_ENDIAN_BITFIELD
1583 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1585 uint16_t link_flags;
1586 #else /* __LITTLE_ENDIAN_BITFIELD */
1587 uint16_t link_flags;
1589 uint8_t fabric_AL_PA; /* If using a Fabric Assigned AL_PA */
1592 #define FLAGS_LOCAL_LB 0x01 /* link_flags (=1) ENDEC loopback */
1593 #define FLAGS_TOPOLOGY_MODE_LOOP_PT 0x00 /* Attempt loop then pt-pt */
1594 #define FLAGS_TOPOLOGY_MODE_PT_PT 0x02 /* Attempt pt-pt only */
1595 #define FLAGS_TOPOLOGY_MODE_LOOP 0x04 /* Attempt loop only */
1596 #define FLAGS_TOPOLOGY_MODE_PT_LOOP 0x06 /* Attempt pt-pt then loop */
1597 #define FLAGS_UNREG_LOGIN_ALL 0x08 /* UNREG_LOGIN all on link down */
1598 #define FLAGS_LIRP_LILP 0x80 /* LIRP / LILP is disabled */
1600 #define FLAGS_TOPOLOGY_FAILOVER 0x0400 /* Bit 10 */
1601 #define FLAGS_LINK_SPEED 0x0800 /* Bit 11 */
1602 #define FLAGS_IMED_ABORT 0x04000 /* Bit 14 */
1604 uint32_t link_speed;
1605 #define LINK_SPEED_AUTO 0 /* Auto selection */
1606 #define LINK_SPEED_1G 1 /* 1 Gigabaud */
1607 #define LINK_SPEED_2G 2 /* 2 Gigabaud */
1608 #define LINK_SPEED_4G 4 /* 4 Gigabaud */
1609 #define LINK_SPEED_8G 8 /* 8 Gigabaud */
1610 #define LINK_SPEED_10G 16 /* 10 Gigabaud */
1614 /* Structure for MB Command DOWN_LINK (06) */
1620 /* Structure for MB Command CONFIG_LINK (07) */
1623 #ifdef __BIG_ENDIAN_BITFIELD
1626 uint32_t cr_delay:6;
1627 uint32_t cr_count:8;
1630 #else /* __LITTLE_ENDIAN_BITFIELD */
1633 uint32_t cr_count:8;
1634 uint32_t cr_delay:6;
1648 #ifdef __BIG_ENDIAN_BITFIELD
1649 uint32_t rrq_enable:1;
1650 uint32_t rrq_immed:1;
1652 uint32_t ack0_enable:1;
1653 #else /* __LITTLE_ENDIAN_BITFIELD */
1654 uint32_t ack0_enable:1;
1656 uint32_t rrq_immed:1;
1657 uint32_t rrq_enable:1;
1661 /* Structure for MB Command PART_SLIM (08)
1662 * will be removed since SLI1 is no longer supported!
1665 #ifdef __BIG_ENDIAN_BITFIELD
1670 #else /* __LITTLE_ENDIAN_BITFIELD */
1679 #ifdef __BIG_ENDIAN_BITFIELD
1680 uint32_t unused1:24;
1682 #else /* __LITTLE_ENDIAN_BITFIELD */
1684 uint32_t unused1:24;
1687 RING_DEF ringdef[4];
1691 /* Structure for MB Command CONFIG_RING (09) */
1694 #ifdef __BIG_ENDIAN_BITFIELD
1697 uint32_t recvNotify:1;
1702 #else /* __LITTLE_ENDIAN_BITFIELD */
1707 uint32_t recvNotify:1;
1712 #ifdef __BIG_ENDIAN_BITFIELD
1713 uint16_t maxRespXchg;
1714 uint16_t maxOrigXchg;
1715 #else /* __LITTLE_ENDIAN_BITFIELD */
1716 uint16_t maxOrigXchg;
1717 uint16_t maxRespXchg;
1723 /* Structure for MB Command RESET_RING (10) */
1729 /* Structure for MB Command READ_CONFIG (11) */
1732 #ifdef __BIG_ENDIAN_BITFIELD
1735 uint32_t cr_delay:6;
1736 uint32_t cr_count:8;
1739 #else /* __LITTLE_ENDIAN_BITFIELD */
1742 uint32_t cr_count:8;
1743 uint32_t cr_delay:6;
1748 #ifdef __BIG_ENDIAN_BITFIELD
1749 uint32_t topology:8;
1751 #else /* __LITTLE_ENDIAN_BITFIELD */
1753 uint32_t topology:8;
1756 /* Defines for topology (defined previously) */
1757 #ifdef __BIG_ENDIAN_BITFIELD
1762 #else /* __LITTLE_ENDIAN_BITFIELD */
1775 #define LMT_RESERVED 0x000 /* Not used */
1776 #define LMT_1Gb 0x004
1777 #define LMT_2Gb 0x008
1778 #define LMT_4Gb 0x040
1779 #define LMT_8Gb 0x080
1780 #define LMT_10Gb 0x100
1787 uint32_t avail_iocb;
1795 /* Structure for MB Command READ_RCONFIG (12) */
1798 #ifdef __BIG_ENDIAN_BITFIELD
1800 uint32_t recvNotify:1;
1805 #else /* __LITTLE_ENDIAN_BITFIELD */
1810 uint32_t recvNotify:1;
1814 #ifdef __BIG_ENDIAN_BITFIELD
1817 #else /* __LITTLE_ENDIAN_BITFIELD */
1824 #ifdef __BIG_ENDIAN_BITFIELD
1825 uint16_t cmdRingOffset;
1826 uint16_t cmdEntryCnt;
1827 uint16_t rspRingOffset;
1828 uint16_t rspEntryCnt;
1829 uint16_t nextCmdOffset;
1831 uint16_t nextRspOffset;
1833 #else /* __LITTLE_ENDIAN_BITFIELD */
1834 uint16_t cmdEntryCnt;
1835 uint16_t cmdRingOffset;
1836 uint16_t rspEntryCnt;
1837 uint16_t rspRingOffset;
1839 uint16_t nextCmdOffset;
1841 uint16_t nextRspOffset;
1845 /* Structure for MB Command READ_SPARM (13) */
1846 /* Structure for MB Command READ_SPARM64 (0x8D) */
1852 struct ulp_bde sp; /* This BDE points to struct serv_parm
1854 struct ulp_bde64 sp64;
1856 #ifdef __BIG_ENDIAN_BITFIELD
1859 #else /* __LITTLE_ENDIAN_BITFIELD */
1865 /* Structure for MB Command READ_STATUS (14) */
1868 #ifdef __BIG_ENDIAN_BITFIELD
1870 uint32_t clrCounters:1;
1871 uint16_t activeXriCnt;
1872 uint16_t activeRpiCnt;
1873 #else /* __LITTLE_ENDIAN_BITFIELD */
1874 uint32_t clrCounters:1;
1876 uint16_t activeRpiCnt;
1877 uint16_t activeXriCnt;
1880 uint32_t xmitByteCnt;
1881 uint32_t rcvByteCnt;
1882 uint32_t xmitFrameCnt;
1883 uint32_t rcvFrameCnt;
1884 uint32_t xmitSeqCnt;
1886 uint32_t totalOrigExchanges;
1887 uint32_t totalRespExchanges;
1888 uint32_t rcvPbsyCnt;
1889 uint32_t rcvFbsyCnt;
1892 /* Structure for MB Command READ_RPI (15) */
1893 /* Structure for MB Command READ_RPI64 (0x8F) */
1896 #ifdef __BIG_ENDIAN_BITFIELD
1901 #else /* __LITTLE_ENDIAN_BITFIELD */
1910 struct ulp_bde64 sp64;
1915 /* Structure for MB Command READ_XRI (16) */
1918 #ifdef __BIG_ENDIAN_BITFIELD
1935 uint32_t exchOrig:1;
1936 #else /* __LITTLE_ENDIAN_BITFIELD */
1951 uint32_t exchOrig:1;
1957 /* Structure for MB Command READ_REV (17) */
1960 #ifdef __BIG_ENDIAN_BITFIELD
1968 #else /* __LITTLE_ENDIAN_BITFIELD */
1983 #ifdef __BIG_ENDIAN_BITFIELD
1988 uint16_t ProgFixLvl:2;
1989 uint16_t ProgDistType:2;
1991 #else /* __LITTLE_ENDIAN_BITFIELD */
1993 uint16_t ProgDistType:2;
1994 uint16_t ProgFixLvl:2;
2004 #ifdef __BIG_ENDIAN_BITFIELD
2005 uint8_t feaLevelHigh;
2006 uint8_t feaLevelLow;
2009 #else /* __LITTLE_ENDIAN_BITFIELD */
2012 uint8_t feaLevelLow;
2013 uint8_t feaLevelHigh;
2016 uint32_t postKernRev;
2018 uint8_t opFwName[16];
2020 uint8_t sli1FwName[16];
2022 uint8_t sli2FwName[16];
2024 uint32_t RandomData[6];
2027 /* Structure for MB Command READ_LINK_STAT (18) */
2031 uint32_t linkFailureCnt;
2032 uint32_t lossSyncCnt;
2034 uint32_t lossSignalCnt;
2035 uint32_t primSeqErrCnt;
2036 uint32_t invalidXmitWord;
2038 uint32_t primSeqTimeout;
2039 uint32_t elasticOverrun;
2040 uint32_t arbTimeout;
2043 /* Structure for MB Command REG_LOGIN (19) */
2044 /* Structure for MB Command REG_LOGIN64 (0x93) */
2047 #ifdef __BIG_ENDIAN_BITFIELD
2052 #else /* __LITTLE_ENDIAN_BITFIELD */
2061 struct ulp_bde64 sp64;
2064 #ifdef __BIG_ENDIAN_BITFIELD
2067 #else /* __LITTLE_ENDIAN_BITFIELD */
2074 /* Word 30 contents for REG_LOGIN */
2077 #ifdef __BIG_ENDIAN_BITFIELD
2079 uint16_t wd30_class:4;
2081 #else /* __LITTLE_ENDIAN_BITFIELD */
2083 uint16_t wd30_class:4;
2090 /* Structure for MB Command UNREG_LOGIN (20) */
2093 #ifdef __BIG_ENDIAN_BITFIELD
2102 #else /* __LITTLE_ENDIAN_BITFIELD */
2114 /* Structure for MB Command REG_VPI (0x96) */
2116 #ifdef __BIG_ENDIAN_BITFIELD
2125 #else /* __LITTLE_ENDIAN */
2137 /* Structure for MB Command UNREG_VPI (0x97) */
2144 #ifdef __BIG_ENDIAN_BITFIELD
2147 #else /* __LITTLE_ENDIAN */
2153 /* Structure for MB Command UNREG_D_ID (0x23) */
2161 #ifdef __BIG_ENDIAN_BITFIELD
2170 /* Structure for MB Command READ_LA (21) */
2171 /* Structure for MB Command READ_LA64 (0x95) */
2174 uint32_t eventTag; /* Event tag */
2175 #ifdef __BIG_ENDIAN_BITFIELD
2180 #else /* __LITTLE_ENDIAN_BITFIELD */
2187 #define AT_RESERVED 0x00 /* Reserved - attType */
2188 #define AT_LINK_UP 0x01 /* Link is up */
2189 #define AT_LINK_DOWN 0x02 /* Link is down */
2191 #ifdef __BIG_ENDIAN_BITFIELD
2192 uint8_t granted_AL_PA;
2196 #else /* __LITTLE_ENDIAN_BITFIELD */
2200 uint8_t granted_AL_PA;
2203 #define TOPOLOGY_PT_PT 0x01 /* Topology is pt-pt / pt-fabric */
2204 #define TOPOLOGY_LOOP 0x02 /* Topology is FC-AL */
2207 struct ulp_bde lilpBde; /* This BDE points to a 128 byte buffer
2209 /* store the LILP AL_PA position map into */
2210 struct ulp_bde64 lilpBde64;
2213 #ifdef __BIG_ENDIAN_BITFIELD
2217 uint32_t DlnkSpeed:8;
2221 #else /* __LITTLE_ENDIAN_BITFIELD */
2225 uint32_t DlnkSpeed:8;
2231 #ifdef __BIG_ENDIAN_BITFIELD
2235 uint32_t UlnkSpeed:8;
2239 #else /* __LITTLE_ENDIAN_BITFIELD */
2243 uint32_t UlnkSpeed:8;
2249 #define LA_UNKNW_LINK 0x0 /* lnkSpeed */
2250 #define LA_1GHZ_LINK 0x04 /* lnkSpeed */
2251 #define LA_2GHZ_LINK 0x08 /* lnkSpeed */
2252 #define LA_4GHZ_LINK 0x10 /* lnkSpeed */
2253 #define LA_8GHZ_LINK 0x20 /* lnkSpeed */
2254 #define LA_10GHZ_LINK 0x40 /* lnkSpeed */
2258 /* Structure for MB Command CLEAR_LA (22) */
2261 uint32_t eventTag; /* Event tag */
2265 /* Structure for MB Command DUMP */
2268 #ifdef __BIG_ENDIAN_BITFIELD
2274 uint32_t entry_index:16;
2275 uint32_t region_id:16;
2276 #else /* __LITTLE_ENDIAN_BITFIELD */
2282 uint32_t region_id:16;
2283 uint32_t entry_index:16;
2288 uint32_t resp_offset;
2291 #define DMP_MEM_REG 0x1
2292 #define DMP_NV_PARAMS 0x2
2294 #define DMP_REGION_VPD 0xe
2295 #define DMP_VPD_SIZE 0x400 /* maximum amount of VPD */
2296 #define DMP_RSP_OFFSET 0x14 /* word 5 contains first word of rsp */
2297 #define DMP_RSP_SIZE 0x6C /* maximum of 27 words of rsp data */
2300 #ifdef __BIG_ENDIAN_BITFIELD
2305 #else /* __LITTLE_ENDIAN */
2314 /* Structure for MB Command CONFIG_HBQ (7c) */
2316 struct config_hbq_var {
2317 #ifdef __BIG_ENDIAN_BITFIELD
2319 uint32_t recvNotify :1; /* Receive Notification */
2320 uint32_t numMask :8; /* # Mask Entries */
2321 uint32_t profile :8; /* Selection Profile */
2323 #else /* __LITTLE_ENDIAN */
2325 uint32_t profile :8; /* Selection Profile */
2326 uint32_t numMask :8; /* # Mask Entries */
2327 uint32_t recvNotify :1; /* Receive Notification */
2331 #ifdef __BIG_ENDIAN_BITFIELD
2334 uint32_t ringMask :4;
2335 #else /* __LITTLE_ENDIAN */
2336 uint32_t ringMask :4;
2341 #ifdef __BIG_ENDIAN_BITFIELD
2342 uint32_t entry_count :16;
2344 uint32_t headerLen :8;
2345 #else /* __LITTLE_ENDIAN */
2346 uint32_t headerLen :8;
2348 uint32_t entry_count :16;
2351 uint32_t hbqaddrLow;
2352 uint32_t hbqaddrHigh;
2354 #ifdef __BIG_ENDIAN_BITFIELD
2356 uint32_t logEntry :1;
2357 #else /* __LITTLE_ENDIAN */
2358 uint32_t logEntry :1;
2362 uint32_t rsvd6; /* w7 */
2363 uint32_t rsvd7; /* w8 */
2364 uint32_t rsvd8; /* w9 */
2366 struct hbq_mask hbqMasks[6];
2370 uint32_t allprofiles[12];
2373 #ifdef __BIG_ENDIAN_BITFIELD
2374 uint32_t seqlenoff :16;
2375 uint32_t maxlen :16;
2376 #else /* __LITTLE_ENDIAN */
2377 uint32_t maxlen :16;
2378 uint32_t seqlenoff :16;
2380 #ifdef __BIG_ENDIAN_BITFIELD
2382 uint32_t seqlenbcnt :4;
2383 #else /* __LITTLE_ENDIAN */
2384 uint32_t seqlenbcnt :4;
2391 #ifdef __BIG_ENDIAN_BITFIELD
2392 uint32_t seqlenoff :16;
2393 uint32_t maxlen :16;
2394 #else /* __LITTLE_ENDIAN */
2395 uint32_t maxlen :16;
2396 uint32_t seqlenoff :16;
2398 #ifdef __BIG_ENDIAN_BITFIELD
2399 uint32_t cmdcodeoff :28;
2401 uint32_t seqlenbcnt :4;
2402 #else /* __LITTLE_ENDIAN */
2403 uint32_t seqlenbcnt :4;
2405 uint32_t cmdcodeoff :28;
2407 uint32_t cmdmatch[8];
2413 #ifdef __BIG_ENDIAN_BITFIELD
2414 uint32_t seqlenoff :16;
2415 uint32_t maxlen :16;
2416 #else /* __LITTLE_ENDIAN */
2417 uint32_t maxlen :16;
2418 uint32_t seqlenoff :16;
2420 #ifdef __BIG_ENDIAN_BITFIELD
2421 uint32_t cmdcodeoff :28;
2423 uint32_t seqlenbcnt :4;
2424 #else /* __LITTLE_ENDIAN */
2425 uint32_t seqlenbcnt :4;
2427 uint32_t cmdcodeoff :28;
2429 uint32_t cmdmatch[8];
2440 /* Structure for MB Command CONFIG_PORT (0x88) */
2442 #ifdef __BIG_ENDIAN_BITFIELD
2447 uint32_t sli_mode : 4;
2448 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
2450 #else /* __LITTLE_ENDIAN */
2451 uint32_t pcbLen : 24; /* bit 23:0 of memory based port
2453 uint32_t sli_mode : 4;
2460 uint32_t pcbLow; /* bit 31:0 of memory based port config block */
2461 uint32_t pcbHigh; /* bit 63:32 of memory based port config block */
2462 uint32_t hbainit[6];
2464 #ifdef __BIG_ENDIAN_BITFIELD
2465 uint32_t rsvd : 24; /* Reserved */
2466 uint32_t cmv : 1; /* Configure Max VPIs */
2467 uint32_t ccrp : 1; /* Config Command Ring Polling */
2468 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
2469 uint32_t chbs : 1; /* Cofigure Host Backing store */
2470 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
2471 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
2472 uint32_t cmx : 1; /* Configure Max XRIs */
2473 uint32_t cmr : 1; /* Configure Max RPIs */
2474 #else /* __LITTLE_ENDIAN */
2475 uint32_t cmr : 1; /* Configure Max RPIs */
2476 uint32_t cmx : 1; /* Configure Max XRIs */
2477 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
2478 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
2479 uint32_t chbs : 1; /* Cofigure Host Backing store */
2480 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
2481 uint32_t ccrp : 1; /* Config Command Ring Polling */
2482 uint32_t cmv : 1; /* Configure Max VPIs */
2483 uint32_t rsvd : 24; /* Reserved */
2485 #ifdef __BIG_ENDIAN_BITFIELD
2486 uint32_t rsvd2 : 24; /* Reserved */
2487 uint32_t gmv : 1; /* Grant Max VPIs */
2488 uint32_t gcrp : 1; /* Grant Command Ring Polling */
2489 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
2490 uint32_t ghbs : 1; /* Grant Host Backing Store */
2491 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
2492 uint32_t gerbm : 1; /* Grant ERBM Request */
2493 uint32_t gmx : 1; /* Grant Max XRIs */
2494 uint32_t gmr : 1; /* Grant Max RPIs */
2495 #else /* __LITTLE_ENDIAN */
2496 uint32_t gmr : 1; /* Grant Max RPIs */
2497 uint32_t gmx : 1; /* Grant Max XRIs */
2498 uint32_t gerbm : 1; /* Grant ERBM Request */
2499 uint32_t ginb : 1; /* Grant Interrupt Notification Block */
2500 uint32_t ghbs : 1; /* Grant Host Backing Store */
2501 uint32_t gsah : 1; /* Grant Synchronous Abort Handling */
2502 uint32_t gcrp : 1; /* Grant Command Ring Polling */
2503 uint32_t gmv : 1; /* Grant Max VPIs */
2504 uint32_t rsvd2 : 24; /* Reserved */
2507 #ifdef __BIG_ENDIAN_BITFIELD
2508 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
2509 uint32_t max_xri : 16; /* Max XRIs Port should configure */
2510 #else /* __LITTLE_ENDIAN */
2511 uint32_t max_xri : 16; /* Max XRIs Port should configure */
2512 uint32_t max_rpi : 16; /* Max RPIs Port should configure */
2515 #ifdef __BIG_ENDIAN_BITFIELD
2516 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
2517 uint32_t rsvd3 : 16; /* Max HBQs Host expect to configure */
2518 #else /* __LITTLE_ENDIAN */
2519 uint32_t rsvd3 : 16; /* Max HBQs Host expect to configure */
2520 uint32_t max_hbq : 16; /* Max HBQs Host expect to configure */
2523 uint32_t rsvd4; /* Reserved */
2525 #ifdef __BIG_ENDIAN_BITFIELD
2526 uint32_t rsvd5 : 16; /* Reserved */
2527 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
2528 #else /* __LITTLE_ENDIAN */
2529 uint32_t max_vpi : 16; /* Max number of virt N-Ports */
2530 uint32_t rsvd5 : 16; /* Reserved */
2535 /* SLI-2 Port Control Block */
2538 #define SLIMOFF 0x30 /* WORD */
2540 typedef struct _SLI2_RDSC {
2541 uint32_t cmdEntries;
2542 uint32_t cmdAddrLow;
2543 uint32_t cmdAddrHigh;
2545 uint32_t rspEntries;
2546 uint32_t rspAddrLow;
2547 uint32_t rspAddrHigh;
2550 typedef struct _PCB {
2551 #ifdef __BIG_ENDIAN_BITFIELD
2553 #define TYPE_NATIVE_SLI2 0x01;
2555 #define FEATURE_INITIAL_SLI2 0x01;
2558 #else /* __LITTLE_ENDIAN_BITFIELD */
2562 #define FEATURE_INITIAL_SLI2 0x01;
2564 #define TYPE_NATIVE_SLI2 0x01;
2567 uint32_t mailBoxSize;
2569 uint32_t mbAddrHigh;
2571 uint32_t hgpAddrLow;
2572 uint32_t hgpAddrHigh;
2574 uint32_t pgpAddrLow;
2575 uint32_t pgpAddrHigh;
2576 SLI2_RDSC rdsc[MAX_RINGS];
2581 #ifdef __BIG_ENDIAN_BITFIELD
2583 uint32_t discardFarp:1;
2584 uint32_t IPEnable:1;
2585 uint32_t nodeName:1;
2586 uint32_t portName:1;
2587 uint32_t filterEnable:1;
2588 #else /* __LITTLE_ENDIAN_BITFIELD */
2589 uint32_t filterEnable:1;
2590 uint32_t portName:1;
2591 uint32_t nodeName:1;
2592 uint32_t IPEnable:1;
2593 uint32_t discardFarp:1;
2597 uint8_t portname[8]; /* Used to be struct lpfc_name */
2598 uint8_t nodename[8];
2605 /* Union of all Mailbox Command types */
2606 #define MAILBOX_CMD_WSIZE 32
2607 #define MAILBOX_CMD_SIZE (MAILBOX_CMD_WSIZE * sizeof(uint32_t))
2610 uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
2611 * feature/max ring number
2613 LOAD_SM_VAR varLdSM; /* cmd = 1 (LOAD_SM) */
2614 READ_NV_VAR varRDnvp; /* cmd = 2 (READ_NVPARMS) */
2615 WRITE_NV_VAR varWTnvp; /* cmd = 3 (WRITE_NVPARMS) */
2616 BIU_DIAG_VAR varBIUdiag; /* cmd = 4 (RUN_BIU_DIAG) */
2617 INIT_LINK_VAR varInitLnk; /* cmd = 5 (INIT_LINK) */
2618 DOWN_LINK_VAR varDwnLnk; /* cmd = 6 (DOWN_LINK) */
2619 CONFIG_LINK varCfgLnk; /* cmd = 7 (CONFIG_LINK) */
2620 PART_SLIM_VAR varSlim; /* cmd = 8 (PART_SLIM) */
2621 CONFIG_RING_VAR varCfgRing; /* cmd = 9 (CONFIG_RING) */
2622 RESET_RING_VAR varRstRing; /* cmd = 10 (RESET_RING) */
2623 READ_CONFIG_VAR varRdConfig; /* cmd = 11 (READ_CONFIG) */
2624 READ_RCONF_VAR varRdRConfig; /* cmd = 12 (READ_RCONFIG) */
2625 READ_SPARM_VAR varRdSparm; /* cmd = 13 (READ_SPARM(64)) */
2626 READ_STATUS_VAR varRdStatus; /* cmd = 14 (READ_STATUS) */
2627 READ_RPI_VAR varRdRPI; /* cmd = 15 (READ_RPI(64)) */
2628 READ_XRI_VAR varRdXRI; /* cmd = 16 (READ_XRI) */
2629 READ_REV_VAR varRdRev; /* cmd = 17 (READ_REV) */
2630 READ_LNK_VAR varRdLnk; /* cmd = 18 (READ_LNK_STAT) */
2631 REG_LOGIN_VAR varRegLogin; /* cmd = 19 (REG_LOGIN(64)) */
2632 UNREG_LOGIN_VAR varUnregLogin; /* cmd = 20 (UNREG_LOGIN) */
2633 READ_LA_VAR varReadLA; /* cmd = 21 (READ_LA(64)) */
2634 CLEAR_LA_VAR varClearLA; /* cmd = 22 (CLEAR_LA) */
2635 DUMP_VAR varDmp; /* Warm Start DUMP mbx cmd */
2636 UNREG_D_ID_VAR varUnregDID; /* cmd = 0x23 (UNREG_D_ID) */
2637 CONFIG_FARP_VAR varCfgFarp; /* cmd = 0x25 (CONFIG_FARP)
2640 struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ) */
2641 CONFIG_PORT_VAR varCfgPort; /* cmd = 0x88 (CONFIG_PORT) */
2642 REG_VPI_VAR varRegVpi; /* cmd = 0x96 (REG_VPI) */
2643 UNREG_VPI_VAR varUnregVpi; /* cmd = 0x97 (UNREG_VPI) */
2647 * SLI-2 specific structures
2661 uint32_t unused1[16];
2662 struct lpfc_hgp host[MAX_RINGS];
2663 struct lpfc_pgp port[MAX_RINGS];
2667 struct lpfc_hgp host[MAX_RINGS];
2668 uint32_t reserved[8];
2669 uint32_t hbq_put[16];
2673 struct lpfc_pgp port[MAX_RINGS];
2674 uint32_t hbq_get[16];
2678 struct sli2_desc s2;
2679 struct sli3_desc s3;
2680 struct sli3_pgp s3_pgp;
2684 #ifdef __BIG_ENDIAN_BITFIELD
2687 uint8_t mbxReserved:6;
2689 uint8_t mbxOwner:1; /* Low order bit first word */
2690 #else /* __LITTLE_ENDIAN_BITFIELD */
2691 uint8_t mbxOwner:1; /* Low order bit first word */
2693 uint8_t mbxReserved:6;
2703 * Begin Structure Definitions for IOCB Commands
2707 #ifdef __BIG_ENDIAN_BITFIELD
2711 uint8_t statLocalError;
2712 #else /* __LITTLE_ENDIAN_BITFIELD */
2713 uint8_t statLocalError;
2718 /* statRsn P/F_RJT reason codes */
2719 #define RJT_BAD_D_ID 0x01 /* Invalid D_ID field */
2720 #define RJT_BAD_S_ID 0x02 /* Invalid S_ID field */
2721 #define RJT_UNAVAIL_TEMP 0x03 /* N_Port unavailable temp. */
2722 #define RJT_UNAVAIL_PERM 0x04 /* N_Port unavailable perm. */
2723 #define RJT_UNSUP_CLASS 0x05 /* Class not supported */
2724 #define RJT_DELIM_ERR 0x06 /* Delimiter usage error */
2725 #define RJT_UNSUP_TYPE 0x07 /* Type not supported */
2726 #define RJT_BAD_CONTROL 0x08 /* Invalid link conrtol */
2727 #define RJT_BAD_RCTL 0x09 /* R_CTL invalid */
2728 #define RJT_BAD_FCTL 0x0A /* F_CTL invalid */
2729 #define RJT_BAD_OXID 0x0B /* OX_ID invalid */
2730 #define RJT_BAD_RXID 0x0C /* RX_ID invalid */
2731 #define RJT_BAD_SEQID 0x0D /* SEQ_ID invalid */
2732 #define RJT_BAD_DFCTL 0x0E /* DF_CTL invalid */
2733 #define RJT_BAD_SEQCNT 0x0F /* SEQ_CNT invalid */
2734 #define RJT_BAD_PARM 0x10 /* Param. field invalid */
2735 #define RJT_XCHG_ERR 0x11 /* Exchange error */
2736 #define RJT_PROT_ERR 0x12 /* Protocol error */
2737 #define RJT_BAD_LENGTH 0x13 /* Invalid Length */
2738 #define RJT_UNEXPECTED_ACK 0x14 /* Unexpected ACK */
2739 #define RJT_LOGIN_REQUIRED 0x16 /* Login required */
2740 #define RJT_TOO_MANY_SEQ 0x17 /* Excessive sequences */
2741 #define RJT_XCHG_NOT_STRT 0x18 /* Exchange not started */
2742 #define RJT_UNSUP_SEC_HDR 0x19 /* Security hdr not supported */
2743 #define RJT_UNAVAIL_PATH 0x1A /* Fabric Path not available */
2744 #define RJT_VENDOR_UNIQUE 0xFF /* Vendor unique error */
2746 #define IOERR_SUCCESS 0x00 /* statLocalError */
2747 #define IOERR_MISSING_CONTINUE 0x01
2748 #define IOERR_SEQUENCE_TIMEOUT 0x02
2749 #define IOERR_INTERNAL_ERROR 0x03
2750 #define IOERR_INVALID_RPI 0x04
2751 #define IOERR_NO_XRI 0x05
2752 #define IOERR_ILLEGAL_COMMAND 0x06
2753 #define IOERR_XCHG_DROPPED 0x07
2754 #define IOERR_ILLEGAL_FIELD 0x08
2755 #define IOERR_BAD_CONTINUE 0x09
2756 #define IOERR_TOO_MANY_BUFFERS 0x0A
2757 #define IOERR_RCV_BUFFER_WAITING 0x0B
2758 #define IOERR_NO_CONNECTION 0x0C
2759 #define IOERR_TX_DMA_FAILED 0x0D
2760 #define IOERR_RX_DMA_FAILED 0x0E
2761 #define IOERR_ILLEGAL_FRAME 0x0F
2762 #define IOERR_EXTRA_DATA 0x10
2763 #define IOERR_NO_RESOURCES 0x11
2764 #define IOERR_RESERVED 0x12
2765 #define IOERR_ILLEGAL_LENGTH 0x13
2766 #define IOERR_UNSUPPORTED_FEATURE 0x14
2767 #define IOERR_ABORT_IN_PROGRESS 0x15
2768 #define IOERR_ABORT_REQUESTED 0x16
2769 #define IOERR_RECEIVE_BUFFER_TIMEOUT 0x17
2770 #define IOERR_LOOP_OPEN_FAILURE 0x18
2771 #define IOERR_RING_RESET 0x19
2772 #define IOERR_LINK_DOWN 0x1A
2773 #define IOERR_CORRUPTED_DATA 0x1B
2774 #define IOERR_CORRUPTED_RPI 0x1C
2775 #define IOERR_OUT_OF_ORDER_DATA 0x1D
2776 #define IOERR_OUT_OF_ORDER_ACK 0x1E
2777 #define IOERR_DUP_FRAME 0x1F
2778 #define IOERR_LINK_CONTROL_FRAME 0x20 /* ACK_N received */
2779 #define IOERR_BAD_HOST_ADDRESS 0x21
2780 #define IOERR_RCV_HDRBUF_WAITING 0x22
2781 #define IOERR_MISSING_HDR_BUFFER 0x23
2782 #define IOERR_MSEQ_CHAIN_CORRUPTED 0x24
2783 #define IOERR_ABORTMULT_REQUESTED 0x25
2784 #define IOERR_BUFFER_SHORTAGE 0x28
2785 #define IOERR_DEFAULT 0x29
2786 #define IOERR_CNT 0x2A
2788 #define IOERR_DRVR_MASK 0x100
2789 #define IOERR_SLI_DOWN 0x101 /* ulpStatus - Driver defined */
2790 #define IOERR_SLI_BRESET 0x102
2791 #define IOERR_SLI_ABORTED 0x103
2796 #ifdef __BIG_ENDIAN_BITFIELD
2797 uint8_t Rctl; /* R_CTL field */
2798 uint8_t Type; /* TYPE field */
2799 uint8_t Dfctl; /* DF_CTL field */
2800 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
2801 #else /* __LITTLE_ENDIAN_BITFIELD */
2802 uint8_t Fctl; /* Bits 0-7 of IOCB word 5 */
2803 uint8_t Dfctl; /* DF_CTL field */
2804 uint8_t Type; /* TYPE field */
2805 uint8_t Rctl; /* R_CTL field */
2808 #define BC 0x02 /* Broadcast Received - Fctl */
2809 #define SI 0x04 /* Sequence Initiative */
2810 #define LA 0x08 /* Ignore Link Attention state */
2811 #define LS 0x80 /* Last Sequence */
2816 /* IOCB Command template for a generic response */
2818 uint32_t reserved[4];
2822 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
2824 struct ulp_bde xrsqbde[2];
2825 uint32_t xrsqRo; /* Starting Relative Offset */
2826 WORD5 w5; /* Header control/status word */
2829 /* IOCB Command template for ELS_REQUEST */
2831 struct ulp_bde elsReq;
2832 struct ulp_bde elsRsp;
2834 #ifdef __BIG_ENDIAN_BITFIELD
2835 uint32_t word4Rsvd:7;
2838 uint32_t word5Rsvd:8;
2839 uint32_t remoteID:24;
2840 #else /* __LITTLE_ENDIAN_BITFIELD */
2843 uint32_t word4Rsvd:7;
2844 uint32_t remoteID:24;
2845 uint32_t word5Rsvd:8;
2849 /* IOCB Command template for RCV_ELS_REQ */
2851 struct ulp_bde elsReq[2];
2854 #ifdef __BIG_ENDIAN_BITFIELD
2855 uint32_t word5Rsvd:8;
2856 uint32_t remoteID:24;
2857 #else /* __LITTLE_ENDIAN_BITFIELD */
2858 uint32_t remoteID:24;
2859 uint32_t word5Rsvd:8;
2863 /* IOCB Command template for ABORT / CLOSE_XRI */
2867 #define ABORT_TYPE_ABTX 0x00000000
2868 #define ABORT_TYPE_ABTS 0x00000001
2870 #ifdef __BIG_ENDIAN_BITFIELD
2871 uint16_t abortContextTag; /* ulpContext from command to abort/close */
2872 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
2873 #else /* __LITTLE_ENDIAN_BITFIELD */
2874 uint16_t abortIoTag; /* ulpIoTag from command to abort/close */
2875 uint16_t abortContextTag; /* ulpContext from command to abort/close */
2879 /* IOCB Command template for ABORT_MXRI64 */
2887 /* IOCB Command template for GET_RPI */
2891 #ifdef __BIG_ENDIAN_BITFIELD
2892 uint32_t word5Rsvd:8;
2893 uint32_t remoteID:24;
2894 #else /* __LITTLE_ENDIAN_BITFIELD */
2895 uint32_t remoteID:24;
2896 uint32_t word5Rsvd:8;
2900 /* IOCB Command template for all FCP Initiator commands */
2902 struct ulp_bde fcpi_cmnd; /* FCP_CMND payload descriptor */
2903 struct ulp_bde fcpi_rsp; /* Rcv buffer */
2905 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
2908 /* IOCB Command template for all FCP Target commands */
2910 struct ulp_bde fcpt_Buffer[2]; /* FCP_CMND payload descriptor */
2911 uint32_t fcpt_Offset;
2912 uint32_t fcpt_Length; /* transfer ready for IWRITE */
2915 /* SLI-2 IOCB structure definitions */
2917 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
2920 uint32_t xrsqRo; /* Starting Relative Offset */
2921 WORD5 w5; /* Header control/status word */
2924 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */
2926 struct ulp_bde64 rcvBde;
2928 uint32_t xrsqRo; /* Starting Relative Offset */
2929 WORD5 w5; /* Header control/status word */
2932 /* IOCB Command template for ELS_REQUEST64 */
2935 #ifdef __BIG_ENDIAN_BITFIELD
2936 uint32_t word4Rsvd:7;
2939 uint32_t word5Rsvd:8;
2940 uint32_t remoteID:24;
2941 #else /* __LITTLE_ENDIAN_BITFIELD */
2944 uint32_t word4Rsvd:7;
2945 uint32_t remoteID:24;
2946 uint32_t word5Rsvd:8;
2950 /* IOCB Command template for GEN_REQUEST64 */
2953 uint32_t xrsqRo; /* Starting Relative Offset */
2954 WORD5 w5; /* Header control/status word */
2957 /* IOCB Command template for RCV_ELS_REQ64 */
2959 struct ulp_bde64 elsReq;
2963 #ifdef __BIG_ENDIAN_BITFIELD
2964 uint32_t word5Rsvd:8;
2965 uint32_t remoteID:24;
2966 #else /* __LITTLE_ENDIAN_BITFIELD */
2967 uint32_t remoteID:24;
2968 uint32_t word5Rsvd:8;
2972 /* IOCB Command template for all 64 bit FCP Initiator commands */
2976 uint32_t fcpi_XRdy; /* transfer ready for IWRITE */
2979 /* IOCB Command template for all 64 bit FCP Target commands */
2982 uint32_t fcpt_Offset;
2983 uint32_t fcpt_Length; /* transfer ready for IWRITE */
2986 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
2987 or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
2991 #ifdef __BIG_ENDIAN_BITFIELD
2994 #else /* __LITTLE_ENDIAN */
2998 uint32_t word10Rsvd;
2999 uint32_t acc_len; /* accumulated length */
3000 struct ulp_bde64 bde2;
3005 typedef struct _IOCB { /* IOCB structure */
3007 GENERIC_RSP grsp; /* Generic response */
3008 XR_SEQ_FIELDS xrseq; /* XMIT / BCAST / RCV_SEQUENCE cmd */
3009 struct ulp_bde cont[3]; /* up to 3 continuation bdes */
3010 RCV_ELS_REQ rcvels; /* RCV_ELS_REQ template */
3011 AC_XRI acxri; /* ABORT / CLOSE_XRI template */
3012 A_MXRI64 amxri; /* abort multiple xri command overlay */
3013 GET_RPI getrpi; /* GET_RPI template */
3014 FCPI_FIELDS fcpi; /* FCP Initiator template */
3015 FCPT_FIELDS fcpt; /* FCP target template */
3017 /* SLI-2 structures */
3019 struct ulp_bde64 cont64[2]; /* up to 2 64 bit continuation
3021 ELS_REQUEST64 elsreq64; /* ELS_REQUEST template */
3022 GEN_REQUEST64 genreq64; /* GEN_REQUEST template */
3023 RCV_ELS_REQ64 rcvels64; /* RCV_ELS_REQ template */
3024 XMT_SEQ_FIELDS64 xseq64; /* XMIT / BCAST cmd */
3025 FCPI_FIELDS64 fcpi64; /* FCP 64 bit Initiator template */
3026 FCPT_FIELDS64 fcpt64; /* FCP 64 bit target template */
3028 uint32_t ulpWord[IOCB_WORD_SZ - 2]; /* generic 6 'words' */
3032 #ifdef __BIG_ENDIAN_BITFIELD
3033 uint16_t ulpContext; /* High order bits word 6 */
3034 uint16_t ulpIoTag; /* Low order bits word 6 */
3035 #else /* __LITTLE_ENDIAN_BITFIELD */
3036 uint16_t ulpIoTag; /* Low order bits word 6 */
3037 uint16_t ulpContext; /* High order bits word 6 */
3041 #ifdef __BIG_ENDIAN_BITFIELD
3042 uint16_t ulpContext; /* High order bits word 6 */
3043 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
3044 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
3045 #else /* __LITTLE_ENDIAN_BITFIELD */
3046 uint16_t ulpIoTag0:14; /* Low order bits word 6 */
3047 uint16_t ulpIoTag1:2; /* Low order bits word 6 */
3048 uint16_t ulpContext; /* High order bits word 6 */
3052 #define ulpContext un1.t1.ulpContext
3053 #define ulpIoTag un1.t1.ulpIoTag
3054 #define ulpIoTag0 un1.t2.ulpIoTag0
3056 #ifdef __BIG_ENDIAN_BITFIELD
3057 uint32_t ulpTimeout:8;
3059 uint32_t ulpFCP2Rcvy:1;
3062 uint32_t ulpClass:3;
3063 uint32_t ulpCommand:8;
3064 uint32_t ulpStatus:4;
3065 uint32_t ulpBdeCount:2;
3067 uint32_t ulpOwner:1; /* Low order bit word 7 */
3068 #else /* __LITTLE_ENDIAN_BITFIELD */
3069 uint32_t ulpOwner:1; /* Low order bit word 7 */
3071 uint32_t ulpBdeCount:2;
3072 uint32_t ulpStatus:4;
3073 uint32_t ulpCommand:8;
3074 uint32_t ulpClass:3;
3077 uint32_t ulpFCP2Rcvy:1;
3079 uint32_t ulpTimeout:8;
3083 struct rcv_sli3 rcvsli3; /* words 8 - 15 */
3084 uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
3087 #define ulpCt_h ulpXS
3088 #define ulpCt_l ulpFCP2Rcvy
3090 #define IOCB_FCP 1 /* IOCB is used for FCP ELS cmds-ulpRsvByte */
3091 #define IOCB_IP 2 /* IOCB is used for IP ELS cmds */
3092 #define PARM_UNUSED 0 /* PU field (Word 4) not used */
3093 #define PARM_REL_OFF 1 /* PU field (Word 4) = R. O. */
3094 #define PARM_READ_CHECK 2 /* PU field (Word 4) = Data Transfer Length */
3095 #define PARM_NPIV_DID 3
3096 #define CLASS1 0 /* Class 1 */
3097 #define CLASS2 1 /* Class 2 */
3098 #define CLASS3 2 /* Class 3 */
3099 #define CLASS_FCP_INTERMIX 7 /* FCP Data->Cls 1, all else->Cls 2 */
3101 #define IOSTAT_SUCCESS 0x0 /* ulpStatus - HBA defined */
3102 #define IOSTAT_FCP_RSP_ERROR 0x1
3103 #define IOSTAT_REMOTE_STOP 0x2
3104 #define IOSTAT_LOCAL_REJECT 0x3
3105 #define IOSTAT_NPORT_RJT 0x4
3106 #define IOSTAT_FABRIC_RJT 0x5
3107 #define IOSTAT_NPORT_BSY 0x6
3108 #define IOSTAT_FABRIC_BSY 0x7
3109 #define IOSTAT_INTERMED_RSP 0x8
3110 #define IOSTAT_LS_RJT 0x9
3111 #define IOSTAT_BA_RJT 0xA
3112 #define IOSTAT_RSVD1 0xB
3113 #define IOSTAT_RSVD2 0xC
3114 #define IOSTAT_RSVD3 0xD
3115 #define IOSTAT_RSVD4 0xE
3116 #define IOSTAT_NEED_BUFFER 0xF
3117 #define IOSTAT_DRIVER_REJECT 0x10 /* ulpStatus - Driver defined */
3118 #define IOSTAT_DEFAULT 0xF /* Same as rsvd5 for now */
3119 #define IOSTAT_CNT 0x11
3123 /* Structure used for a single HBQ entry */
3124 struct lpfc_hbq_entry {
3125 struct ulp_bde64 bde;
3126 uint32_t buffer_tag;
3130 #define SLI1_SLIM_SIZE (4 * 1024)
3132 /* Up to 498 IOCBs will fit into 16k
3133 * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
3135 #define SLI2_SLIM_SIZE (64 * 1024)
3137 /* Maximum IOCBs that will fit in SLI2 slim */
3138 #define MAX_SLI2_IOCB 498
3139 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
3140 (sizeof(MAILBOX_t) + sizeof(PCB_t)))
3142 /* HBQ entries are 4 words each = 4k */
3143 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) * \
3144 lpfc_sli_hbq_count())
3146 struct lpfc_sli2_slim {
3149 IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
3153 * This function checks PCI device to allow special handling for LC HBAs.
3156 * device : struct pci_dev 's device field
3162 lpfc_is_LC_HBA(unsigned short device)
3164 if ((device == PCI_DEVICE_ID_TFLY) ||
3165 (device == PCI_DEVICE_ID_PFLY) ||
3166 (device == PCI_DEVICE_ID_LP101) ||
3167 (device == PCI_DEVICE_ID_BMID) ||
3168 (device == PCI_DEVICE_ID_BSMB) ||
3169 (device == PCI_DEVICE_ID_ZMID) ||
3170 (device == PCI_DEVICE_ID_ZSMB) ||
3171 (device == PCI_DEVICE_ID_RFLY))
3178 * Determine if an IOCB failed because of a link event or firmware reset.
3182 lpfc_error_lost_link(IOCB_t *iocbp)
3184 return (iocbp->ulpStatus == IOSTAT_LOCAL_REJECT &&
3185 (iocbp->un.ulpWord[4] == IOERR_SLI_ABORTED ||
3186 iocbp->un.ulpWord[4] == IOERR_LINK_DOWN ||
3187 iocbp->un.ulpWord[4] == IOERR_SLI_DOWN));