2 * ipr.h -- driver for IBM Power Linux RAID adapters
4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
6 * Copyright (C) 2003, 2004 IBM Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 * Alan Cox <alan@redhat.com> - Removed several careless u32/dma_addr_t errors
23 * that broke 64bit platforms.
29 #include <linux/types.h>
30 #include <linux/completion.h>
31 #include <linux/list.h>
32 #include <linux/kref.h>
33 #include <scsi/scsi.h>
34 #include <scsi/scsi_cmnd.h>
39 #define IPR_DRIVER_VERSION "2.0.14"
40 #define IPR_DRIVER_DATE "(May 2, 2005)"
43 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
44 * ops per device for devices not running tagged command queuing.
45 * This can be adjusted at runtime through sysfs device attributes.
47 #define IPR_MAX_CMD_PER_LUN 6
50 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
51 * ops the mid-layer can send to the adapter.
53 #define IPR_NUM_BASE_CMD_BLKS 100
55 #define IPR_SUBS_DEV_ID_2780 0x0264
56 #define IPR_SUBS_DEV_ID_5702 0x0266
57 #define IPR_SUBS_DEV_ID_5703 0x0278
58 #define IPR_SUBS_DEV_ID_572E 0x028D
59 #define IPR_SUBS_DEV_ID_573E 0x02D3
60 #define IPR_SUBS_DEV_ID_573D 0x02D4
61 #define IPR_SUBS_DEV_ID_571A 0x02C0
62 #define IPR_SUBS_DEV_ID_571B 0x02BE
63 #define IPR_SUBS_DEV_ID_571E 0x02BF
64 #define IPR_SUBS_DEV_ID_571F 0x02D5
65 #define IPR_SUBS_DEV_ID_572A 0x02C1
66 #define IPR_SUBS_DEV_ID_572B 0x02C2
67 #define IPR_SUBS_DEV_ID_575B 0x030D
69 #define IPR_NAME "ipr"
74 #define IPR_RC_JOB_CONTINUE 1
75 #define IPR_RC_JOB_RETURN 2
80 #define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
81 #define IPR_IOASC_SYNC_REQUIRED 0x023f0000
82 #define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
83 #define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
84 #define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
85 #define IPR_IOASC_IOASC_MASK 0xFFFFFF00
86 #define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
87 #define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
88 #define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
89 #define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
90 #define IPR_IOASC_BUS_WAS_RESET 0x06290000
91 #define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
92 #define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
94 #define IPR_FIRST_DRIVER_IOASC 0x10000000
95 #define IPR_IOASC_IOA_WAS_RESET 0x10000001
96 #define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
98 #define IPR_NUM_LOG_HCAMS 2
99 #define IPR_NUM_CFG_CHG_HCAMS 2
100 #define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
101 #define IPR_MAX_NUM_TARGETS_PER_BUS 0x10
102 #define IPR_MAX_NUM_LUNS_PER_TARGET 256
103 #define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8
104 #define IPR_VSET_BUS 0xff
105 #define IPR_IOA_BUS 0xff
106 #define IPR_IOA_TARGET 0xff
107 #define IPR_IOA_LUN 0xff
108 #define IPR_MAX_NUM_BUSES 4
109 #define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES
111 #define IPR_NUM_RESET_RELOAD_RETRIES 3
113 /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
114 #define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
115 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 3)
117 #define IPR_MAX_COMMANDS IPR_NUM_BASE_CMD_BLKS
118 #define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
119 IPR_NUM_INTERNAL_CMD_BLKS)
121 #define IPR_MAX_PHYSICAL_DEVS 192
123 #define IPR_MAX_SGLIST 64
124 #define IPR_IOA_MAX_SECTORS 32767
125 #define IPR_VSET_MAX_SECTORS 512
126 #define IPR_MAX_CDB_LEN 16
128 #define IPR_DEFAULT_BUS_WIDTH 16
129 #define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
130 #define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
131 #define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
132 #define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
134 #define IPR_IOA_RES_HANDLE 0xffffffff
135 #define IPR_IOA_RES_ADDR 0x00ffffff
140 #define IPR_QUERY_RSRC_STATE 0xC2
141 #define IPR_RESET_DEVICE 0xC3
142 #define IPR_RESET_TYPE_SELECT 0x80
143 #define IPR_LUN_RESET 0x40
144 #define IPR_TARGET_RESET 0x20
145 #define IPR_BUS_RESET 0x10
146 #define IPR_ID_HOST_RR_Q 0xC4
147 #define IPR_QUERY_IOA_CONFIG 0xC5
148 #define IPR_CANCEL_ALL_REQUESTS 0xCE
149 #define IPR_HOST_CONTROLLED_ASYNC 0xCF
150 #define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
151 #define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
152 #define IPR_SET_SUPPORTED_DEVICES 0xFB
153 #define IPR_IOA_SHUTDOWN 0xF7
154 #define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
159 #define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
160 #define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
161 #define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
162 #define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
163 #define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
164 #define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
165 #define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
166 #define IPR_WRITE_BUFFER_TIMEOUT (10 * 60 * HZ)
167 #define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
168 #define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
169 #define IPR_OPERATIONAL_TIMEOUT (5 * 60)
170 #define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
171 #define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
172 #define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
173 #define IPR_DUMP_TIMEOUT (15 * HZ)
178 #define IPR_VENDOR_ID_LEN 8
179 #define IPR_PROD_ID_LEN 16
180 #define IPR_SERIAL_NUM_LEN 8
185 #define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
186 #define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
187 #define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
188 #define IPR_GET_FMT2_BAR_SEL(mbx) \
189 (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
190 #define IPR_SDT_FMT2_BAR0_SEL 0x0
191 #define IPR_SDT_FMT2_BAR1_SEL 0x1
192 #define IPR_SDT_FMT2_BAR2_SEL 0x2
193 #define IPR_SDT_FMT2_BAR3_SEL 0x3
194 #define IPR_SDT_FMT2_BAR4_SEL 0x4
195 #define IPR_SDT_FMT2_BAR5_SEL 0x5
196 #define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
197 #define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
198 #define IPR_DOORBELL 0x82800000
199 #define IPR_RUNTIME_RESET 0x40000000
201 #define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
202 #define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
203 #define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
204 #define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
205 #define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
206 #define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
207 #define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
208 #define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
209 #define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
210 #define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
211 #define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
213 #define IPR_PCII_ERROR_INTERRUPTS \
214 (IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
215 IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
217 #define IPR_PCII_OPER_INTERRUPTS \
218 (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
220 #define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
221 #define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
223 #define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
224 #define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
229 #define IPR_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
230 #define IPR_NUM_SDT_ENTRIES 511
231 #define IPR_MAX_NUM_DUMP_PAGES ((IPR_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
236 #define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
239 * Adapter interface types
242 struct ipr_res_addr {
247 #define IPR_GET_PHYS_LOC(res_addr) \
248 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
249 }__attribute__((packed, aligned (4)));
251 struct ipr_std_inq_vpids {
252 u8 vendor_id[IPR_VENDOR_ID_LEN];
253 u8 product_id[IPR_PROD_ID_LEN];
254 }__attribute__((packed));
257 struct ipr_std_inq_vpids vpids;
258 u8 sn[IPR_SERIAL_NUM_LEN];
259 }__attribute__((packed));
264 }__attribute__((packed));
266 struct ipr_std_inq_data {
267 u8 peri_qual_dev_type;
268 #define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
269 #define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
271 u8 removeable_medium_rsvd;
272 #define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
274 #define IPR_IS_DASD_DEVICE(std_inq) \
275 ((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
276 !(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
278 #define IPR_IS_SES_DEVICE(std_inq) \
279 (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
288 struct ipr_std_inq_vpids vpids;
290 u8 ros_rsvd_ram_rsvd[4];
292 u8 serial_num[IPR_SERIAL_NUM_LEN];
293 }__attribute__ ((packed));
295 struct ipr_config_table_entry {
299 #define IPR_IS_IOA_RESOURCE 0x80
300 #define IPR_IS_ARRAY_MEMBER 0x20
301 #define IPR_IS_HOT_SPARE 0x10
304 #define IPR_RES_SUBTYPE(res) (((res)->cfgte.rsvd_subtype) & 0x0f)
305 #define IPR_SUBTYPE_AF_DASD 0
306 #define IPR_SUBTYPE_GENERIC_SCSI 1
307 #define IPR_SUBTYPE_VOLUME_SET 2
309 #define IPR_QUEUEING_MODEL(res) ((((res)->cfgte.flags) & 0x70) >> 4)
310 #define IPR_QUEUE_FROZEN_MODEL 0
311 #define IPR_QUEUE_NACA_MODEL 1
313 struct ipr_res_addr res_addr;
316 struct ipr_std_inq_data std_inq_data;
317 }__attribute__ ((packed, aligned (4)));
319 struct ipr_config_table_hdr {
322 #define IPR_UCODE_DOWNLOAD_REQ 0x10
324 }__attribute__((packed, aligned (4)));
326 struct ipr_config_table {
327 struct ipr_config_table_hdr hdr;
328 struct ipr_config_table_entry dev[IPR_MAX_PHYSICAL_DEVS];
329 }__attribute__((packed, aligned (4)));
331 struct ipr_hostrcb_cfg_ch_not {
332 struct ipr_config_table_entry cfgte;
334 }__attribute__((packed, aligned (4)));
336 struct ipr_supported_device {
340 struct ipr_std_inq_vpids vpids;
342 }__attribute__((packed, aligned (4)));
344 /* Command packet structure */
346 __be16 reserved; /* Reserved by IOA */
348 #define IPR_RQTYPE_SCSICDB 0x00
349 #define IPR_RQTYPE_IOACMD 0x01
350 #define IPR_RQTYPE_HCAM 0x02
355 #define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
356 #define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
357 #define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
358 #define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
359 #define IPR_FLAGS_HI_NO_LINK_DESC 0x04
362 #define IPR_FLAGS_LO_ALIGNED_BFR 0x20
363 #define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
364 #define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
365 #define IPR_FLAGS_LO_SIMPLE_TASK 0x02
366 #define IPR_FLAGS_LO_ORDERED_TASK 0x04
367 #define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
368 #define IPR_FLAGS_LO_ACA_TASK 0x08
372 }__attribute__ ((packed, aligned(4)));
374 /* IOA Request Control Block 128 bytes */
376 __be32 ioarcb_host_pci_addr;
379 __be32 host_response_handle;
384 __be32 write_data_transfer_length;
385 __be32 read_data_transfer_length;
386 __be32 write_ioadl_addr;
387 __be32 write_ioadl_len;
388 __be32 read_ioadl_addr;
389 __be32 read_ioadl_len;
391 __be32 ioasa_host_pci_addr;
395 struct ipr_cmd_pkt cmd_pkt;
397 __be32 add_cmd_parms_len;
398 __be32 add_cmd_parms[10];
399 }__attribute__((packed, aligned (4)));
401 struct ipr_ioadl_desc {
402 __be32 flags_and_data_len;
403 #define IPR_IOADL_FLAGS_MASK 0xff000000
404 #define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
405 #define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
406 #define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
407 #define IPR_IOADL_FLAGS_READ 0x48000000
408 #define IPR_IOADL_FLAGS_READ_LAST 0x49000000
409 #define IPR_IOADL_FLAGS_WRITE 0x68000000
410 #define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
411 #define IPR_IOADL_FLAGS_LAST 0x01000000
414 }__attribute__((packed, aligned (8)));
416 struct ipr_ioasa_vset {
417 __be32 failing_lba_hi;
418 __be32 failing_lba_lo;
420 }__attribute__((packed, aligned (4)));
422 struct ipr_ioasa_af_dasd {
425 }__attribute__((packed, aligned (4)));
427 struct ipr_ioasa_gpdd {
432 }__attribute__((packed, aligned (4)));
434 struct ipr_auto_sense {
435 __be16 auto_sense_len;
437 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
442 #define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
443 #define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
444 #define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
445 #define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
447 __be16 ret_stat_len; /* Length of the returned IOASA */
449 __be16 avail_stat_len; /* Total Length of status available. */
451 __be32 residual_data_len; /* number of bytes in the host data */
452 /* buffers that were not used by the IOARCB command. */
455 #define IPR_NO_ILID 0
456 #define IPR_DRIVER_ILID 0xffffffff
460 __be32 fd_phys_locator;
462 __be32 fd_res_handle;
464 __be32 ioasc_specific; /* status code specific field */
465 #define IPR_ADDITIONAL_STATUS_FMT 0x80000000
466 #define IPR_AUTOSENSE_VALID 0x40000000
467 #define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
468 #define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
469 #define IPR_FIELD_POINTER_MASK 0x0000ffff
472 struct ipr_ioasa_vset vset;
473 struct ipr_ioasa_af_dasd dasd;
474 struct ipr_ioasa_gpdd gpdd;
477 struct ipr_auto_sense auto_sense;
478 }__attribute__((packed, aligned (4)));
480 struct ipr_mode_parm_hdr {
483 u8 device_spec_parms;
485 }__attribute__((packed));
487 struct ipr_mode_pages {
488 struct ipr_mode_parm_hdr hdr;
489 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
490 }__attribute__((packed));
492 struct ipr_mode_page_hdr {
494 #define IPR_MODE_PAGE_PS 0x80
495 #define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
497 }__attribute__ ((packed));
499 struct ipr_dev_bus_entry {
500 struct ipr_res_addr res_addr;
502 #define IPR_SCSI_ATTR_ENABLE_QAS 0x80
503 #define IPR_SCSI_ATTR_DISABLE_QAS 0x40
504 #define IPR_SCSI_ATTR_QAS_MASK 0xC0
505 #define IPR_SCSI_ATTR_ENABLE_TM 0x20
506 #define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
507 #define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
508 #define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
512 u8 extended_reset_delay;
513 #define IPR_EXTENDED_RESET_DELAY 7
515 __be32 max_xfer_rate;
520 }__attribute__((packed, aligned (4)));
522 struct ipr_mode_page28 {
523 struct ipr_mode_page_hdr hdr;
526 struct ipr_dev_bus_entry bus[0];
527 }__attribute__((packed));
530 struct ipr_std_inq_data std_inq_data;
531 u8 ascii_part_num[12];
533 u8 ascii_plant_code[4];
534 }__attribute__((packed));
536 struct ipr_inquiry_page3 {
537 u8 peri_qual_dev_type;
549 }__attribute__((packed));
551 #define IPR_INQUIRY_PAGE0_ENTRIES 20
552 struct ipr_inquiry_page0 {
553 u8 peri_qual_dev_type;
557 u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
558 }__attribute__((packed));
560 struct ipr_hostrcb_device_data_entry {
562 struct ipr_res_addr dev_res_addr;
563 struct ipr_vpd new_vpd;
564 struct ipr_vpd ioa_last_with_dev_vpd;
565 struct ipr_vpd cfc_last_with_dev_vpd;
567 }__attribute__((packed, aligned (4)));
569 struct ipr_hostrcb_device_data_entry_enhanced {
570 struct ipr_ext_vpd vpd;
572 struct ipr_res_addr dev_res_addr;
573 struct ipr_ext_vpd new_vpd;
575 struct ipr_ext_vpd ioa_last_with_dev_vpd;
576 struct ipr_ext_vpd cfc_last_with_dev_vpd;
577 }__attribute__((packed, aligned (4)));
579 struct ipr_hostrcb_array_data_entry {
581 struct ipr_res_addr expected_dev_res_addr;
582 struct ipr_res_addr dev_res_addr;
583 }__attribute__((packed, aligned (4)));
585 struct ipr_hostrcb_array_data_entry_enhanced {
586 struct ipr_ext_vpd vpd;
588 struct ipr_res_addr expected_dev_res_addr;
589 struct ipr_res_addr dev_res_addr;
590 }__attribute__((packed, aligned (4)));
592 struct ipr_hostrcb_type_ff_error {
593 __be32 ioa_data[502];
594 }__attribute__((packed, aligned (4)));
596 struct ipr_hostrcb_type_01_error {
600 __be32 ioa_data[236];
601 }__attribute__((packed, aligned (4)));
603 struct ipr_hostrcb_type_02_error {
604 struct ipr_vpd ioa_vpd;
605 struct ipr_vpd cfc_vpd;
606 struct ipr_vpd ioa_last_attached_to_cfc_vpd;
607 struct ipr_vpd cfc_last_attached_to_ioa_vpd;
609 }__attribute__((packed, aligned (4)));
611 struct ipr_hostrcb_type_12_error {
612 struct ipr_ext_vpd ioa_vpd;
613 struct ipr_ext_vpd cfc_vpd;
614 struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd;
615 struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd;
617 }__attribute__((packed, aligned (4)));
619 struct ipr_hostrcb_type_03_error {
620 struct ipr_vpd ioa_vpd;
621 struct ipr_vpd cfc_vpd;
622 __be32 errors_detected;
623 __be32 errors_logged;
625 struct ipr_hostrcb_device_data_entry dev[3];
626 }__attribute__((packed, aligned (4)));
628 struct ipr_hostrcb_type_13_error {
629 struct ipr_ext_vpd ioa_vpd;
630 struct ipr_ext_vpd cfc_vpd;
631 __be32 errors_detected;
632 __be32 errors_logged;
633 struct ipr_hostrcb_device_data_entry_enhanced dev[3];
634 }__attribute__((packed, aligned (4)));
636 struct ipr_hostrcb_type_04_error {
637 struct ipr_vpd ioa_vpd;
638 struct ipr_vpd cfc_vpd;
640 struct ipr_hostrcb_array_data_entry array_member[10];
641 __be32 exposed_mode_adn;
643 struct ipr_vpd incomp_dev_vpd;
645 struct ipr_hostrcb_array_data_entry array_member2[8];
646 struct ipr_res_addr last_func_vset_res_addr;
647 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
648 u8 protection_level[8];
649 }__attribute__((packed, aligned (4)));
651 struct ipr_hostrcb_type_14_error {
652 struct ipr_ext_vpd ioa_vpd;
653 struct ipr_ext_vpd cfc_vpd;
654 __be32 exposed_mode_adn;
656 struct ipr_res_addr last_func_vset_res_addr;
657 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
658 u8 protection_level[8];
660 struct ipr_hostrcb_array_data_entry_enhanced array_member[18];
661 }__attribute__((packed, aligned (4)));
663 struct ipr_hostrcb_type_07_error {
664 u8 failure_reason[64];
667 }__attribute__((packed, aligned (4)));
669 struct ipr_hostrcb_type_17_error {
670 u8 failure_reason[64];
671 struct ipr_ext_vpd vpd;
673 }__attribute__((packed, aligned (4)));
675 struct ipr_hostrcb_error {
676 __be32 failing_dev_ioasc;
677 struct ipr_res_addr failing_dev_res_addr;
678 __be32 failing_dev_res_handle;
681 struct ipr_hostrcb_type_ff_error type_ff_error;
682 struct ipr_hostrcb_type_01_error type_01_error;
683 struct ipr_hostrcb_type_02_error type_02_error;
684 struct ipr_hostrcb_type_03_error type_03_error;
685 struct ipr_hostrcb_type_04_error type_04_error;
686 struct ipr_hostrcb_type_07_error type_07_error;
687 struct ipr_hostrcb_type_12_error type_12_error;
688 struct ipr_hostrcb_type_13_error type_13_error;
689 struct ipr_hostrcb_type_14_error type_14_error;
690 struct ipr_hostrcb_type_17_error type_17_error;
692 }__attribute__((packed, aligned (4)));
694 struct ipr_hostrcb_raw {
695 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
696 }__attribute__((packed, aligned (4)));
700 #define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
701 #define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
704 #define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
705 #define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
706 #define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
707 #define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
708 #define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
710 u8 notifications_lost;
711 #define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
712 #define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
715 #define IPR_HOSTRCB_INTERNAL_OPER 0x80
716 #define IPR_HOSTRCB_ERR_RESP_SENT 0x40
719 #define IPR_HOST_RCB_OVERLAY_ID_1 0x01
720 #define IPR_HOST_RCB_OVERLAY_ID_2 0x02
721 #define IPR_HOST_RCB_OVERLAY_ID_3 0x03
722 #define IPR_HOST_RCB_OVERLAY_ID_4 0x04
723 #define IPR_HOST_RCB_OVERLAY_ID_6 0x06
724 #define IPR_HOST_RCB_OVERLAY_ID_7 0x07
725 #define IPR_HOST_RCB_OVERLAY_ID_12 0x12
726 #define IPR_HOST_RCB_OVERLAY_ID_13 0x13
727 #define IPR_HOST_RCB_OVERLAY_ID_14 0x14
728 #define IPR_HOST_RCB_OVERLAY_ID_16 0x16
729 #define IPR_HOST_RCB_OVERLAY_ID_17 0x17
730 #define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
734 __be32 time_since_last_ioa_reset;
739 struct ipr_hostrcb_error error;
740 struct ipr_hostrcb_cfg_ch_not ccn;
741 struct ipr_hostrcb_raw raw;
743 }__attribute__((packed, aligned (4)));
746 struct ipr_hcam hcam;
747 dma_addr_t hostrcb_dma;
748 struct list_head queue;
751 /* IPR smart dump table structures */
752 struct ipr_sdt_entry {
753 __be32 bar_str_offset;
759 #define IPR_SDT_ENDIAN 0x80
760 #define IPR_SDT_VALID_ENTRY 0x20
764 }__attribute__((packed, aligned (4)));
766 struct ipr_sdt_header {
769 __be32 num_entries_used;
771 }__attribute__((packed, aligned (4)));
774 struct ipr_sdt_header hdr;
775 struct ipr_sdt_entry entry[IPR_NUM_SDT_ENTRIES];
776 }__attribute__((packed, aligned (4)));
779 struct ipr_sdt_header hdr;
780 struct ipr_sdt_entry entry[1];
781 }__attribute__((packed, aligned (4)));
786 struct ipr_bus_attributes {
794 struct ipr_resource_entry {
795 struct ipr_config_table_entry cfgte;
796 u8 needs_sync_complete:1;
800 u8 resetting_device:1;
802 struct scsi_device *sdev;
803 struct list_head queue;
806 struct ipr_resource_hdr {
811 struct ipr_resource_table {
812 struct ipr_resource_hdr hdr;
813 struct ipr_resource_entry dev[IPR_MAX_PHYSICAL_DEVS];
816 struct ipr_misc_cbs {
817 struct ipr_ioa_vpd ioa_vpd;
818 struct ipr_inquiry_page0 page0_data;
819 struct ipr_inquiry_page3 page3_data;
820 struct ipr_mode_pages mode_pages;
821 struct ipr_supported_device supp_dev;
824 struct ipr_interrupt_offsets {
825 unsigned long set_interrupt_mask_reg;
826 unsigned long clr_interrupt_mask_reg;
827 unsigned long sense_interrupt_mask_reg;
828 unsigned long clr_interrupt_reg;
830 unsigned long sense_interrupt_reg;
831 unsigned long ioarrin_reg;
832 unsigned long sense_uproc_interrupt_reg;
833 unsigned long set_uproc_interrupt_reg;
834 unsigned long clr_uproc_interrupt_reg;
837 struct ipr_interrupts {
838 void __iomem *set_interrupt_mask_reg;
839 void __iomem *clr_interrupt_mask_reg;
840 void __iomem *sense_interrupt_mask_reg;
841 void __iomem *clr_interrupt_reg;
843 void __iomem *sense_interrupt_reg;
844 void __iomem *ioarrin_reg;
845 void __iomem *sense_uproc_interrupt_reg;
846 void __iomem *set_uproc_interrupt_reg;
847 void __iomem *clr_uproc_interrupt_reg;
850 struct ipr_chip_cfg_t {
853 struct ipr_interrupt_offsets regs;
859 const struct ipr_chip_cfg_t *cfg;
862 enum ipr_shutdown_type {
863 IPR_SHUTDOWN_NORMAL = 0x00,
864 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
865 IPR_SHUTDOWN_ABBREV = 0x80,
866 IPR_SHUTDOWN_NONE = 0x100
869 struct ipr_trace_entry {
874 #define IPR_TRACE_START 0x00
875 #define IPR_TRACE_FINISH 0xff
891 struct scatterlist scatterlist[1];
902 enum ipr_cache_state {
909 /* Per-controller data */
912 #define IPR_EYECATCHER "iprcfg"
914 struct list_head queue;
916 u8 allow_interrupts:1;
917 u8 in_reset_reload:1;
918 u8 in_ioa_bringdown:1;
919 u8 ioa_unit_checked:1;
923 u8 allow_ml_add_del:1;
925 enum ipr_cache_state cache_state;
926 u16 type; /* CCIN of the card */
929 #define IPR_MAX_LOG_LEVEL 4
930 #define IPR_DEFAULT_LOG_LEVEL 2
932 #define IPR_NUM_TRACE_INDEX_BITS 8
933 #define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
934 #define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
936 #define IPR_TRACE_START_LABEL "trace"
937 struct ipr_trace_entry *trace;
938 u32 trace_index:IPR_NUM_TRACE_INDEX_BITS;
941 * Queue for free command blocks
943 char ipr_free_label[8];
944 #define IPR_FREEQ_LABEL "free-q"
945 struct list_head free_q;
948 * Queue for command blocks outstanding to the adapter
950 char ipr_pending_label[8];
951 #define IPR_PENDQ_LABEL "pend-q"
952 struct list_head pending_q;
954 char cfg_table_start[8];
955 #define IPR_CFG_TBL_START "cfg"
956 struct ipr_config_table *cfg_table;
957 dma_addr_t cfg_table_dma;
959 char resource_table_label[8];
960 #define IPR_RES_TABLE_LABEL "res_tbl"
961 struct ipr_resource_entry *res_entries;
962 struct list_head free_res_q;
963 struct list_head used_res_q;
965 char ipr_hcam_label[8];
966 #define IPR_HCAM_LABEL "hcams"
967 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
968 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
969 struct list_head hostrcb_free_q;
970 struct list_head hostrcb_pending_q;
973 dma_addr_t host_rrq_dma;
974 #define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
975 #define IPR_HRRQ_RESP_BIT_SET 0x00000002
976 #define IPR_HRRQ_TOGGLE_BIT 0x00000001
977 #define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
978 volatile __be32 *hrrq_start;
979 volatile __be32 *hrrq_end;
980 volatile __be32 *hrrq_curr;
981 volatile u32 toggle_bit;
983 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
985 const struct ipr_chip_cfg_t *chip_cfg;
987 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
988 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
989 void __iomem *ioa_mailbox;
990 struct ipr_interrupts regs;
992 u16 saved_pcix_cmd_reg;
998 struct Scsi_Host *host;
999 struct pci_dev *pdev;
1000 struct ipr_sglist *ucode_sglist;
1001 struct ipr_mode_pages *saved_mode_pages;
1002 u8 saved_mode_page_len;
1004 struct work_struct work_q;
1006 wait_queue_head_t reset_wait_q;
1008 struct ipr_dump *dump;
1009 enum ipr_sdt_state sdt_state;
1011 struct ipr_misc_cbs *vpd_cbs;
1012 dma_addr_t vpd_cbs_dma;
1014 struct pci_pool *ipr_cmd_pool;
1016 struct ipr_cmnd *reset_cmd;
1018 char ipr_cmd_label[8];
1019 #define IPR_CMD_LABEL "ipr_cmnd"
1020 struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS];
1021 u32 ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS];
1025 struct ipr_ioarcb ioarcb;
1026 struct ipr_ioasa ioasa;
1027 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
1028 struct list_head queue;
1029 struct scsi_cmnd *scsi_cmd;
1030 struct completion completion;
1031 struct timer_list timer;
1032 void (*done) (struct ipr_cmnd *);
1033 int (*job_step) (struct ipr_cmnd *);
1035 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
1036 dma_addr_t sense_buffer_dma;
1037 unsigned short dma_use_sg;
1038 dma_addr_t dma_handle;
1039 struct ipr_cmnd *sibling;
1041 enum ipr_shutdown_type shutdown_type;
1042 struct ipr_hostrcb *hostrcb;
1043 unsigned long time_left;
1044 unsigned long scratch;
1045 struct ipr_resource_entry *res;
1046 struct scsi_device *sdev;
1049 struct ipr_ioa_cfg *ioa_cfg;
1052 struct ipr_ses_table_entry {
1053 char product_id[17];
1054 char compare_product_id_byte[17];
1055 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
1058 struct ipr_dump_header {
1060 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1063 u32 first_entry_offset;
1065 #define IPR_DUMP_STATUS_SUCCESS 0
1066 #define IPR_DUMP_STATUS_QUAL_SUCCESS 2
1067 #define IPR_DUMP_STATUS_FAILED 0xffffffff
1069 #define IPR_DUMP_OS_LINUX 0x4C4E5558
1071 #define IPR_DUMP_DRIVER_NAME 0x49505232
1072 }__attribute__((packed, aligned (4)));
1074 struct ipr_dump_entry_header {
1076 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1081 #define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
1082 #define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
1084 #define IPR_DUMP_IOA_DUMP_ID 0x494F4131
1085 #define IPR_DUMP_LOCATION_ID 0x4C4F4341
1086 #define IPR_DUMP_TRACE_ID 0x54524143
1087 #define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
1088 #define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1089 #define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
1090 #define IPR_DUMP_PEND_OPS 0x414F5053
1092 }__attribute__((packed, aligned (4)));
1094 struct ipr_dump_location_entry {
1095 struct ipr_dump_entry_header hdr;
1096 u8 location[BUS_ID_SIZE];
1097 }__attribute__((packed));
1099 struct ipr_dump_trace_entry {
1100 struct ipr_dump_entry_header hdr;
1101 u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1102 }__attribute__((packed, aligned (4)));
1104 struct ipr_dump_version_entry {
1105 struct ipr_dump_entry_header hdr;
1106 u8 version[sizeof(IPR_DRIVER_VERSION)];
1109 struct ipr_dump_ioa_type_entry {
1110 struct ipr_dump_entry_header hdr;
1115 struct ipr_driver_dump {
1116 struct ipr_dump_header hdr;
1117 struct ipr_dump_version_entry version_entry;
1118 struct ipr_dump_location_entry location_entry;
1119 struct ipr_dump_ioa_type_entry ioa_type_entry;
1120 struct ipr_dump_trace_entry trace_entry;
1121 }__attribute__((packed));
1123 struct ipr_ioa_dump {
1124 struct ipr_dump_entry_header hdr;
1126 __be32 *ioa_data[IPR_MAX_NUM_DUMP_PAGES];
1128 u32 next_page_index;
1131 #define IPR_SDT_FMT2 2
1132 #define IPR_SDT_UNKNOWN 3
1133 }__attribute__((packed, aligned (4)));
1137 struct ipr_ioa_cfg *ioa_cfg;
1138 struct ipr_driver_dump driver_dump;
1139 struct ipr_ioa_dump ioa_dump;
1142 struct ipr_error_table_t {
1149 struct ipr_software_inq_lid_info {
1151 __be32 timestamp[3];
1152 }__attribute__((packed, aligned (4)));
1154 struct ipr_ucode_image_header {
1155 __be32 header_length;
1156 __be32 lid_table_offset;
1159 u8 minor_release[2];
1161 char eyecatcher[16];
1163 struct ipr_software_inq_lid_info lid[1];
1164 }__attribute__((packed, aligned (4)));
1169 #define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1171 #ifdef CONFIG_SCSI_IPR_TRACE
1172 #define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1173 #define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1175 #define ipr_create_trace_file(kobj, attr) 0
1176 #define ipr_remove_trace_file(kobj, attr) do { } while(0)
1179 #ifdef CONFIG_SCSI_IPR_DUMP
1180 #define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1181 #define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1183 #define ipr_create_dump_file(kobj, attr) 0
1184 #define ipr_remove_dump_file(kobj, attr) do { } while(0)
1188 * Error logging macros
1190 #define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1191 #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1192 #define ipr_crit(...) printk(KERN_CRIT IPR_NAME ": "__VA_ARGS__)
1193 #define ipr_warn(...) printk(KERN_WARNING IPR_NAME": "__VA_ARGS__)
1194 #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1196 #define ipr_sdev_printk(level, sdev, fmt, args...) \
1197 sdev_printk(level, sdev, fmt, ## args)
1199 #define ipr_sdev_err(sdev, fmt, ...) \
1200 ipr_sdev_printk(KERN_ERR, sdev, fmt, ##__VA_ARGS__)
1202 #define ipr_sdev_info(sdev, fmt, ...) \
1203 ipr_sdev_printk(KERN_INFO, sdev, fmt, ##__VA_ARGS__)
1205 #define ipr_sdev_dbg(sdev, fmt, ...) \
1206 IPR_DBG_CMD(ipr_sdev_printk(KERN_INFO, sdev, fmt, ##__VA_ARGS__))
1208 #define ipr_res_printk(level, ioa_cfg, res, fmt, ...) \
1209 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, ioa_cfg->host->host_no, \
1210 res.bus, res.target, res.lun, ##__VA_ARGS__)
1212 #define ipr_res_err(ioa_cfg, res, fmt, ...) \
1213 ipr_res_printk(KERN_ERR, ioa_cfg, res, fmt, ##__VA_ARGS__)
1214 #define ipr_res_dbg(ioa_cfg, res, fmt, ...) \
1215 IPR_DBG_CMD(ipr_res_printk(KERN_INFO, ioa_cfg, res, fmt, ##__VA_ARGS__))
1217 #define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1219 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
1220 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
1222 ipr_err(fmt": %d:%d:%d:%d\n", \
1223 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
1224 (res).bus, (res).target, (res).lun); \
1228 #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
1229 __FILE__, __FUNCTION__, __LINE__)
1231 #define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __FUNCTION__))
1232 #define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __FUNCTION__))
1234 #define ipr_err_separator \
1235 ipr_err("----------------------------------------------------------\n")
1243 * ipr_is_ioa_resource - Determine if a resource is the IOA
1244 * @res: resource entry struct
1247 * 1 if IOA / 0 if not IOA
1249 static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1251 return (res->cfgte.flags & IPR_IS_IOA_RESOURCE) ? 1 : 0;
1255 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1256 * @res: resource entry struct
1259 * 1 if AF DASD / 0 if not AF DASD
1261 static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1263 if (IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data) &&
1264 !ipr_is_ioa_resource(res) &&
1265 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_AF_DASD)
1272 * ipr_is_vset_device - Determine if a resource is a VSET
1273 * @res: resource entry struct
1276 * 1 if VSET / 0 if not VSET
1278 static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1280 if (IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data) &&
1281 !ipr_is_ioa_resource(res) &&
1282 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_VOLUME_SET)
1289 * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1290 * @res: resource entry struct
1293 * 1 if GSCSI / 0 if not GSCSI
1295 static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1297 if (!ipr_is_ioa_resource(res) &&
1298 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_GENERIC_SCSI)
1305 * ipr_is_naca_model - Determine if a resource is using NACA queueing model
1306 * @res: resource entry struct
1309 * 1 if NACA queueing model / 0 if not NACA queueing model
1311 static inline int ipr_is_naca_model(struct ipr_resource_entry *res)
1313 if (ipr_is_gscsi(res) && IPR_QUEUEING_MODEL(res) == IPR_QUEUE_NACA_MODEL)
1319 * ipr_is_device - Determine if resource address is that of a device
1320 * @res_addr: resource address struct
1323 * 1 if AF / 0 if not AF
1325 static inline int ipr_is_device(struct ipr_res_addr *res_addr)
1327 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1328 (res_addr->target < IPR_MAX_NUM_TARGETS_PER_BUS))
1335 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1336 * @sdt_word: SDT address
1339 * 1 if format 2 / 0 if not
1341 static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1343 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1346 case IPR_SDT_FMT2_BAR0_SEL:
1347 case IPR_SDT_FMT2_BAR1_SEL:
1348 case IPR_SDT_FMT2_BAR2_SEL:
1349 case IPR_SDT_FMT2_BAR3_SEL:
1350 case IPR_SDT_FMT2_BAR4_SEL:
1351 case IPR_SDT_FMT2_BAR5_SEL:
1352 case IPR_SDT_FMT2_EXP_ROM_SEL: