2 * ipr.h -- driver for IBM Power Linux RAID adapters
4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
6 * Copyright (C) 2003, 2004 IBM Corporation
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 * Alan Cox <alan@redhat.com> - Removed several careless u32/dma_addr_t errors
23 * that broke 64bit platforms.
29 #include <linux/types.h>
30 #include <linux/completion.h>
31 #include <linux/list.h>
32 #include <linux/kref.h>
33 #include <scsi/scsi.h>
34 #include <scsi/scsi_cmnd.h>
39 #define IPR_DRIVER_VERSION "2.0.14"
40 #define IPR_DRIVER_DATE "(May 2, 2005)"
43 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
44 * ops per device for devices not running tagged command queuing.
45 * This can be adjusted at runtime through sysfs device attributes.
47 #define IPR_MAX_CMD_PER_LUN 6
50 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
51 * ops the mid-layer can send to the adapter.
53 #define IPR_NUM_BASE_CMD_BLKS 100
55 #define IPR_SUBS_DEV_ID_2780 0x0264
56 #define IPR_SUBS_DEV_ID_5702 0x0266
57 #define IPR_SUBS_DEV_ID_5703 0x0278
58 #define IPR_SUBS_DEV_ID_572E 0x028D
59 #define IPR_SUBS_DEV_ID_573E 0x02D3
60 #define IPR_SUBS_DEV_ID_573D 0x02D4
61 #define IPR_SUBS_DEV_ID_571A 0x02C0
62 #define IPR_SUBS_DEV_ID_571B 0x02BE
63 #define IPR_SUBS_DEV_ID_571E 0x02BF
65 #define IPR_NAME "ipr"
70 #define IPR_RC_JOB_CONTINUE 1
71 #define IPR_RC_JOB_RETURN 2
76 #define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
77 #define IPR_IOASC_SYNC_REQUIRED 0x023f0000
78 #define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
79 #define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
80 #define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
81 #define IPR_IOASC_IOASC_MASK 0xFFFFFF00
82 #define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
83 #define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
84 #define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100
85 #define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000
86 #define IPR_IOASC_BUS_WAS_RESET 0x06290000
87 #define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
88 #define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
90 #define IPR_FIRST_DRIVER_IOASC 0x10000000
91 #define IPR_IOASC_IOA_WAS_RESET 0x10000001
92 #define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
94 #define IPR_NUM_LOG_HCAMS 2
95 #define IPR_NUM_CFG_CHG_HCAMS 2
96 #define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
97 #define IPR_MAX_NUM_TARGETS_PER_BUS 0x10
98 #define IPR_MAX_NUM_LUNS_PER_TARGET 256
99 #define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8
100 #define IPR_VSET_BUS 0xff
101 #define IPR_IOA_BUS 0xff
102 #define IPR_IOA_TARGET 0xff
103 #define IPR_IOA_LUN 0xff
104 #define IPR_MAX_NUM_BUSES 4
105 #define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES
107 #define IPR_NUM_RESET_RELOAD_RETRIES 3
109 /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
110 #define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
111 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 3)
113 #define IPR_MAX_COMMANDS IPR_NUM_BASE_CMD_BLKS
114 #define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
115 IPR_NUM_INTERNAL_CMD_BLKS)
117 #define IPR_MAX_PHYSICAL_DEVS 192
119 #define IPR_MAX_SGLIST 64
120 #define IPR_IOA_MAX_SECTORS 32767
121 #define IPR_VSET_MAX_SECTORS 512
122 #define IPR_MAX_CDB_LEN 16
124 #define IPR_DEFAULT_BUS_WIDTH 16
125 #define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
126 #define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
127 #define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
128 #define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
130 #define IPR_IOA_RES_HANDLE 0xffffffff
131 #define IPR_IOA_RES_ADDR 0x00ffffff
136 #define IPR_QUERY_RSRC_STATE 0xC2
137 #define IPR_RESET_DEVICE 0xC3
138 #define IPR_RESET_TYPE_SELECT 0x80
139 #define IPR_LUN_RESET 0x40
140 #define IPR_TARGET_RESET 0x20
141 #define IPR_BUS_RESET 0x10
142 #define IPR_ID_HOST_RR_Q 0xC4
143 #define IPR_QUERY_IOA_CONFIG 0xC5
144 #define IPR_CANCEL_ALL_REQUESTS 0xCE
145 #define IPR_HOST_CONTROLLED_ASYNC 0xCF
146 #define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
147 #define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
148 #define IPR_SET_SUPPORTED_DEVICES 0xFB
149 #define IPR_IOA_SHUTDOWN 0xF7
150 #define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
155 #define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
156 #define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
157 #define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
158 #define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
159 #define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
160 #define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
161 #define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
162 #define IPR_WRITE_BUFFER_TIMEOUT (10 * 60 * HZ)
163 #define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
164 #define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
165 #define IPR_OPERATIONAL_TIMEOUT (5 * 60)
166 #define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
167 #define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
168 #define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
169 #define IPR_DUMP_TIMEOUT (15 * HZ)
174 #define IPR_VENDOR_ID_LEN 8
175 #define IPR_PROD_ID_LEN 16
176 #define IPR_SERIAL_NUM_LEN 8
181 #define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
182 #define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
183 #define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
184 #define IPR_GET_FMT2_BAR_SEL(mbx) \
185 (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
186 #define IPR_SDT_FMT2_BAR0_SEL 0x0
187 #define IPR_SDT_FMT2_BAR1_SEL 0x1
188 #define IPR_SDT_FMT2_BAR2_SEL 0x2
189 #define IPR_SDT_FMT2_BAR3_SEL 0x3
190 #define IPR_SDT_FMT2_BAR4_SEL 0x4
191 #define IPR_SDT_FMT2_BAR5_SEL 0x5
192 #define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
193 #define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
194 #define IPR_DOORBELL 0x82800000
195 #define IPR_RUNTIME_RESET 0x40000000
197 #define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
198 #define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
199 #define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
200 #define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
201 #define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
202 #define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
203 #define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
204 #define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
205 #define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
206 #define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
207 #define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
209 #define IPR_PCII_ERROR_INTERRUPTS \
210 (IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
211 IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
213 #define IPR_PCII_OPER_INTERRUPTS \
214 (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
216 #define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
217 #define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
219 #define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
220 #define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
225 #define IPR_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
226 #define IPR_NUM_SDT_ENTRIES 511
227 #define IPR_MAX_NUM_DUMP_PAGES ((IPR_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
232 #define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
235 * Adapter interface types
238 struct ipr_res_addr {
243 #define IPR_GET_PHYS_LOC(res_addr) \
244 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
245 }__attribute__((packed, aligned (4)));
247 struct ipr_std_inq_vpids {
248 u8 vendor_id[IPR_VENDOR_ID_LEN];
249 u8 product_id[IPR_PROD_ID_LEN];
250 }__attribute__((packed));
253 struct ipr_std_inq_vpids vpids;
254 u8 sn[IPR_SERIAL_NUM_LEN];
255 }__attribute__((packed));
257 struct ipr_std_inq_data {
258 u8 peri_qual_dev_type;
259 #define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
260 #define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
262 u8 removeable_medium_rsvd;
263 #define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
265 #define IPR_IS_DASD_DEVICE(std_inq) \
266 ((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
267 !(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
269 #define IPR_IS_SES_DEVICE(std_inq) \
270 (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
279 struct ipr_std_inq_vpids vpids;
281 u8 ros_rsvd_ram_rsvd[4];
283 u8 serial_num[IPR_SERIAL_NUM_LEN];
284 }__attribute__ ((packed));
286 struct ipr_config_table_entry {
290 #define IPR_IS_IOA_RESOURCE 0x80
291 #define IPR_IS_ARRAY_MEMBER 0x20
292 #define IPR_IS_HOT_SPARE 0x10
295 #define IPR_RES_SUBTYPE(res) (((res)->cfgte.rsvd_subtype) & 0x0f)
296 #define IPR_SUBTYPE_AF_DASD 0
297 #define IPR_SUBTYPE_GENERIC_SCSI 1
298 #define IPR_SUBTYPE_VOLUME_SET 2
300 struct ipr_res_addr res_addr;
303 struct ipr_std_inq_data std_inq_data;
304 }__attribute__ ((packed, aligned (4)));
306 struct ipr_config_table_hdr {
309 #define IPR_UCODE_DOWNLOAD_REQ 0x10
311 }__attribute__((packed, aligned (4)));
313 struct ipr_config_table {
314 struct ipr_config_table_hdr hdr;
315 struct ipr_config_table_entry dev[IPR_MAX_PHYSICAL_DEVS];
316 }__attribute__((packed, aligned (4)));
318 struct ipr_hostrcb_cfg_ch_not {
319 struct ipr_config_table_entry cfgte;
321 }__attribute__((packed, aligned (4)));
323 struct ipr_supported_device {
327 struct ipr_std_inq_vpids vpids;
329 }__attribute__((packed, aligned (4)));
331 /* Command packet structure */
333 __be16 reserved; /* Reserved by IOA */
335 #define IPR_RQTYPE_SCSICDB 0x00
336 #define IPR_RQTYPE_IOACMD 0x01
337 #define IPR_RQTYPE_HCAM 0x02
342 #define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
343 #define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
344 #define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
345 #define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
346 #define IPR_FLAGS_HI_NO_LINK_DESC 0x04
349 #define IPR_FLAGS_LO_ALIGNED_BFR 0x20
350 #define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
351 #define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
352 #define IPR_FLAGS_LO_SIMPLE_TASK 0x02
353 #define IPR_FLAGS_LO_ORDERED_TASK 0x04
354 #define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
355 #define IPR_FLAGS_LO_ACA_TASK 0x08
359 }__attribute__ ((packed, aligned(4)));
361 /* IOA Request Control Block 128 bytes */
363 __be32 ioarcb_host_pci_addr;
366 __be32 host_response_handle;
371 __be32 write_data_transfer_length;
372 __be32 read_data_transfer_length;
373 __be32 write_ioadl_addr;
374 __be32 write_ioadl_len;
375 __be32 read_ioadl_addr;
376 __be32 read_ioadl_len;
378 __be32 ioasa_host_pci_addr;
382 struct ipr_cmd_pkt cmd_pkt;
384 __be32 add_cmd_parms_len;
385 __be32 add_cmd_parms[10];
386 }__attribute__((packed, aligned (4)));
388 struct ipr_ioadl_desc {
389 __be32 flags_and_data_len;
390 #define IPR_IOADL_FLAGS_MASK 0xff000000
391 #define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
392 #define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
393 #define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
394 #define IPR_IOADL_FLAGS_READ 0x48000000
395 #define IPR_IOADL_FLAGS_READ_LAST 0x49000000
396 #define IPR_IOADL_FLAGS_WRITE 0x68000000
397 #define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
398 #define IPR_IOADL_FLAGS_LAST 0x01000000
401 }__attribute__((packed, aligned (8)));
403 struct ipr_ioasa_vset {
404 __be32 failing_lba_hi;
405 __be32 failing_lba_lo;
407 }__attribute__((packed, aligned (4)));
409 struct ipr_ioasa_af_dasd {
412 }__attribute__((packed, aligned (4)));
414 struct ipr_ioasa_gpdd {
419 }__attribute__((packed, aligned (4)));
421 struct ipr_auto_sense {
422 __be16 auto_sense_len;
424 __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)];
429 #define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
430 #define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
431 #define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
432 #define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
434 __be16 ret_stat_len; /* Length of the returned IOASA */
436 __be16 avail_stat_len; /* Total Length of status available. */
438 __be32 residual_data_len; /* number of bytes in the host data */
439 /* buffers that were not used by the IOARCB command. */
442 #define IPR_NO_ILID 0
443 #define IPR_DRIVER_ILID 0xffffffff
447 __be32 fd_phys_locator;
449 __be32 fd_res_handle;
451 __be32 ioasc_specific; /* status code specific field */
452 #define IPR_ADDITIONAL_STATUS_FMT 0x80000000
453 #define IPR_AUTOSENSE_VALID 0x40000000
454 #define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
455 #define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
456 #define IPR_FIELD_POINTER_MASK 0x0000ffff
459 struct ipr_ioasa_vset vset;
460 struct ipr_ioasa_af_dasd dasd;
461 struct ipr_ioasa_gpdd gpdd;
464 struct ipr_auto_sense auto_sense;
465 }__attribute__((packed, aligned (4)));
467 struct ipr_mode_parm_hdr {
470 u8 device_spec_parms;
472 }__attribute__((packed));
474 struct ipr_mode_pages {
475 struct ipr_mode_parm_hdr hdr;
476 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
477 }__attribute__((packed));
479 struct ipr_mode_page_hdr {
481 #define IPR_MODE_PAGE_PS 0x80
482 #define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
484 }__attribute__ ((packed));
486 struct ipr_dev_bus_entry {
487 struct ipr_res_addr res_addr;
489 #define IPR_SCSI_ATTR_ENABLE_QAS 0x80
490 #define IPR_SCSI_ATTR_DISABLE_QAS 0x40
491 #define IPR_SCSI_ATTR_QAS_MASK 0xC0
492 #define IPR_SCSI_ATTR_ENABLE_TM 0x20
493 #define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
494 #define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
495 #define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
499 u8 extended_reset_delay;
500 #define IPR_EXTENDED_RESET_DELAY 7
502 __be32 max_xfer_rate;
507 }__attribute__((packed, aligned (4)));
509 struct ipr_mode_page28 {
510 struct ipr_mode_page_hdr hdr;
513 struct ipr_dev_bus_entry bus[0];
514 }__attribute__((packed));
517 struct ipr_std_inq_data std_inq_data;
518 u8 ascii_part_num[12];
520 u8 ascii_plant_code[4];
521 }__attribute__((packed));
523 struct ipr_inquiry_page3 {
524 u8 peri_qual_dev_type;
536 }__attribute__((packed));
538 #define IPR_INQUIRY_PAGE0_ENTRIES 20
539 struct ipr_inquiry_page0 {
540 u8 peri_qual_dev_type;
544 u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
545 }__attribute__((packed));
547 struct ipr_hostrcb_device_data_entry {
549 struct ipr_res_addr dev_res_addr;
550 struct ipr_vpd new_vpd;
551 struct ipr_vpd ioa_last_with_dev_vpd;
552 struct ipr_vpd cfc_last_with_dev_vpd;
554 }__attribute__((packed, aligned (4)));
556 struct ipr_hostrcb_array_data_entry {
558 struct ipr_res_addr expected_dev_res_addr;
559 struct ipr_res_addr dev_res_addr;
560 }__attribute__((packed, aligned (4)));
562 struct ipr_hostrcb_type_ff_error {
563 __be32 ioa_data[246];
564 }__attribute__((packed, aligned (4)));
566 struct ipr_hostrcb_type_01_error {
570 __be32 ioa_data[236];
571 }__attribute__((packed, aligned (4)));
573 struct ipr_hostrcb_type_02_error {
574 struct ipr_vpd ioa_vpd;
575 struct ipr_vpd cfc_vpd;
576 struct ipr_vpd ioa_last_attached_to_cfc_vpd;
577 struct ipr_vpd cfc_last_attached_to_ioa_vpd;
579 }__attribute__((packed, aligned (4)));
581 struct ipr_hostrcb_type_03_error {
582 struct ipr_vpd ioa_vpd;
583 struct ipr_vpd cfc_vpd;
584 __be32 errors_detected;
585 __be32 errors_logged;
587 struct ipr_hostrcb_device_data_entry dev[3];
588 }__attribute__((packed, aligned (4)));
590 struct ipr_hostrcb_type_04_error {
591 struct ipr_vpd ioa_vpd;
592 struct ipr_vpd cfc_vpd;
594 struct ipr_hostrcb_array_data_entry array_member[10];
595 __be32 exposed_mode_adn;
597 struct ipr_vpd incomp_dev_vpd;
599 struct ipr_hostrcb_array_data_entry array_member2[8];
600 struct ipr_res_addr last_func_vset_res_addr;
601 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
602 u8 protection_level[8];
603 }__attribute__((packed, aligned (4)));
605 struct ipr_hostrcb_type_07_error {
606 u8 failure_reason[64];
609 }__attribute__((packed, aligned (4)));
611 struct ipr_hostrcb_error {
612 __be32 failing_dev_ioasc;
613 struct ipr_res_addr failing_dev_res_addr;
614 __be32 failing_dev_res_handle;
617 struct ipr_hostrcb_type_ff_error type_ff_error;
618 struct ipr_hostrcb_type_01_error type_01_error;
619 struct ipr_hostrcb_type_02_error type_02_error;
620 struct ipr_hostrcb_type_03_error type_03_error;
621 struct ipr_hostrcb_type_04_error type_04_error;
622 struct ipr_hostrcb_type_07_error type_07_error;
624 }__attribute__((packed, aligned (4)));
626 struct ipr_hostrcb_raw {
627 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
628 }__attribute__((packed, aligned (4)));
632 #define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
633 #define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
636 #define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
637 #define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
638 #define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
639 #define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
640 #define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
642 u8 notifications_lost;
643 #define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
644 #define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
647 #define IPR_HOSTRCB_INTERNAL_OPER 0x80
648 #define IPR_HOSTRCB_ERR_RESP_SENT 0x40
651 #define IPR_HOST_RCB_OVERLAY_ID_1 0x01
652 #define IPR_HOST_RCB_OVERLAY_ID_2 0x02
653 #define IPR_HOST_RCB_OVERLAY_ID_3 0x03
654 #define IPR_HOST_RCB_OVERLAY_ID_4 0x04
655 #define IPR_HOST_RCB_OVERLAY_ID_6 0x06
656 #define IPR_HOST_RCB_OVERLAY_ID_7 0x07
657 #define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
661 __be32 time_since_last_ioa_reset;
666 struct ipr_hostrcb_error error;
667 struct ipr_hostrcb_cfg_ch_not ccn;
668 struct ipr_hostrcb_raw raw;
670 }__attribute__((packed, aligned (4)));
673 struct ipr_hcam hcam;
674 dma_addr_t hostrcb_dma;
675 struct list_head queue;
678 /* IPR smart dump table structures */
679 struct ipr_sdt_entry {
680 __be32 bar_str_offset;
686 #define IPR_SDT_ENDIAN 0x80
687 #define IPR_SDT_VALID_ENTRY 0x20
691 }__attribute__((packed, aligned (4)));
693 struct ipr_sdt_header {
696 __be32 num_entries_used;
698 }__attribute__((packed, aligned (4)));
701 struct ipr_sdt_header hdr;
702 struct ipr_sdt_entry entry[IPR_NUM_SDT_ENTRIES];
703 }__attribute__((packed, aligned (4)));
706 struct ipr_sdt_header hdr;
707 struct ipr_sdt_entry entry[1];
708 }__attribute__((packed, aligned (4)));
713 struct ipr_bus_attributes {
721 struct ipr_resource_entry {
722 struct ipr_config_table_entry cfgte;
723 u8 needs_sync_complete:1;
727 u8 resetting_device:1;
729 struct scsi_device *sdev;
730 struct list_head queue;
733 struct ipr_resource_hdr {
738 struct ipr_resource_table {
739 struct ipr_resource_hdr hdr;
740 struct ipr_resource_entry dev[IPR_MAX_PHYSICAL_DEVS];
743 struct ipr_misc_cbs {
744 struct ipr_ioa_vpd ioa_vpd;
745 struct ipr_inquiry_page0 page0_data;
746 struct ipr_inquiry_page3 page3_data;
747 struct ipr_mode_pages mode_pages;
748 struct ipr_supported_device supp_dev;
751 struct ipr_interrupt_offsets {
752 unsigned long set_interrupt_mask_reg;
753 unsigned long clr_interrupt_mask_reg;
754 unsigned long sense_interrupt_mask_reg;
755 unsigned long clr_interrupt_reg;
757 unsigned long sense_interrupt_reg;
758 unsigned long ioarrin_reg;
759 unsigned long sense_uproc_interrupt_reg;
760 unsigned long set_uproc_interrupt_reg;
761 unsigned long clr_uproc_interrupt_reg;
764 struct ipr_interrupts {
765 void __iomem *set_interrupt_mask_reg;
766 void __iomem *clr_interrupt_mask_reg;
767 void __iomem *sense_interrupt_mask_reg;
768 void __iomem *clr_interrupt_reg;
770 void __iomem *sense_interrupt_reg;
771 void __iomem *ioarrin_reg;
772 void __iomem *sense_uproc_interrupt_reg;
773 void __iomem *set_uproc_interrupt_reg;
774 void __iomem *clr_uproc_interrupt_reg;
777 struct ipr_chip_cfg_t {
780 struct ipr_interrupt_offsets regs;
786 const struct ipr_chip_cfg_t *cfg;
789 enum ipr_shutdown_type {
790 IPR_SHUTDOWN_NORMAL = 0x00,
791 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
792 IPR_SHUTDOWN_ABBREV = 0x80,
793 IPR_SHUTDOWN_NONE = 0x100
796 struct ipr_trace_entry {
801 #define IPR_TRACE_START 0x00
802 #define IPR_TRACE_FINISH 0xff
818 struct scatterlist scatterlist[1];
829 enum ipr_cache_state {
836 /* Per-controller data */
839 #define IPR_EYECATCHER "iprcfg"
841 struct list_head queue;
843 u8 allow_interrupts:1;
844 u8 in_reset_reload:1;
845 u8 in_ioa_bringdown:1;
846 u8 ioa_unit_checked:1;
850 u8 allow_ml_add_del:1;
852 enum ipr_cache_state cache_state;
853 u16 type; /* CCIN of the card */
856 #define IPR_MAX_LOG_LEVEL 4
857 #define IPR_DEFAULT_LOG_LEVEL 2
859 #define IPR_NUM_TRACE_INDEX_BITS 8
860 #define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
861 #define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
863 #define IPR_TRACE_START_LABEL "trace"
864 struct ipr_trace_entry *trace;
865 u32 trace_index:IPR_NUM_TRACE_INDEX_BITS;
868 * Queue for free command blocks
870 char ipr_free_label[8];
871 #define IPR_FREEQ_LABEL "free-q"
872 struct list_head free_q;
875 * Queue for command blocks outstanding to the adapter
877 char ipr_pending_label[8];
878 #define IPR_PENDQ_LABEL "pend-q"
879 struct list_head pending_q;
881 char cfg_table_start[8];
882 #define IPR_CFG_TBL_START "cfg"
883 struct ipr_config_table *cfg_table;
884 dma_addr_t cfg_table_dma;
886 char resource_table_label[8];
887 #define IPR_RES_TABLE_LABEL "res_tbl"
888 struct ipr_resource_entry *res_entries;
889 struct list_head free_res_q;
890 struct list_head used_res_q;
892 char ipr_hcam_label[8];
893 #define IPR_HCAM_LABEL "hcams"
894 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
895 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
896 struct list_head hostrcb_free_q;
897 struct list_head hostrcb_pending_q;
900 dma_addr_t host_rrq_dma;
901 #define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
902 #define IPR_HRRQ_RESP_BIT_SET 0x00000002
903 #define IPR_HRRQ_TOGGLE_BIT 0x00000001
904 #define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
905 volatile __be32 *hrrq_start;
906 volatile __be32 *hrrq_end;
907 volatile __be32 *hrrq_curr;
908 volatile u32 toggle_bit;
910 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
912 const struct ipr_chip_cfg_t *chip_cfg;
914 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
915 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
916 void __iomem *ioa_mailbox;
917 struct ipr_interrupts regs;
919 u16 saved_pcix_cmd_reg;
925 struct Scsi_Host *host;
926 struct pci_dev *pdev;
927 struct ipr_sglist *ucode_sglist;
928 struct ipr_mode_pages *saved_mode_pages;
929 u8 saved_mode_page_len;
931 struct work_struct work_q;
933 wait_queue_head_t reset_wait_q;
935 struct ipr_dump *dump;
936 enum ipr_sdt_state sdt_state;
938 struct ipr_misc_cbs *vpd_cbs;
939 dma_addr_t vpd_cbs_dma;
941 struct pci_pool *ipr_cmd_pool;
943 struct ipr_cmnd *reset_cmd;
945 char ipr_cmd_label[8];
946 #define IPR_CMD_LABEL "ipr_cmnd"
947 struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS];
948 u32 ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS];
952 struct ipr_ioarcb ioarcb;
953 struct ipr_ioasa ioasa;
954 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
955 struct list_head queue;
956 struct scsi_cmnd *scsi_cmd;
957 struct completion completion;
958 struct timer_list timer;
959 void (*done) (struct ipr_cmnd *);
960 int (*job_step) (struct ipr_cmnd *);
962 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
963 dma_addr_t sense_buffer_dma;
964 unsigned short dma_use_sg;
965 dma_addr_t dma_handle;
966 struct ipr_cmnd *sibling;
968 enum ipr_shutdown_type shutdown_type;
969 struct ipr_hostrcb *hostrcb;
970 unsigned long time_left;
971 unsigned long scratch;
972 struct ipr_resource_entry *res;
973 struct scsi_device *sdev;
976 struct ipr_ioa_cfg *ioa_cfg;
979 struct ipr_ses_table_entry {
981 char compare_product_id_byte[17];
982 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
985 struct ipr_dump_header {
987 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
990 u32 first_entry_offset;
992 #define IPR_DUMP_STATUS_SUCCESS 0
993 #define IPR_DUMP_STATUS_QUAL_SUCCESS 2
994 #define IPR_DUMP_STATUS_FAILED 0xffffffff
996 #define IPR_DUMP_OS_LINUX 0x4C4E5558
998 #define IPR_DUMP_DRIVER_NAME 0x49505232
999 }__attribute__((packed, aligned (4)));
1001 struct ipr_dump_entry_header {
1003 #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1008 #define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
1009 #define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
1011 #define IPR_DUMP_IOA_DUMP_ID 0x494F4131
1012 #define IPR_DUMP_LOCATION_ID 0x4C4F4341
1013 #define IPR_DUMP_TRACE_ID 0x54524143
1014 #define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
1015 #define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1016 #define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
1017 #define IPR_DUMP_PEND_OPS 0x414F5053
1019 }__attribute__((packed, aligned (4)));
1021 struct ipr_dump_location_entry {
1022 struct ipr_dump_entry_header hdr;
1023 u8 location[BUS_ID_SIZE];
1024 }__attribute__((packed));
1026 struct ipr_dump_trace_entry {
1027 struct ipr_dump_entry_header hdr;
1028 u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1029 }__attribute__((packed, aligned (4)));
1031 struct ipr_dump_version_entry {
1032 struct ipr_dump_entry_header hdr;
1033 u8 version[sizeof(IPR_DRIVER_VERSION)];
1036 struct ipr_dump_ioa_type_entry {
1037 struct ipr_dump_entry_header hdr;
1042 struct ipr_driver_dump {
1043 struct ipr_dump_header hdr;
1044 struct ipr_dump_version_entry version_entry;
1045 struct ipr_dump_location_entry location_entry;
1046 struct ipr_dump_ioa_type_entry ioa_type_entry;
1047 struct ipr_dump_trace_entry trace_entry;
1048 }__attribute__((packed));
1050 struct ipr_ioa_dump {
1051 struct ipr_dump_entry_header hdr;
1053 __be32 *ioa_data[IPR_MAX_NUM_DUMP_PAGES];
1055 u32 next_page_index;
1058 #define IPR_SDT_FMT2 2
1059 #define IPR_SDT_UNKNOWN 3
1060 }__attribute__((packed, aligned (4)));
1064 struct ipr_ioa_cfg *ioa_cfg;
1065 struct ipr_driver_dump driver_dump;
1066 struct ipr_ioa_dump ioa_dump;
1069 struct ipr_error_table_t {
1076 struct ipr_software_inq_lid_info {
1078 __be32 timestamp[3];
1079 }__attribute__((packed, aligned (4)));
1081 struct ipr_ucode_image_header {
1082 __be32 header_length;
1083 __be32 lid_table_offset;
1086 u8 minor_release[2];
1088 char eyecatcher[16];
1090 struct ipr_software_inq_lid_info lid[1];
1091 }__attribute__((packed, aligned (4)));
1096 #define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; }
1098 #ifdef CONFIG_SCSI_IPR_TRACE
1099 #define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1100 #define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1102 #define ipr_create_trace_file(kobj, attr) 0
1103 #define ipr_remove_trace_file(kobj, attr) do { } while(0)
1106 #ifdef CONFIG_SCSI_IPR_DUMP
1107 #define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1108 #define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1110 #define ipr_create_dump_file(kobj, attr) 0
1111 #define ipr_remove_dump_file(kobj, attr) do { } while(0)
1115 * Error logging macros
1117 #define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1118 #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1119 #define ipr_crit(...) printk(KERN_CRIT IPR_NAME ": "__VA_ARGS__)
1120 #define ipr_warn(...) printk(KERN_WARNING IPR_NAME": "__VA_ARGS__)
1121 #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1123 #define ipr_sdev_printk(level, sdev, fmt, args...) \
1124 sdev_printk(level, sdev, fmt, ## args)
1126 #define ipr_sdev_err(sdev, fmt, ...) \
1127 ipr_sdev_printk(KERN_ERR, sdev, fmt, ##__VA_ARGS__)
1129 #define ipr_sdev_info(sdev, fmt, ...) \
1130 ipr_sdev_printk(KERN_INFO, sdev, fmt, ##__VA_ARGS__)
1132 #define ipr_sdev_dbg(sdev, fmt, ...) \
1133 IPR_DBG_CMD(ipr_sdev_printk(KERN_INFO, sdev, fmt, ##__VA_ARGS__))
1135 #define ipr_res_printk(level, ioa_cfg, res, fmt, ...) \
1136 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, ioa_cfg->host->host_no, \
1137 res.bus, res.target, res.lun, ##__VA_ARGS__)
1139 #define ipr_res_err(ioa_cfg, res, fmt, ...) \
1140 ipr_res_printk(KERN_ERR, ioa_cfg, res, fmt, ##__VA_ARGS__)
1141 #define ipr_res_dbg(ioa_cfg, res, fmt, ...) \
1142 IPR_DBG_CMD(ipr_res_printk(KERN_INFO, ioa_cfg, res, fmt, ##__VA_ARGS__))
1144 #define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1146 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
1147 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
1149 ipr_err(fmt": %d:%d:%d:%d\n", \
1150 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
1151 (res).bus, (res).target, (res).lun); \
1155 #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
1156 __FILE__, __FUNCTION__, __LINE__)
1158 #define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __FUNCTION__))
1159 #define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __FUNCTION__))
1161 #define ipr_err_separator \
1162 ipr_err("----------------------------------------------------------\n")
1170 * ipr_is_ioa_resource - Determine if a resource is the IOA
1171 * @res: resource entry struct
1174 * 1 if IOA / 0 if not IOA
1176 static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1178 return (res->cfgte.flags & IPR_IS_IOA_RESOURCE) ? 1 : 0;
1182 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1183 * @res: resource entry struct
1186 * 1 if AF DASD / 0 if not AF DASD
1188 static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1190 if (IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data) &&
1191 !ipr_is_ioa_resource(res) &&
1192 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_AF_DASD)
1199 * ipr_is_vset_device - Determine if a resource is a VSET
1200 * @res: resource entry struct
1203 * 1 if VSET / 0 if not VSET
1205 static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1207 if (IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data) &&
1208 !ipr_is_ioa_resource(res) &&
1209 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_VOLUME_SET)
1216 * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1217 * @res: resource entry struct
1220 * 1 if GSCSI / 0 if not GSCSI
1222 static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1224 if (!ipr_is_ioa_resource(res) &&
1225 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_GENERIC_SCSI)
1232 * ipr_is_device - Determine if resource address is that of a device
1233 * @res_addr: resource address struct
1236 * 1 if AF / 0 if not AF
1238 static inline int ipr_is_device(struct ipr_res_addr *res_addr)
1240 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1241 (res_addr->target < IPR_MAX_NUM_TARGETS_PER_BUS))
1248 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1249 * @sdt_word: SDT address
1252 * 1 if format 2 / 0 if not
1254 static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1256 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1259 case IPR_SDT_FMT2_BAR0_SEL:
1260 case IPR_SDT_FMT2_BAR1_SEL:
1261 case IPR_SDT_FMT2_BAR2_SEL:
1262 case IPR_SDT_FMT2_BAR3_SEL:
1263 case IPR_SDT_FMT2_BAR4_SEL:
1264 case IPR_SDT_FMT2_BAR5_SEL:
1265 case IPR_SDT_FMT2_EXP_ROM_SEL: