2 * ata_piix.c - Intel PATA/SATA controllers
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
13 * Copyright header from piix.c:
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
38 * Hardware documentation available at http://developer.intel.com/
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below.going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
95 #define DRV_NAME "ata_piix"
96 #define DRV_VERSION "1.05"
99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
100 ICH5_PMR = 0x90, /* port mapping register */
101 ICH5_PCS = 0x92, /* port control and status */
102 PIIX_SCC = 0x0A, /* sub-class code register */
104 PIIX_FLAG_IGN_PRESENT = (1 << 25), /* ignore PCS present bits */
105 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
106 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
107 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
108 PIIX_FLAG_COMBINED = (1 << 29), /* combined mode possible */
109 /* ICH6/7 use different scheme for map value */
110 PIIX_FLAG_COMBINED_ICH6 = PIIX_FLAG_COMBINED | (1 << 30),
112 /* combined mode. if set, PATA is channel 0.
113 * if clear, PATA is channel 1.
115 PIIX_COMB_PATA_P0 = (1 << 1),
116 PIIX_COMB = (1 << 2), /* combined mode enabled? */
118 PIIX_PORT_ENABLED = (1 << 0),
119 PIIX_PORT_PRESENT = (1 << 4),
121 PIIX_80C_PRI = (1 << 5) | (1 << 4),
122 PIIX_80C_SEC = (1 << 7) | (1 << 6),
133 PIIX_AHCI_DEVICE = 6,
136 static int piix_init_one (struct pci_dev *pdev,
137 const struct pci_device_id *ent);
139 static int piix_pata_probe_reset(struct ata_port *ap, unsigned int *classes);
140 static int piix_sata_probe_reset(struct ata_port *ap, unsigned int *classes);
141 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
142 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
144 static unsigned int in_module_init = 1;
146 static const struct pci_device_id piix_pci_tbl[] = {
147 #ifdef ATA_ENABLE_PATA
148 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata },
149 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
150 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
153 /* NOTE: The following PCI ids must be kept in sync with the
154 * list in drivers/pci/quirks.c.
158 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
160 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
161 /* 6300ESB (ICH5 variant with broken PCS present bits) */
162 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
163 /* 6300ESB pretending RAID */
164 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
165 /* 82801FB/FW (ICH6/ICH6W) */
166 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
167 /* 82801FR/FRW (ICH6R/ICH6RW) */
168 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
169 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
170 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
171 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
172 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
173 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
174 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
175 /* Enterprise Southbridge 2 (where's the datasheet?) */
176 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
177 /* SATA Controller 1 IDE (ICH8, no datasheet yet) */
178 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
179 /* SATA Controller 2 IDE (ICH8, ditto) */
180 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
181 /* Mobile SATA Controller IDE (ICH8M, ditto) */
182 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
184 { } /* terminate list */
187 static struct pci_driver piix_pci_driver = {
189 .id_table = piix_pci_tbl,
190 .probe = piix_init_one,
191 .remove = ata_pci_remove_one,
192 .suspend = ata_pci_device_suspend,
193 .resume = ata_pci_device_resume,
196 static struct scsi_host_template piix_sht = {
197 .module = THIS_MODULE,
199 .ioctl = ata_scsi_ioctl,
200 .queuecommand = ata_scsi_queuecmd,
201 .eh_timed_out = ata_scsi_timed_out,
202 .eh_strategy_handler = ata_scsi_error,
203 .can_queue = ATA_DEF_QUEUE,
204 .this_id = ATA_SHT_THIS_ID,
205 .sg_tablesize = LIBATA_MAX_PRD,
206 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
207 .emulated = ATA_SHT_EMULATED,
208 .use_clustering = ATA_SHT_USE_CLUSTERING,
209 .proc_name = DRV_NAME,
210 .dma_boundary = ATA_DMA_BOUNDARY,
211 .slave_configure = ata_scsi_slave_config,
212 .bios_param = ata_std_bios_param,
213 .resume = ata_scsi_device_resume,
214 .suspend = ata_scsi_device_suspend,
217 static const struct ata_port_operations piix_pata_ops = {
218 .port_disable = ata_port_disable,
219 .set_piomode = piix_set_piomode,
220 .set_dmamode = piix_set_dmamode,
222 .tf_load = ata_tf_load,
223 .tf_read = ata_tf_read,
224 .check_status = ata_check_status,
225 .exec_command = ata_exec_command,
226 .dev_select = ata_std_dev_select,
228 .probe_reset = piix_pata_probe_reset,
230 .bmdma_setup = ata_bmdma_setup,
231 .bmdma_start = ata_bmdma_start,
232 .bmdma_stop = ata_bmdma_stop,
233 .bmdma_status = ata_bmdma_status,
234 .qc_prep = ata_qc_prep,
235 .qc_issue = ata_qc_issue_prot,
237 .eng_timeout = ata_eng_timeout,
239 .irq_handler = ata_interrupt,
240 .irq_clear = ata_bmdma_irq_clear,
242 .port_start = ata_port_start,
243 .port_stop = ata_port_stop,
244 .host_stop = ata_host_stop,
247 static const struct ata_port_operations piix_sata_ops = {
248 .port_disable = ata_port_disable,
250 .tf_load = ata_tf_load,
251 .tf_read = ata_tf_read,
252 .check_status = ata_check_status,
253 .exec_command = ata_exec_command,
254 .dev_select = ata_std_dev_select,
256 .probe_reset = piix_sata_probe_reset,
258 .bmdma_setup = ata_bmdma_setup,
259 .bmdma_start = ata_bmdma_start,
260 .bmdma_stop = ata_bmdma_stop,
261 .bmdma_status = ata_bmdma_status,
262 .qc_prep = ata_qc_prep,
263 .qc_issue = ata_qc_issue_prot,
265 .eng_timeout = ata_eng_timeout,
267 .irq_handler = ata_interrupt,
268 .irq_clear = ata_bmdma_irq_clear,
270 .port_start = ata_port_start,
271 .port_stop = ata_port_stop,
272 .host_stop = ata_host_stop,
275 static struct ata_port_info piix_port_info[] = {
279 .host_flags = ATA_FLAG_SLAVE_POSS,
280 .pio_mask = 0x1f, /* pio0-4 */
282 .mwdma_mask = 0x06, /* mwdma1-2 */
284 .mwdma_mask = 0x00, /* mwdma broken */
286 .udma_mask = ATA_UDMA_MASK_40C,
287 .port_ops = &piix_pata_ops,
293 .host_flags = ATA_FLAG_SLAVE_POSS | PIIX_FLAG_CHECKINTR,
294 .pio_mask = 0x1f, /* pio0-4 */
296 .mwdma_mask = 0x06, /* mwdma1-2 */
298 .mwdma_mask = 0x00, /* mwdma broken */
300 .udma_mask = 0x3f, /* udma0-5 */
301 .port_ops = &piix_pata_ops,
307 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED |
309 .pio_mask = 0x1f, /* pio0-4 */
310 .mwdma_mask = 0x07, /* mwdma0-2 */
311 .udma_mask = 0x7f, /* udma0-6 */
312 .port_ops = &piix_sata_ops,
318 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED |
319 PIIX_FLAG_CHECKINTR | PIIX_FLAG_IGN_PRESENT,
320 .pio_mask = 0x1f, /* pio0-4 */
321 .mwdma_mask = 0x07, /* mwdma0-2 */
322 .udma_mask = 0x7f, /* udma0-6 */
323 .port_ops = &piix_sata_ops,
329 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
330 PIIX_FLAG_CHECKINTR | ATA_FLAG_SLAVE_POSS |
332 .pio_mask = 0x1f, /* pio0-4 */
333 .mwdma_mask = 0x07, /* mwdma0-2 */
334 .udma_mask = 0x7f, /* udma0-6 */
335 .port_ops = &piix_sata_ops,
341 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
342 PIIX_FLAG_CHECKINTR | ATA_FLAG_SLAVE_POSS |
343 PIIX_FLAG_SCR | PIIX_FLAG_AHCI,
344 .pio_mask = 0x1f, /* pio0-4 */
345 .mwdma_mask = 0x07, /* mwdma0-2 */
346 .udma_mask = 0x7f, /* udma0-6 */
347 .port_ops = &piix_sata_ops,
350 /* ich6m_sata_ahci */
353 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
354 PIIX_FLAG_CHECKINTR | ATA_FLAG_SLAVE_POSS |
355 PIIX_FLAG_SCR | PIIX_FLAG_AHCI,
356 .pio_mask = 0x1f, /* pio0-4 */
357 .mwdma_mask = 0x07, /* mwdma0-2 */
358 .udma_mask = 0x7f, /* udma0-6 */
359 .port_ops = &piix_sata_ops,
363 static struct pci_bits piix_enable_bits[] = {
364 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
365 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
368 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
369 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
370 MODULE_LICENSE("GPL");
371 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
372 MODULE_VERSION(DRV_VERSION);
375 * piix_pata_cbl_detect - Probe host controller cable detect info
376 * @ap: Port for which cable detect info is desired
378 * Read 80c cable indicator from ATA PCI device's PCI config
379 * register. This register is normally set by firmware (BIOS).
382 * None (inherited from caller).
384 static void piix_pata_cbl_detect(struct ata_port *ap)
386 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
389 /* no 80c support in host controller? */
390 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
393 /* check BIOS cable detect results */
394 mask = ap->hard_port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
395 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
396 if ((tmp & mask) == 0)
399 ap->cbl = ATA_CBL_PATA80;
403 ap->cbl = ATA_CBL_PATA40;
404 ap->udma_mask &= ATA_UDMA_MASK_40C;
408 * piix_pata_probeinit - probeinit for PATA host controller
411 * Probeinit including cable detection.
414 * None (inherited from caller).
416 static void piix_pata_probeinit(struct ata_port *ap)
418 piix_pata_cbl_detect(ap);
419 ata_std_probeinit(ap);
423 * piix_pata_probe_reset - Perform reset on PATA port and classify
425 * @classes: Resulting classes of attached devices
427 * Reset PATA phy and classify attached devices.
430 * None (inherited from caller).
432 static int piix_pata_probe_reset(struct ata_port *ap, unsigned int *classes)
434 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
436 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->hard_port_no])) {
437 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
441 return ata_drive_probe_reset(ap, piix_pata_probeinit,
442 ata_std_softreset, NULL,
443 ata_std_postreset, classes);
447 * piix_sata_probe - Probe PCI device for present SATA devices
448 * @ap: Port associated with the PCI device we wish to probe
450 * Reads SATA PCI device's PCI config register Port Configuration
451 * and Status (PCS) to determine port and device availability.
454 * None (inherited from caller).
457 * Non-zero if port is enabled, it may or may not have a device
458 * attached in that case (PRESENT bit would only be set if BIOS probe
459 * was done). Zero is returned if port is disabled.
461 static int piix_sata_probe (struct ata_port *ap)
463 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
464 int combined = (ap->flags & ATA_FLAG_SLAVE_POSS);
465 int orig_mask, mask, i;
468 pci_read_config_byte(pdev, ICH5_PCS, &pcs);
469 orig_mask = (int) pcs & 0xff;
471 /* TODO: this is vaguely wrong for ICH6 combined mode,
472 * where only two of the four SATA ports are mapped
473 * onto a single ATA channel. It is also vaguely inaccurate
474 * for ICH5, which has only two ports. However, this is ok,
475 * as further device presence detection code will handle
476 * any false positives produced here.
479 for (i = 0; i < 4; i++) {
480 mask = (PIIX_PORT_ENABLED << i);
482 if ((orig_mask & mask) == mask)
483 if (combined || (i == ap->hard_port_no))
491 * piix_sata_probe_reset - Perform reset on SATA port and classify
493 * @classes: Resulting classes of attached devices
495 * Reset SATA phy and classify attached devices.
498 * None (inherited from caller).
500 static int piix_sata_probe_reset(struct ata_port *ap, unsigned int *classes)
502 if (!piix_sata_probe(ap)) {
503 printk(KERN_INFO "ata%u: SATA port has no device.\n", ap->id);
507 return ata_drive_probe_reset(ap, ata_std_probeinit,
508 ata_std_softreset, NULL,
509 ata_std_postreset, classes);
513 * piix_set_piomode - Initialize host controller PATA PIO timings
514 * @ap: Port whose timings we are configuring
517 * Set PIO mode for device, in host controller PCI config space.
520 * None (inherited from caller).
523 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
525 unsigned int pio = adev->pio_mode - XFER_PIO_0;
526 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
527 unsigned int is_slave = (adev->devno != 0);
528 unsigned int master_port= ap->hard_port_no ? 0x42 : 0x40;
529 unsigned int slave_port = 0x44;
533 static const /* ISP RTC */
534 u8 timings[][2] = { { 0, 0 },
540 pci_read_config_word(dev, master_port, &master_data);
542 master_data |= 0x4000;
543 /* enable PPE, IE and TIME */
544 master_data |= 0x0070;
545 pci_read_config_byte(dev, slave_port, &slave_data);
546 slave_data &= (ap->hard_port_no ? 0x0f : 0xf0);
548 (timings[pio][0] << 2) |
549 (timings[pio][1] << (ap->hard_port_no ? 4 : 0));
551 master_data &= 0xccf8;
552 /* enable PPE, IE and TIME */
553 master_data |= 0x0007;
555 (timings[pio][0] << 12) |
556 (timings[pio][1] << 8);
558 pci_write_config_word(dev, master_port, master_data);
560 pci_write_config_byte(dev, slave_port, slave_data);
564 * piix_set_dmamode - Initialize host controller PATA PIO timings
565 * @ap: Port whose timings we are configuring
567 * @udma: udma mode, 0 - 6
569 * Set UDMA mode for device, in host controller PCI config space.
572 * None (inherited from caller).
575 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
577 unsigned int udma = adev->dma_mode; /* FIXME: MWDMA too */
578 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
579 u8 maslave = ap->hard_port_no ? 0x42 : 0x40;
581 unsigned int drive_dn = (ap->hard_port_no ? 2 : 0) + adev->devno;
582 int a_speed = 3 << (drive_dn * 4);
583 int u_flag = 1 << drive_dn;
584 int v_flag = 0x01 << drive_dn;
585 int w_flag = 0x10 << drive_dn;
589 u8 reg48, reg54, reg55;
591 pci_read_config_word(dev, maslave, ®4042);
592 DPRINTK("reg4042 = 0x%04x\n", reg4042);
593 sitre = (reg4042 & 0x4000) ? 1 : 0;
594 pci_read_config_byte(dev, 0x48, ®48);
595 pci_read_config_word(dev, 0x4a, ®4a);
596 pci_read_config_byte(dev, 0x54, ®54);
597 pci_read_config_byte(dev, 0x55, ®55);
601 case XFER_UDMA_2: u_speed = 2 << (drive_dn * 4); break;
605 case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break;
606 case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break;
608 case XFER_MW_DMA_1: break;
614 if (speed >= XFER_UDMA_0) {
615 if (!(reg48 & u_flag))
616 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
617 if (speed == XFER_UDMA_5) {
618 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
620 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
622 if ((reg4a & a_speed) != u_speed)
623 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
624 if (speed > XFER_UDMA_2) {
625 if (!(reg54 & v_flag))
626 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
628 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
631 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
633 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
635 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
637 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
641 #define AHCI_PCI_BAR 5
642 #define AHCI_GLOBAL_CTL 0x04
643 #define AHCI_ENABLE (1 << 31)
644 static int piix_disable_ahci(struct pci_dev *pdev)
650 /* BUG: pci_enable_device has not yet been called. This
651 * works because this device is usually set up by BIOS.
654 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
655 !pci_resource_len(pdev, AHCI_PCI_BAR))
658 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
662 tmp = readl(mmio + AHCI_GLOBAL_CTL);
663 if (tmp & AHCI_ENABLE) {
665 writel(tmp, mmio + AHCI_GLOBAL_CTL);
667 tmp = readl(mmio + AHCI_GLOBAL_CTL);
668 if (tmp & AHCI_ENABLE)
672 pci_iounmap(pdev, mmio);
677 * piix_check_450nx_errata - Check for problem 450NX setup
678 * @ata_dev: the PCI device to check
680 * Check for the present of 450NX errata #19 and errata #25. If
681 * they are found return an error code so we can turn off DMA
684 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
686 struct pci_dev *pdev = NULL;
691 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
693 /* Look for 450NX PXB. Check for problem configurations
694 A PCI quirk checks bit 6 already */
695 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
696 pci_read_config_word(pdev, 0x41, &cfg);
697 /* Only on the original revision: IDE DMA can hang */
700 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
701 else if(cfg & (1<<14) && rev < 5)
705 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
707 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
712 * piix_init_one - Register PIIX ATA PCI device with kernel services
713 * @pdev: PCI device to register
714 * @ent: Entry in piix_pci_tbl matching with @pdev
716 * Called from kernel PCI layer. We probe for combined mode (sigh),
717 * and then hand over control to libata, for it to do the rest.
720 * Inherited from PCI layer (may sleep).
723 * Zero on success, or -ERRNO value.
726 static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
728 static int printed_version;
729 struct ata_port_info *port_info[2];
730 unsigned int combined = 0;
731 unsigned int pata_chan = 0, sata_chan = 0;
732 unsigned long host_flags;
734 if (!printed_version++)
735 dev_printk(KERN_DEBUG, &pdev->dev,
736 "version " DRV_VERSION "\n");
738 /* no hotplugging support (FIXME) */
742 port_info[0] = &piix_port_info[ent->driver_data];
743 port_info[1] = &piix_port_info[ent->driver_data];
745 host_flags = port_info[0]->host_flags;
747 if (host_flags & PIIX_FLAG_AHCI) {
749 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
750 if (tmp == PIIX_AHCI_DEVICE) {
751 int rc = piix_disable_ahci(pdev);
757 if (host_flags & PIIX_FLAG_COMBINED) {
759 pci_read_config_byte(pdev, ICH5_PMR, &tmp);
761 if (host_flags & PIIX_FLAG_COMBINED_ICH6) {
774 dev_printk(KERN_WARNING, &pdev->dev,
775 "invalid MAP value %u\n", tmp);
779 if (tmp & PIIX_COMB) {
781 if (tmp & PIIX_COMB_PATA_P0)
789 /* On ICH5, some BIOSen disable the interrupt using the
790 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
791 * On ICH6, this bit has the same effect, but only when
792 * MSI is disabled (and it is disabled, as we don't use
793 * message-signalled interrupts currently).
795 if (host_flags & PIIX_FLAG_CHECKINTR)
799 port_info[sata_chan] = &piix_port_info[ent->driver_data];
800 port_info[sata_chan]->host_flags |= ATA_FLAG_SLAVE_POSS;
801 port_info[pata_chan] = &piix_port_info[ich5_pata];
803 dev_printk(KERN_WARNING, &pdev->dev,
804 "combined mode detected (p=%u, s=%u)\n",
805 pata_chan, sata_chan);
807 if (piix_check_450nx_errata(pdev)) {
808 /* This writes into the master table but it does not
809 really matter for this errata as we will apply it to
810 all the PIIX devices on the board */
811 port_info[0]->mwdma_mask = 0;
812 port_info[0]->udma_mask = 0;
813 port_info[1]->mwdma_mask = 0;
814 port_info[1]->udma_mask = 0;
816 return ata_pci_init_one(pdev, port_info, 2);
819 static int __init piix_init(void)
823 DPRINTK("pci_module_init\n");
824 rc = pci_module_init(&piix_pci_driver);
834 static void __exit piix_exit(void)
836 pci_unregister_driver(&piix_pci_driver);
839 module_init(piix_init);
840 module_exit(piix_exit);