2 * ata_piix.c - Intel PATA/SATA controllers
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
13 * Copyright header from piix.c:
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
38 * Hardware documentation available at http://developer.intel.com/
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below.going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
95 #define DRV_NAME "ata_piix"
96 #define DRV_VERSION "1.10"
99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
100 ICH5_PMR = 0x90, /* port mapping register */
101 ICH5_PCS = 0x92, /* port control and status */
102 PIIX_SCC = 0x0A, /* sub-class code register */
104 PIIX_FLAG_IGNORE_PCS = (1 << 25), /* ignore PCS present bits */
105 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
106 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
107 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
108 PIIX_FLAG_COMBINED = (1 << 29), /* combined mode possible */
109 /* ICH6/7 use different scheme for map value */
110 PIIX_FLAG_COMBINED_ICH6 = PIIX_FLAG_COMBINED | (1 << 30),
112 /* combined mode. if set, PATA is channel 0.
113 * if clear, PATA is channel 1.
115 PIIX_PORT_ENABLED = (1 << 0),
116 PIIX_PORT_PRESENT = (1 << 4),
118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
130 /* constants for mapping table */
136 NA = -2, /* not avaliable */
137 RV = -3, /* reserved */
139 PIIX_AHCI_DEVICE = 6,
147 static int piix_init_one (struct pci_dev *pdev,
148 const struct pci_device_id *ent);
150 static int piix_pata_probe_reset(struct ata_port *ap, unsigned int *classes);
151 static int piix_sata_probe_reset(struct ata_port *ap, unsigned int *classes);
152 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
153 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
155 static unsigned int in_module_init = 1;
157 static const struct pci_device_id piix_pci_tbl[] = {
158 #ifdef ATA_ENABLE_PATA
159 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata },
160 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
161 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
162 { 0x8086, 0x27df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
165 /* NOTE: The following PCI ids must be kept in sync with the
166 * list in drivers/pci/quirks.c.
170 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
172 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
173 /* 6300ESB (ICH5 variant with broken PCS present bits) */
174 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
175 /* 6300ESB pretending RAID */
176 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
177 /* 82801FB/FW (ICH6/ICH6W) */
178 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
179 /* 82801FR/FRW (ICH6R/ICH6RW) */
180 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
181 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
182 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
183 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
184 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
185 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
186 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
187 /* Enterprise Southbridge 2 (where's the datasheet?) */
188 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
189 /* SATA Controller 1 IDE (ICH8, no datasheet yet) */
190 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
191 /* SATA Controller 2 IDE (ICH8, ditto) */
192 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
193 /* Mobile SATA Controller IDE (ICH8M, ditto) */
194 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
196 { } /* terminate list */
199 static struct pci_driver piix_pci_driver = {
201 .id_table = piix_pci_tbl,
202 .probe = piix_init_one,
203 .remove = ata_pci_remove_one,
204 .suspend = ata_pci_device_suspend,
205 .resume = ata_pci_device_resume,
208 static struct scsi_host_template piix_sht = {
209 .module = THIS_MODULE,
211 .ioctl = ata_scsi_ioctl,
212 .queuecommand = ata_scsi_queuecmd,
213 .can_queue = ATA_DEF_QUEUE,
214 .this_id = ATA_SHT_THIS_ID,
215 .sg_tablesize = LIBATA_MAX_PRD,
216 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
217 .emulated = ATA_SHT_EMULATED,
218 .use_clustering = ATA_SHT_USE_CLUSTERING,
219 .proc_name = DRV_NAME,
220 .dma_boundary = ATA_DMA_BOUNDARY,
221 .slave_configure = ata_scsi_slave_config,
222 .bios_param = ata_std_bios_param,
223 .resume = ata_scsi_device_resume,
224 .suspend = ata_scsi_device_suspend,
227 static const struct ata_port_operations piix_pata_ops = {
228 .port_disable = ata_port_disable,
229 .set_piomode = piix_set_piomode,
230 .set_dmamode = piix_set_dmamode,
231 .mode_filter = ata_pci_default_filter,
233 .tf_load = ata_tf_load,
234 .tf_read = ata_tf_read,
235 .check_status = ata_check_status,
236 .exec_command = ata_exec_command,
237 .dev_select = ata_std_dev_select,
239 .probe_reset = piix_pata_probe_reset,
241 .bmdma_setup = ata_bmdma_setup,
242 .bmdma_start = ata_bmdma_start,
243 .bmdma_stop = ata_bmdma_stop,
244 .bmdma_status = ata_bmdma_status,
245 .qc_prep = ata_qc_prep,
246 .qc_issue = ata_qc_issue_prot,
247 .data_xfer = ata_pio_data_xfer,
249 .freeze = ata_bmdma_freeze,
250 .thaw = ata_bmdma_thaw,
251 .error_handler = ata_bmdma_error_handler,
252 .post_internal_cmd = ata_bmdma_post_internal_cmd,
254 .irq_handler = ata_interrupt,
255 .irq_clear = ata_bmdma_irq_clear,
257 .port_start = ata_port_start,
258 .port_stop = ata_port_stop,
259 .host_stop = ata_host_stop,
262 static const struct ata_port_operations piix_sata_ops = {
263 .port_disable = ata_port_disable,
265 .tf_load = ata_tf_load,
266 .tf_read = ata_tf_read,
267 .check_status = ata_check_status,
268 .exec_command = ata_exec_command,
269 .dev_select = ata_std_dev_select,
271 .probe_reset = piix_sata_probe_reset,
273 .bmdma_setup = ata_bmdma_setup,
274 .bmdma_start = ata_bmdma_start,
275 .bmdma_stop = ata_bmdma_stop,
276 .bmdma_status = ata_bmdma_status,
277 .qc_prep = ata_qc_prep,
278 .qc_issue = ata_qc_issue_prot,
279 .data_xfer = ata_pio_data_xfer,
281 .freeze = ata_bmdma_freeze,
282 .thaw = ata_bmdma_thaw,
283 .error_handler = ata_bmdma_error_handler,
284 .post_internal_cmd = ata_bmdma_post_internal_cmd,
286 .irq_handler = ata_interrupt,
287 .irq_clear = ata_bmdma_irq_clear,
289 .port_start = ata_port_start,
290 .port_stop = ata_port_stop,
291 .host_stop = ata_host_stop,
294 static struct piix_map_db ich5_map_db = {
297 /* PM PS SM SS MAP */
298 { P0, NA, P1, NA }, /* 000b */
299 { P1, NA, P0, NA }, /* 001b */
302 { P0, P1, IDE, IDE }, /* 100b */
303 { P1, P0, IDE, IDE }, /* 101b */
304 { IDE, IDE, P0, P1 }, /* 110b */
305 { IDE, IDE, P1, P0 }, /* 111b */
309 static struct piix_map_db ich6_map_db = {
312 /* PM PS SM SS MAP */
313 { P0, P2, P1, P3 }, /* 00b */
314 { IDE, IDE, P1, P3 }, /* 01b */
315 { P0, P2, IDE, IDE }, /* 10b */
320 static struct piix_map_db ich6m_map_db = {
323 /* PM PS SM SS MAP */
324 { P0, P2, RV, RV }, /* 00b */
326 { P0, P2, IDE, IDE }, /* 10b */
331 static struct ata_port_info piix_port_info[] = {
335 .host_flags = ATA_FLAG_SLAVE_POSS,
336 .pio_mask = 0x1f, /* pio0-4 */
338 .mwdma_mask = 0x06, /* mwdma1-2 */
340 .mwdma_mask = 0x00, /* mwdma broken */
342 .udma_mask = ATA_UDMA_MASK_40C,
343 .port_ops = &piix_pata_ops,
349 .host_flags = ATA_FLAG_SLAVE_POSS | PIIX_FLAG_CHECKINTR,
350 .pio_mask = 0x1f, /* pio0-4 */
352 .mwdma_mask = 0x06, /* mwdma1-2 */
354 .mwdma_mask = 0x00, /* mwdma broken */
356 .udma_mask = 0x3f, /* udma0-5 */
357 .port_ops = &piix_pata_ops,
363 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED |
365 .pio_mask = 0x1f, /* pio0-4 */
366 .mwdma_mask = 0x07, /* mwdma0-2 */
367 .udma_mask = 0x7f, /* udma0-6 */
368 .port_ops = &piix_sata_ops,
369 .private_data = &ich5_map_db,
375 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED |
376 PIIX_FLAG_CHECKINTR | PIIX_FLAG_IGNORE_PCS,
377 .pio_mask = 0x1f, /* pio0-4 */
378 .mwdma_mask = 0x07, /* mwdma0-2 */
379 .udma_mask = 0x7f, /* udma0-6 */
380 .port_ops = &piix_sata_ops,
381 .private_data = &ich5_map_db,
387 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
388 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR,
389 .pio_mask = 0x1f, /* pio0-4 */
390 .mwdma_mask = 0x07, /* mwdma0-2 */
391 .udma_mask = 0x7f, /* udma0-6 */
392 .port_ops = &piix_sata_ops,
393 .private_data = &ich6_map_db,
399 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
400 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
402 .pio_mask = 0x1f, /* pio0-4 */
403 .mwdma_mask = 0x07, /* mwdma0-2 */
404 .udma_mask = 0x7f, /* udma0-6 */
405 .port_ops = &piix_sata_ops,
406 .private_data = &ich6_map_db,
409 /* ich6m_sata_ahci */
412 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
413 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
415 .pio_mask = 0x1f, /* pio0-4 */
416 .mwdma_mask = 0x07, /* mwdma0-2 */
417 .udma_mask = 0x7f, /* udma0-6 */
418 .port_ops = &piix_sata_ops,
419 .private_data = &ich6m_map_db,
423 static struct pci_bits piix_enable_bits[] = {
424 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
425 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
428 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
429 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
430 MODULE_LICENSE("GPL");
431 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
432 MODULE_VERSION(DRV_VERSION);
435 * piix_pata_cbl_detect - Probe host controller cable detect info
436 * @ap: Port for which cable detect info is desired
438 * Read 80c cable indicator from ATA PCI device's PCI config
439 * register. This register is normally set by firmware (BIOS).
442 * None (inherited from caller).
444 static void piix_pata_cbl_detect(struct ata_port *ap)
446 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
449 /* no 80c support in host controller? */
450 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
453 /* check BIOS cable detect results */
454 mask = ap->hard_port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
455 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
456 if ((tmp & mask) == 0)
459 ap->cbl = ATA_CBL_PATA80;
463 ap->cbl = ATA_CBL_PATA40;
464 ap->udma_mask &= ATA_UDMA_MASK_40C;
468 * piix_pata_probeinit - probeinit for PATA host controller
471 * Probeinit including cable detection.
474 * None (inherited from caller).
476 static void piix_pata_probeinit(struct ata_port *ap)
478 piix_pata_cbl_detect(ap);
479 ata_std_probeinit(ap);
483 * piix_pata_probe_reset - Perform reset on PATA port and classify
485 * @classes: Resulting classes of attached devices
487 * Reset PATA phy and classify attached devices.
490 * None (inherited from caller).
492 static int piix_pata_probe_reset(struct ata_port *ap, unsigned int *classes)
494 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
496 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->hard_port_no])) {
497 ata_port_printk(ap, KERN_INFO, "port disabled. ignoring.\n");
501 return ata_drive_probe_reset(ap, piix_pata_probeinit,
502 ata_std_softreset, NULL,
503 ata_std_postreset, classes);
507 * piix_sata_probe - Probe PCI device for present SATA devices
508 * @ap: Port associated with the PCI device we wish to probe
510 * Reads and configures SATA PCI device's PCI config register
511 * Port Configuration and Status (PCS) to determine port and
512 * device availability.
515 * None (inherited from caller).
518 * Mask of avaliable devices on the port.
520 static unsigned int piix_sata_probe (struct ata_port *ap)
522 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
523 const unsigned int *map = ap->host_set->private_data;
524 int base = 2 * ap->hard_port_no;
525 unsigned int present_mask = 0;
529 pci_read_config_byte(pdev, ICH5_PCS, &pcs);
530 DPRINTK("ata%u: ENTER, pcs=0x%x base=%d\n", ap->id, pcs, base);
532 /* enable all ports on this ap and wait for them to settle */
533 for (i = 0; i < 2; i++) {
534 port = map[base + i];
539 pci_write_config_byte(pdev, ICH5_PCS, pcs);
542 /* let's see which devices are present */
543 pci_read_config_byte(pdev, ICH5_PCS, &pcs);
545 for (i = 0; i < 2; i++) {
546 port = map[base + i];
549 if (ap->flags & PIIX_FLAG_IGNORE_PCS || pcs & 1 << (4 + port))
550 present_mask |= 1 << i;
555 /* disable offline ports on non-AHCI controllers */
556 if (!(ap->flags & PIIX_FLAG_AHCI))
557 pci_write_config_byte(pdev, ICH5_PCS, pcs);
559 DPRINTK("ata%u: LEAVE, pcs=0x%x present_mask=0x%x\n",
560 ap->id, pcs, present_mask);
566 * piix_sata_probe_reset - Perform reset on SATA port and classify
568 * @classes: Resulting classes of attached devices
570 * Reset SATA phy and classify attached devices.
573 * None (inherited from caller).
575 static int piix_sata_probe_reset(struct ata_port *ap, unsigned int *classes)
577 if (!piix_sata_probe(ap)) {
578 ata_port_printk(ap, KERN_INFO, "SATA port has no device.\n");
582 return ata_drive_probe_reset(ap, ata_std_probeinit,
583 ata_std_softreset, NULL,
584 ata_std_postreset, classes);
588 * piix_set_piomode - Initialize host controller PATA PIO timings
589 * @ap: Port whose timings we are configuring
592 * Set PIO mode for device, in host controller PCI config space.
595 * None (inherited from caller).
598 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
600 unsigned int pio = adev->pio_mode - XFER_PIO_0;
601 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
602 unsigned int is_slave = (adev->devno != 0);
603 unsigned int master_port= ap->hard_port_no ? 0x42 : 0x40;
604 unsigned int slave_port = 0x44;
608 static const /* ISP RTC */
609 u8 timings[][2] = { { 0, 0 },
615 pci_read_config_word(dev, master_port, &master_data);
617 master_data |= 0x4000;
618 /* enable PPE, IE and TIME */
619 master_data |= 0x0070;
620 pci_read_config_byte(dev, slave_port, &slave_data);
621 slave_data &= (ap->hard_port_no ? 0x0f : 0xf0);
623 (timings[pio][0] << 2) |
624 (timings[pio][1] << (ap->hard_port_no ? 4 : 0));
626 master_data &= 0xccf8;
627 /* enable PPE, IE and TIME */
628 master_data |= 0x0007;
630 (timings[pio][0] << 12) |
631 (timings[pio][1] << 8);
633 pci_write_config_word(dev, master_port, master_data);
635 pci_write_config_byte(dev, slave_port, slave_data);
639 * piix_set_dmamode - Initialize host controller PATA PIO timings
640 * @ap: Port whose timings we are configuring
642 * @udma: udma mode, 0 - 6
644 * Set UDMA mode for device, in host controller PCI config space.
647 * None (inherited from caller).
650 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
652 unsigned int udma = adev->dma_mode; /* FIXME: MWDMA too */
653 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
654 u8 maslave = ap->hard_port_no ? 0x42 : 0x40;
656 unsigned int drive_dn = (ap->hard_port_no ? 2 : 0) + adev->devno;
657 int a_speed = 3 << (drive_dn * 4);
658 int u_flag = 1 << drive_dn;
659 int v_flag = 0x01 << drive_dn;
660 int w_flag = 0x10 << drive_dn;
664 u8 reg48, reg54, reg55;
666 pci_read_config_word(dev, maslave, ®4042);
667 DPRINTK("reg4042 = 0x%04x\n", reg4042);
668 sitre = (reg4042 & 0x4000) ? 1 : 0;
669 pci_read_config_byte(dev, 0x48, ®48);
670 pci_read_config_word(dev, 0x4a, ®4a);
671 pci_read_config_byte(dev, 0x54, ®54);
672 pci_read_config_byte(dev, 0x55, ®55);
676 case XFER_UDMA_2: u_speed = 2 << (drive_dn * 4); break;
680 case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break;
681 case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break;
683 case XFER_MW_DMA_1: break;
689 if (speed >= XFER_UDMA_0) {
690 if (!(reg48 & u_flag))
691 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
692 if (speed == XFER_UDMA_5) {
693 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
695 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
697 if ((reg4a & a_speed) != u_speed)
698 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
699 if (speed > XFER_UDMA_2) {
700 if (!(reg54 & v_flag))
701 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
703 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
706 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
708 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
710 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
712 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
716 #define AHCI_PCI_BAR 5
717 #define AHCI_GLOBAL_CTL 0x04
718 #define AHCI_ENABLE (1 << 31)
719 static int piix_disable_ahci(struct pci_dev *pdev)
725 /* BUG: pci_enable_device has not yet been called. This
726 * works because this device is usually set up by BIOS.
729 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
730 !pci_resource_len(pdev, AHCI_PCI_BAR))
733 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
737 tmp = readl(mmio + AHCI_GLOBAL_CTL);
738 if (tmp & AHCI_ENABLE) {
740 writel(tmp, mmio + AHCI_GLOBAL_CTL);
742 tmp = readl(mmio + AHCI_GLOBAL_CTL);
743 if (tmp & AHCI_ENABLE)
747 pci_iounmap(pdev, mmio);
752 * piix_check_450nx_errata - Check for problem 450NX setup
753 * @ata_dev: the PCI device to check
755 * Check for the present of 450NX errata #19 and errata #25. If
756 * they are found return an error code so we can turn off DMA
759 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
761 struct pci_dev *pdev = NULL;
766 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
768 /* Look for 450NX PXB. Check for problem configurations
769 A PCI quirk checks bit 6 already */
770 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
771 pci_read_config_word(pdev, 0x41, &cfg);
772 /* Only on the original revision: IDE DMA can hang */
775 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
776 else if (cfg & (1<<14) && rev < 5)
780 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
781 if (no_piix_dma == 2)
782 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
786 static void __devinit piix_init_sata_map(struct pci_dev *pdev,
787 struct ata_port_info *pinfo)
789 struct piix_map_db *map_db = pinfo[0].private_data;
790 const unsigned int *map;
791 int i, invalid_map = 0;
794 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
796 map = map_db->map[map_value & map_db->mask];
798 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
799 for (i = 0; i < 4; i++) {
811 WARN_ON((i & 1) || map[i + 1] != IDE);
812 pinfo[i / 2] = piix_port_info[ich5_pata];
818 printk(" P%d", map[i]);
820 pinfo[i / 2].host_flags |= ATA_FLAG_SLAVE_POSS;
827 dev_printk(KERN_ERR, &pdev->dev,
828 "invalid MAP value %u\n", map_value);
830 pinfo[0].private_data = (void *)map;
831 pinfo[1].private_data = (void *)map;
835 * piix_init_one - Register PIIX ATA PCI device with kernel services
836 * @pdev: PCI device to register
837 * @ent: Entry in piix_pci_tbl matching with @pdev
839 * Called from kernel PCI layer. We probe for combined mode (sigh),
840 * and then hand over control to libata, for it to do the rest.
843 * Inherited from PCI layer (may sleep).
846 * Zero on success, or -ERRNO value.
849 static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
851 static int printed_version;
852 struct ata_port_info port_info[2];
853 struct ata_port_info *ppinfo[2] = { &port_info[0], &port_info[1] };
854 unsigned long host_flags;
856 if (!printed_version++)
857 dev_printk(KERN_DEBUG, &pdev->dev,
858 "version " DRV_VERSION "\n");
860 /* no hotplugging support (FIXME) */
864 port_info[0] = piix_port_info[ent->driver_data];
865 port_info[1] = piix_port_info[ent->driver_data];
867 host_flags = port_info[0].host_flags;
869 if (host_flags & PIIX_FLAG_AHCI) {
871 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
872 if (tmp == PIIX_AHCI_DEVICE) {
873 int rc = piix_disable_ahci(pdev);
879 /* Initialize SATA map */
880 if (host_flags & ATA_FLAG_SATA)
881 piix_init_sata_map(pdev, port_info);
883 /* On ICH5, some BIOSen disable the interrupt using the
884 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
885 * On ICH6, this bit has the same effect, but only when
886 * MSI is disabled (and it is disabled, as we don't use
887 * message-signalled interrupts currently).
889 if (host_flags & PIIX_FLAG_CHECKINTR)
892 if (piix_check_450nx_errata(pdev)) {
893 /* This writes into the master table but it does not
894 really matter for this errata as we will apply it to
895 all the PIIX devices on the board */
896 port_info[0].mwdma_mask = 0;
897 port_info[0].udma_mask = 0;
898 port_info[1].mwdma_mask = 0;
899 port_info[1].udma_mask = 0;
901 return ata_pci_init_one(pdev, ppinfo, 2);
904 static int __init piix_init(void)
908 DPRINTK("pci_module_init\n");
909 rc = pci_module_init(&piix_pci_driver);
919 static void __exit piix_exit(void)
921 pci_unregister_driver(&piix_pci_driver);
924 module_init(piix_init);
925 module_exit(piix_exit);