2 * ata_piix.c - Intel PATA/SATA controllers
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
13 * Copyright header from piix.c:
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
38 * Hardware documentation available at http://developer.intel.com/
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below.going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
85 #include <linux/kernel.h>
86 #include <linux/module.h>
87 #include <linux/pci.h>
88 #include <linux/init.h>
89 #include <linux/blkdev.h>
90 #include <linux/delay.h>
91 #include <linux/device.h>
92 #include <scsi/scsi_host.h>
93 #include <linux/libata.h>
95 #define DRV_NAME "ata_piix"
96 #define DRV_VERSION "1.05"
99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
100 ICH5_PMR = 0x90, /* port mapping register */
101 ICH5_PCS = 0x92, /* port control and status */
102 PIIX_SCC = 0x0A, /* sub-class code register */
104 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
105 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
106 PIIX_FLAG_COMBINED = (1 << 29), /* combined mode possible */
107 /* ICH6/7 use different scheme for map value */
108 PIIX_FLAG_COMBINED_ICH6 = PIIX_FLAG_COMBINED | (1 << 30),
110 /* combined mode. if set, PATA is channel 0.
111 * if clear, PATA is channel 1.
113 PIIX_COMB_PATA_P0 = (1 << 1),
114 PIIX_COMB = (1 << 2), /* combined mode enabled? */
116 PIIX_PORT_ENABLED = (1 << 0),
117 PIIX_PORT_PRESENT = (1 << 4),
119 PIIX_80C_PRI = (1 << 5) | (1 << 4),
120 PIIX_80C_SEC = (1 << 7) | (1 << 6),
128 PIIX_AHCI_DEVICE = 6,
131 static int piix_init_one (struct pci_dev *pdev,
132 const struct pci_device_id *ent);
134 static void piix_pata_phy_reset(struct ata_port *ap);
135 static void piix_sata_phy_reset(struct ata_port *ap);
136 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
137 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
139 static unsigned int in_module_init = 1;
141 static const struct pci_device_id piix_pci_tbl[] = {
142 #ifdef ATA_ENABLE_PATA
143 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata },
144 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
145 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
148 /* NOTE: The following PCI ids must be kept in sync with the
149 * list in drivers/pci/quirks.c.
152 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
153 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
154 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
155 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
156 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
157 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
158 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
159 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
160 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
161 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
162 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
163 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
164 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
166 { } /* terminate list */
169 static struct pci_driver piix_pci_driver = {
171 .id_table = piix_pci_tbl,
172 .probe = piix_init_one,
173 .remove = ata_pci_remove_one,
174 .suspend = ata_pci_device_suspend,
175 .resume = ata_pci_device_resume,
178 static struct scsi_host_template piix_sht = {
179 .module = THIS_MODULE,
181 .ioctl = ata_scsi_ioctl,
182 .queuecommand = ata_scsi_queuecmd,
183 .eh_strategy_handler = ata_scsi_error,
184 .can_queue = ATA_DEF_QUEUE,
185 .this_id = ATA_SHT_THIS_ID,
186 .sg_tablesize = LIBATA_MAX_PRD,
187 .max_sectors = ATA_MAX_SECTORS,
188 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
189 .emulated = ATA_SHT_EMULATED,
190 .use_clustering = ATA_SHT_USE_CLUSTERING,
191 .proc_name = DRV_NAME,
192 .dma_boundary = ATA_DMA_BOUNDARY,
193 .slave_configure = ata_scsi_slave_config,
194 .bios_param = ata_std_bios_param,
195 .resume = ata_scsi_device_resume,
196 .suspend = ata_scsi_device_suspend,
199 static const struct ata_port_operations piix_pata_ops = {
200 .port_disable = ata_port_disable,
201 .set_piomode = piix_set_piomode,
202 .set_dmamode = piix_set_dmamode,
204 .tf_load = ata_tf_load,
205 .tf_read = ata_tf_read,
206 .check_status = ata_check_status,
207 .exec_command = ata_exec_command,
208 .dev_select = ata_std_dev_select,
210 .phy_reset = piix_pata_phy_reset,
212 .bmdma_setup = ata_bmdma_setup,
213 .bmdma_start = ata_bmdma_start,
214 .bmdma_stop = ata_bmdma_stop,
215 .bmdma_status = ata_bmdma_status,
216 .qc_prep = ata_qc_prep,
217 .qc_issue = ata_qc_issue_prot,
219 .eng_timeout = ata_eng_timeout,
221 .irq_handler = ata_interrupt,
222 .irq_clear = ata_bmdma_irq_clear,
224 .port_start = ata_port_start,
225 .port_stop = ata_port_stop,
226 .host_stop = ata_host_stop,
229 static const struct ata_port_operations piix_sata_ops = {
230 .port_disable = ata_port_disable,
232 .tf_load = ata_tf_load,
233 .tf_read = ata_tf_read,
234 .check_status = ata_check_status,
235 .exec_command = ata_exec_command,
236 .dev_select = ata_std_dev_select,
238 .phy_reset = piix_sata_phy_reset,
240 .bmdma_setup = ata_bmdma_setup,
241 .bmdma_start = ata_bmdma_start,
242 .bmdma_stop = ata_bmdma_stop,
243 .bmdma_status = ata_bmdma_status,
244 .qc_prep = ata_qc_prep,
245 .qc_issue = ata_qc_issue_prot,
247 .eng_timeout = ata_eng_timeout,
249 .irq_handler = ata_interrupt,
250 .irq_clear = ata_bmdma_irq_clear,
252 .port_start = ata_port_start,
253 .port_stop = ata_port_stop,
254 .host_stop = ata_host_stop,
257 static struct ata_port_info piix_port_info[] = {
261 .host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST |
263 .pio_mask = 0x1f, /* pio0-4 */
265 .mwdma_mask = 0x06, /* mwdma1-2 */
267 .mwdma_mask = 0x00, /* mwdma broken */
269 .udma_mask = 0x3f, /* udma0-5 */
270 .port_ops = &piix_pata_ops,
276 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
277 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR,
278 .pio_mask = 0x1f, /* pio0-4 */
279 .mwdma_mask = 0x07, /* mwdma0-2 */
280 .udma_mask = 0x7f, /* udma0-6 */
281 .port_ops = &piix_sata_ops,
287 .host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
288 .pio_mask = 0x1f, /* pio0-4 */
290 .mwdma_mask = 0x06, /* mwdma1-2 */
292 .mwdma_mask = 0x00, /* mwdma broken */
294 .udma_mask = ATA_UDMA_MASK_40C,
295 .port_ops = &piix_pata_ops,
301 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
302 PIIX_FLAG_COMBINED_ICH6 |
303 PIIX_FLAG_CHECKINTR | ATA_FLAG_SLAVE_POSS,
304 .pio_mask = 0x1f, /* pio0-4 */
305 .mwdma_mask = 0x07, /* mwdma0-2 */
306 .udma_mask = 0x7f, /* udma0-6 */
307 .port_ops = &piix_sata_ops,
313 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
314 PIIX_FLAG_COMBINED_ICH6 |
315 PIIX_FLAG_CHECKINTR | ATA_FLAG_SLAVE_POSS |
317 .pio_mask = 0x1f, /* pio0-4 */
318 .mwdma_mask = 0x07, /* mwdma0-2 */
319 .udma_mask = 0x7f, /* udma0-6 */
320 .port_ops = &piix_sata_ops,
324 static struct pci_bits piix_enable_bits[] = {
325 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
326 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
329 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
330 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
331 MODULE_LICENSE("GPL");
332 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
333 MODULE_VERSION(DRV_VERSION);
336 * piix_pata_cbl_detect - Probe host controller cable detect info
337 * @ap: Port for which cable detect info is desired
339 * Read 80c cable indicator from ATA PCI device's PCI config
340 * register. This register is normally set by firmware (BIOS).
343 * None (inherited from caller).
345 static void piix_pata_cbl_detect(struct ata_port *ap)
347 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
350 /* no 80c support in host controller? */
351 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
354 /* check BIOS cable detect results */
355 mask = ap->hard_port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
356 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
357 if ((tmp & mask) == 0)
360 ap->cbl = ATA_CBL_PATA80;
364 ap->cbl = ATA_CBL_PATA40;
365 ap->udma_mask &= ATA_UDMA_MASK_40C;
369 * piix_pata_phy_reset - Probe specified port on PATA host controller
375 * None (inherited from caller).
378 static void piix_pata_phy_reset(struct ata_port *ap)
380 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
382 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->hard_port_no])) {
383 ata_port_disable(ap);
384 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
388 piix_pata_cbl_detect(ap);
396 * piix_sata_probe - Probe PCI device for present SATA devices
397 * @ap: Port associated with the PCI device we wish to probe
399 * Reads SATA PCI device's PCI config register Port Configuration
400 * and Status (PCS) to determine port and device availability.
403 * None (inherited from caller).
406 * Non-zero if port is enabled, it may or may not have a device
407 * attached in that case (PRESENT bit would only be set if BIOS probe
408 * was done). Zero is returned if port is disabled.
410 static int piix_sata_probe (struct ata_port *ap)
412 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
413 int combined = (ap->flags & ATA_FLAG_SLAVE_POSS);
414 int orig_mask, mask, i;
417 mask = (PIIX_PORT_PRESENT << ap->hard_port_no) |
418 (PIIX_PORT_ENABLED << ap->hard_port_no);
420 pci_read_config_byte(pdev, ICH5_PCS, &pcs);
421 orig_mask = (int) pcs & 0xff;
423 /* TODO: this is vaguely wrong for ICH6 combined mode,
424 * where only two of the four SATA ports are mapped
425 * onto a single ATA channel. It is also vaguely inaccurate
426 * for ICH5, which has only two ports. However, this is ok,
427 * as further device presence detection code will handle
428 * any false positives produced here.
431 for (i = 0; i < 4; i++) {
432 mask = (PIIX_PORT_ENABLED << i);
434 if ((orig_mask & mask) == mask)
435 if (combined || (i == ap->hard_port_no))
443 * piix_sata_phy_reset - Probe specified port on SATA host controller
449 * None (inherited from caller).
452 static void piix_sata_phy_reset(struct ata_port *ap)
454 if (!piix_sata_probe(ap)) {
455 ata_port_disable(ap);
456 printk(KERN_INFO "ata%u: SATA port has no device.\n", ap->id);
460 ap->cbl = ATA_CBL_SATA;
468 * piix_set_piomode - Initialize host controller PATA PIO timings
469 * @ap: Port whose timings we are configuring
472 * Set PIO mode for device, in host controller PCI config space.
475 * None (inherited from caller).
478 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
480 unsigned int pio = adev->pio_mode - XFER_PIO_0;
481 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
482 unsigned int is_slave = (adev->devno != 0);
483 unsigned int master_port= ap->hard_port_no ? 0x42 : 0x40;
484 unsigned int slave_port = 0x44;
488 static const /* ISP RTC */
489 u8 timings[][2] = { { 0, 0 },
495 pci_read_config_word(dev, master_port, &master_data);
497 master_data |= 0x4000;
498 /* enable PPE, IE and TIME */
499 master_data |= 0x0070;
500 pci_read_config_byte(dev, slave_port, &slave_data);
501 slave_data &= (ap->hard_port_no ? 0x0f : 0xf0);
503 (timings[pio][0] << 2) |
504 (timings[pio][1] << (ap->hard_port_no ? 4 : 0));
506 master_data &= 0xccf8;
507 /* enable PPE, IE and TIME */
508 master_data |= 0x0007;
510 (timings[pio][0] << 12) |
511 (timings[pio][1] << 8);
513 pci_write_config_word(dev, master_port, master_data);
515 pci_write_config_byte(dev, slave_port, slave_data);
519 * piix_set_dmamode - Initialize host controller PATA PIO timings
520 * @ap: Port whose timings we are configuring
522 * @udma: udma mode, 0 - 6
524 * Set UDMA mode for device, in host controller PCI config space.
527 * None (inherited from caller).
530 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
532 unsigned int udma = adev->dma_mode; /* FIXME: MWDMA too */
533 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
534 u8 maslave = ap->hard_port_no ? 0x42 : 0x40;
536 unsigned int drive_dn = (ap->hard_port_no ? 2 : 0) + adev->devno;
537 int a_speed = 3 << (drive_dn * 4);
538 int u_flag = 1 << drive_dn;
539 int v_flag = 0x01 << drive_dn;
540 int w_flag = 0x10 << drive_dn;
544 u8 reg48, reg54, reg55;
546 pci_read_config_word(dev, maslave, ®4042);
547 DPRINTK("reg4042 = 0x%04x\n", reg4042);
548 sitre = (reg4042 & 0x4000) ? 1 : 0;
549 pci_read_config_byte(dev, 0x48, ®48);
550 pci_read_config_word(dev, 0x4a, ®4a);
551 pci_read_config_byte(dev, 0x54, ®54);
552 pci_read_config_byte(dev, 0x55, ®55);
556 case XFER_UDMA_2: u_speed = 2 << (drive_dn * 4); break;
560 case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break;
561 case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break;
563 case XFER_MW_DMA_1: break;
569 if (speed >= XFER_UDMA_0) {
570 if (!(reg48 & u_flag))
571 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
572 if (speed == XFER_UDMA_5) {
573 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
575 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
577 if ((reg4a & a_speed) != u_speed)
578 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
579 if (speed > XFER_UDMA_2) {
580 if (!(reg54 & v_flag))
581 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
583 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
586 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
588 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
590 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
592 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
596 #define AHCI_PCI_BAR 5
597 #define AHCI_GLOBAL_CTL 0x04
598 #define AHCI_ENABLE (1 << 31)
599 static int piix_disable_ahci(struct pci_dev *pdev)
605 /* BUG: pci_enable_device has not yet been called. This
606 * works because this device is usually set up by BIOS.
609 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
610 !pci_resource_len(pdev, AHCI_PCI_BAR))
613 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
617 tmp = readl(mmio + AHCI_GLOBAL_CTL);
618 if (tmp & AHCI_ENABLE) {
620 writel(tmp, mmio + AHCI_GLOBAL_CTL);
622 tmp = readl(mmio + AHCI_GLOBAL_CTL);
623 if (tmp & AHCI_ENABLE)
627 pci_iounmap(pdev, mmio);
632 * piix_check_450nx_errata - Check for problem 450NX setup
633 * @ata_dev: the PCI device to check
635 * Check for the present of 450NX errata #19 and errata #25. If
636 * they are found return an error code so we can turn off DMA
639 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
641 struct pci_dev *pdev = NULL;
646 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
648 /* Look for 450NX PXB. Check for problem configurations
649 A PCI quirk checks bit 6 already */
650 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
651 pci_read_config_word(pdev, 0x41, &cfg);
652 /* Only on the original revision: IDE DMA can hang */
655 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
656 else if(cfg & (1<<14) && rev < 5)
660 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
662 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
667 * piix_init_one - Register PIIX ATA PCI device with kernel services
668 * @pdev: PCI device to register
669 * @ent: Entry in piix_pci_tbl matching with @pdev
671 * Called from kernel PCI layer. We probe for combined mode (sigh),
672 * and then hand over control to libata, for it to do the rest.
675 * Inherited from PCI layer (may sleep).
678 * Zero on success, or -ERRNO value.
681 static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
683 static int printed_version;
684 struct ata_port_info *port_info[2];
685 unsigned int combined = 0;
686 unsigned int pata_chan = 0, sata_chan = 0;
687 unsigned long host_flags;
689 if (!printed_version++)
690 dev_printk(KERN_DEBUG, &pdev->dev,
691 "version " DRV_VERSION "\n");
693 /* no hotplugging support (FIXME) */
697 port_info[0] = &piix_port_info[ent->driver_data];
698 port_info[1] = &piix_port_info[ent->driver_data];
700 host_flags = port_info[0]->host_flags;
702 if (host_flags & PIIX_FLAG_AHCI) {
704 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
705 if (tmp == PIIX_AHCI_DEVICE) {
706 int rc = piix_disable_ahci(pdev);
712 if (host_flags & PIIX_FLAG_COMBINED) {
714 pci_read_config_byte(pdev, ICH5_PMR, &tmp);
716 if (host_flags & PIIX_FLAG_COMBINED_ICH6) {
729 dev_printk(KERN_WARNING, &pdev->dev,
730 "invalid MAP value %u\n", tmp);
734 if (tmp & PIIX_COMB) {
736 if (tmp & PIIX_COMB_PATA_P0)
744 /* On ICH5, some BIOSen disable the interrupt using the
745 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
746 * On ICH6, this bit has the same effect, but only when
747 * MSI is disabled (and it is disabled, as we don't use
748 * message-signalled interrupts currently).
750 if (host_flags & PIIX_FLAG_CHECKINTR)
754 port_info[sata_chan] = &piix_port_info[ent->driver_data];
755 port_info[sata_chan]->host_flags |= ATA_FLAG_SLAVE_POSS;
756 port_info[pata_chan] = &piix_port_info[ich5_pata];
758 dev_printk(KERN_WARNING, &pdev->dev,
759 "combined mode detected (p=%u, s=%u)\n",
760 pata_chan, sata_chan);
762 if (piix_check_450nx_errata(pdev)) {
763 /* This writes into the master table but it does not
764 really matter for this errata as we will apply it to
765 all the PIIX devices on the board */
766 port_info[0]->mwdma_mask = 0;
767 port_info[0]->udma_mask = 0;
768 port_info[1]->mwdma_mask = 0;
769 port_info[1]->udma_mask = 0;
771 return ata_pci_init_one(pdev, port_info, 2);
774 static int __init piix_init(void)
778 DPRINTK("pci_module_init\n");
779 rc = pci_module_init(&piix_pci_driver);
789 static void __exit piix_exit(void)
791 pci_unregister_driver(&piix_pci_driver);
794 module_init(piix_init);
795 module_exit(piix_exit);