2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "1.2"
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
59 AHCI_CMD_SLOT_SZ = 32 * 32,
61 AHCI_CMD_TBL_HDR = 0x80,
62 AHCI_CMD_TBL_CDB = 0x40,
63 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16),
64 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ +
66 AHCI_IRQ_ON_SG = (1 << 31),
67 AHCI_CMD_ATAPI = (1 << 5),
68 AHCI_CMD_WRITE = (1 << 6),
69 AHCI_CMD_PREFETCH = (1 << 7),
70 AHCI_CMD_RESET = (1 << 8),
71 AHCI_CMD_CLR_BUSY = (1 << 10),
73 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
77 /* global controller registers */
78 HOST_CAP = 0x00, /* host capabilities */
79 HOST_CTL = 0x04, /* global host control */
80 HOST_IRQ_STAT = 0x08, /* interrupt status */
81 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
82 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
85 HOST_RESET = (1 << 0), /* reset controller; self-clear */
86 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
87 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
90 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
91 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
93 /* registers for each SATA port */
94 PORT_LST_ADDR = 0x00, /* command list DMA addr */
95 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
96 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
97 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
98 PORT_IRQ_STAT = 0x10, /* interrupt status */
99 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
100 PORT_CMD = 0x18, /* port command */
101 PORT_TFDATA = 0x20, /* taskfile data */
102 PORT_SIG = 0x24, /* device TF signature */
103 PORT_CMD_ISSUE = 0x38, /* command issue */
104 PORT_SCR = 0x28, /* SATA phy register block */
105 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
106 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
107 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
108 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
110 /* PORT_IRQ_{STAT,MASK} bits */
111 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
112 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
113 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
114 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
115 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
116 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
117 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
118 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
120 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
121 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
122 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
123 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
124 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
125 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
126 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
127 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
128 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
130 PORT_IRQ_FATAL = PORT_IRQ_TF_ERR |
132 PORT_IRQ_HBUS_DATA_ERR |
134 DEF_PORT_IRQ = PORT_IRQ_FATAL | PORT_IRQ_PHYRDY |
135 PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE |
136 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS |
137 PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS |
138 PORT_IRQ_D2H_REG_FIS,
141 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
142 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
143 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
144 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
145 PORT_CMD_CLO = (1 << 3), /* Command list override */
146 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
147 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
148 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
150 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
151 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
152 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
154 /* hpriv->flags bits */
155 AHCI_FLAG_MSI = (1 << 0),
158 struct ahci_cmd_hdr {
173 struct ahci_host_priv {
175 u32 cap; /* cache of HOST_CAP register */
176 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
179 struct ahci_port_priv {
180 struct ahci_cmd_hdr *cmd_slot;
181 dma_addr_t cmd_slot_dma;
183 dma_addr_t cmd_tbl_dma;
184 struct ahci_sg *cmd_tbl_sg;
186 dma_addr_t rx_fis_dma;
189 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
190 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
191 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
192 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
193 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
194 static int ahci_probe_reset(struct ata_port *ap, unsigned int *classes);
195 static void ahci_irq_clear(struct ata_port *ap);
196 static void ahci_eng_timeout(struct ata_port *ap);
197 static int ahci_port_start(struct ata_port *ap);
198 static void ahci_port_stop(struct ata_port *ap);
199 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
200 static void ahci_qc_prep(struct ata_queued_cmd *qc);
201 static u8 ahci_check_status(struct ata_port *ap);
202 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc);
203 static void ahci_remove_one (struct pci_dev *pdev);
205 static struct scsi_host_template ahci_sht = {
206 .module = THIS_MODULE,
208 .ioctl = ata_scsi_ioctl,
209 .queuecommand = ata_scsi_queuecmd,
210 .eh_strategy_handler = ata_scsi_error,
211 .can_queue = ATA_DEF_QUEUE,
212 .this_id = ATA_SHT_THIS_ID,
213 .sg_tablesize = AHCI_MAX_SG,
214 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
215 .emulated = ATA_SHT_EMULATED,
216 .use_clustering = AHCI_USE_CLUSTERING,
217 .proc_name = DRV_NAME,
218 .dma_boundary = AHCI_DMA_BOUNDARY,
219 .slave_configure = ata_scsi_slave_config,
220 .bios_param = ata_std_bios_param,
223 static const struct ata_port_operations ahci_ops = {
224 .port_disable = ata_port_disable,
226 .check_status = ahci_check_status,
227 .check_altstatus = ahci_check_status,
228 .dev_select = ata_noop_dev_select,
230 .tf_read = ahci_tf_read,
232 .probe_reset = ahci_probe_reset,
234 .qc_prep = ahci_qc_prep,
235 .qc_issue = ahci_qc_issue,
237 .eng_timeout = ahci_eng_timeout,
239 .irq_handler = ahci_interrupt,
240 .irq_clear = ahci_irq_clear,
242 .scr_read = ahci_scr_read,
243 .scr_write = ahci_scr_write,
245 .port_start = ahci_port_start,
246 .port_stop = ahci_port_stop,
249 static const struct ata_port_info ahci_port_info[] = {
253 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
254 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
255 .pio_mask = 0x1f, /* pio0-4 */
256 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
257 .port_ops = &ahci_ops,
261 static const struct pci_device_id ahci_pci_tbl[] = {
262 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
263 board_ahci }, /* ICH6 */
264 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
265 board_ahci }, /* ICH6M */
266 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
267 board_ahci }, /* ICH7 */
268 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
269 board_ahci }, /* ICH7M */
270 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
271 board_ahci }, /* ICH7R */
272 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
273 board_ahci }, /* ULi M5288 */
274 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
275 board_ahci }, /* ESB2 */
276 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
277 board_ahci }, /* ESB2 */
278 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
279 board_ahci }, /* ESB2 */
280 { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
281 board_ahci }, /* ICH7-M DH */
282 { PCI_VENDOR_ID_INTEL, 0x2821, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
283 board_ahci }, /* ICH8 */
284 { PCI_VENDOR_ID_INTEL, 0x2822, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
285 board_ahci }, /* ICH8 */
286 { PCI_VENDOR_ID_INTEL, 0x2824, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
287 board_ahci }, /* ICH8 */
288 { PCI_VENDOR_ID_INTEL, 0x2829, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
289 board_ahci }, /* ICH8M */
290 { PCI_VENDOR_ID_INTEL, 0x282a, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
291 board_ahci }, /* ICH8M */
292 { 0x197b, 0x2360, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
293 board_ahci }, /* JMicron JMB360 */
294 { 0x197b, 0x2363, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
295 board_ahci }, /* JMicron JMB363 */
296 { } /* terminate list */
300 static struct pci_driver ahci_pci_driver = {
302 .id_table = ahci_pci_tbl,
303 .probe = ahci_init_one,
304 .remove = ahci_remove_one,
308 static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
310 return base + 0x100 + (port * 0x80);
313 static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
315 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
318 static int ahci_port_start(struct ata_port *ap)
320 struct device *dev = ap->host_set->dev;
321 struct ahci_host_priv *hpriv = ap->host_set->private_data;
322 struct ahci_port_priv *pp;
323 void __iomem *mmio = ap->host_set->mmio_base;
324 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
329 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
332 memset(pp, 0, sizeof(*pp));
334 rc = ata_pad_alloc(ap, dev);
340 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
342 ata_pad_free(ap, dev);
346 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
349 * First item in chunk of DMA memory: 32-slot command table,
350 * 32 bytes each in size
353 pp->cmd_slot_dma = mem_dma;
355 mem += AHCI_CMD_SLOT_SZ;
356 mem_dma += AHCI_CMD_SLOT_SZ;
359 * Second item: Received-FIS area
362 pp->rx_fis_dma = mem_dma;
364 mem += AHCI_RX_FIS_SZ;
365 mem_dma += AHCI_RX_FIS_SZ;
368 * Third item: data area for storing a single command
369 * and its scatter-gather table
372 pp->cmd_tbl_dma = mem_dma;
374 pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR;
376 ap->private_data = pp;
378 if (hpriv->cap & HOST_CAP_64)
379 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
380 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
381 readl(port_mmio + PORT_LST_ADDR); /* flush */
383 if (hpriv->cap & HOST_CAP_64)
384 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
385 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
386 readl(port_mmio + PORT_FIS_ADDR); /* flush */
388 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
389 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
390 PORT_CMD_START, port_mmio + PORT_CMD);
391 readl(port_mmio + PORT_CMD); /* flush */
397 static void ahci_port_stop(struct ata_port *ap)
399 struct device *dev = ap->host_set->dev;
400 struct ahci_port_priv *pp = ap->private_data;
401 void __iomem *mmio = ap->host_set->mmio_base;
402 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
405 tmp = readl(port_mmio + PORT_CMD);
406 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
407 writel(tmp, port_mmio + PORT_CMD);
408 readl(port_mmio + PORT_CMD); /* flush */
410 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
411 * this is slightly incorrect.
415 ap->private_data = NULL;
416 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
417 pp->cmd_slot, pp->cmd_slot_dma);
418 ata_pad_free(ap, dev);
422 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
427 case SCR_STATUS: sc_reg = 0; break;
428 case SCR_CONTROL: sc_reg = 1; break;
429 case SCR_ERROR: sc_reg = 2; break;
430 case SCR_ACTIVE: sc_reg = 3; break;
435 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
439 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
445 case SCR_STATUS: sc_reg = 0; break;
446 case SCR_CONTROL: sc_reg = 1; break;
447 case SCR_ERROR: sc_reg = 2; break;
448 case SCR_ACTIVE: sc_reg = 3; break;
453 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
456 static int ahci_stop_engine(struct ata_port *ap)
458 void __iomem *mmio = ap->host_set->mmio_base;
459 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
463 tmp = readl(port_mmio + PORT_CMD);
464 tmp &= ~PORT_CMD_START;
465 writel(tmp, port_mmio + PORT_CMD);
467 /* wait for engine to stop. TODO: this could be
468 * as long as 500 msec
472 tmp = readl(port_mmio + PORT_CMD);
473 if ((tmp & PORT_CMD_LIST_ON) == 0)
481 static void ahci_start_engine(struct ata_port *ap)
483 void __iomem *mmio = ap->host_set->mmio_base;
484 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
487 tmp = readl(port_mmio + PORT_CMD);
488 tmp |= PORT_CMD_START;
489 writel(tmp, port_mmio + PORT_CMD);
490 readl(port_mmio + PORT_CMD); /* flush */
493 static unsigned int ahci_dev_classify(struct ata_port *ap)
495 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
496 struct ata_taskfile tf;
499 tmp = readl(port_mmio + PORT_SIG);
500 tf.lbah = (tmp >> 24) & 0xff;
501 tf.lbam = (tmp >> 16) & 0xff;
502 tf.lbal = (tmp >> 8) & 0xff;
503 tf.nsect = (tmp) & 0xff;
505 return ata_dev_classify(&tf);
508 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, u32 opts)
510 pp->cmd_slot[0].opts = cpu_to_le32(opts);
511 pp->cmd_slot[0].status = 0;
512 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
513 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
516 static int ahci_hardreset(struct ata_port *ap, int verbose, unsigned int *class)
522 ahci_stop_engine(ap);
523 rc = sata_std_hardreset(ap, verbose, class);
524 ahci_start_engine(ap);
527 *class = ahci_dev_classify(ap);
528 if (*class == ATA_DEV_UNKNOWN)
529 *class = ATA_DEV_NONE;
531 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
535 static void ahci_postreset(struct ata_port *ap, unsigned int *class)
537 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
540 ata_std_postreset(ap, class);
542 /* Make sure port's ATAPI bit is set appropriately */
543 new_tmp = tmp = readl(port_mmio + PORT_CMD);
544 if (*class == ATA_DEV_ATAPI)
545 new_tmp |= PORT_CMD_ATAPI;
547 new_tmp &= ~PORT_CMD_ATAPI;
548 if (new_tmp != tmp) {
549 writel(new_tmp, port_mmio + PORT_CMD);
550 readl(port_mmio + PORT_CMD); /* flush */
554 static int ahci_probe_reset(struct ata_port *ap, unsigned int *classes)
556 return ata_drive_probe_reset(ap, NULL, NULL, ahci_hardreset,
557 ahci_postreset, classes);
560 static u8 ahci_check_status(struct ata_port *ap)
562 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
564 return readl(mmio + PORT_TFDATA) & 0xFF;
567 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
569 struct ahci_port_priv *pp = ap->private_data;
570 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
572 ata_tf_from_fis(d2h_fis, tf);
575 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc)
577 struct ahci_port_priv *pp = qc->ap->private_data;
578 struct scatterlist *sg;
579 struct ahci_sg *ahci_sg;
580 unsigned int n_sg = 0;
585 * Next, the S/G list.
587 ahci_sg = pp->cmd_tbl_sg;
588 ata_for_each_sg(sg, qc) {
589 dma_addr_t addr = sg_dma_address(sg);
590 u32 sg_len = sg_dma_len(sg);
592 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
593 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
594 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
603 static void ahci_qc_prep(struct ata_queued_cmd *qc)
605 struct ata_port *ap = qc->ap;
606 struct ahci_port_priv *pp = ap->private_data;
607 int is_atapi = is_atapi_taskfile(&qc->tf);
609 const u32 cmd_fis_len = 5; /* five dwords */
613 * Fill in command table information. First, the header,
614 * a SATA Register - Host to Device command FIS.
616 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
618 memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
619 memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb,
624 if (qc->flags & ATA_QCFLAG_DMAMAP)
625 n_elem = ahci_fill_sg(qc);
628 * Fill in command slot information.
630 opts = cmd_fis_len | n_elem << 16;
631 if (qc->tf.flags & ATA_TFLAG_WRITE)
632 opts |= AHCI_CMD_WRITE;
634 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
636 ahci_fill_cmd_slot(pp, opts);
639 static void ahci_restart_port(struct ata_port *ap, u32 irq_stat)
641 void __iomem *mmio = ap->host_set->mmio_base;
642 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
645 if ((ap->device[0].class != ATA_DEV_ATAPI) ||
646 ((irq_stat & PORT_IRQ_TF_ERR) == 0))
647 printk(KERN_WARNING "ata%u: port reset, "
648 "p_is %x is %x pis %x cmd %x tf %x ss %x se %x\n",
651 readl(mmio + HOST_IRQ_STAT),
652 readl(port_mmio + PORT_IRQ_STAT),
653 readl(port_mmio + PORT_CMD),
654 readl(port_mmio + PORT_TFDATA),
655 readl(port_mmio + PORT_SCR_STAT),
656 readl(port_mmio + PORT_SCR_ERR));
659 ahci_stop_engine(ap);
661 /* clear SATA phy error, if any */
662 tmp = readl(port_mmio + PORT_SCR_ERR);
663 writel(tmp, port_mmio + PORT_SCR_ERR);
665 /* if DRQ/BSY is set, device needs to be reset.
666 * if so, issue COMRESET
668 tmp = readl(port_mmio + PORT_TFDATA);
669 if (tmp & (ATA_BUSY | ATA_DRQ)) {
670 writel(0x301, port_mmio + PORT_SCR_CTL);
671 readl(port_mmio + PORT_SCR_CTL); /* flush */
673 writel(0x300, port_mmio + PORT_SCR_CTL);
674 readl(port_mmio + PORT_SCR_CTL); /* flush */
678 ahci_start_engine(ap);
681 static void ahci_eng_timeout(struct ata_port *ap)
683 struct ata_host_set *host_set = ap->host_set;
684 void __iomem *mmio = host_set->mmio_base;
685 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
686 struct ata_queued_cmd *qc;
689 printk(KERN_WARNING "ata%u: handling error/timeout\n", ap->id);
691 spin_lock_irqsave(&host_set->lock, flags);
693 ahci_restart_port(ap, readl(port_mmio + PORT_IRQ_STAT));
694 qc = ata_qc_from_tag(ap, ap->active_tag);
695 qc->err_mask |= AC_ERR_TIMEOUT;
697 spin_unlock_irqrestore(&host_set->lock, flags);
699 ata_eh_qc_complete(qc);
702 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
704 void __iomem *mmio = ap->host_set->mmio_base;
705 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
706 u32 status, serr, ci;
708 serr = readl(port_mmio + PORT_SCR_ERR);
709 writel(serr, port_mmio + PORT_SCR_ERR);
711 status = readl(port_mmio + PORT_IRQ_STAT);
712 writel(status, port_mmio + PORT_IRQ_STAT);
714 ci = readl(port_mmio + PORT_CMD_ISSUE);
715 if (likely((ci & 0x1) == 0)) {
717 WARN_ON(qc->err_mask);
723 if (status & PORT_IRQ_FATAL) {
724 unsigned int err_mask;
725 if (status & PORT_IRQ_TF_ERR)
726 err_mask = AC_ERR_DEV;
727 else if (status & PORT_IRQ_IF_ERR)
728 err_mask = AC_ERR_ATA_BUS;
730 err_mask = AC_ERR_HOST_BUS;
732 /* command processing has stopped due to error; restart */
733 ahci_restart_port(ap, status);
736 qc->err_mask |= err_mask;
744 static void ahci_irq_clear(struct ata_port *ap)
749 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
751 struct ata_host_set *host_set = dev_instance;
752 struct ahci_host_priv *hpriv;
753 unsigned int i, handled = 0;
755 u32 irq_stat, irq_ack = 0;
759 hpriv = host_set->private_data;
760 mmio = host_set->mmio_base;
762 /* sigh. 0xffffffff is a valid return from h/w */
763 irq_stat = readl(mmio + HOST_IRQ_STAT);
764 irq_stat &= hpriv->port_map;
768 spin_lock(&host_set->lock);
770 for (i = 0; i < host_set->n_ports; i++) {
773 if (!(irq_stat & (1 << i)))
776 ap = host_set->ports[i];
778 struct ata_queued_cmd *qc;
779 qc = ata_qc_from_tag(ap, ap->active_tag);
780 if (!ahci_host_intr(ap, qc))
782 dev_printk(KERN_WARNING, host_set->dev,
783 "unhandled interrupt on port %u\n",
786 VPRINTK("port %u\n", i);
788 VPRINTK("port %u (no irq)\n", i);
790 dev_printk(KERN_WARNING, host_set->dev,
791 "interrupt on disabled port %u\n", i);
798 writel(irq_ack, mmio + HOST_IRQ_STAT);
802 spin_unlock(&host_set->lock);
806 return IRQ_RETVAL(handled);
809 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
811 struct ata_port *ap = qc->ap;
812 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
814 writel(1, port_mmio + PORT_CMD_ISSUE);
815 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
820 static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
821 unsigned int port_idx)
823 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
824 base = ahci_port_base_ul(base, port_idx);
825 VPRINTK("base now==0x%lx\n", base);
827 port->cmd_addr = base;
828 port->scr_addr = base + PORT_SCR;
833 static int ahci_host_init(struct ata_probe_ent *probe_ent)
835 struct ahci_host_priv *hpriv = probe_ent->private_data;
836 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
837 void __iomem *mmio = probe_ent->mmio_base;
839 unsigned int i, j, using_dac;
841 void __iomem *port_mmio;
843 cap_save = readl(mmio + HOST_CAP);
844 cap_save &= ( (1<<28) | (1<<17) );
845 cap_save |= (1 << 27);
847 /* global controller reset */
848 tmp = readl(mmio + HOST_CTL);
849 if ((tmp & HOST_RESET) == 0) {
850 writel(tmp | HOST_RESET, mmio + HOST_CTL);
851 readl(mmio + HOST_CTL); /* flush */
854 /* reset must complete within 1 second, or
855 * the hardware should be considered fried.
859 tmp = readl(mmio + HOST_CTL);
860 if (tmp & HOST_RESET) {
861 dev_printk(KERN_ERR, &pdev->dev,
862 "controller reset failed (0x%x)\n", tmp);
866 writel(HOST_AHCI_EN, mmio + HOST_CTL);
867 (void) readl(mmio + HOST_CTL); /* flush */
868 writel(cap_save, mmio + HOST_CAP);
869 writel(0xf, mmio + HOST_PORTS_IMPL);
870 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
872 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
875 pci_read_config_word(pdev, 0x92, &tmp16);
877 pci_write_config_word(pdev, 0x92, tmp16);
880 hpriv->cap = readl(mmio + HOST_CAP);
881 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
882 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
884 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
885 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
887 using_dac = hpriv->cap & HOST_CAP_64;
889 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
890 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
892 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
894 dev_printk(KERN_ERR, &pdev->dev,
895 "64-bit DMA enable failed\n");
900 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
902 dev_printk(KERN_ERR, &pdev->dev,
903 "32-bit DMA enable failed\n");
906 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
908 dev_printk(KERN_ERR, &pdev->dev,
909 "32-bit consistent DMA enable failed\n");
914 for (i = 0; i < probe_ent->n_ports; i++) {
915 #if 0 /* BIOSen initialize this incorrectly */
916 if (!(hpriv->port_map & (1 << i)))
920 port_mmio = ahci_port_base(mmio, i);
921 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
923 ahci_setup_port(&probe_ent->port[i],
924 (unsigned long) mmio, i);
926 /* make sure port is not active */
927 tmp = readl(port_mmio + PORT_CMD);
928 VPRINTK("PORT_CMD 0x%x\n", tmp);
929 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
930 PORT_CMD_FIS_RX | PORT_CMD_START)) {
931 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
932 PORT_CMD_FIS_RX | PORT_CMD_START);
933 writel(tmp, port_mmio + PORT_CMD);
934 readl(port_mmio + PORT_CMD); /* flush */
936 /* spec says 500 msecs for each bit, so
937 * this is slightly incorrect.
942 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
947 tmp = readl(port_mmio + PORT_SCR_STAT);
948 if ((tmp & 0xf) == 0x3)
953 tmp = readl(port_mmio + PORT_SCR_ERR);
954 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
955 writel(tmp, port_mmio + PORT_SCR_ERR);
957 /* ack any pending irq events for this port */
958 tmp = readl(port_mmio + PORT_IRQ_STAT);
959 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
961 writel(tmp, port_mmio + PORT_IRQ_STAT);
963 writel(1 << i, mmio + HOST_IRQ_STAT);
965 /* set irq mask (enables interrupts) */
966 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
969 tmp = readl(mmio + HOST_CTL);
970 VPRINTK("HOST_CTL 0x%x\n", tmp);
971 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
972 tmp = readl(mmio + HOST_CTL);
973 VPRINTK("HOST_CTL 0x%x\n", tmp);
975 pci_set_master(pdev);
980 static void ahci_print_info(struct ata_probe_ent *probe_ent)
982 struct ahci_host_priv *hpriv = probe_ent->private_data;
983 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
984 void __iomem *mmio = probe_ent->mmio_base;
985 u32 vers, cap, impl, speed;
990 vers = readl(mmio + HOST_VERSION);
992 impl = hpriv->port_map;
994 speed = (cap >> 20) & 0xf;
1002 pci_read_config_word(pdev, 0x0a, &cc);
1005 else if (cc == 0x0106)
1007 else if (cc == 0x0104)
1012 dev_printk(KERN_INFO, &pdev->dev,
1013 "AHCI %02x%02x.%02x%02x "
1014 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1017 (vers >> 24) & 0xff,
1018 (vers >> 16) & 0xff,
1022 ((cap >> 8) & 0x1f) + 1,
1028 dev_printk(KERN_INFO, &pdev->dev,
1034 cap & (1 << 31) ? "64bit " : "",
1035 cap & (1 << 30) ? "ncq " : "",
1036 cap & (1 << 28) ? "ilck " : "",
1037 cap & (1 << 27) ? "stag " : "",
1038 cap & (1 << 26) ? "pm " : "",
1039 cap & (1 << 25) ? "led " : "",
1041 cap & (1 << 24) ? "clo " : "",
1042 cap & (1 << 19) ? "nz " : "",
1043 cap & (1 << 18) ? "only " : "",
1044 cap & (1 << 17) ? "pmp " : "",
1045 cap & (1 << 15) ? "pio " : "",
1046 cap & (1 << 14) ? "slum " : "",
1047 cap & (1 << 13) ? "part " : ""
1051 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1053 static int printed_version;
1054 struct ata_probe_ent *probe_ent = NULL;
1055 struct ahci_host_priv *hpriv;
1057 void __iomem *mmio_base;
1058 unsigned int board_idx = (unsigned int) ent->driver_data;
1059 int have_msi, pci_dev_busy = 0;
1064 if (!printed_version++)
1065 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1067 rc = pci_enable_device(pdev);
1071 rc = pci_request_regions(pdev, DRV_NAME);
1077 if (pci_enable_msi(pdev) == 0)
1084 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1085 if (probe_ent == NULL) {
1090 memset(probe_ent, 0, sizeof(*probe_ent));
1091 probe_ent->dev = pci_dev_to_dev(pdev);
1092 INIT_LIST_HEAD(&probe_ent->node);
1094 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1095 if (mmio_base == NULL) {
1097 goto err_out_free_ent;
1099 base = (unsigned long) mmio_base;
1101 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1104 goto err_out_iounmap;
1106 memset(hpriv, 0, sizeof(*hpriv));
1108 probe_ent->sht = ahci_port_info[board_idx].sht;
1109 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1110 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1111 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1112 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1114 probe_ent->irq = pdev->irq;
1115 probe_ent->irq_flags = SA_SHIRQ;
1116 probe_ent->mmio_base = mmio_base;
1117 probe_ent->private_data = hpriv;
1120 hpriv->flags |= AHCI_FLAG_MSI;
1122 /* JMicron-specific fixup: make sure we're in AHCI mode */
1123 if (pdev->vendor == 0x197b)
1124 pci_write_config_byte(pdev, 0x41, 0xa1);
1126 /* initialize adapter */
1127 rc = ahci_host_init(probe_ent);
1131 ahci_print_info(probe_ent);
1133 /* FIXME: check ata_device_add return value */
1134 ata_device_add(probe_ent);
1142 pci_iounmap(pdev, mmio_base);
1147 pci_disable_msi(pdev);
1150 pci_release_regions(pdev);
1153 pci_disable_device(pdev);
1157 static void ahci_remove_one (struct pci_dev *pdev)
1159 struct device *dev = pci_dev_to_dev(pdev);
1160 struct ata_host_set *host_set = dev_get_drvdata(dev);
1161 struct ahci_host_priv *hpriv = host_set->private_data;
1162 struct ata_port *ap;
1166 for (i = 0; i < host_set->n_ports; i++) {
1167 ap = host_set->ports[i];
1169 scsi_remove_host(ap->host);
1172 have_msi = hpriv->flags & AHCI_FLAG_MSI;
1173 free_irq(host_set->irq, host_set);
1175 for (i = 0; i < host_set->n_ports; i++) {
1176 ap = host_set->ports[i];
1178 ata_scsi_release(ap->host);
1179 scsi_host_put(ap->host);
1183 pci_iounmap(pdev, host_set->mmio_base);
1187 pci_disable_msi(pdev);
1190 pci_release_regions(pdev);
1191 pci_disable_device(pdev);
1192 dev_set_drvdata(dev, NULL);
1195 static int __init ahci_init(void)
1197 return pci_module_init(&ahci_pci_driver);
1200 static void __exit ahci_exit(void)
1202 pci_unregister_driver(&ahci_pci_driver);
1206 MODULE_AUTHOR("Jeff Garzik");
1207 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1208 MODULE_LICENSE("GPL");
1209 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1210 MODULE_VERSION(DRV_VERSION);
1212 module_init(ahci_init);
1213 module_exit(ahci_exit);