2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "1.2"
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
59 AHCI_CMD_SLOT_SZ = 32 * 32,
61 AHCI_CMD_TBL_HDR = 0x80,
62 AHCI_CMD_TBL_CDB = 0x40,
63 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16),
64 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ +
66 AHCI_IRQ_ON_SG = (1 << 31),
67 AHCI_CMD_ATAPI = (1 << 5),
68 AHCI_CMD_WRITE = (1 << 6),
69 AHCI_CMD_RESET = (1 << 8),
70 AHCI_CMD_CLR_BUSY = (1 << 10),
72 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
76 /* global controller registers */
77 HOST_CAP = 0x00, /* host capabilities */
78 HOST_CTL = 0x04, /* global host control */
79 HOST_IRQ_STAT = 0x08, /* interrupt status */
80 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
81 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
84 HOST_RESET = (1 << 0), /* reset controller; self-clear */
85 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
86 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
89 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
90 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
92 /* registers for each SATA port */
93 PORT_LST_ADDR = 0x00, /* command list DMA addr */
94 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
95 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
96 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
97 PORT_IRQ_STAT = 0x10, /* interrupt status */
98 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
99 PORT_CMD = 0x18, /* port command */
100 PORT_TFDATA = 0x20, /* taskfile data */
101 PORT_SIG = 0x24, /* device TF signature */
102 PORT_CMD_ISSUE = 0x38, /* command issue */
103 PORT_SCR = 0x28, /* SATA phy register block */
104 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
105 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
106 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
107 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
109 /* PORT_IRQ_{STAT,MASK} bits */
110 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
111 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
112 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
113 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
114 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
115 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
116 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
117 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
119 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
120 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
121 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
122 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
123 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
124 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
125 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
126 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
127 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
129 PORT_IRQ_FATAL = PORT_IRQ_TF_ERR |
131 PORT_IRQ_HBUS_DATA_ERR |
133 DEF_PORT_IRQ = PORT_IRQ_FATAL | PORT_IRQ_PHYRDY |
134 PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE |
135 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS |
136 PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS |
137 PORT_IRQ_D2H_REG_FIS,
140 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
141 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
142 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
143 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
144 PORT_CMD_CLO = (1 << 3), /* Command list override */
145 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
146 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
147 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
149 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
150 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
151 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
153 /* hpriv->flags bits */
154 AHCI_FLAG_MSI = (1 << 0),
157 struct ahci_cmd_hdr {
172 struct ahci_host_priv {
174 u32 cap; /* cache of HOST_CAP register */
175 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
178 struct ahci_port_priv {
179 struct ahci_cmd_hdr *cmd_slot;
180 dma_addr_t cmd_slot_dma;
182 dma_addr_t cmd_tbl_dma;
183 struct ahci_sg *cmd_tbl_sg;
185 dma_addr_t rx_fis_dma;
188 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
189 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
190 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
191 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
192 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
193 static void ahci_phy_reset(struct ata_port *ap);
194 static void ahci_irq_clear(struct ata_port *ap);
195 static void ahci_eng_timeout(struct ata_port *ap);
196 static int ahci_port_start(struct ata_port *ap);
197 static void ahci_port_stop(struct ata_port *ap);
198 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
199 static void ahci_qc_prep(struct ata_queued_cmd *qc);
200 static u8 ahci_check_status(struct ata_port *ap);
201 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc);
202 static void ahci_remove_one (struct pci_dev *pdev);
204 static struct scsi_host_template ahci_sht = {
205 .module = THIS_MODULE,
207 .ioctl = ata_scsi_ioctl,
208 .queuecommand = ata_scsi_queuecmd,
209 .eh_timed_out = ata_scsi_timed_out,
210 .eh_strategy_handler = ata_scsi_error,
211 .can_queue = ATA_DEF_QUEUE,
212 .this_id = ATA_SHT_THIS_ID,
213 .sg_tablesize = AHCI_MAX_SG,
214 .max_sectors = ATA_MAX_SECTORS,
215 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
216 .emulated = ATA_SHT_EMULATED,
217 .use_clustering = AHCI_USE_CLUSTERING,
218 .proc_name = DRV_NAME,
219 .dma_boundary = AHCI_DMA_BOUNDARY,
220 .slave_configure = ata_scsi_slave_config,
221 .bios_param = ata_std_bios_param,
224 static const struct ata_port_operations ahci_ops = {
225 .port_disable = ata_port_disable,
227 .check_status = ahci_check_status,
228 .check_altstatus = ahci_check_status,
229 .dev_select = ata_noop_dev_select,
231 .tf_read = ahci_tf_read,
233 .phy_reset = ahci_phy_reset,
235 .qc_prep = ahci_qc_prep,
236 .qc_issue = ahci_qc_issue,
238 .eng_timeout = ahci_eng_timeout,
240 .irq_handler = ahci_interrupt,
241 .irq_clear = ahci_irq_clear,
243 .scr_read = ahci_scr_read,
244 .scr_write = ahci_scr_write,
246 .port_start = ahci_port_start,
247 .port_stop = ahci_port_stop,
250 static const struct ata_port_info ahci_port_info[] = {
254 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
255 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
257 .pio_mask = 0x1f, /* pio0-4 */
258 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
259 .port_ops = &ahci_ops,
263 static const struct pci_device_id ahci_pci_tbl[] = {
264 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
265 board_ahci }, /* ICH6 */
266 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
267 board_ahci }, /* ICH6M */
268 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
269 board_ahci }, /* ICH7 */
270 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
271 board_ahci }, /* ICH7M */
272 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
273 board_ahci }, /* ICH7R */
274 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
275 board_ahci }, /* ULi M5288 */
276 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
277 board_ahci }, /* ESB2 */
278 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
279 board_ahci }, /* ESB2 */
280 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
281 board_ahci }, /* ESB2 */
282 { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
283 board_ahci }, /* ICH7-M DH */
284 { PCI_VENDOR_ID_INTEL, 0x2821, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
285 board_ahci }, /* ICH8 */
286 { PCI_VENDOR_ID_INTEL, 0x2822, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
287 board_ahci }, /* ICH8 */
288 { PCI_VENDOR_ID_INTEL, 0x2824, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
289 board_ahci }, /* ICH8 */
290 { PCI_VENDOR_ID_INTEL, 0x2829, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
291 board_ahci }, /* ICH8M */
292 { PCI_VENDOR_ID_INTEL, 0x282a, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
293 board_ahci }, /* ICH8M */
294 { 0x197b, 0x2360, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
295 board_ahci }, /* JMicron JMB360 */
296 { 0x197b, 0x2363, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
297 board_ahci }, /* JMicron JMB363 */
298 { } /* terminate list */
302 static struct pci_driver ahci_pci_driver = {
304 .id_table = ahci_pci_tbl,
305 .probe = ahci_init_one,
306 .remove = ahci_remove_one,
310 static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
312 return base + 0x100 + (port * 0x80);
315 static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
317 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
320 static int ahci_port_start(struct ata_port *ap)
322 struct device *dev = ap->host_set->dev;
323 struct ahci_host_priv *hpriv = ap->host_set->private_data;
324 struct ahci_port_priv *pp;
325 void __iomem *mmio = ap->host_set->mmio_base;
326 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
331 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
334 memset(pp, 0, sizeof(*pp));
336 rc = ata_pad_alloc(ap, dev);
342 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
344 ata_pad_free(ap, dev);
348 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
351 * First item in chunk of DMA memory: 32-slot command table,
352 * 32 bytes each in size
355 pp->cmd_slot_dma = mem_dma;
357 mem += AHCI_CMD_SLOT_SZ;
358 mem_dma += AHCI_CMD_SLOT_SZ;
361 * Second item: Received-FIS area
364 pp->rx_fis_dma = mem_dma;
366 mem += AHCI_RX_FIS_SZ;
367 mem_dma += AHCI_RX_FIS_SZ;
370 * Third item: data area for storing a single command
371 * and its scatter-gather table
374 pp->cmd_tbl_dma = mem_dma;
376 pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR;
378 ap->private_data = pp;
380 if (hpriv->cap & HOST_CAP_64)
381 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
382 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
383 readl(port_mmio + PORT_LST_ADDR); /* flush */
385 if (hpriv->cap & HOST_CAP_64)
386 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
387 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
388 readl(port_mmio + PORT_FIS_ADDR); /* flush */
390 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
391 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
392 PORT_CMD_START, port_mmio + PORT_CMD);
393 readl(port_mmio + PORT_CMD); /* flush */
399 static void ahci_port_stop(struct ata_port *ap)
401 struct device *dev = ap->host_set->dev;
402 struct ahci_port_priv *pp = ap->private_data;
403 void __iomem *mmio = ap->host_set->mmio_base;
404 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
407 tmp = readl(port_mmio + PORT_CMD);
408 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
409 writel(tmp, port_mmio + PORT_CMD);
410 readl(port_mmio + PORT_CMD); /* flush */
412 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
413 * this is slightly incorrect.
417 ap->private_data = NULL;
418 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
419 pp->cmd_slot, pp->cmd_slot_dma);
420 ata_pad_free(ap, dev);
424 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
429 case SCR_STATUS: sc_reg = 0; break;
430 case SCR_CONTROL: sc_reg = 1; break;
431 case SCR_ERROR: sc_reg = 2; break;
432 case SCR_ACTIVE: sc_reg = 3; break;
437 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
441 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
447 case SCR_STATUS: sc_reg = 0; break;
448 case SCR_CONTROL: sc_reg = 1; break;
449 case SCR_ERROR: sc_reg = 2; break;
450 case SCR_ACTIVE: sc_reg = 3; break;
455 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
458 static int ahci_stop_engine(struct ata_port *ap)
460 void __iomem *mmio = ap->host_set->mmio_base;
461 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
465 tmp = readl(port_mmio + PORT_CMD);
466 tmp &= ~PORT_CMD_START;
467 writel(tmp, port_mmio + PORT_CMD);
469 /* wait for engine to stop. TODO: this could be
470 * as long as 500 msec
474 tmp = readl(port_mmio + PORT_CMD);
475 if ((tmp & PORT_CMD_LIST_ON) == 0)
483 static void ahci_start_engine(struct ata_port *ap)
485 void __iomem *mmio = ap->host_set->mmio_base;
486 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
489 tmp = readl(port_mmio + PORT_CMD);
490 tmp |= PORT_CMD_START;
491 writel(tmp, port_mmio + PORT_CMD);
492 readl(port_mmio + PORT_CMD); /* flush */
495 static unsigned int ahci_dev_classify(struct ata_port *ap)
497 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
498 struct ata_taskfile tf;
501 tmp = readl(port_mmio + PORT_SIG);
502 tf.lbah = (tmp >> 24) & 0xff;
503 tf.lbam = (tmp >> 16) & 0xff;
504 tf.lbal = (tmp >> 8) & 0xff;
505 tf.nsect = (tmp) & 0xff;
507 return ata_dev_classify(&tf);
510 static void ahci_phy_reset(struct ata_port *ap)
512 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
513 struct ata_device *dev = &ap->device[0];
516 ahci_stop_engine(ap);
517 __sata_phy_reset(ap);
518 ahci_start_engine(ap);
520 if (ap->flags & ATA_FLAG_PORT_DISABLED)
523 dev->class = ahci_dev_classify(ap);
524 if (!ata_dev_present(dev)) {
525 ata_port_disable(ap);
529 /* Make sure port's ATAPI bit is set appropriately */
530 new_tmp = tmp = readl(port_mmio + PORT_CMD);
531 if (dev->class == ATA_DEV_ATAPI)
532 new_tmp |= PORT_CMD_ATAPI;
534 new_tmp &= ~PORT_CMD_ATAPI;
535 if (new_tmp != tmp) {
536 writel(new_tmp, port_mmio + PORT_CMD);
537 readl(port_mmio + PORT_CMD); /* flush */
541 static u8 ahci_check_status(struct ata_port *ap)
543 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
545 return readl(mmio + PORT_TFDATA) & 0xFF;
548 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
550 struct ahci_port_priv *pp = ap->private_data;
551 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
553 ata_tf_from_fis(d2h_fis, tf);
556 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc)
558 struct ahci_port_priv *pp = qc->ap->private_data;
559 struct scatterlist *sg;
560 struct ahci_sg *ahci_sg;
561 unsigned int n_sg = 0;
566 * Next, the S/G list.
568 ahci_sg = pp->cmd_tbl_sg;
569 ata_for_each_sg(sg, qc) {
570 dma_addr_t addr = sg_dma_address(sg);
571 u32 sg_len = sg_dma_len(sg);
573 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
574 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
575 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
584 static void ahci_qc_prep(struct ata_queued_cmd *qc)
586 struct ata_port *ap = qc->ap;
587 struct ahci_port_priv *pp = ap->private_data;
589 const u32 cmd_fis_len = 5; /* five dwords */
593 * Fill in command slot information (currently only one slot,
594 * slot 0, is currently since we don't do queueing)
598 if (qc->tf.flags & ATA_TFLAG_WRITE)
599 opts |= AHCI_CMD_WRITE;
600 if (is_atapi_taskfile(&qc->tf))
601 opts |= AHCI_CMD_ATAPI;
603 pp->cmd_slot[0].opts = cpu_to_le32(opts);
604 pp->cmd_slot[0].status = 0;
605 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
606 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
609 * Fill in command table information. First, the header,
610 * a SATA Register - Host to Device command FIS.
612 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
613 if (opts & AHCI_CMD_ATAPI) {
614 memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
615 memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, ap->cdb_len);
618 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
621 n_elem = ahci_fill_sg(qc);
623 pp->cmd_slot[0].opts |= cpu_to_le32(n_elem << 16);
626 static void ahci_restart_port(struct ata_port *ap, u32 irq_stat)
628 void __iomem *mmio = ap->host_set->mmio_base;
629 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
632 if ((ap->device[0].class != ATA_DEV_ATAPI) ||
633 ((irq_stat & PORT_IRQ_TF_ERR) == 0))
634 printk(KERN_WARNING "ata%u: port reset, "
635 "p_is %x is %x pis %x cmd %x tf %x ss %x se %x\n",
638 readl(mmio + HOST_IRQ_STAT),
639 readl(port_mmio + PORT_IRQ_STAT),
640 readl(port_mmio + PORT_CMD),
641 readl(port_mmio + PORT_TFDATA),
642 readl(port_mmio + PORT_SCR_STAT),
643 readl(port_mmio + PORT_SCR_ERR));
646 ahci_stop_engine(ap);
648 /* clear SATA phy error, if any */
649 tmp = readl(port_mmio + PORT_SCR_ERR);
650 writel(tmp, port_mmio + PORT_SCR_ERR);
652 /* if DRQ/BSY is set, device needs to be reset.
653 * if so, issue COMRESET
655 tmp = readl(port_mmio + PORT_TFDATA);
656 if (tmp & (ATA_BUSY | ATA_DRQ)) {
657 writel(0x301, port_mmio + PORT_SCR_CTL);
658 readl(port_mmio + PORT_SCR_CTL); /* flush */
660 writel(0x300, port_mmio + PORT_SCR_CTL);
661 readl(port_mmio + PORT_SCR_CTL); /* flush */
665 ahci_start_engine(ap);
668 static void ahci_eng_timeout(struct ata_port *ap)
670 struct ata_host_set *host_set = ap->host_set;
671 void __iomem *mmio = host_set->mmio_base;
672 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
673 struct ata_queued_cmd *qc;
676 printk(KERN_WARNING "ata%u: handling error/timeout\n", ap->id);
678 spin_lock_irqsave(&host_set->lock, flags);
680 qc = ata_qc_from_tag(ap, ap->active_tag);
682 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
685 ahci_restart_port(ap, readl(port_mmio + PORT_IRQ_STAT));
686 qc->err_mask |= AC_ERR_TIMEOUT;
689 spin_unlock_irqrestore(&host_set->lock, flags);
692 ata_eh_qc_complete(qc);
695 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
697 void __iomem *mmio = ap->host_set->mmio_base;
698 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
699 u32 status, serr, ci;
701 serr = readl(port_mmio + PORT_SCR_ERR);
702 writel(serr, port_mmio + PORT_SCR_ERR);
704 status = readl(port_mmio + PORT_IRQ_STAT);
705 writel(status, port_mmio + PORT_IRQ_STAT);
707 ci = readl(port_mmio + PORT_CMD_ISSUE);
708 if (likely((ci & 0x1) == 0)) {
710 assert(qc->err_mask == 0);
716 if (status & PORT_IRQ_FATAL) {
717 unsigned int err_mask;
718 if (status & PORT_IRQ_TF_ERR)
719 err_mask = AC_ERR_DEV;
720 else if (status & PORT_IRQ_IF_ERR)
721 err_mask = AC_ERR_ATA_BUS;
723 err_mask = AC_ERR_HOST_BUS;
725 /* command processing has stopped due to error; restart */
726 ahci_restart_port(ap, status);
729 qc->err_mask |= err_mask;
737 static void ahci_irq_clear(struct ata_port *ap)
742 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
744 struct ata_host_set *host_set = dev_instance;
745 struct ahci_host_priv *hpriv;
746 unsigned int i, handled = 0;
748 u32 irq_stat, irq_ack = 0;
752 hpriv = host_set->private_data;
753 mmio = host_set->mmio_base;
755 /* sigh. 0xffffffff is a valid return from h/w */
756 irq_stat = readl(mmio + HOST_IRQ_STAT);
757 irq_stat &= hpriv->port_map;
761 spin_lock(&host_set->lock);
763 for (i = 0; i < host_set->n_ports; i++) {
766 if (!(irq_stat & (1 << i)))
769 ap = host_set->ports[i];
771 struct ata_queued_cmd *qc;
772 qc = ata_qc_from_tag(ap, ap->active_tag);
773 if (!ahci_host_intr(ap, qc))
774 if (ata_ratelimit()) {
775 struct pci_dev *pdev =
776 to_pci_dev(ap->host_set->dev);
777 dev_printk(KERN_WARNING, &pdev->dev,
778 "unhandled interrupt on port %u\n",
782 VPRINTK("port %u\n", i);
784 VPRINTK("port %u (no irq)\n", i);
785 if (ata_ratelimit()) {
786 struct pci_dev *pdev =
787 to_pci_dev(ap->host_set->dev);
788 dev_printk(KERN_WARNING, &pdev->dev,
789 "interrupt on disabled port %u\n", i);
797 writel(irq_ack, mmio + HOST_IRQ_STAT);
801 spin_unlock(&host_set->lock);
805 return IRQ_RETVAL(handled);
808 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
810 struct ata_port *ap = qc->ap;
811 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
813 writel(1, port_mmio + PORT_CMD_ISSUE);
814 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
819 static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
820 unsigned int port_idx)
822 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
823 base = ahci_port_base_ul(base, port_idx);
824 VPRINTK("base now==0x%lx\n", base);
826 port->cmd_addr = base;
827 port->scr_addr = base + PORT_SCR;
832 static int ahci_host_init(struct ata_probe_ent *probe_ent)
834 struct ahci_host_priv *hpriv = probe_ent->private_data;
835 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
836 void __iomem *mmio = probe_ent->mmio_base;
838 unsigned int i, j, using_dac;
840 void __iomem *port_mmio;
842 cap_save = readl(mmio + HOST_CAP);
843 cap_save &= ( (1<<28) | (1<<17) );
844 cap_save |= (1 << 27);
846 /* global controller reset */
847 tmp = readl(mmio + HOST_CTL);
848 if ((tmp & HOST_RESET) == 0) {
849 writel(tmp | HOST_RESET, mmio + HOST_CTL);
850 readl(mmio + HOST_CTL); /* flush */
853 /* reset must complete within 1 second, or
854 * the hardware should be considered fried.
858 tmp = readl(mmio + HOST_CTL);
859 if (tmp & HOST_RESET) {
860 dev_printk(KERN_ERR, &pdev->dev,
861 "controller reset failed (0x%x)\n", tmp);
865 writel(HOST_AHCI_EN, mmio + HOST_CTL);
866 (void) readl(mmio + HOST_CTL); /* flush */
867 writel(cap_save, mmio + HOST_CAP);
868 writel(0xf, mmio + HOST_PORTS_IMPL);
869 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
871 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
874 pci_read_config_word(pdev, 0x92, &tmp16);
876 pci_write_config_word(pdev, 0x92, tmp16);
879 hpriv->cap = readl(mmio + HOST_CAP);
880 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
881 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
883 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
884 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
886 using_dac = hpriv->cap & HOST_CAP_64;
888 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
889 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
891 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
893 dev_printk(KERN_ERR, &pdev->dev,
894 "64-bit DMA enable failed\n");
899 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
901 dev_printk(KERN_ERR, &pdev->dev,
902 "32-bit DMA enable failed\n");
905 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
907 dev_printk(KERN_ERR, &pdev->dev,
908 "32-bit consistent DMA enable failed\n");
913 for (i = 0; i < probe_ent->n_ports; i++) {
914 #if 0 /* BIOSen initialize this incorrectly */
915 if (!(hpriv->port_map & (1 << i)))
919 port_mmio = ahci_port_base(mmio, i);
920 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
922 ahci_setup_port(&probe_ent->port[i],
923 (unsigned long) mmio, i);
925 /* make sure port is not active */
926 tmp = readl(port_mmio + PORT_CMD);
927 VPRINTK("PORT_CMD 0x%x\n", tmp);
928 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
929 PORT_CMD_FIS_RX | PORT_CMD_START)) {
930 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
931 PORT_CMD_FIS_RX | PORT_CMD_START);
932 writel(tmp, port_mmio + PORT_CMD);
933 readl(port_mmio + PORT_CMD); /* flush */
935 /* spec says 500 msecs for each bit, so
936 * this is slightly incorrect.
941 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
946 tmp = readl(port_mmio + PORT_SCR_STAT);
947 if ((tmp & 0xf) == 0x3)
952 tmp = readl(port_mmio + PORT_SCR_ERR);
953 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
954 writel(tmp, port_mmio + PORT_SCR_ERR);
956 /* ack any pending irq events for this port */
957 tmp = readl(port_mmio + PORT_IRQ_STAT);
958 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
960 writel(tmp, port_mmio + PORT_IRQ_STAT);
962 writel(1 << i, mmio + HOST_IRQ_STAT);
964 /* set irq mask (enables interrupts) */
965 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
968 tmp = readl(mmio + HOST_CTL);
969 VPRINTK("HOST_CTL 0x%x\n", tmp);
970 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
971 tmp = readl(mmio + HOST_CTL);
972 VPRINTK("HOST_CTL 0x%x\n", tmp);
974 pci_set_master(pdev);
979 static void ahci_print_info(struct ata_probe_ent *probe_ent)
981 struct ahci_host_priv *hpriv = probe_ent->private_data;
982 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
983 void __iomem *mmio = probe_ent->mmio_base;
984 u32 vers, cap, impl, speed;
989 vers = readl(mmio + HOST_VERSION);
991 impl = hpriv->port_map;
993 speed = (cap >> 20) & 0xf;
1001 pci_read_config_word(pdev, 0x0a, &cc);
1004 else if (cc == 0x0106)
1006 else if (cc == 0x0104)
1011 dev_printk(KERN_INFO, &pdev->dev,
1012 "AHCI %02x%02x.%02x%02x "
1013 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1016 (vers >> 24) & 0xff,
1017 (vers >> 16) & 0xff,
1021 ((cap >> 8) & 0x1f) + 1,
1027 dev_printk(KERN_INFO, &pdev->dev,
1033 cap & (1 << 31) ? "64bit " : "",
1034 cap & (1 << 30) ? "ncq " : "",
1035 cap & (1 << 28) ? "ilck " : "",
1036 cap & (1 << 27) ? "stag " : "",
1037 cap & (1 << 26) ? "pm " : "",
1038 cap & (1 << 25) ? "led " : "",
1040 cap & (1 << 24) ? "clo " : "",
1041 cap & (1 << 19) ? "nz " : "",
1042 cap & (1 << 18) ? "only " : "",
1043 cap & (1 << 17) ? "pmp " : "",
1044 cap & (1 << 15) ? "pio " : "",
1045 cap & (1 << 14) ? "slum " : "",
1046 cap & (1 << 13) ? "part " : ""
1050 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1052 static int printed_version;
1053 struct ata_probe_ent *probe_ent = NULL;
1054 struct ahci_host_priv *hpriv;
1056 void __iomem *mmio_base;
1057 unsigned int board_idx = (unsigned int) ent->driver_data;
1058 int have_msi, pci_dev_busy = 0;
1063 if (!printed_version++)
1064 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1066 rc = pci_enable_device(pdev);
1070 rc = pci_request_regions(pdev, DRV_NAME);
1076 if (pci_enable_msi(pdev) == 0)
1083 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1084 if (probe_ent == NULL) {
1089 memset(probe_ent, 0, sizeof(*probe_ent));
1090 probe_ent->dev = pci_dev_to_dev(pdev);
1091 INIT_LIST_HEAD(&probe_ent->node);
1093 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1094 if (mmio_base == NULL) {
1096 goto err_out_free_ent;
1098 base = (unsigned long) mmio_base;
1100 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1103 goto err_out_iounmap;
1105 memset(hpriv, 0, sizeof(*hpriv));
1107 probe_ent->sht = ahci_port_info[board_idx].sht;
1108 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1109 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1110 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1111 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1113 probe_ent->irq = pdev->irq;
1114 probe_ent->irq_flags = SA_SHIRQ;
1115 probe_ent->mmio_base = mmio_base;
1116 probe_ent->private_data = hpriv;
1119 hpriv->flags |= AHCI_FLAG_MSI;
1121 /* JMicron-specific fixup: make sure we're in AHCI mode */
1122 if (pdev->vendor == 0x197b)
1123 pci_write_config_byte(pdev, 0x41, 0xa1);
1125 /* initialize adapter */
1126 rc = ahci_host_init(probe_ent);
1130 ahci_print_info(probe_ent);
1132 /* FIXME: check ata_device_add return value */
1133 ata_device_add(probe_ent);
1141 pci_iounmap(pdev, mmio_base);
1146 pci_disable_msi(pdev);
1149 pci_release_regions(pdev);
1152 pci_disable_device(pdev);
1156 static void ahci_remove_one (struct pci_dev *pdev)
1158 struct device *dev = pci_dev_to_dev(pdev);
1159 struct ata_host_set *host_set = dev_get_drvdata(dev);
1160 struct ahci_host_priv *hpriv = host_set->private_data;
1161 struct ata_port *ap;
1165 for (i = 0; i < host_set->n_ports; i++) {
1166 ap = host_set->ports[i];
1168 scsi_remove_host(ap->host);
1171 have_msi = hpriv->flags & AHCI_FLAG_MSI;
1172 free_irq(host_set->irq, host_set);
1174 for (i = 0; i < host_set->n_ports; i++) {
1175 ap = host_set->ports[i];
1177 ata_scsi_release(ap->host);
1178 scsi_host_put(ap->host);
1182 pci_iounmap(pdev, host_set->mmio_base);
1186 pci_disable_msi(pdev);
1189 pci_release_regions(pdev);
1190 pci_disable_device(pdev);
1191 dev_set_drvdata(dev, NULL);
1194 static int __init ahci_init(void)
1196 return pci_module_init(&ahci_pci_driver);
1199 static void __exit ahci_exit(void)
1201 pci_unregister_driver(&ahci_pci_driver);
1205 MODULE_AUTHOR("Jeff Garzik");
1206 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1207 MODULE_LICENSE("GPL");
1208 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1209 MODULE_VERSION(DRV_VERSION);
1211 module_init(ahci_init);
1212 module_exit(ahci_exit);