2 * ahci.c - AHCI SATA support
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2004-2005 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/device.h>
45 #include <scsi/scsi_host.h>
46 #include <scsi/scsi_cmnd.h>
47 #include <linux/libata.h>
50 #define DRV_NAME "ahci"
51 #define DRV_VERSION "2.0"
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
61 AHCI_CMD_SLOT_SZ = AHCI_MAX_CMDS * AHCI_CMD_SZ,
63 AHCI_CMD_TBL_CDB = 0x40,
64 AHCI_CMD_TBL_HDR_SZ = 0x80,
65 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR_SZ + (AHCI_MAX_SG * 16),
66 AHCI_CMD_TBL_AR_SZ = AHCI_CMD_TBL_SZ * AHCI_MAX_CMDS,
67 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_AR_SZ +
69 AHCI_IRQ_ON_SG = (1 << 31),
70 AHCI_CMD_ATAPI = (1 << 5),
71 AHCI_CMD_WRITE = (1 << 6),
72 AHCI_CMD_PREFETCH = (1 << 7),
73 AHCI_CMD_RESET = (1 << 8),
74 AHCI_CMD_CLR_BUSY = (1 << 10),
76 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
77 RX_FIS_UNK = 0x60, /* offset of Unknown FIS data */
80 board_ahci_vt8251 = 1,
82 /* global controller registers */
83 HOST_CAP = 0x00, /* host capabilities */
84 HOST_CTL = 0x04, /* global host control */
85 HOST_IRQ_STAT = 0x08, /* interrupt status */
86 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
87 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
90 HOST_RESET = (1 << 0), /* reset controller; self-clear */
91 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
92 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
95 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
96 HOST_CAP_NCQ = (1 << 30), /* Native Command Queueing */
97 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
99 /* registers for each SATA port */
100 PORT_LST_ADDR = 0x00, /* command list DMA addr */
101 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
102 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
103 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
104 PORT_IRQ_STAT = 0x10, /* interrupt status */
105 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
106 PORT_CMD = 0x18, /* port command */
107 PORT_TFDATA = 0x20, /* taskfile data */
108 PORT_SIG = 0x24, /* device TF signature */
109 PORT_CMD_ISSUE = 0x38, /* command issue */
110 PORT_SCR = 0x28, /* SATA phy register block */
111 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
112 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
113 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
114 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
116 /* PORT_IRQ_{STAT,MASK} bits */
117 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
118 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
119 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
120 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
121 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
122 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
123 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
124 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
126 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
127 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
128 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
129 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
130 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
131 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
132 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
133 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
134 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
136 PORT_IRQ_FREEZE = PORT_IRQ_HBUS_ERR |
141 PORT_IRQ_ERROR = PORT_IRQ_FREEZE |
143 PORT_IRQ_HBUS_DATA_ERR,
144 DEF_PORT_IRQ = PORT_IRQ_ERROR | PORT_IRQ_SG_DONE |
145 PORT_IRQ_SDB_FIS | PORT_IRQ_DMAS_FIS |
146 PORT_IRQ_PIOS_FIS | PORT_IRQ_D2H_REG_FIS,
149 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
150 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
151 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
152 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
153 PORT_CMD_CLO = (1 << 3), /* Command list override */
154 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
155 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
156 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
158 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
159 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
160 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
162 /* hpriv->flags bits */
163 AHCI_FLAG_MSI = (1 << 0),
166 AHCI_FLAG_RESET_NEEDS_CLO = (1 << 24),
167 AHCI_FLAG_NO_NCQ = (1 << 25),
170 struct ahci_cmd_hdr {
185 struct ahci_host_priv {
187 u32 cap; /* cache of HOST_CAP register */
188 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
191 struct ahci_port_priv {
192 struct ahci_cmd_hdr *cmd_slot;
193 dma_addr_t cmd_slot_dma;
195 dma_addr_t cmd_tbl_dma;
197 dma_addr_t rx_fis_dma;
200 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
201 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
202 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
203 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
204 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
205 static void ahci_irq_clear(struct ata_port *ap);
206 static int ahci_port_start(struct ata_port *ap);
207 static void ahci_port_stop(struct ata_port *ap);
208 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
209 static void ahci_qc_prep(struct ata_queued_cmd *qc);
210 static u8 ahci_check_status(struct ata_port *ap);
211 static void ahci_freeze(struct ata_port *ap);
212 static void ahci_thaw(struct ata_port *ap);
213 static void ahci_error_handler(struct ata_port *ap);
214 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc);
215 static void ahci_remove_one (struct pci_dev *pdev);
217 static struct scsi_host_template ahci_sht = {
218 .module = THIS_MODULE,
220 .ioctl = ata_scsi_ioctl,
221 .queuecommand = ata_scsi_queuecmd,
222 .change_queue_depth = ata_scsi_change_queue_depth,
223 .can_queue = AHCI_MAX_CMDS - 1,
224 .this_id = ATA_SHT_THIS_ID,
225 .sg_tablesize = AHCI_MAX_SG,
226 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
227 .emulated = ATA_SHT_EMULATED,
228 .use_clustering = AHCI_USE_CLUSTERING,
229 .proc_name = DRV_NAME,
230 .dma_boundary = AHCI_DMA_BOUNDARY,
231 .slave_configure = ata_scsi_slave_config,
232 .slave_destroy = ata_scsi_slave_destroy,
233 .bios_param = ata_std_bios_param,
236 static const struct ata_port_operations ahci_ops = {
237 .port_disable = ata_port_disable,
239 .check_status = ahci_check_status,
240 .check_altstatus = ahci_check_status,
241 .dev_select = ata_noop_dev_select,
243 .tf_read = ahci_tf_read,
245 .qc_prep = ahci_qc_prep,
246 .qc_issue = ahci_qc_issue,
248 .irq_handler = ahci_interrupt,
249 .irq_clear = ahci_irq_clear,
251 .scr_read = ahci_scr_read,
252 .scr_write = ahci_scr_write,
254 .freeze = ahci_freeze,
257 .error_handler = ahci_error_handler,
258 .post_internal_cmd = ahci_post_internal_cmd,
260 .port_start = ahci_port_start,
261 .port_stop = ahci_port_stop,
264 static const struct ata_port_info ahci_port_info[] = {
268 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
269 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
270 ATA_FLAG_SKIP_D2H_BSY,
271 .pio_mask = 0x1f, /* pio0-4 */
272 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
273 .port_ops = &ahci_ops,
275 /* board_ahci_vt8251 */
278 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
279 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
280 ATA_FLAG_SKIP_D2H_BSY |
281 AHCI_FLAG_RESET_NEEDS_CLO | AHCI_FLAG_NO_NCQ,
282 .pio_mask = 0x1f, /* pio0-4 */
283 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
284 .port_ops = &ahci_ops,
288 static const struct pci_device_id ahci_pci_tbl[] = {
290 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
291 board_ahci }, /* ICH6 */
292 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
293 board_ahci }, /* ICH6M */
294 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
295 board_ahci }, /* ICH7 */
296 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
297 board_ahci }, /* ICH7M */
298 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
299 board_ahci }, /* ICH7R */
300 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
301 board_ahci }, /* ULi M5288 */
302 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
303 board_ahci }, /* ESB2 */
304 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
305 board_ahci }, /* ESB2 */
306 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
307 board_ahci }, /* ESB2 */
308 { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
309 board_ahci }, /* ICH7-M DH */
310 { PCI_VENDOR_ID_INTEL, 0x2821, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
311 board_ahci }, /* ICH8 */
312 { PCI_VENDOR_ID_INTEL, 0x2822, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
313 board_ahci }, /* ICH8 */
314 { PCI_VENDOR_ID_INTEL, 0x2824, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
315 board_ahci }, /* ICH8 */
316 { PCI_VENDOR_ID_INTEL, 0x2829, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
317 board_ahci }, /* ICH8M */
318 { PCI_VENDOR_ID_INTEL, 0x282a, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
319 board_ahci }, /* ICH8M */
322 { 0x197b, 0x2360, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
323 board_ahci }, /* JMicron JMB360 */
324 { 0x197b, 0x2361, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
325 board_ahci }, /* JMicron JMB361 */
326 { 0x197b, 0x2363, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
327 board_ahci }, /* JMicron JMB363 */
328 { 0x197b, 0x2365, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
329 board_ahci }, /* JMicron JMB365 */
330 { 0x197b, 0x2366, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
331 board_ahci }, /* JMicron JMB366 */
334 { PCI_VENDOR_ID_ATI, 0x4380, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
335 board_ahci }, /* ATI SB600 non-raid */
336 { PCI_VENDOR_ID_ATI, 0x4381, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
337 board_ahci }, /* ATI SB600 raid */
340 { PCI_VENDOR_ID_VIA, 0x3349, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
341 board_ahci_vt8251 }, /* VIA VT8251 */
344 { PCI_VENDOR_ID_NVIDIA, 0x044c, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
345 board_ahci }, /* MCP65 */
346 { PCI_VENDOR_ID_NVIDIA, 0x044d, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
347 board_ahci }, /* MCP65 */
348 { PCI_VENDOR_ID_NVIDIA, 0x044e, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
349 board_ahci }, /* MCP65 */
350 { PCI_VENDOR_ID_NVIDIA, 0x044f, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
351 board_ahci }, /* MCP65 */
353 { } /* terminate list */
357 static struct pci_driver ahci_pci_driver = {
359 .id_table = ahci_pci_tbl,
360 .probe = ahci_init_one,
361 .remove = ahci_remove_one,
365 static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
367 return base + 0x100 + (port * 0x80);
370 static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
372 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
375 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
380 case SCR_STATUS: sc_reg = 0; break;
381 case SCR_CONTROL: sc_reg = 1; break;
382 case SCR_ERROR: sc_reg = 2; break;
383 case SCR_ACTIVE: sc_reg = 3; break;
388 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
392 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
398 case SCR_STATUS: sc_reg = 0; break;
399 case SCR_CONTROL: sc_reg = 1; break;
400 case SCR_ERROR: sc_reg = 2; break;
401 case SCR_ACTIVE: sc_reg = 3; break;
406 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
409 static void ahci_start_engine(void __iomem *port_mmio)
414 tmp = readl(port_mmio + PORT_CMD);
415 tmp |= PORT_CMD_START;
416 writel(tmp, port_mmio + PORT_CMD);
417 readl(port_mmio + PORT_CMD); /* flush */
420 static int ahci_stop_engine(void __iomem *port_mmio)
424 tmp = readl(port_mmio + PORT_CMD);
426 /* check if the HBA is idle */
427 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
430 /* setting HBA to idle */
431 tmp &= ~PORT_CMD_START;
432 writel(tmp, port_mmio + PORT_CMD);
434 /* wait for engine to stop. This could be as long as 500 msec */
435 tmp = ata_wait_register(port_mmio + PORT_CMD,
436 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
437 if (tmp & PORT_CMD_LIST_ON)
443 static unsigned int ahci_dev_classify(struct ata_port *ap)
445 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
446 struct ata_taskfile tf;
449 tmp = readl(port_mmio + PORT_SIG);
450 tf.lbah = (tmp >> 24) & 0xff;
451 tf.lbam = (tmp >> 16) & 0xff;
452 tf.lbal = (tmp >> 8) & 0xff;
453 tf.nsect = (tmp) & 0xff;
455 return ata_dev_classify(&tf);
458 static void ahci_fill_cmd_slot(struct ahci_port_priv *pp, unsigned int tag,
461 dma_addr_t cmd_tbl_dma;
463 cmd_tbl_dma = pp->cmd_tbl_dma + tag * AHCI_CMD_TBL_SZ;
465 pp->cmd_slot[tag].opts = cpu_to_le32(opts);
466 pp->cmd_slot[tag].status = 0;
467 pp->cmd_slot[tag].tbl_addr = cpu_to_le32(cmd_tbl_dma & 0xffffffff);
468 pp->cmd_slot[tag].tbl_addr_hi = cpu_to_le32((cmd_tbl_dma >> 16) >> 16);
471 static int ahci_clo(struct ata_port *ap)
473 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
474 struct ahci_host_priv *hpriv = ap->host_set->private_data;
477 if (!(hpriv->cap & HOST_CAP_CLO))
480 tmp = readl(port_mmio + PORT_CMD);
482 writel(tmp, port_mmio + PORT_CMD);
484 tmp = ata_wait_register(port_mmio + PORT_CMD,
485 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
486 if (tmp & PORT_CMD_CLO)
492 static int ahci_prereset(struct ata_port *ap)
494 if ((ap->flags & AHCI_FLAG_RESET_NEEDS_CLO) &&
495 (ata_busy_wait(ap, ATA_BUSY, 1000) & ATA_BUSY)) {
496 /* ATA_BUSY hasn't cleared, so send a CLO */
500 return ata_std_prereset(ap);
503 static int ahci_softreset(struct ata_port *ap, unsigned int *class)
505 struct ahci_port_priv *pp = ap->private_data;
506 void __iomem *mmio = ap->host_set->mmio_base;
507 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
508 const u32 cmd_fis_len = 5; /* five dwords */
509 const char *reason = NULL;
510 struct ata_taskfile tf;
517 if (ata_port_offline(ap)) {
518 DPRINTK("PHY reports no device\n");
519 *class = ATA_DEV_NONE;
523 /* prepare for SRST (AHCI-1.1 10.4.1) */
524 rc = ahci_stop_engine(port_mmio);
526 reason = "failed to stop engine";
530 /* check BUSY/DRQ, perform Command List Override if necessary */
531 ahci_tf_read(ap, &tf);
532 if (tf.command & (ATA_BUSY | ATA_DRQ)) {
535 if (rc == -EOPNOTSUPP) {
536 reason = "port busy but CLO unavailable";
539 reason = "port busy but CLO failed";
545 ahci_start_engine(port_mmio);
547 ata_tf_init(ap->device, &tf);
550 /* issue the first D2H Register FIS */
551 ahci_fill_cmd_slot(pp, 0,
552 cmd_fis_len | AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY);
555 ata_tf_to_fis(&tf, fis, 0);
556 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
558 writel(1, port_mmio + PORT_CMD_ISSUE);
560 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1, 1, 500);
563 reason = "1st FIS failed";
567 /* spec says at least 5us, but be generous and sleep for 1ms */
570 /* issue the second D2H Register FIS */
571 ahci_fill_cmd_slot(pp, 0, cmd_fis_len);
574 ata_tf_to_fis(&tf, fis, 0);
575 fis[1] &= ~(1 << 7); /* turn off Command FIS bit */
577 writel(1, port_mmio + PORT_CMD_ISSUE);
578 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
580 /* spec mandates ">= 2ms" before checking status.
581 * We wait 150ms, because that was the magic delay used for
582 * ATAPI devices in Hale Landis's ATADRVR, for the period of time
583 * between when the ATA command register is written, and then
584 * status is checked. Because waiting for "a while" before
585 * checking status is fine, post SRST, we perform this magic
586 * delay here as well.
590 *class = ATA_DEV_NONE;
591 if (ata_port_online(ap)) {
592 if (ata_busy_sleep(ap, ATA_TMOUT_BOOT_QUICK, ATA_TMOUT_BOOT)) {
594 reason = "device not ready";
597 *class = ahci_dev_classify(ap);
600 DPRINTK("EXIT, class=%u\n", *class);
604 ahci_start_engine(port_mmio);
606 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
610 static int ahci_hardreset(struct ata_port *ap, unsigned int *class)
612 struct ahci_port_priv *pp = ap->private_data;
613 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
614 struct ata_taskfile tf;
615 void __iomem *mmio = ap->host_set->mmio_base;
616 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
621 ahci_stop_engine(port_mmio);
623 /* clear D2H reception area to properly wait for D2H FIS */
624 ata_tf_init(ap->device, &tf);
626 ata_tf_to_fis(&tf, d2h_fis, 0);
628 rc = sata_std_hardreset(ap, class);
630 ahci_start_engine(port_mmio);
632 if (rc == 0 && ata_port_online(ap))
633 *class = ahci_dev_classify(ap);
634 if (*class == ATA_DEV_UNKNOWN)
635 *class = ATA_DEV_NONE;
637 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
641 static void ahci_postreset(struct ata_port *ap, unsigned int *class)
643 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
646 ata_std_postreset(ap, class);
648 /* Make sure port's ATAPI bit is set appropriately */
649 new_tmp = tmp = readl(port_mmio + PORT_CMD);
650 if (*class == ATA_DEV_ATAPI)
651 new_tmp |= PORT_CMD_ATAPI;
653 new_tmp &= ~PORT_CMD_ATAPI;
654 if (new_tmp != tmp) {
655 writel(new_tmp, port_mmio + PORT_CMD);
656 readl(port_mmio + PORT_CMD); /* flush */
660 static u8 ahci_check_status(struct ata_port *ap)
662 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
664 return readl(mmio + PORT_TFDATA) & 0xFF;
667 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
669 struct ahci_port_priv *pp = ap->private_data;
670 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
672 ata_tf_from_fis(d2h_fis, tf);
675 static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc, void *cmd_tbl)
677 struct scatterlist *sg;
678 struct ahci_sg *ahci_sg;
679 unsigned int n_sg = 0;
684 * Next, the S/G list.
686 ahci_sg = cmd_tbl + AHCI_CMD_TBL_HDR_SZ;
687 ata_for_each_sg(sg, qc) {
688 dma_addr_t addr = sg_dma_address(sg);
689 u32 sg_len = sg_dma_len(sg);
691 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
692 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
693 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
702 static void ahci_qc_prep(struct ata_queued_cmd *qc)
704 struct ata_port *ap = qc->ap;
705 struct ahci_port_priv *pp = ap->private_data;
706 int is_atapi = is_atapi_taskfile(&qc->tf);
709 const u32 cmd_fis_len = 5; /* five dwords */
713 * Fill in command table information. First, the header,
714 * a SATA Register - Host to Device command FIS.
716 cmd_tbl = pp->cmd_tbl + qc->tag * AHCI_CMD_TBL_SZ;
718 ata_tf_to_fis(&qc->tf, cmd_tbl, 0);
720 memset(cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
721 memcpy(cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, qc->dev->cdb_len);
725 if (qc->flags & ATA_QCFLAG_DMAMAP)
726 n_elem = ahci_fill_sg(qc, cmd_tbl);
729 * Fill in command slot information.
731 opts = cmd_fis_len | n_elem << 16;
732 if (qc->tf.flags & ATA_TFLAG_WRITE)
733 opts |= AHCI_CMD_WRITE;
735 opts |= AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH;
737 ahci_fill_cmd_slot(pp, qc->tag, opts);
740 static void ahci_error_intr(struct ata_port *ap, u32 irq_stat)
742 struct ahci_port_priv *pp = ap->private_data;
743 struct ata_eh_info *ehi = &ap->eh_info;
744 unsigned int err_mask = 0, action = 0;
745 struct ata_queued_cmd *qc;
748 ata_ehi_clear_desc(ehi);
750 /* AHCI needs SError cleared; otherwise, it might lock up */
751 serror = ahci_scr_read(ap, SCR_ERROR);
752 ahci_scr_write(ap, SCR_ERROR, serror);
754 /* analyze @irq_stat */
755 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
757 if (irq_stat & PORT_IRQ_TF_ERR)
758 err_mask |= AC_ERR_DEV;
760 if (irq_stat & (PORT_IRQ_HBUS_ERR | PORT_IRQ_HBUS_DATA_ERR)) {
761 err_mask |= AC_ERR_HOST_BUS;
762 action |= ATA_EH_SOFTRESET;
765 if (irq_stat & PORT_IRQ_IF_ERR) {
766 err_mask |= AC_ERR_ATA_BUS;
767 action |= ATA_EH_SOFTRESET;
768 ata_ehi_push_desc(ehi, ", interface fatal error");
771 if (irq_stat & (PORT_IRQ_CONNECT | PORT_IRQ_PHYRDY)) {
772 ata_ehi_hotplugged(ehi);
773 ata_ehi_push_desc(ehi, ", %s", irq_stat & PORT_IRQ_CONNECT ?
774 "connection status changed" : "PHY RDY changed");
777 if (irq_stat & PORT_IRQ_UNK_FIS) {
778 u32 *unk = (u32 *)(pp->rx_fis + RX_FIS_UNK);
780 err_mask |= AC_ERR_HSM;
781 action |= ATA_EH_SOFTRESET;
782 ata_ehi_push_desc(ehi, ", unknown FIS %08x %08x %08x %08x",
783 unk[0], unk[1], unk[2], unk[3]);
786 /* okay, let's hand over to EH */
787 ehi->serror |= serror;
788 ehi->action |= action;
790 qc = ata_qc_from_tag(ap, ap->active_tag);
792 qc->err_mask |= err_mask;
794 ehi->err_mask |= err_mask;
796 if (irq_stat & PORT_IRQ_FREEZE)
802 static void ahci_host_intr(struct ata_port *ap)
804 void __iomem *mmio = ap->host_set->mmio_base;
805 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
806 struct ata_eh_info *ehi = &ap->eh_info;
807 u32 status, qc_active;
810 status = readl(port_mmio + PORT_IRQ_STAT);
811 writel(status, port_mmio + PORT_IRQ_STAT);
813 if (unlikely(status & PORT_IRQ_ERROR)) {
814 ahci_error_intr(ap, status);
819 qc_active = readl(port_mmio + PORT_SCR_ACT);
821 qc_active = readl(port_mmio + PORT_CMD_ISSUE);
823 rc = ata_qc_complete_multiple(ap, qc_active, NULL);
827 ehi->err_mask |= AC_ERR_HSM;
828 ehi->action |= ATA_EH_SOFTRESET;
833 /* hmmm... a spurious interupt */
835 /* some devices send D2H reg with I bit set during NCQ command phase */
836 if (ap->sactive && status & PORT_IRQ_D2H_REG_FIS)
839 /* ignore interim PIO setup fis interrupts */
840 if (ata_tag_valid(ap->active_tag)) {
841 struct ata_queued_cmd *qc =
842 ata_qc_from_tag(ap, ap->active_tag);
844 if (qc && qc->tf.protocol == ATA_PROT_PIO &&
845 (status & PORT_IRQ_PIOS_FIS))
850 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
851 "(irq_stat 0x%x active_tag %d sactive 0x%x)\n",
852 status, ap->active_tag, ap->sactive);
855 static void ahci_irq_clear(struct ata_port *ap)
860 static irqreturn_t ahci_interrupt(int irq, void *dev_instance, struct pt_regs *regs)
862 struct ata_host_set *host_set = dev_instance;
863 struct ahci_host_priv *hpriv;
864 unsigned int i, handled = 0;
866 u32 irq_stat, irq_ack = 0;
870 hpriv = host_set->private_data;
871 mmio = host_set->mmio_base;
873 /* sigh. 0xffffffff is a valid return from h/w */
874 irq_stat = readl(mmio + HOST_IRQ_STAT);
875 irq_stat &= hpriv->port_map;
879 spin_lock(&host_set->lock);
881 for (i = 0; i < host_set->n_ports; i++) {
884 if (!(irq_stat & (1 << i)))
887 ap = host_set->ports[i];
890 VPRINTK("port %u\n", i);
892 VPRINTK("port %u (no irq)\n", i);
894 dev_printk(KERN_WARNING, host_set->dev,
895 "interrupt on disabled port %u\n", i);
902 writel(irq_ack, mmio + HOST_IRQ_STAT);
906 spin_unlock(&host_set->lock);
910 return IRQ_RETVAL(handled);
913 static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
915 struct ata_port *ap = qc->ap;
916 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
918 if (qc->tf.protocol == ATA_PROT_NCQ)
919 writel(1 << qc->tag, port_mmio + PORT_SCR_ACT);
920 writel(1 << qc->tag, port_mmio + PORT_CMD_ISSUE);
921 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
926 static void ahci_freeze(struct ata_port *ap)
928 void __iomem *mmio = ap->host_set->mmio_base;
929 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
932 writel(0, port_mmio + PORT_IRQ_MASK);
935 static void ahci_thaw(struct ata_port *ap)
937 void __iomem *mmio = ap->host_set->mmio_base;
938 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
942 tmp = readl(port_mmio + PORT_IRQ_STAT);
943 writel(tmp, port_mmio + PORT_IRQ_STAT);
944 writel(1 << ap->id, mmio + HOST_IRQ_STAT);
946 /* turn IRQ back on */
947 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
950 static void ahci_error_handler(struct ata_port *ap)
952 void __iomem *mmio = ap->host_set->mmio_base;
953 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
955 if (!(ap->pflags & ATA_PFLAG_FROZEN)) {
957 ahci_stop_engine(port_mmio);
958 ahci_start_engine(port_mmio);
961 /* perform recovery */
962 ata_do_eh(ap, ahci_prereset, ahci_softreset, ahci_hardreset,
966 static void ahci_post_internal_cmd(struct ata_queued_cmd *qc)
968 struct ata_port *ap = qc->ap;
969 void __iomem *mmio = ap->host_set->mmio_base;
970 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
972 if (qc->flags & ATA_QCFLAG_FAILED)
973 qc->err_mask |= AC_ERR_OTHER;
976 /* make DMA engine forget about the failed command */
977 ahci_stop_engine(port_mmio);
978 ahci_start_engine(port_mmio);
982 static int ahci_port_start(struct ata_port *ap)
984 struct device *dev = ap->host_set->dev;
985 struct ahci_host_priv *hpriv = ap->host_set->private_data;
986 struct ahci_port_priv *pp;
987 void __iomem *mmio = ap->host_set->mmio_base;
988 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
993 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
996 memset(pp, 0, sizeof(*pp));
998 rc = ata_pad_alloc(ap, dev);
1004 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
1006 ata_pad_free(ap, dev);
1010 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
1013 * First item in chunk of DMA memory: 32-slot command table,
1014 * 32 bytes each in size
1017 pp->cmd_slot_dma = mem_dma;
1019 mem += AHCI_CMD_SLOT_SZ;
1020 mem_dma += AHCI_CMD_SLOT_SZ;
1023 * Second item: Received-FIS area
1026 pp->rx_fis_dma = mem_dma;
1028 mem += AHCI_RX_FIS_SZ;
1029 mem_dma += AHCI_RX_FIS_SZ;
1032 * Third item: data area for storing a single command
1033 * and its scatter-gather table
1036 pp->cmd_tbl_dma = mem_dma;
1038 ap->private_data = pp;
1040 if (hpriv->cap & HOST_CAP_64)
1041 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
1042 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
1043 readl(port_mmio + PORT_LST_ADDR); /* flush */
1045 if (hpriv->cap & HOST_CAP_64)
1046 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
1047 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
1048 readl(port_mmio + PORT_FIS_ADDR); /* flush */
1050 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
1051 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
1052 PORT_CMD_START, port_mmio + PORT_CMD);
1053 readl(port_mmio + PORT_CMD); /* flush */
1058 static void ahci_port_stop(struct ata_port *ap)
1060 struct device *dev = ap->host_set->dev;
1061 struct ahci_port_priv *pp = ap->private_data;
1062 void __iomem *mmio = ap->host_set->mmio_base;
1063 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1066 tmp = readl(port_mmio + PORT_CMD);
1067 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
1068 writel(tmp, port_mmio + PORT_CMD);
1069 readl(port_mmio + PORT_CMD); /* flush */
1071 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
1072 * this is slightly incorrect.
1076 ap->private_data = NULL;
1077 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
1078 pp->cmd_slot, pp->cmd_slot_dma);
1079 ata_pad_free(ap, dev);
1083 static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
1084 unsigned int port_idx)
1086 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
1087 base = ahci_port_base_ul(base, port_idx);
1088 VPRINTK("base now==0x%lx\n", base);
1090 port->cmd_addr = base;
1091 port->scr_addr = base + PORT_SCR;
1096 static int ahci_host_init(struct ata_probe_ent *probe_ent)
1098 struct ahci_host_priv *hpriv = probe_ent->private_data;
1099 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1100 void __iomem *mmio = probe_ent->mmio_base;
1102 unsigned int i, j, using_dac;
1104 void __iomem *port_mmio;
1106 cap_save = readl(mmio + HOST_CAP);
1107 cap_save &= ( (1<<28) | (1<<17) );
1108 cap_save |= (1 << 27);
1110 /* global controller reset */
1111 tmp = readl(mmio + HOST_CTL);
1112 if ((tmp & HOST_RESET) == 0) {
1113 writel(tmp | HOST_RESET, mmio + HOST_CTL);
1114 readl(mmio + HOST_CTL); /* flush */
1117 /* reset must complete within 1 second, or
1118 * the hardware should be considered fried.
1122 tmp = readl(mmio + HOST_CTL);
1123 if (tmp & HOST_RESET) {
1124 dev_printk(KERN_ERR, &pdev->dev,
1125 "controller reset failed (0x%x)\n", tmp);
1129 writel(HOST_AHCI_EN, mmio + HOST_CTL);
1130 (void) readl(mmio + HOST_CTL); /* flush */
1131 writel(cap_save, mmio + HOST_CAP);
1132 writel(0xf, mmio + HOST_PORTS_IMPL);
1133 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
1135 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
1138 pci_read_config_word(pdev, 0x92, &tmp16);
1140 pci_write_config_word(pdev, 0x92, tmp16);
1143 hpriv->cap = readl(mmio + HOST_CAP);
1144 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
1145 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
1147 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
1148 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
1150 using_dac = hpriv->cap & HOST_CAP_64;
1152 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1153 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1155 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1157 dev_printk(KERN_ERR, &pdev->dev,
1158 "64-bit DMA enable failed\n");
1163 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1165 dev_printk(KERN_ERR, &pdev->dev,
1166 "32-bit DMA enable failed\n");
1169 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1171 dev_printk(KERN_ERR, &pdev->dev,
1172 "32-bit consistent DMA enable failed\n");
1177 for (i = 0; i < probe_ent->n_ports; i++) {
1178 #if 0 /* BIOSen initialize this incorrectly */
1179 if (!(hpriv->port_map & (1 << i)))
1183 port_mmio = ahci_port_base(mmio, i);
1184 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
1186 ahci_setup_port(&probe_ent->port[i],
1187 (unsigned long) mmio, i);
1189 /* make sure port is not active */
1190 tmp = readl(port_mmio + PORT_CMD);
1191 VPRINTK("PORT_CMD 0x%x\n", tmp);
1192 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
1193 PORT_CMD_FIS_RX | PORT_CMD_START)) {
1194 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
1195 PORT_CMD_FIS_RX | PORT_CMD_START);
1196 writel(tmp, port_mmio + PORT_CMD);
1197 readl(port_mmio + PORT_CMD); /* flush */
1199 /* spec says 500 msecs for each bit, so
1200 * this is slightly incorrect.
1205 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
1210 tmp = readl(port_mmio + PORT_SCR_STAT);
1211 if ((tmp & 0xf) == 0x3)
1216 tmp = readl(port_mmio + PORT_SCR_ERR);
1217 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
1218 writel(tmp, port_mmio + PORT_SCR_ERR);
1220 /* ack any pending irq events for this port */
1221 tmp = readl(port_mmio + PORT_IRQ_STAT);
1222 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
1224 writel(tmp, port_mmio + PORT_IRQ_STAT);
1226 writel(1 << i, mmio + HOST_IRQ_STAT);
1229 tmp = readl(mmio + HOST_CTL);
1230 VPRINTK("HOST_CTL 0x%x\n", tmp);
1231 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
1232 tmp = readl(mmio + HOST_CTL);
1233 VPRINTK("HOST_CTL 0x%x\n", tmp);
1235 pci_set_master(pdev);
1240 static void ahci_print_info(struct ata_probe_ent *probe_ent)
1242 struct ahci_host_priv *hpriv = probe_ent->private_data;
1243 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1244 void __iomem *mmio = probe_ent->mmio_base;
1245 u32 vers, cap, impl, speed;
1246 const char *speed_s;
1250 vers = readl(mmio + HOST_VERSION);
1252 impl = hpriv->port_map;
1254 speed = (cap >> 20) & 0xf;
1257 else if (speed == 2)
1262 pci_read_config_word(pdev, 0x0a, &cc);
1265 else if (cc == 0x0106)
1267 else if (cc == 0x0104)
1272 dev_printk(KERN_INFO, &pdev->dev,
1273 "AHCI %02x%02x.%02x%02x "
1274 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1277 (vers >> 24) & 0xff,
1278 (vers >> 16) & 0xff,
1282 ((cap >> 8) & 0x1f) + 1,
1288 dev_printk(KERN_INFO, &pdev->dev,
1294 cap & (1 << 31) ? "64bit " : "",
1295 cap & (1 << 30) ? "ncq " : "",
1296 cap & (1 << 28) ? "ilck " : "",
1297 cap & (1 << 27) ? "stag " : "",
1298 cap & (1 << 26) ? "pm " : "",
1299 cap & (1 << 25) ? "led " : "",
1301 cap & (1 << 24) ? "clo " : "",
1302 cap & (1 << 19) ? "nz " : "",
1303 cap & (1 << 18) ? "only " : "",
1304 cap & (1 << 17) ? "pmp " : "",
1305 cap & (1 << 15) ? "pio " : "",
1306 cap & (1 << 14) ? "slum " : "",
1307 cap & (1 << 13) ? "part " : ""
1311 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1313 static int printed_version;
1314 struct ata_probe_ent *probe_ent = NULL;
1315 struct ahci_host_priv *hpriv;
1317 void __iomem *mmio_base;
1318 unsigned int board_idx = (unsigned int) ent->driver_data;
1319 int have_msi, pci_dev_busy = 0;
1324 WARN_ON(ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1326 if (!printed_version++)
1327 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1329 /* JMicron-specific fixup: make sure we're in AHCI mode */
1330 /* This is protected from races with ata_jmicron by the pci probe
1332 if (pdev->vendor == PCI_VENDOR_ID_JMICRON) {
1333 /* AHCI enable, AHCI on function 0 */
1334 pci_write_config_byte(pdev, 0x41, 0xa1);
1335 /* Function 1 is the PATA controller */
1336 if (PCI_FUNC(pdev->devfn))
1340 rc = pci_enable_device(pdev);
1344 rc = pci_request_regions(pdev, DRV_NAME);
1350 if (pci_enable_msi(pdev) == 0)
1357 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1358 if (probe_ent == NULL) {
1363 memset(probe_ent, 0, sizeof(*probe_ent));
1364 probe_ent->dev = pci_dev_to_dev(pdev);
1365 INIT_LIST_HEAD(&probe_ent->node);
1367 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1368 if (mmio_base == NULL) {
1370 goto err_out_free_ent;
1372 base = (unsigned long) mmio_base;
1374 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1377 goto err_out_iounmap;
1379 memset(hpriv, 0, sizeof(*hpriv));
1381 probe_ent->sht = ahci_port_info[board_idx].sht;
1382 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1383 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1384 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1385 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1387 probe_ent->irq = pdev->irq;
1388 probe_ent->irq_flags = IRQF_SHARED;
1389 probe_ent->mmio_base = mmio_base;
1390 probe_ent->private_data = hpriv;
1393 hpriv->flags |= AHCI_FLAG_MSI;
1395 /* initialize adapter */
1396 rc = ahci_host_init(probe_ent);
1400 if (!(probe_ent->host_flags & AHCI_FLAG_NO_NCQ) &&
1401 (hpriv->cap & HOST_CAP_NCQ))
1402 probe_ent->host_flags |= ATA_FLAG_NCQ;
1404 ahci_print_info(probe_ent);
1406 /* FIXME: check ata_device_add return value */
1407 ata_device_add(probe_ent);
1415 pci_iounmap(pdev, mmio_base);
1420 pci_disable_msi(pdev);
1423 pci_release_regions(pdev);
1426 pci_disable_device(pdev);
1430 static void ahci_remove_one (struct pci_dev *pdev)
1432 struct device *dev = pci_dev_to_dev(pdev);
1433 struct ata_host_set *host_set = dev_get_drvdata(dev);
1434 struct ahci_host_priv *hpriv = host_set->private_data;
1438 for (i = 0; i < host_set->n_ports; i++)
1439 ata_port_detach(host_set->ports[i]);
1441 have_msi = hpriv->flags & AHCI_FLAG_MSI;
1442 free_irq(host_set->irq, host_set);
1444 for (i = 0; i < host_set->n_ports; i++) {
1445 struct ata_port *ap = host_set->ports[i];
1447 ata_scsi_release(ap->host);
1448 scsi_host_put(ap->host);
1452 pci_iounmap(pdev, host_set->mmio_base);
1456 pci_disable_msi(pdev);
1459 pci_release_regions(pdev);
1460 pci_disable_device(pdev);
1461 dev_set_drvdata(dev, NULL);
1464 static int __init ahci_init(void)
1466 return pci_module_init(&ahci_pci_driver);
1469 static void __exit ahci_exit(void)
1471 pci_unregister_driver(&ahci_pci_driver);
1475 MODULE_AUTHOR("Jeff Garzik");
1476 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1477 MODULE_LICENSE("GPL");
1478 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1479 MODULE_VERSION(DRV_VERSION);
1481 module_init(ahci_init);
1482 module_exit(ahci_exit);