1 #define ASC_VERSION "3.3K" /* AdvanSys Driver Version */
4 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
6 * Copyright (c) 1995-2000 Advanced System Products, Inc.
7 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that redistributions of source
12 * code retain the above copyright notice and this comment without
15 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
16 * changed its name to ConnectCom Solutions, Inc.
22 Documentation for the AdvanSys Driver
24 A. Linux Kernels Supported by this Driver
25 B. Adapters Supported by this Driver
26 C. Linux source files modified by AdvanSys Driver
28 E. Driver Compile Time Options and Debugging
30 G. Tests to run before releasing new driver
32 I. Known Problems/Fix List
33 J. Credits (Chronological Order)
35 A. Linux Kernels Supported by this Driver
37 This driver has been tested in the following Linux kernels: v2.2.18
38 v2.4.0. The driver is supported on v2.2 and v2.4 kernels and on x86,
39 alpha, and PowerPC platforms.
41 B. Adapters Supported by this Driver
43 AdvanSys (Advanced System Products, Inc.) manufactures the following
44 RISC-based, Bus-Mastering, Fast (10 Mhz) and Ultra (20 Mhz) Narrow
45 (8-bit transfer) SCSI Host Adapters for the ISA, EISA, VL, and PCI
46 buses and RISC-based, Bus-Mastering, Ultra (20 Mhz) Wide (16-bit
47 transfer) SCSI Host Adapters for the PCI bus.
49 The CDB counts below indicate the number of SCSI CDB (Command
50 Descriptor Block) requests that can be stored in the RISC chip
51 cache and board LRAM. A CDB is a single SCSI command. The driver
52 detect routine will display the number of CDBs available for each
53 adapter detected. The number of CDBs used by the driver can be
54 lowered in the BIOS by changing the 'Host Queue Size' adapter setting.
57 ABP-480 - Bus-Master CardBus (16 CDB) (2.4 kernel and greater)
59 Connectivity Products:
60 ABP510/5150 - Bus-Master ISA (240 CDB)
61 ABP5140 - Bus-Master ISA PnP (16 CDB)
62 ABP5142 - Bus-Master ISA PnP with floppy (16 CDB)
63 ABP902/3902 - Bus-Master PCI (16 CDB)
64 ABP3905 - Bus-Master PCI (16 CDB)
65 ABP915 - Bus-Master PCI (16 CDB)
66 ABP920 - Bus-Master PCI (16 CDB)
67 ABP3922 - Bus-Master PCI (16 CDB)
68 ABP3925 - Bus-Master PCI (16 CDB)
69 ABP930 - Bus-Master PCI (16 CDB)
70 ABP930U - Bus-Master PCI Ultra (16 CDB)
71 ABP930UA - Bus-Master PCI Ultra (16 CDB)
72 ABP960 - Bus-Master PCI MAC/PC (16 CDB)
73 ABP960U - Bus-Master PCI MAC/PC Ultra (16 CDB)
75 Single Channel Products:
76 ABP542 - Bus-Master ISA with floppy (240 CDB)
77 ABP742 - Bus-Master EISA (240 CDB)
78 ABP842 - Bus-Master VL (240 CDB)
79 ABP940 - Bus-Master PCI (240 CDB)
80 ABP940U - Bus-Master PCI Ultra (240 CDB)
81 ABP940UA/3940UA - Bus-Master PCI Ultra (240 CDB)
82 ABP970 - Bus-Master PCI MAC/PC (240 CDB)
83 ABP970U - Bus-Master PCI MAC/PC Ultra (240 CDB)
84 ABP3960UA - Bus-Master PCI MAC/PC Ultra (240 CDB)
85 ABP940UW/3940UW - Bus-Master PCI Ultra-Wide (253 CDB)
86 ABP970UW - Bus-Master PCI MAC/PC Ultra-Wide (253 CDB)
87 ABP3940U2W - Bus-Master PCI LVD/Ultra2-Wide (253 CDB)
89 Multi-Channel Products:
90 ABP752 - Dual Channel Bus-Master EISA (240 CDB Per Channel)
91 ABP852 - Dual Channel Bus-Master VL (240 CDB Per Channel)
92 ABP950 - Dual Channel Bus-Master PCI (240 CDB Per Channel)
93 ABP950UW - Dual Channel Bus-Master PCI Ultra-Wide (253 CDB Per Channel)
94 ABP980 - Four Channel Bus-Master PCI (240 CDB Per Channel)
95 ABP980U - Four Channel Bus-Master PCI Ultra (240 CDB Per Channel)
96 ABP980UA/3980UA - Four Channel Bus-Master PCI Ultra (16 CDB Per Chan.)
97 ABP3950U2W - Bus-Master PCI LVD/Ultra2-Wide and Ultra-Wide (253 CDB)
98 ABP3950U3W - Bus-Master PCI Dual LVD2/Ultra3-Wide (253 CDB)
100 C. Linux source files modified by AdvanSys Driver
102 This section for historical purposes documents the changes
103 originally made to the Linux kernel source to add the advansys
104 driver. As Linux has changed some of these files have also
107 1. linux/arch/i386/config.in:
109 bool 'AdvanSys SCSI support' CONFIG_SCSI_ADVANSYS y
111 2. linux/drivers/scsi/hosts.c:
113 #ifdef CONFIG_SCSI_ADVANSYS
114 #include "advansys.h"
117 and after "static Scsi_Host_Template builtin_scsi_hosts[] =":
119 #ifdef CONFIG_SCSI_ADVANSYS
123 3. linux/drivers/scsi/Makefile:
125 ifdef CONFIG_SCSI_ADVANSYS
126 SCSI_SRCS := $(SCSI_SRCS) advansys.c
127 SCSI_OBJS := $(SCSI_OBJS) advansys.o
129 SCSI_MODULE_OBJS := $(SCSI_MODULE_OBJS) advansys.o
132 4. linux/init/main.c:
134 extern void advansys_setup(char *str, int *ints);
136 and add the following lines to the bootsetups[] array.
138 #ifdef CONFIG_SCSI_ADVANSYS
139 { "advansys=", advansys_setup },
144 1. Use tab stops set to 4 for the source files. For vi use 'se tabstops=4'.
146 2. This driver should be maintained in multiple files. But to make
147 it easier to include with Linux and to follow Linux conventions,
148 the whole driver is maintained in the source files advansys.h and
149 advansys.c. In this file logical sections of the driver begin with
150 a comment that contains '---'. The following are the logical sections
154 --- Linux Include File
157 --- Asc Library Constants and Macros
158 --- Adv Library Constants and Macros
159 --- Driver Constants and Macros
160 --- Driver Structures
162 --- Driver Function Prototypes
163 --- Linux 'Scsi_Host_Template' and advansys_setup() Functions
164 --- Loadable Driver Support
165 --- Miscellaneous Driver Functions
166 --- Functions Required by the Asc Library
167 --- Functions Required by the Adv Library
168 --- Tracing and Debugging Functions
169 --- Asc Library Functions
170 --- Adv Library Functions
172 3. The string 'XXX' is used to flag code that needs to be re-written
173 or that contains a problem that needs to be addressed.
175 4. I have stripped comments from and reformatted the source for the
176 Asc Library and Adv Library to reduce the size of this file. This
177 source can be found under the following headings. The Asc Library
178 is used to support Narrow Boards. The Adv Library is used to
181 --- Asc Library Constants and Macros
182 --- Adv Library Constants and Macros
183 --- Asc Library Functions
184 --- Adv Library Functions
186 E. Driver Compile Time Options and Debugging
188 In this source file the following constants can be defined. They are
189 defined in the source below. Both of these options are enabled by
192 1. ADVANSYS_ASSERT - Enable driver assertions (Def: Enabled)
194 Enabling this option adds assertion logic statements to the
195 driver. If an assertion fails a message will be displayed to
196 the console, but the system will continue to operate. Any
197 assertions encountered should be reported to the person
198 responsible for the driver. Assertion statements may proactively
199 detect problems with the driver and facilitate fixing these
200 problems. Enabling assertions will add a small overhead to the
201 execution of the driver.
203 2. ADVANSYS_DEBUG - Enable driver debugging (Def: Disabled)
205 Enabling this option adds tracing functions to the driver and
206 the ability to set a driver tracing level at boot time. This
207 option will also export symbols not required outside the driver to
208 the kernel name space. This option is very useful for debugging
209 the driver, but it will add to the size of the driver execution
210 image and add overhead to the execution of the driver.
212 The amount of debugging output can be controlled with the global
213 variable 'asc_dbglvl'. The higher the number the more output. By
214 default the debug level is 0.
216 If the driver is loaded at boot time and the LILO Driver Option
217 is included in the system, the debug level can be changed by
218 specifying a 5th (ASC_NUM_IOPORT_PROBE + 1) I/O Port. The
219 first three hex digits of the pseudo I/O Port must be set to
220 'deb' and the fourth hex digit specifies the debug level: 0 - F.
221 The following command line will look for an adapter at 0x330
222 and set the debug level to 2.
224 linux advansys=0x330,0,0,0,0xdeb2
226 If the driver is built as a loadable module this variable can be
227 defined when the driver is loaded. The following insmod command
228 will set the debug level to one.
230 insmod advansys.o asc_dbglvl=1
232 Debugging Message Levels:
234 1: High-Level Tracing
237 To enable debug output to console, please make sure that:
239 a. System and kernel logging is enabled (syslogd, klogd running).
240 b. Kernel messages are routed to console output. Check
241 /etc/syslog.conf for an entry similar to this:
245 c. klogd is started with the appropriate -c parameter
248 This will cause printk() messages to be be displayed on the
249 current console. Refer to the klogd(8) and syslogd(8) man pages
252 Alternatively you can enable printk() to console with this
253 program. However, this is not the 'official' way to do this.
254 Debug output is logged in /var/log/messages.
258 syscall(103, 7, 0, 0);
261 Increasing LOG_BUF_LEN in kernel/printk.c to something like
262 40960 allows more debug messages to be buffered in the kernel
263 and written to the console or log file.
265 3. ADVANSYS_STATS - Enable statistics (Def: Enabled >= v1.3.0)
267 Enabling this option adds statistics collection and display
268 through /proc to the driver. The information is useful for
269 monitoring driver and device performance. It will add to the
270 size of the driver execution image and add minor overhead to
271 the execution of the driver.
273 Statistics are maintained on a per adapter basis. Driver entry
274 point call counts and transfer size counts are maintained.
275 Statistics are only available for kernels greater than or equal
276 to v1.3.0 with the CONFIG_PROC_FS (/proc) file system configured.
278 AdvanSys SCSI adapter files have the following path name format:
280 /proc/scsi/advansys/[0-(ASC_NUM_BOARD_SUPPORTED-1)]
282 This information can be displayed with cat. For example:
284 cat /proc/scsi/advansys/0
286 When ADVANSYS_STATS is not defined the AdvanSys /proc files only
287 contain adapter and device configuration information.
289 F. Driver LILO Option
291 If init/main.c is modified as described in the 'Directions for Adding
292 the AdvanSys Driver to Linux' section (B.4.) above, the driver will
293 recognize the 'advansys' LILO command line and /etc/lilo.conf option.
294 This option can be used to either disable I/O port scanning or to limit
295 scanning to 1 - 4 I/O ports. Regardless of the option setting EISA and
296 PCI boards will still be searched for and detected. This option only
297 affects searching for ISA and VL boards.
300 1. Eliminate I/O port scanning:
301 boot: linux advansys=
303 boot: linux advansys=0x0
304 2. Limit I/O port scanning to one I/O port:
305 boot: linux advansys=0x110
306 3. Limit I/O port scanning to four I/O ports:
307 boot: linux advansys=0x110,0x210,0x230,0x330
309 For a loadable module the same effect can be achieved by setting
310 the 'asc_iopflag' variable and 'asc_ioport' array when loading
313 insmod advansys.o asc_iopflag=1 asc_ioport=0x110,0x330
315 If ADVANSYS_DEBUG is defined a 5th (ASC_NUM_IOPORT_PROBE + 1)
316 I/O Port may be added to specify the driver debug level. Refer to
317 the 'Driver Compile Time Options and Debugging' section above for
320 G. Tests to run before releasing new driver
322 1. In the supported kernels verify there are no warning or compile
323 errors when the kernel is built as both a driver and as a module
324 and with the following options:
326 ADVANSYS_DEBUG - enabled and disabled
327 CONFIG_SMP - enabled and disabled
328 CONFIG_PROC_FS - enabled and disabled
330 2. Run tests on an x86, alpha, and PowerPC with at least one narrow
331 card and one wide card attached to a hard disk and CD-ROM drive:
332 fdisk, mkfs, fsck, bonnie, copy/compare test from the
333 CD-ROM to the hard drive.
341 1. Prevent advansys_detect() from being called twice.
342 2. Add LILO 0xdeb[0-f] option to set 'asc_dbglvl'.
345 1. Prevent re-entrancy in the interrupt handler which
346 resulted in the driver hanging Linux.
347 2. Fix problem that prevented ABP-940 cards from being
348 recognized on some PCI motherboards.
349 3. Add support for the ABP-5140 PnP ISA card.
350 4. Fix check condition return status.
351 5. Add conditionally compiled code for Linux v1.3.X.
354 1. Fix problem in advansys_biosparam() that resulted in the
355 wrong drive geometry being returned for drives > 1GB with
356 extended translation enabled.
357 2. Add additional tracing during device initialization.
358 3. Change code that only applies to ISA PnP adapter.
359 4. Eliminate 'make dep' warning.
360 5. Try to fix problem with handling resets by increasing their
364 1. Change definitions to eliminate conflicts with other subsystems.
365 2. Add versioning code for the shared interrupt changes.
366 3. Eliminate problem in asc_rmqueue() with iterating after removing
368 4. Remove reset request loop problem from the "Known Problems or
369 Issues" section. This problem was isolated and fixed in the
370 mid-level SCSI driver.
373 1. Add support for ABP-940U (PCI Ultra) adapter.
374 2. Add support for IRQ sharing by setting the SA_SHIRQ flag for
375 request_irq and supplying a dev_id pointer to both request_irq()
377 3. In AscSearchIOPortAddr11() restore a call to check_region() which
378 should be used before I/O port probing.
379 4. Fix bug in asc_prt_hex() which resulted in the displaying
381 5. Incorporate miscellaneous Asc Library bug fixes and new microcode.
382 6. Change driver versioning to be specific to each Linux sub-level.
383 7. Change statistics gathering to be per adapter instead of global
385 8. Add more information and statistics to the adapter /proc file:
386 /proc/scsi/advansys[0...].
387 9. Remove 'cmd_per_lun' from the "Known Problems or Issues" list.
388 This problem has been addressed with the SCSI mid-level changes
389 made in v1.3.89. The advansys_select_queue_depths() function
390 was added for the v1.3.89 changes.
393 1. Incorporate miscellaneous Asc Library bug fixes and new microcode.
396 1. Enable clustering and optimize the setting of the maximum number
397 of scatter gather elements for any particular board. Clustering
398 increases CPU utilization, but results in a relatively larger
399 increase in I/O throughput.
400 2. Improve the performance of the request queuing functions by
401 adding a last pointer to the queue structure.
402 3. Correct problems with reset and abort request handling that
403 could have hung or crashed Linux.
404 4. Add more information to the adapter /proc file:
405 /proc/scsi/advansys[0...].
406 5. Remove the request timeout issue form the driver issues list.
407 6. Miscellaneous documentation additions and changes.
410 1. Make changes to handle the new v2.1.0 kernel memory mapping
411 in which a kernel virtual address may not be equivalent to its
412 bus or DMA memory address.
413 2. Change abort and reset request handling to make it yet even
415 3. Try to mitigate request starvation by sending ordered requests
416 to heavily loaded, tag queuing enabled devices.
417 4. Maintain statistics on request response time.
418 5. Add request response time statistics and other information to
419 the adapter /proc file: /proc/scsi/advansys[0...].
422 1. Add conditionally compiled code (ASC_QUEUE_FLOW_CONTROL) to
423 make use of mid-level SCSI driver device queue depth flow
424 control mechanism. This will eliminate aborts caused by a
425 device being unable to keep up with requests and eliminate
426 repeat busy or QUEUE FULL status returned by a device.
427 2. Incorporate miscellaneous Asc Library bug fixes.
428 3. To allow the driver to work in kernels with broken module
429 support set 'cmd_per_lun' if the driver is compiled as a
430 module. This change affects kernels v1.3.89 to present.
431 4. Remove PCI BIOS address from the driver banner. The PCI BIOS
432 is relocated by the motherboard BIOS and its new address can
433 not be determined by the driver.
434 5. Add mid-level SCSI queue depth information to the adapter
435 /proc file: /proc/scsi/advansys[0...].
438 1. Change allocation of global structures used for device
439 initialization to guarantee they are in DMA-able memory.
440 Previously when the driver was loaded as a module these
441 structures might not have been in DMA-able memory, causing
442 device initialization to fail.
445 1. In advansys_reset(), if the request is a synchronous reset
446 request, even if the request serial number has changed, then
447 complete the request.
448 2. Add Asc Library bug fixes including new microcode.
449 3. Clear inquiry buffer before using it.
450 4. Correct ifdef typo.
453 1. Add Asc Library bug fixes including new microcode.
454 2. Add synchronous data transfer rate information to the
455 adapter /proc file: /proc/scsi/advansys[0...].
456 3. Change ADVANSYS_DEBUG to be disabled by default. This
457 will reduce the size of the driver image, eliminate execution
458 overhead, and remove unneeded symbols from the kernel symbol
459 space that were previously added by the driver.
460 4. Add new compile-time option ADVANSYS_ASSERT for assertion
461 code that used to be defined within ADVANSYS_DEBUG. This
462 option is enabled by default.
465 1. Change version number to 2.8 to synchronize the Linux driver
466 version numbering with other AdvanSys drivers.
467 2. Reformat source files without tabs to present the same view
468 of the file to everyone regardless of the editor tab setting
470 3. Add Asc Library bug fixes.
473 1. Change version number to 3.1 to indicate that support for
474 Ultra-Wide adapters (ABP-940UW) is included in this release.
475 2. Add Asc Library (Narrow Board) bug fixes.
476 3. Report an underrun condition with the host status byte set
477 to DID_UNDERRUN. Currently DID_UNDERRUN is defined to 0 which
478 causes the underrun condition to be ignored. When Linux defines
479 its own DID_UNDERRUN the constant defined in this file can be
481 4. Add patch to AscWaitTixISRDone().
482 5. Add support for up to 16 different AdvanSys host adapter SCSI
483 channels in one system. This allows four cards with four channels
484 to be used in one system.
487 1. Handle that PCI register base addresses are not always page
488 aligned even though ioremap() requires that the address argument
492 1. Update latest BIOS version checked for from the /proc file.
493 2. Don't set microcode SDTR variable at initialization. Instead
494 wait until device capabilities have been detected from an Inquiry
498 1. Improve performance when the driver is compiled as module by
499 allowing up to 64 scatter-gather elements instead of 8.
502 1. Set time delay in AscWaitTixISRDone() to 1000 ms.
503 2. Include SMP locking changes.
504 3. For v2.1.93 and newer kernels use CONFIG_PCI and new PCI BIOS
506 4. Update board serial number printing.
507 5. Try allocating an IRQ both with and without the SA_INTERRUPT
508 flag set to allow IRQ sharing with drivers that do not set
509 the SA_INTERRUPT flag. Also display a more descriptive error
510 message if request_irq() fails.
511 6. Update to latest Asc and Adv Libraries.
514 1. Update Adv Library to 4.16 which includes support for
515 the ASC38C0800 (Ultra2/LVD) IC.
518 1. Correct PCI compile time option for v2.1.93 and greater
519 kernels, advansys_info() string, and debug compile time
521 2. Correct DvcSleepMilliSecond() for v2.1.0 and greater
522 kernels. This caused an LVD detection/BIST problem problem
524 3. Sort PCI cards by PCI Bus, Slot, Function ascending order
525 to be consistent with the BIOS.
526 4. Update to Asc Library S121 and Adv Library 5.2.
529 1. Correct PCI card detection bug introduced in 3.2B that
530 prevented PCI cards from being detected in kernels older
534 1. Correct /proc device synchronous speed information display.
535 Also when re-negotiation is pending for a target device
536 note this condition with an * and footnote.
537 2. Correct initialization problem with Ultra-Wide cards that
538 have a pre-3.2 BIOS. A microcode variable changed locations
539 in 3.2 and greater BIOSes which caused WDTR to be attempted
540 erroneously with drives that don't support WDTR.
543 1. Fix compile error caused by v2.3.13 PCI structure change.
544 2. Remove field from ASCEEP_CONFIG that resulted in an EEPROM
545 checksum error for ISA cards.
546 3. Remove ASC_QUEUE_FLOW_CONTROL conditional code. The mid-level
547 SCSI changes that it depended on were never included in Linux.
550 1. Handle new initial function code added in v2.3.16 for all
554 1. Fix PCI board detection in v2.3.13 and greater kernels.
555 2. Fix comiple errors in v2.3.X with debugging enabled.
558 1. Add 64-bit address, long support for Alpha and UltraSPARC.
559 The driver has been verified to work on an Alpha system.
560 2. Add partial byte order handling support for Power PC and
561 other big-endian platforms. This support has not yet been
562 completed or verified.
563 3. For wide boards replace block zeroing of request and
564 scatter-gather structures with individual field initialization
565 to improve performance.
566 4. Correct and clarify ROM BIOS version detection.
569 1. Update to Adv Library 5.4.
570 2. Add v2.3.19 underrun reporting to asc_isr_callback() and
571 adv_isr_callback(). Remove DID_UNDERRUN constant and other
572 no longer needed code that previously documented the lack
573 of underrun handling.
576 1. Eliminate compile errors for v2.0 and earlier kernels.
579 1. Correct debug compile error in asc_prt_adv_scsi_req_q().
580 2. Update Adv Library to 5.5.
581 3. Add ifdef handling for /proc changes added in v2.3.28.
582 4. Increase Wide board scatter-gather list maximum length to
583 255 when the driver is compiled into the kernel.
586 1. Fix bug in adv_get_sglist() that caused an assertion failure
587 at line 7475. The reqp->sgblkp pointer must be initialized
588 to NULL in adv_get_sglist().
591 1. Really fix bug in adv_get_sglist().
592 2. Incorporate v2.3.29 changes into driver.
595 1. Add CONFIG_ISA ifdef code.
596 2. Include advansys_interrupts_enabled name change patch.
597 3. For >= v2.3.28 use new SCSI error handling with new function
598 advansys_eh_bus_reset(). Don't include an abort function
599 because of base library limitations.
600 4. For >= v2.3.28 use per board lock instead of io_request_lock.
601 5. For >= v2.3.28 eliminate advansys_command() and
602 advansys_command_done().
603 6. Add some changes for PowerPC (Big Endian) support, but it isn't
605 7. Fix "nonexistent resource free" problem that occurred on a module
606 unload for boards with an I/O space >= 255. The 'n_io_port' field
607 is only one byte and can not be used to hold an ioport length more
611 1. Update to Adv Library 5.8.
612 2. For wide cards add support for CDBs up to 16 bytes.
613 3. Eliminate warnings when CONFIG_PROC_FS is not defined.
616 1. Support for PowerPC (Big Endian) wide cards. Narrow cards
618 2. Change bitfields to shift and mask access for endian
622 1. Update for latest 2.4 kernel.
623 2. Test ABP-480 CardBus support in 2.4 kernel - works!
624 3. Update to Asc Library S123.
625 4. Update to Adv Library 5.12.
628 1. Update for latest 2.4 kernel.
629 2. Create patches for 2.2 and 2.4 kernels.
632 1. Now that 2.4 is released remove ifdef code for kernel versions
633 less than 2.2. The driver is now only supported in kernels 2.2,
635 2. Add code to release and acquire the io_request_lock in
636 the driver entrypoint functions: advansys_detect and
637 advansys_queuecommand. In kernel 2.4 the SCSI mid-level driver
638 still holds the io_request_lock on entry to SCSI low-level drivers.
639 This was supposed to be removed before 2.4 was released but never
640 happened. When the mid-level SCSI driver is changed all references
641 to the io_request_lock should be removed from the driver.
642 3. Simplify error handling by removing advansys_abort(),
643 AscAbortSRB(), AscResetDevice(). SCSI bus reset requests are
644 now handled by resetting the SCSI bus and fully re-initializing
645 the chip. This simple method of error recovery has proven to work
646 most reliably after attempts at different methods. Also now only
647 support the "new" error handling method and remove the obsolete
648 error handling interface.
649 4. Fix debug build errors.
652 1. Merge with ConnectCom version from Andy Kellner which
653 updates Adv Library to 5.14.
654 2. Make PowerPC (Big Endian) work for narrow cards and
655 fix problems writing EEPROM for wide cards.
656 3. Remove interrupts_enabled assertion function.
659 1. Return an error from narrow boards if passed a 16 byte
660 CDB. The wide board can already handle 16 byte CDBs.
663 1. hacks for lk 2.5 series (D. Gilbert)
666 1. change select_queue_depths to slave_configure
667 2. make cmd_per_lun be sane again
670 1. continuing cleanup for lk 2.6 series
671 2. Fix problem in lk 2.6.7-bk2 that broke PCI wide cards
672 3. Fix problem that oopsed ISA cards
674 I. Known Problems/Fix List (XXX)
676 1. Need to add memory mapping workaround. Test the memory mapping.
677 If it doesn't work revert to I/O port access. Can a test be done
679 2. Handle an interrupt not working. Keep an interrupt counter in
680 the interrupt handler. In the timeout function if the interrupt
681 has not occurred then print a message and run in polled mode.
682 3. Allow bus type scanning order to be changed.
683 4. Need to add support for target mode commands, cf. CAM XPT.
685 J. Credits (Chronological Order)
687 Bob Frey <bfrey@turbolinux.com.cn> wrote the AdvanSys SCSI driver
688 and maintained it up to 3.3F. He continues to answer questions
689 and help maintain the driver.
691 Nathan Hartwell <mage@cdc3.cdc.net> provided the directions and
692 basis for the Linux v1.3.X changes which were included in the
695 Thomas E Zerucha <zerucha@shell.portal.com> pointed out a bug
696 in advansys_biosparam() which was fixed in the 1.3 release.
698 Erik Ratcliffe <erik@caldera.com> has done testing of the
699 AdvanSys driver in the Caldera releases.
701 Rik van Riel <H.H.vanRiel@fys.ruu.nl> provided a patch to
702 AscWaitTixISRDone() which he found necessary to make the
703 driver work with a SCSI-1 disk.
705 Mark Moran <mmoran@mmoran.com> has helped test Ultra-Wide
706 support in the 3.1A driver.
708 Doug Gilbert <dgilbert@interlog.com> has made changes and
709 suggestions to improve the driver and done a lot of testing.
711 Ken Mort <ken@mort.net> reported a DEBUG compile bug fixed
714 Tom Rini <trini@kernel.crashing.org> provided the CONFIG_ISA
715 patch and helped with PowerPC wide and narrow board support.
717 Philip Blundell <philb@gnu.org> provided an
718 advansys_interrupts_enabled patch.
720 Dave Jones <dave@denial.force9.co.uk> reported the compiler
721 warnings generated when CONFIG_PROC_FS was not defined in
724 Jerry Quinn <jlquinn@us.ibm.com> fixed PowerPC support (endian
725 problems) for wide cards.
727 Bryan Henderson <bryanh@giraffe-data.com> helped debug narrow
730 Manuel Veloso <veloso@pobox.com> worked hard on PowerPC narrow
731 board support and fixed a bug in AscGetEEPConfig().
733 Arnaldo Carvalho de Melo <acme@conectiva.com.br> made
734 save_flags/restore_flags changes.
736 Andy Kellner <AKellner@connectcom.net> continues the Advansys SCSI
737 driver development for ConnectCom (Version > 3.3F).
739 K. ConnectCom (AdvanSys) Contact Information
741 Mail: ConnectCom Solutions, Inc.
744 Operator/Sales: 1-408-383-9400
746 Tech Support: 1-408-467-2930
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754 * --- Linux Include Files
757 #include <linux/config.h>
758 #include <linux/module.h>
760 #if defined(CONFIG_X86) && !defined(CONFIG_ISA)
762 #endif /* CONFIG_X86 && !CONFIG_ISA */
764 #include <linux/string.h>
765 #include <linux/kernel.h>
766 #include <linux/types.h>
767 #include <linux/ioport.h>
768 #include <linux/interrupt.h>
769 #include <linux/delay.h>
770 #include <linux/slab.h>
771 #include <linux/mm.h>
772 #include <linux/proc_fs.h>
773 #include <linux/init.h>
774 #include <linux/blkdev.h>
775 #include <linux/stat.h>
776 #include <linux/spinlock.h>
777 #include <linux/dma-mapping.h>
780 #include <asm/system.h>
783 /* FIXME: (by jejb@steeleye.com) This warning is present for two
786 * 1) This driver badly needs converting to the correct driver model
789 * 2) Although all of the necessary command mapping places have the
790 * appropriate dma_map.. APIs, the driver still processes its internal
791 * queue using bus_to_virt() and virt_to_bus() which are illegal under
792 * the API. The entire queue processing structure will need to be
793 * altered to fix this.
795 #warning this driver is still not properly converted to the DMA API
797 #include <scsi/scsi_cmnd.h>
798 #include <scsi/scsi_device.h>
799 #include <scsi/scsi_tcq.h>
800 #include <scsi/scsi.h>
801 #include <scsi/scsi_host.h>
802 #include "advansys.h"
804 #include <linux/pci.h>
805 #endif /* CONFIG_PCI */
812 /* Enable driver assertions. */
813 #define ADVANSYS_ASSERT
815 /* Enable driver /proc statistics. */
816 #define ADVANSYS_STATS
818 /* Enable driver tracing. */
819 /* #define ADVANSYS_DEBUG */
823 * --- Debugging Header
826 #ifdef ADVANSYS_DEBUG
828 #else /* ADVANSYS_DEBUG */
829 #define STATIC static
830 #endif /* ADVANSYS_DEBUG */
834 * --- Asc Library Constants and Macros
837 #define ASC_LIB_VERSION_MAJOR 1
838 #define ASC_LIB_VERSION_MINOR 24
839 #define ASC_LIB_SERIAL_NUMBER 123
842 * Portable Data Types
844 * Any instance where a 32-bit long or pointer type is assumed
845 * for precision or HW defined structures, the following define
846 * types must be used. In Linux the char, short, and int types
847 * are all consistent at 8, 16, and 32 bits respectively. Pointers
848 * and long types are 64 bits on Alpha and UltraSPARC.
850 #define ASC_PADDR __u32 /* Physical/Bus address data type. */
851 #define ASC_VADDR __u32 /* Virtual address data type. */
852 #define ASC_DCNT __u32 /* Unsigned Data count type. */
853 #define ASC_SDCNT __s32 /* Signed Data count type. */
856 * These macros are used to convert a virtual address to a
857 * 32-bit value. This currently can be used on Linux Alpha
858 * which uses 64-bit virtual address but a 32-bit bus address.
859 * This is likely to break in the future, but doing this now
860 * will give us time to change the HW and FW to handle 64-bit
863 #define ASC_VADDR_TO_U32 virt_to_bus
864 #define ASC_U32_TO_VADDR bus_to_virt
866 typedef unsigned char uchar;
877 #define UW_ERR (uint)(0xFFFF)
878 #define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
879 #define AscPCIConfigVendorIDRegister 0x0000
880 #define AscPCIConfigDeviceIDRegister 0x0002
881 #define AscPCIConfigCommandRegister 0x0004
882 #define AscPCIConfigStatusRegister 0x0006
883 #define AscPCIConfigRevisionIDRegister 0x0008
884 #define AscPCIConfigCacheSize 0x000C
885 #define AscPCIConfigLatencyTimer 0x000D
886 #define AscPCIIOBaseRegister 0x0010
887 #define AscPCICmdRegBits_IOMemBusMaster 0x0007
888 #define ASC_PCI_ID2BUS(id) ((id) & 0xFF)
889 #define ASC_PCI_ID2DEV(id) (((id) >> 11) & 0x1F)
890 #define ASC_PCI_ID2FUNC(id) (((id) >> 8) & 0x7)
891 #define ASC_PCI_MKID(bus, dev, func) ((((dev) & 0x1F) << 11) | (((func) & 0x7) << 8) | ((bus) & 0xFF))
892 #define ASC_PCI_VENDORID 0x10CD
893 #define ASC_PCI_DEVICEID_1200A 0x1100
894 #define ASC_PCI_DEVICEID_1200B 0x1200
895 #define ASC_PCI_DEVICEID_ULTRA 0x1300
896 #define ASC_PCI_REVISION_3150 0x02
897 #define ASC_PCI_REVISION_3050 0x03
899 #define ASC_DVCLIB_CALL_DONE (1)
900 #define ASC_DVCLIB_CALL_FAILED (0)
901 #define ASC_DVCLIB_CALL_ERROR (-1)
904 * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
905 * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
906 * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
909 #define CC_VERY_LONG_SG_LIST 0
910 #define ASC_SRB2SCSIQ(srb_ptr) (srb_ptr)
912 #define PortAddr unsigned short /* port address size */
913 #define inp(port) inb(port)
914 #define outp(port, byte) outb((byte), (port))
916 #define inpw(port) inw(port)
917 #define outpw(port, word) outw((word), (port))
919 #define ASC_MAX_SG_QUEUE 7
920 #define ASC_MAX_SG_LIST 255
922 #define ASC_CS_TYPE unsigned short
924 #define ASC_IS_ISA (0x0001)
925 #define ASC_IS_ISAPNP (0x0081)
926 #define ASC_IS_EISA (0x0002)
927 #define ASC_IS_PCI (0x0004)
928 #define ASC_IS_PCI_ULTRA (0x0104)
929 #define ASC_IS_PCMCIA (0x0008)
930 #define ASC_IS_MCA (0x0020)
931 #define ASC_IS_VL (0x0040)
932 #define ASC_ISA_PNP_PORT_ADDR (0x279)
933 #define ASC_ISA_PNP_PORT_WRITE (ASC_ISA_PNP_PORT_ADDR+0x800)
934 #define ASC_IS_WIDESCSI_16 (0x0100)
935 #define ASC_IS_WIDESCSI_32 (0x0200)
936 #define ASC_IS_BIG_ENDIAN (0x8000)
937 #define ASC_CHIP_MIN_VER_VL (0x01)
938 #define ASC_CHIP_MAX_VER_VL (0x07)
939 #define ASC_CHIP_MIN_VER_PCI (0x09)
940 #define ASC_CHIP_MAX_VER_PCI (0x0F)
941 #define ASC_CHIP_VER_PCI_BIT (0x08)
942 #define ASC_CHIP_MIN_VER_ISA (0x11)
943 #define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
944 #define ASC_CHIP_MAX_VER_ISA (0x27)
945 #define ASC_CHIP_VER_ISA_BIT (0x30)
946 #define ASC_CHIP_VER_ISAPNP_BIT (0x20)
947 #define ASC_CHIP_VER_ASYN_BUG (0x21)
948 #define ASC_CHIP_VER_PCI 0x08
949 #define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
950 #define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
951 #define ASC_CHIP_MIN_VER_EISA (0x41)
952 #define ASC_CHIP_MAX_VER_EISA (0x47)
953 #define ASC_CHIP_VER_EISA_BIT (0x40)
954 #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
955 #define ASC_MAX_LIB_SUPPORTED_ISA_CHIP_VER 0x21
956 #define ASC_MAX_LIB_SUPPORTED_PCI_CHIP_VER 0x0A
957 #define ASC_MAX_VL_DMA_ADDR (0x07FFFFFFL)
958 #define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
959 #define ASC_MAX_PCI_DMA_ADDR (0xFFFFFFFFL)
960 #define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
961 #define ASC_MAX_ISA_DMA_ADDR (0x00FFFFFFL)
962 #define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL)
963 #define ASC_MAX_EISA_DMA_ADDR (0x07FFFFFFL)
964 #define ASC_MAX_EISA_DMA_COUNT (0x07FFFFFFL)
966 #define ASC_SCSI_ID_BITS 3
967 #define ASC_SCSI_TIX_TYPE uchar
968 #define ASC_ALL_DEVICE_BIT_SET 0xFF
969 #define ASC_SCSI_BIT_ID_TYPE uchar
970 #define ASC_MAX_TID 7
971 #define ASC_MAX_LUN 7
972 #define ASC_SCSI_WIDTH_BIT_SET 0xFF
973 #define ASC_MAX_SENSE_LEN 32
974 #define ASC_MIN_SENSE_LEN 14
975 #define ASC_MAX_CDB_LEN 12
976 #define ASC_SCSI_RESET_HOLD_TIME_US 60
978 #define ADV_INQ_CLOCKING_ST_ONLY 0x0
979 #define ADV_INQ_CLOCKING_DT_ONLY 0x1
980 #define ADV_INQ_CLOCKING_ST_AND_DT 0x3
983 * Inquiry SPC-2 SPI Byte 1 EVPD (Enable Vital Product Data)
984 * and CmdDt (Command Support Data) field bit definitions.
986 #define ADV_INQ_RTN_VPD_AND_CMDDT 0x3
987 #define ADV_INQ_RTN_CMDDT_FOR_OP_CODE 0x2
988 #define ADV_INQ_RTN_VPD_FOR_PG_CODE 0x1
989 #define ADV_INQ_RTN_STD_INQUIRY_DATA 0x0
991 #define ASC_SCSIDIR_NOCHK 0x00
992 #define ASC_SCSIDIR_T2H 0x08
993 #define ASC_SCSIDIR_H2T 0x10
994 #define ASC_SCSIDIR_NODATA 0x18
995 #define SCSI_ASC_NOMEDIA 0x3A
996 #define ASC_SRB_HOST(x) ((uchar)((uchar)(x) >> 4))
997 #define ASC_SRB_TID(x) ((uchar)((uchar)(x) & (uchar)0x0F))
998 #define ASC_SRB_LUN(x) ((uchar)((uint)(x) >> 13))
999 #define PUT_CDB1(x) ((uchar)((uint)(x) >> 8))
1000 #define MS_CMD_DONE 0x00
1001 #define MS_EXTEND 0x01
1002 #define MS_SDTR_LEN 0x03
1003 #define MS_SDTR_CODE 0x01
1004 #define MS_WDTR_LEN 0x02
1005 #define MS_WDTR_CODE 0x03
1006 #define MS_MDP_LEN 0x05
1007 #define MS_MDP_CODE 0x00
1010 * Inquiry data structure and bitfield macros
1012 * Only quantities of more than 1 bit are shifted, since the others are
1013 * just tested for true or false. C bitfields aren't portable between big
1014 * and little-endian platforms so they are not used.
1017 #define ASC_INQ_DVC_TYPE(inq) ((inq)->periph & 0x1f)
1018 #define ASC_INQ_QUALIFIER(inq) (((inq)->periph & 0xe0) >> 5)
1019 #define ASC_INQ_DVC_TYPE_MOD(inq) ((inq)->devtype & 0x7f)
1020 #define ASC_INQ_REMOVABLE(inq) ((inq)->devtype & 0x80)
1021 #define ASC_INQ_ANSI_VER(inq) ((inq)->ver & 0x07)
1022 #define ASC_INQ_ECMA_VER(inq) (((inq)->ver & 0x38) >> 3)
1023 #define ASC_INQ_ISO_VER(inq) (((inq)->ver & 0xc0) >> 6)
1024 #define ASC_INQ_RESPONSE_FMT(inq) ((inq)->byte3 & 0x0f)
1025 #define ASC_INQ_TERM_IO(inq) ((inq)->byte3 & 0x40)
1026 #define ASC_INQ_ASYNC_NOTIF(inq) ((inq)->byte3 & 0x80)
1027 #define ASC_INQ_SOFT_RESET(inq) ((inq)->flags & 0x01)
1028 #define ASC_INQ_CMD_QUEUE(inq) ((inq)->flags & 0x02)
1029 #define ASC_INQ_LINK_CMD(inq) ((inq)->flags & 0x08)
1030 #define ASC_INQ_SYNC(inq) ((inq)->flags & 0x10)
1031 #define ASC_INQ_WIDE16(inq) ((inq)->flags & 0x20)
1032 #define ASC_INQ_WIDE32(inq) ((inq)->flags & 0x40)
1033 #define ASC_INQ_REL_ADDR(inq) ((inq)->flags & 0x80)
1034 #define ASC_INQ_INFO_UNIT(inq) ((inq)->info & 0x01)
1035 #define ASC_INQ_QUICK_ARB(inq) ((inq)->info & 0x02)
1036 #define ASC_INQ_CLOCKING(inq) (((inq)->info & 0x0c) >> 2)
1048 uchar product_id[16];
1049 uchar product_rev_level[4];
1052 #define ASC_SG_LIST_PER_Q 7
1053 #define QS_FREE 0x00
1054 #define QS_READY 0x01
1055 #define QS_DISC1 0x02
1056 #define QS_DISC2 0x04
1057 #define QS_BUSY 0x08
1058 #define QS_ABORTED 0x40
1059 #define QS_DONE 0x80
1060 #define QC_NO_CALLBACK 0x01
1061 #define QC_SG_SWAP_QUEUE 0x02
1062 #define QC_SG_HEAD 0x04
1063 #define QC_DATA_IN 0x08
1064 #define QC_DATA_OUT 0x10
1065 #define QC_URGENT 0x20
1066 #define QC_MSG_OUT 0x40
1067 #define QC_REQ_SENSE 0x80
1068 #define QCSG_SG_XFER_LIST 0x02
1069 #define QCSG_SG_XFER_MORE 0x04
1070 #define QCSG_SG_XFER_END 0x08
1071 #define QD_IN_PROGRESS 0x00
1072 #define QD_NO_ERROR 0x01
1073 #define QD_ABORTED_BY_HOST 0x02
1074 #define QD_WITH_ERROR 0x04
1075 #define QD_INVALID_REQUEST 0x80
1076 #define QD_INVALID_HOST_NUM 0x81
1077 #define QD_INVALID_DEVICE 0x82
1078 #define QD_ERR_INTERNAL 0xFF
1079 #define QHSTA_NO_ERROR 0x00
1080 #define QHSTA_M_SEL_TIMEOUT 0x11
1081 #define QHSTA_M_DATA_OVER_RUN 0x12
1082 #define QHSTA_M_DATA_UNDER_RUN 0x12
1083 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
1084 #define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
1085 #define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
1086 #define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
1087 #define QHSTA_D_HOST_ABORT_FAILED 0x23
1088 #define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
1089 #define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
1090 #define QHSTA_D_ASPI_NO_BUF_POOL 0x26
1091 #define QHSTA_M_WTM_TIMEOUT 0x41
1092 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
1093 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
1094 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
1095 #define QHSTA_M_TARGET_STATUS_BUSY 0x45
1096 #define QHSTA_M_BAD_TAG_CODE 0x46
1097 #define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
1098 #define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
1099 #define QHSTA_D_LRAM_CMP_ERROR 0x81
1100 #define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
1101 #define ASC_FLAG_SCSIQ_REQ 0x01
1102 #define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
1103 #define ASC_FLAG_BIOS_ASYNC_IO 0x04
1104 #define ASC_FLAG_SRB_LINEAR_ADDR 0x08
1105 #define ASC_FLAG_WIN16 0x10
1106 #define ASC_FLAG_WIN32 0x20
1107 #define ASC_FLAG_ISA_OVER_16MB 0x40
1108 #define ASC_FLAG_DOS_VM_CALLBACK 0x80
1109 #define ASC_TAG_FLAG_EXTRA_BYTES 0x10
1110 #define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
1111 #define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
1112 #define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
1113 #define ASC_SCSIQ_CPY_BEG 4
1114 #define ASC_SCSIQ_SGHD_CPY_BEG 2
1115 #define ASC_SCSIQ_B_FWD 0
1116 #define ASC_SCSIQ_B_BWD 1
1117 #define ASC_SCSIQ_B_STATUS 2
1118 #define ASC_SCSIQ_B_QNO 3
1119 #define ASC_SCSIQ_B_CNTL 4
1120 #define ASC_SCSIQ_B_SG_QUEUE_CNT 5
1121 #define ASC_SCSIQ_D_DATA_ADDR 8
1122 #define ASC_SCSIQ_D_DATA_CNT 12
1123 #define ASC_SCSIQ_B_SENSE_LEN 20
1124 #define ASC_SCSIQ_DONE_INFO_BEG 22
1125 #define ASC_SCSIQ_D_SRBPTR 22
1126 #define ASC_SCSIQ_B_TARGET_IX 26
1127 #define ASC_SCSIQ_B_CDB_LEN 28
1128 #define ASC_SCSIQ_B_TAG_CODE 29
1129 #define ASC_SCSIQ_W_VM_ID 30
1130 #define ASC_SCSIQ_DONE_STATUS 32
1131 #define ASC_SCSIQ_HOST_STATUS 33
1132 #define ASC_SCSIQ_SCSI_STATUS 34
1133 #define ASC_SCSIQ_CDB_BEG 36
1134 #define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
1135 #define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
1136 #define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
1137 #define ASC_SCSIQ_B_SG_WK_QP 49
1138 #define ASC_SCSIQ_B_SG_WK_IX 50
1139 #define ASC_SCSIQ_W_ALT_DC1 52
1140 #define ASC_SCSIQ_B_LIST_CNT 6
1141 #define ASC_SCSIQ_B_CUR_LIST_CNT 7
1142 #define ASC_SGQ_B_SG_CNTL 4
1143 #define ASC_SGQ_B_SG_HEAD_QP 5
1144 #define ASC_SGQ_B_SG_LIST_CNT 6
1145 #define ASC_SGQ_B_SG_CUR_LIST_CNT 7
1146 #define ASC_SGQ_LIST_BEG 8
1147 #define ASC_DEF_SCSI1_QNG 4
1148 #define ASC_MAX_SCSI1_QNG 4
1149 #define ASC_DEF_SCSI2_QNG 16
1150 #define ASC_MAX_SCSI2_QNG 32
1151 #define ASC_TAG_CODE_MASK 0x23
1152 #define ASC_STOP_REQ_RISC_STOP 0x01
1153 #define ASC_STOP_ACK_RISC_STOP 0x03
1154 #define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
1155 #define ASC_STOP_CLEAN_UP_DISC_Q 0x20
1156 #define ASC_STOP_HOST_REQ_RISC_HALT 0x40
1157 #define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
1158 #define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
1159 #define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
1160 #define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
1161 #define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
1162 #define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
1163 #define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
1165 typedef struct asc_scsiq_1 {
1172 ASC_PADDR data_addr;
1174 ASC_PADDR sense_addr;
1179 typedef struct asc_scsiq_2 {
1188 typedef struct asc_scsiq_3 {
1195 typedef struct asc_scsiq_4 {
1196 uchar cdb[ASC_MAX_CDB_LEN];
1197 uchar y_first_sg_list_qp;
1198 uchar y_working_sg_qp;
1199 uchar y_working_sg_ix;
1202 ushort x_reconnect_rtn;
1203 ASC_PADDR x_saved_data_addr;
1204 ASC_DCNT x_saved_data_cnt;
1207 typedef struct asc_q_done_info {
1216 ASC_DCNT remain_bytes;
1219 typedef struct asc_sg_list {
1224 typedef struct asc_sg_head {
1227 ushort entry_to_copy;
1229 ASC_SG_LIST sg_list[ASC_MAX_SG_LIST];
1232 #define ASC_MIN_SG_LIST 2
1234 typedef struct asc_min_sg_head {
1237 ushort entry_to_copy;
1239 ASC_SG_LIST sg_list[ASC_MIN_SG_LIST];
1242 #define QCX_SORT (0x0001)
1243 #define QCX_COALEASE (0x0002)
1245 typedef struct asc_scsi_q {
1249 ASC_SG_HEAD *sg_head;
1250 ushort remain_sg_entry_cnt;
1251 ushort next_sg_index;
1254 typedef struct asc_scsi_req_q {
1258 ASC_SG_HEAD *sg_head;
1261 uchar cdb[ASC_MAX_CDB_LEN];
1262 uchar sense[ASC_MIN_SENSE_LEN];
1265 typedef struct asc_scsi_bios_req_q {
1269 ASC_SG_HEAD *sg_head;
1272 uchar cdb[ASC_MAX_CDB_LEN];
1273 uchar sense[ASC_MIN_SENSE_LEN];
1274 } ASC_SCSI_BIOS_REQ_Q;
1276 typedef struct asc_risc_q {
1285 typedef struct asc_sg_list_q {
1291 uchar sg_cur_list_cnt;
1294 typedef struct asc_risc_sg_list_q {
1298 ASC_SG_LIST sg_list[7];
1299 } ASC_RISC_SG_LIST_Q;
1301 #define ASC_EXE_SCSI_IO_MAX_IDLE_LOOP 0x1000000UL
1302 #define ASC_EXE_SCSI_IO_MAX_WAIT_LOOP 1024
1303 #define ASCQ_ERR_NO_ERROR 0
1304 #define ASCQ_ERR_IO_NOT_FOUND 1
1305 #define ASCQ_ERR_LOCAL_MEM 2
1306 #define ASCQ_ERR_CHKSUM 3
1307 #define ASCQ_ERR_START_CHIP 4
1308 #define ASCQ_ERR_INT_TARGET_ID 5
1309 #define ASCQ_ERR_INT_LOCAL_MEM 6
1310 #define ASCQ_ERR_HALT_RISC 7
1311 #define ASCQ_ERR_GET_ASPI_ENTRY 8
1312 #define ASCQ_ERR_CLOSE_ASPI 9
1313 #define ASCQ_ERR_HOST_INQUIRY 0x0A
1314 #define ASCQ_ERR_SAVED_SRB_BAD 0x0B
1315 #define ASCQ_ERR_QCNTL_SG_LIST 0x0C
1316 #define ASCQ_ERR_Q_STATUS 0x0D
1317 #define ASCQ_ERR_WR_SCSIQ 0x0E
1318 #define ASCQ_ERR_PC_ADDR 0x0F
1319 #define ASCQ_ERR_SYN_OFFSET 0x10
1320 #define ASCQ_ERR_SYN_XFER_TIME 0x11
1321 #define ASCQ_ERR_LOCK_DMA 0x12
1322 #define ASCQ_ERR_UNLOCK_DMA 0x13
1323 #define ASCQ_ERR_VDS_CHK_INSTALL 0x14
1324 #define ASCQ_ERR_MICRO_CODE_HALT 0x15
1325 #define ASCQ_ERR_SET_LRAM_ADDR 0x16
1326 #define ASCQ_ERR_CUR_QNG 0x17
1327 #define ASCQ_ERR_SG_Q_LINKS 0x18
1328 #define ASCQ_ERR_SCSIQ_PTR 0x19
1329 #define ASCQ_ERR_ISR_RE_ENTRY 0x1A
1330 #define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
1331 #define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
1332 #define ASCQ_ERR_SG_LIST_ODD_ADDRESS 0x1D
1333 #define ASCQ_ERR_XFER_ADDRESS_TOO_BIG 0x1E
1334 #define ASCQ_ERR_SCSIQ_NULL_PTR 0x1F
1335 #define ASCQ_ERR_SCSIQ_BAD_NEXT_PTR 0x20
1336 #define ASCQ_ERR_GET_NUM_OF_FREE_Q 0x21
1337 #define ASCQ_ERR_SEND_SCSI_Q 0x22
1338 #define ASCQ_ERR_HOST_REQ_RISC_HALT 0x23
1339 #define ASCQ_ERR_RESET_SDTR 0x24
1342 * Warning code values are set in ASC_DVC_VAR 'warn_code'.
1344 #define ASC_WARN_NO_ERROR 0x0000
1345 #define ASC_WARN_IO_PORT_ROTATE 0x0001
1346 #define ASC_WARN_EEPROM_CHKSUM 0x0002
1347 #define ASC_WARN_IRQ_MODIFIED 0x0004
1348 #define ASC_WARN_AUTO_CONFIG 0x0008
1349 #define ASC_WARN_CMD_QNG_CONFLICT 0x0010
1350 #define ASC_WARN_EEPROM_RECOVER 0x0020
1351 #define ASC_WARN_CFG_MSW_RECOVER 0x0040
1352 #define ASC_WARN_SET_PCI_CONFIG_SPACE 0x0080
1355 * Error code values are set in ASC_DVC_VAR 'err_code'.
1357 #define ASC_IERR_WRITE_EEPROM 0x0001
1358 #define ASC_IERR_MCODE_CHKSUM 0x0002
1359 #define ASC_IERR_SET_PC_ADDR 0x0004
1360 #define ASC_IERR_START_STOP_CHIP 0x0008
1361 #define ASC_IERR_IRQ_NO 0x0010
1362 #define ASC_IERR_SET_IRQ_NO 0x0020
1363 #define ASC_IERR_CHIP_VERSION 0x0040
1364 #define ASC_IERR_SET_SCSI_ID 0x0080
1365 #define ASC_IERR_GET_PHY_ADDR 0x0100
1366 #define ASC_IERR_BAD_SIGNATURE 0x0200
1367 #define ASC_IERR_NO_BUS_TYPE 0x0400
1368 #define ASC_IERR_SCAM 0x0800
1369 #define ASC_IERR_SET_SDTR 0x1000
1370 #define ASC_IERR_RW_LRAM 0x8000
1372 #define ASC_DEF_IRQ_NO 10
1373 #define ASC_MAX_IRQ_NO 15
1374 #define ASC_MIN_IRQ_NO 10
1375 #define ASC_MIN_REMAIN_Q (0x02)
1376 #define ASC_DEF_MAX_TOTAL_QNG (0xF0)
1377 #define ASC_MIN_TAG_Q_PER_DVC (0x04)
1378 #define ASC_DEF_TAG_Q_PER_DVC (0x04)
1379 #define ASC_MIN_FREE_Q ASC_MIN_REMAIN_Q
1380 #define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
1381 #define ASC_MAX_TOTAL_QNG 240
1382 #define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
1383 #define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
1384 #define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
1385 #define ASC_MAX_INRAM_TAG_QNG 16
1386 #define ASC_IOADR_TABLE_MAX_IX 11
1387 #define ASC_IOADR_GAP 0x10
1388 #define ASC_SEARCH_IOP_GAP 0x10
1389 #define ASC_MIN_IOP_ADDR (PortAddr)0x0100
1390 #define ASC_MAX_IOP_ADDR (PortAddr)0x3F0
1391 #define ASC_IOADR_1 (PortAddr)0x0110
1392 #define ASC_IOADR_2 (PortAddr)0x0130
1393 #define ASC_IOADR_3 (PortAddr)0x0150
1394 #define ASC_IOADR_4 (PortAddr)0x0190
1395 #define ASC_IOADR_5 (PortAddr)0x0210
1396 #define ASC_IOADR_6 (PortAddr)0x0230
1397 #define ASC_IOADR_7 (PortAddr)0x0250
1398 #define ASC_IOADR_8 (PortAddr)0x0330
1399 #define ASC_IOADR_DEF ASC_IOADR_8
1400 #define ASC_LIB_SCSIQ_WK_SP 256
1401 #define ASC_MAX_SYN_XFER_NO 16
1402 #define ASC_SYN_MAX_OFFSET 0x0F
1403 #define ASC_DEF_SDTR_OFFSET 0x0F
1404 #define ASC_DEF_SDTR_INDEX 0x00
1405 #define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
1406 #define SYN_XFER_NS_0 25
1407 #define SYN_XFER_NS_1 30
1408 #define SYN_XFER_NS_2 35
1409 #define SYN_XFER_NS_3 40
1410 #define SYN_XFER_NS_4 50
1411 #define SYN_XFER_NS_5 60
1412 #define SYN_XFER_NS_6 70
1413 #define SYN_XFER_NS_7 85
1414 #define SYN_ULTRA_XFER_NS_0 12
1415 #define SYN_ULTRA_XFER_NS_1 19
1416 #define SYN_ULTRA_XFER_NS_2 25
1417 #define SYN_ULTRA_XFER_NS_3 32
1418 #define SYN_ULTRA_XFER_NS_4 38
1419 #define SYN_ULTRA_XFER_NS_5 44
1420 #define SYN_ULTRA_XFER_NS_6 50
1421 #define SYN_ULTRA_XFER_NS_7 57
1422 #define SYN_ULTRA_XFER_NS_8 63
1423 #define SYN_ULTRA_XFER_NS_9 69
1424 #define SYN_ULTRA_XFER_NS_10 75
1425 #define SYN_ULTRA_XFER_NS_11 82
1426 #define SYN_ULTRA_XFER_NS_12 88
1427 #define SYN_ULTRA_XFER_NS_13 94
1428 #define SYN_ULTRA_XFER_NS_14 100
1429 #define SYN_ULTRA_XFER_NS_15 107
1431 typedef struct ext_msg {
1437 uchar sdtr_xfer_period;
1438 uchar sdtr_req_ack_offset;
1453 #define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
1454 #define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
1455 #define wdtr_width u_ext_msg.wdtr.wdtr_width
1456 #define mdp_b3 u_ext_msg.mdp_b3
1457 #define mdp_b2 u_ext_msg.mdp_b2
1458 #define mdp_b1 u_ext_msg.mdp_b1
1459 #define mdp_b0 u_ext_msg.mdp_b0
1461 typedef struct asc_dvc_cfg {
1462 ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
1463 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
1464 ASC_SCSI_BIT_ID_TYPE disc_enable;
1465 ASC_SCSI_BIT_ID_TYPE sdtr_enable;
1467 uchar isa_dma_speed;
1468 uchar isa_dma_channel;
1470 ushort lib_serial_no;
1473 ushort mcode_version;
1474 uchar max_tag_qng[ASC_MAX_TID + 1];
1476 uchar sdtr_period_offset[ASC_MAX_TID + 1];
1477 ushort pci_slot_info;
1478 uchar adapter_info[6];
1482 #define ASC_DEF_DVC_CNTL 0xFFFF
1483 #define ASC_DEF_CHIP_SCSI_ID 7
1484 #define ASC_DEF_ISA_DMA_SPEED 4
1485 #define ASC_INIT_STATE_NULL 0x0000
1486 #define ASC_INIT_STATE_BEG_GET_CFG 0x0001
1487 #define ASC_INIT_STATE_END_GET_CFG 0x0002
1488 #define ASC_INIT_STATE_BEG_SET_CFG 0x0004
1489 #define ASC_INIT_STATE_END_SET_CFG 0x0008
1490 #define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
1491 #define ASC_INIT_STATE_END_LOAD_MC 0x0020
1492 #define ASC_INIT_STATE_BEG_INQUIRY 0x0040
1493 #define ASC_INIT_STATE_END_INQUIRY 0x0080
1494 #define ASC_INIT_RESET_SCSI_DONE 0x0100
1495 #define ASC_INIT_STATE_WITHOUT_EEP 0x8000
1496 #define ASC_PCI_DEVICE_ID_REV_A 0x1100
1497 #define ASC_PCI_DEVICE_ID_REV_B 0x1200
1498 #define ASC_BUG_FIX_IF_NOT_DWB 0x0001
1499 #define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
1500 #define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
1501 #define ASC_MIN_TAGGED_CMD 7
1502 #define ASC_MAX_SCSI_RESET_WAIT 30
1504 struct asc_dvc_var; /* Forward Declaration. */
1506 typedef void (* ASC_ISR_CALLBACK)(struct asc_dvc_var *, ASC_QDONE_INFO *);
1507 typedef int (* ASC_EXE_CALLBACK)(struct asc_dvc_var *, ASC_SCSI_Q *);
1509 typedef struct asc_dvc_var {
1513 ushort bug_fix_cntl;
1515 ASC_ISR_CALLBACK isr_callback;
1516 ASC_EXE_CALLBACK exe_callback;
1517 ASC_SCSI_BIT_ID_TYPE init_sdtr;
1518 ASC_SCSI_BIT_ID_TYPE sdtr_done;
1519 ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
1520 ASC_SCSI_BIT_ID_TYPE unit_not_ready;
1521 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
1522 ASC_SCSI_BIT_ID_TYPE start_motor;
1523 uchar scsi_reset_wait;
1526 uchar max_total_qng;
1527 uchar cur_total_qng;
1528 uchar in_critical_cnt;
1530 uchar last_q_shortage;
1532 uchar cur_dvc_qng[ASC_MAX_TID + 1];
1533 uchar max_dvc_qng[ASC_MAX_TID + 1];
1534 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
1535 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
1536 uchar sdtr_period_tbl[ASC_MAX_SYN_XFER_NO];
1538 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
1541 uchar dos_int13_table[ASC_MAX_TID + 1];
1542 ASC_DCNT max_dma_count;
1543 ASC_SCSI_BIT_ID_TYPE no_scam;
1544 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
1545 uchar max_sdtr_index;
1546 uchar host_init_sdtr_index;
1547 struct asc_board *drv_ptr;
1551 typedef struct asc_dvc_inq_info {
1552 uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
1555 typedef struct asc_cap_info {
1560 typedef struct asc_cap_info_array {
1561 ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
1562 } ASC_CAP_INFO_ARRAY;
1564 #define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
1565 #define ASC_MCNTL_NULL_TARGET (ushort)0x0002
1566 #define ASC_CNTL_INITIATOR (ushort)0x0001
1567 #define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
1568 #define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
1569 #define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
1570 #define ASC_CNTL_NO_SCAM (ushort)0x0010
1571 #define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
1572 #define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
1573 #define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
1574 #define ASC_CNTL_RESET_SCSI (ushort)0x0200
1575 #define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
1576 #define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
1577 #define ASC_CNTL_SCSI_PARITY (ushort)0x1000
1578 #define ASC_CNTL_BURST_MODE (ushort)0x2000
1579 #define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
1580 #define ASC_EEP_DVC_CFG_BEG_VL 2
1581 #define ASC_EEP_MAX_DVC_ADDR_VL 15
1582 #define ASC_EEP_DVC_CFG_BEG 32
1583 #define ASC_EEP_MAX_DVC_ADDR 45
1584 #define ASC_EEP_DEFINED_WORDS 10
1585 #define ASC_EEP_MAX_ADDR 63
1586 #define ASC_EEP_RES_WORDS 0
1587 #define ASC_EEP_MAX_RETRY 20
1588 #define ASC_MAX_INIT_BUSY_RETRY 8
1589 #define ASC_EEP_ISA_PNP_WSIZE 16
1592 * These macros keep the chip SCSI id and ISA DMA speed
1593 * bitfields in board order. C bitfields aren't portable
1594 * between big and little-endian platforms so they are
1598 #define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
1599 #define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
1600 #define ASC_EEP_SET_CHIP_ID(cfg, sid) \
1601 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
1602 #define ASC_EEP_SET_DMA_SPD(cfg, spd) \
1603 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
1605 typedef struct asceep_config {
1612 uchar max_total_qng;
1615 uchar power_up_wait;
1617 uchar id_speed; /* low order 4 bits is chip scsi id */
1618 /* high order 4 bits is isa dma speed */
1619 uchar dos_int13_table[ASC_MAX_TID + 1];
1620 uchar adapter_info[6];
1625 #define ASC_PCI_CFG_LSW_SCSI_PARITY 0x0800
1626 #define ASC_PCI_CFG_LSW_BURST_MODE 0x0080
1627 #define ASC_PCI_CFG_LSW_INTR_ABLE 0x0020
1629 #define ASC_EEP_CMD_READ 0x80
1630 #define ASC_EEP_CMD_WRITE 0x40
1631 #define ASC_EEP_CMD_WRITE_ABLE 0x30
1632 #define ASC_EEP_CMD_WRITE_DISABLE 0x00
1633 #define ASC_OVERRUN_BSIZE 0x00000048UL
1634 #define ASC_CTRL_BREAK_ONCE 0x0001
1635 #define ASC_CTRL_BREAK_STAY_IDLE 0x0002
1636 #define ASCV_MSGOUT_BEG 0x0000
1637 #define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
1638 #define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
1639 #define ASCV_BREAK_SAVED_CODE (ushort)0x0006
1640 #define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
1641 #define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
1642 #define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
1643 #define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
1644 #define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
1645 #define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
1646 #define ASCV_BREAK_ADDR (ushort)0x0028
1647 #define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
1648 #define ASCV_BREAK_CONTROL (ushort)0x002C
1649 #define ASCV_BREAK_HIT_COUNT (ushort)0x002E
1651 #define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
1652 #define ASCV_MCODE_CHKSUM_W (ushort)0x0032
1653 #define ASCV_MCODE_SIZE_W (ushort)0x0034
1654 #define ASCV_STOP_CODE_B (ushort)0x0036
1655 #define ASCV_DVC_ERR_CODE_B (ushort)0x0037
1656 #define ASCV_OVERRUN_PADDR_D (ushort)0x0038
1657 #define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
1658 #define ASCV_HALTCODE_W (ushort)0x0040
1659 #define ASCV_CHKSUM_W (ushort)0x0042
1660 #define ASCV_MC_DATE_W (ushort)0x0044
1661 #define ASCV_MC_VER_W (ushort)0x0046
1662 #define ASCV_NEXTRDY_B (ushort)0x0048
1663 #define ASCV_DONENEXT_B (ushort)0x0049
1664 #define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
1665 #define ASCV_SCSIBUSY_B (ushort)0x004B
1666 #define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
1667 #define ASCV_CURCDB_B (ushort)0x004D
1668 #define ASCV_RCLUN_B (ushort)0x004E
1669 #define ASCV_BUSY_QHEAD_B (ushort)0x004F
1670 #define ASCV_DISC1_QHEAD_B (ushort)0x0050
1671 #define ASCV_DISC_ENABLE_B (ushort)0x0052
1672 #define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
1673 #define ASCV_HOSTSCSI_ID_B (ushort)0x0055
1674 #define ASCV_MCODE_CNTL_B (ushort)0x0056
1675 #define ASCV_NULL_TARGET_B (ushort)0x0057
1676 #define ASCV_FREE_Q_HEAD_W (ushort)0x0058
1677 #define ASCV_DONE_Q_TAIL_W (ushort)0x005A
1678 #define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
1679 #define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
1680 #define ASCV_HOST_FLAG_B (ushort)0x005D
1681 #define ASCV_TOTAL_READY_Q_B (ushort)0x0064
1682 #define ASCV_VER_SERIAL_B (ushort)0x0065
1683 #define ASCV_HALTCODE_SAVED_W (ushort)0x0066
1684 #define ASCV_WTM_FLAG_B (ushort)0x0068
1685 #define ASCV_RISC_FLAG_B (ushort)0x006A
1686 #define ASCV_REQ_SG_LIST_QP (ushort)0x006B
1687 #define ASC_HOST_FLAG_IN_ISR 0x01
1688 #define ASC_HOST_FLAG_ACK_INT 0x02
1689 #define ASC_RISC_FLAG_GEN_INT 0x01
1690 #define ASC_RISC_FLAG_REQ_SG_LIST 0x02
1691 #define IOP_CTRL (0x0F)
1692 #define IOP_STATUS (0x0E)
1693 #define IOP_INT_ACK IOP_STATUS
1694 #define IOP_REG_IFC (0x0D)
1695 #define IOP_SYN_OFFSET (0x0B)
1696 #define IOP_EXTRA_CONTROL (0x0D)
1697 #define IOP_REG_PC (0x0C)
1698 #define IOP_RAM_ADDR (0x0A)
1699 #define IOP_RAM_DATA (0x08)
1700 #define IOP_EEP_DATA (0x06)
1701 #define IOP_EEP_CMD (0x07)
1702 #define IOP_VERSION (0x03)
1703 #define IOP_CONFIG_HIGH (0x04)
1704 #define IOP_CONFIG_LOW (0x02)
1705 #define IOP_SIG_BYTE (0x01)
1706 #define IOP_SIG_WORD (0x00)
1707 #define IOP_REG_DC1 (0x0E)
1708 #define IOP_REG_DC0 (0x0C)
1709 #define IOP_REG_SB (0x0B)
1710 #define IOP_REG_DA1 (0x0A)
1711 #define IOP_REG_DA0 (0x08)
1712 #define IOP_REG_SC (0x09)
1713 #define IOP_DMA_SPEED (0x07)
1714 #define IOP_REG_FLAG (0x07)
1715 #define IOP_FIFO_H (0x06)
1716 #define IOP_FIFO_L (0x04)
1717 #define IOP_REG_ID (0x05)
1718 #define IOP_REG_QP (0x03)
1719 #define IOP_REG_IH (0x02)
1720 #define IOP_REG_IX (0x01)
1721 #define IOP_REG_AX (0x00)
1722 #define IFC_REG_LOCK (0x00)
1723 #define IFC_REG_UNLOCK (0x09)
1724 #define IFC_WR_EN_FILTER (0x10)
1725 #define IFC_RD_NO_EEPROM (0x10)
1726 #define IFC_SLEW_RATE (0x20)
1727 #define IFC_ACT_NEG (0x40)
1728 #define IFC_INP_FILTER (0x80)
1729 #define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
1730 #define SC_SEL (uchar)(0x80)
1731 #define SC_BSY (uchar)(0x40)
1732 #define SC_ACK (uchar)(0x20)
1733 #define SC_REQ (uchar)(0x10)
1734 #define SC_ATN (uchar)(0x08)
1735 #define SC_IO (uchar)(0x04)
1736 #define SC_CD (uchar)(0x02)
1737 #define SC_MSG (uchar)(0x01)
1738 #define SEC_SCSI_CTL (uchar)(0x80)
1739 #define SEC_ACTIVE_NEGATE (uchar)(0x40)
1740 #define SEC_SLEW_RATE (uchar)(0x20)
1741 #define SEC_ENABLE_FILTER (uchar)(0x10)
1742 #define ASC_HALT_EXTMSG_IN (ushort)0x8000
1743 #define ASC_HALT_CHK_CONDITION (ushort)0x8100
1744 #define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
1745 #define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
1746 #define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
1747 #define ASC_HALT_SDTR_REJECTED (ushort)0x4000
1748 #define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
1749 #define ASC_MAX_QNO 0xF8
1750 #define ASC_DATA_SEC_BEG (ushort)0x0080
1751 #define ASC_DATA_SEC_END (ushort)0x0080
1752 #define ASC_CODE_SEC_BEG (ushort)0x0080
1753 #define ASC_CODE_SEC_END (ushort)0x0080
1754 #define ASC_QADR_BEG (0x4000)
1755 #define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
1756 #define ASC_QADR_END (ushort)0x7FFF
1757 #define ASC_QLAST_ADR (ushort)0x7FC0
1758 #define ASC_QBLK_SIZE 0x40
1759 #define ASC_BIOS_DATA_QBEG 0xF8
1760 #define ASC_MIN_ACTIVE_QNO 0x01
1761 #define ASC_QLINK_END 0xFF
1762 #define ASC_EEPROM_WORDS 0x10
1763 #define ASC_MAX_MGS_LEN 0x10
1764 #define ASC_BIOS_ADDR_DEF 0xDC00
1765 #define ASC_BIOS_SIZE 0x3800
1766 #define ASC_BIOS_RAM_OFF 0x3800
1767 #define ASC_BIOS_RAM_SIZE 0x800
1768 #define ASC_BIOS_MIN_ADDR 0xC000
1769 #define ASC_BIOS_MAX_ADDR 0xEC00
1770 #define ASC_BIOS_BANK_SIZE 0x0400
1771 #define ASC_MCODE_START_ADDR 0x0080
1772 #define ASC_CFG0_HOST_INT_ON 0x0020
1773 #define ASC_CFG0_BIOS_ON 0x0040
1774 #define ASC_CFG0_VERA_BURST_ON 0x0080
1775 #define ASC_CFG0_SCSI_PARITY_ON 0x0800
1776 #define ASC_CFG1_SCSI_TARGET_ON 0x0080
1777 #define ASC_CFG1_LRAM_8BITS_ON 0x0800
1778 #define ASC_CFG_MSW_CLR_MASK 0x3080
1779 #define CSW_TEST1 (ASC_CS_TYPE)0x8000
1780 #define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
1781 #define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
1782 #define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
1783 #define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
1784 #define CSW_TEST2 (ASC_CS_TYPE)0x0400
1785 #define CSW_TEST3 (ASC_CS_TYPE)0x0200
1786 #define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
1787 #define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
1788 #define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
1789 #define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
1790 #define CSW_HALTED (ASC_CS_TYPE)0x0010
1791 #define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
1792 #define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
1793 #define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
1794 #define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
1795 #define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
1796 #define CIW_INT_ACK (ASC_CS_TYPE)0x0100
1797 #define CIW_TEST1 (ASC_CS_TYPE)0x0200
1798 #define CIW_TEST2 (ASC_CS_TYPE)0x0400
1799 #define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
1800 #define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
1801 #define CC_CHIP_RESET (uchar)0x80
1802 #define CC_SCSI_RESET (uchar)0x40
1803 #define CC_HALT (uchar)0x20
1804 #define CC_SINGLE_STEP (uchar)0x10
1805 #define CC_DMA_ABLE (uchar)0x08
1806 #define CC_TEST (uchar)0x04
1807 #define CC_BANK_ONE (uchar)0x02
1808 #define CC_DIAG (uchar)0x01
1809 #define ASC_1000_ID0W 0x04C1
1810 #define ASC_1000_ID0W_FIX 0x00C1
1811 #define ASC_1000_ID1B 0x25
1812 #define ASC_EISA_BIG_IOP_GAP (0x1C30-0x0C50)
1813 #define ASC_EISA_SMALL_IOP_GAP (0x0020)
1814 #define ASC_EISA_MIN_IOP_ADDR (0x0C30)
1815 #define ASC_EISA_MAX_IOP_ADDR (0xFC50)
1816 #define ASC_EISA_REV_IOP_MASK (0x0C83)
1817 #define ASC_EISA_PID_IOP_MASK (0x0C80)
1818 #define ASC_EISA_CFG_IOP_MASK (0x0C86)
1819 #define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
1820 #define ASC_EISA_ID_740 0x01745004UL
1821 #define ASC_EISA_ID_750 0x01755004UL
1822 #define INS_HALTINT (ushort)0x6281
1823 #define INS_HALT (ushort)0x6280
1824 #define INS_SINT (ushort)0x6200
1825 #define INS_RFLAG_WTM (ushort)0x7380
1826 #define ASC_MC_SAVE_CODE_WSIZE 0x500
1827 #define ASC_MC_SAVE_DATA_WSIZE 0x40
1829 typedef struct asc_mc_saved {
1830 ushort data[ASC_MC_SAVE_DATA_WSIZE];
1831 ushort code[ASC_MC_SAVE_CODE_WSIZE];
1834 #define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
1835 #define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
1836 #define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
1837 #define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
1838 #define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
1839 #define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
1840 #define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
1841 #define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
1842 #define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
1843 #define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
1844 #define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data));
1845 #define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id));
1846 #define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data);
1847 #define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id));
1848 #define AscSynIndexToPeriod(index) (uchar)(asc_dvc->sdtr_period_tbl[ (index) ])
1849 #define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
1850 #define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
1851 #define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
1852 #define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
1853 #define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
1854 #define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
1855 #define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
1856 #define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
1857 #define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
1858 #define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
1859 #define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
1860 #define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
1861 #define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
1862 #define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
1863 #define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
1864 #define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
1865 #define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
1866 #define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
1867 #define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
1868 #define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
1869 #define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
1870 #define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
1871 #define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
1872 #define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
1873 #define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
1874 #define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
1875 #define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
1876 #define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
1877 #define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
1878 #define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
1879 #define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
1880 #define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
1881 #define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
1882 #define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
1883 #define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
1884 #define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
1885 #define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
1886 #define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
1887 #define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
1888 #define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
1889 #define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
1890 #define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
1891 #define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
1892 #define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
1893 #define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
1894 #define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
1895 #define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
1896 #define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
1897 #define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
1898 #define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
1899 #define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
1900 #define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
1901 #define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
1903 STATIC int AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg);
1904 STATIC int AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg);
1905 STATIC void AscWaitEEPRead(void);
1906 STATIC void AscWaitEEPWrite(void);
1907 STATIC ushort AscReadEEPWord(PortAddr, uchar);
1908 STATIC ushort AscWriteEEPWord(PortAddr, uchar, ushort);
1909 STATIC ushort AscGetEEPConfig(PortAddr, ASCEEP_CONFIG *, ushort);
1910 STATIC int AscSetEEPConfigOnce(PortAddr, ASCEEP_CONFIG *, ushort);
1911 STATIC int AscSetEEPConfig(PortAddr, ASCEEP_CONFIG *, ushort);
1912 STATIC int AscStartChip(PortAddr);
1913 STATIC int AscStopChip(PortAddr);
1914 STATIC void AscSetChipIH(PortAddr, ushort);
1915 STATIC int AscIsChipHalted(PortAddr);
1916 STATIC void AscAckInterrupt(PortAddr);
1917 STATIC void AscDisableInterrupt(PortAddr);
1918 STATIC void AscEnableInterrupt(PortAddr);
1919 STATIC void AscSetBank(PortAddr, uchar);
1920 STATIC int AscResetChipAndScsiBus(ASC_DVC_VAR *);
1922 STATIC ushort AscGetIsaDmaChannel(PortAddr);
1923 STATIC ushort AscSetIsaDmaChannel(PortAddr, ushort);
1924 STATIC uchar AscSetIsaDmaSpeed(PortAddr, uchar);
1925 STATIC uchar AscGetIsaDmaSpeed(PortAddr);
1926 #endif /* CONFIG_ISA */
1927 STATIC uchar AscReadLramByte(PortAddr, ushort);
1928 STATIC ushort AscReadLramWord(PortAddr, ushort);
1929 #if CC_VERY_LONG_SG_LIST
1930 STATIC ASC_DCNT AscReadLramDWord(PortAddr, ushort);
1931 #endif /* CC_VERY_LONG_SG_LIST */
1932 STATIC void AscWriteLramWord(PortAddr, ushort, ushort);
1933 STATIC void AscWriteLramByte(PortAddr, ushort, uchar);
1934 STATIC ASC_DCNT AscMemSumLramWord(PortAddr, ushort, int);
1935 STATIC void AscMemWordSetLram(PortAddr, ushort, ushort, int);
1936 STATIC void AscMemWordCopyPtrToLram(PortAddr, ushort, uchar *, int);
1937 STATIC void AscMemDWordCopyPtrToLram(PortAddr, ushort, uchar *, int);
1938 STATIC void AscMemWordCopyPtrFromLram(PortAddr, ushort, uchar *, int);
1939 STATIC ushort AscInitAscDvcVar(ASC_DVC_VAR *);
1940 STATIC ushort AscInitFromEEP(ASC_DVC_VAR *);
1941 STATIC ushort AscInitFromAscDvcVar(ASC_DVC_VAR *);
1942 STATIC ushort AscInitMicroCodeVar(ASC_DVC_VAR *);
1943 STATIC int AscTestExternalLram(ASC_DVC_VAR *);
1944 STATIC uchar AscMsgOutSDTR(ASC_DVC_VAR *, uchar, uchar);
1945 STATIC uchar AscCalSDTRData(ASC_DVC_VAR *, uchar, uchar);
1946 STATIC void AscSetChipSDTR(PortAddr, uchar, uchar);
1947 STATIC uchar AscGetSynPeriodIndex(ASC_DVC_VAR *, uchar);
1948 STATIC uchar AscAllocFreeQueue(PortAddr, uchar);
1949 STATIC uchar AscAllocMultipleFreeQueue(PortAddr, uchar, uchar);
1950 STATIC int AscHostReqRiscHalt(PortAddr);
1951 STATIC int AscStopQueueExe(PortAddr);
1952 STATIC int AscSendScsiQueue(ASC_DVC_VAR *,
1954 uchar n_q_required);
1955 STATIC int AscPutReadyQueue(ASC_DVC_VAR *,
1956 ASC_SCSI_Q *, uchar);
1957 STATIC int AscPutReadySgListQueue(ASC_DVC_VAR *,
1958 ASC_SCSI_Q *, uchar);
1959 STATIC int AscSetChipSynRegAtID(PortAddr, uchar, uchar);
1960 STATIC int AscSetRunChipSynRegAtID(PortAddr, uchar, uchar);
1961 STATIC ushort AscInitLram(ASC_DVC_VAR *);
1962 STATIC ushort AscInitQLinkVar(ASC_DVC_VAR *);
1963 STATIC int AscSetLibErrorCode(ASC_DVC_VAR *, ushort);
1964 STATIC int AscIsrChipHalted(ASC_DVC_VAR *);
1965 STATIC uchar _AscCopyLramScsiDoneQ(PortAddr, ushort,
1966 ASC_QDONE_INFO *, ASC_DCNT);
1967 STATIC int AscIsrQDone(ASC_DVC_VAR *);
1968 STATIC int AscCompareString(uchar *, uchar *, int);
1970 STATIC ushort AscGetEisaChipCfg(PortAddr);
1971 STATIC ASC_DCNT AscGetEisaProductID(PortAddr);
1972 STATIC PortAddr AscSearchIOPortAddrEISA(PortAddr);
1973 STATIC PortAddr AscSearchIOPortAddr11(PortAddr);
1974 STATIC PortAddr AscSearchIOPortAddr(PortAddr, ushort);
1975 STATIC void AscSetISAPNPWaitForKey(void);
1976 #endif /* CONFIG_ISA */
1977 STATIC uchar AscGetChipScsiCtrl(PortAddr);
1978 STATIC uchar AscSetChipScsiID(PortAddr, uchar);
1979 STATIC uchar AscGetChipVersion(PortAddr, ushort);
1980 STATIC ushort AscGetChipBusType(PortAddr);
1981 STATIC ASC_DCNT AscLoadMicroCode(PortAddr, ushort, uchar *, ushort);
1982 STATIC int AscFindSignature(PortAddr);
1983 STATIC void AscToggleIRQAct(PortAddr);
1984 STATIC uchar AscGetChipIRQ(PortAddr, ushort);
1985 STATIC uchar AscSetChipIRQ(PortAddr, uchar, ushort);
1986 STATIC ushort AscGetChipBiosAddress(PortAddr, ushort);
1987 STATIC inline ulong DvcEnterCritical(void);
1988 STATIC inline void DvcLeaveCritical(ulong);
1990 STATIC uchar DvcReadPCIConfigByte(ASC_DVC_VAR *, ushort);
1991 STATIC void DvcWritePCIConfigByte(ASC_DVC_VAR *,
1993 #endif /* CONFIG_PCI */
1994 STATIC ushort AscGetChipBiosAddress(PortAddr, ushort);
1995 STATIC void DvcSleepMilliSecond(ASC_DCNT);
1996 STATIC void DvcDelayNanoSecond(ASC_DVC_VAR *, ASC_DCNT);
1997 STATIC void DvcPutScsiQ(PortAddr, ushort, uchar *, int);
1998 STATIC void DvcGetQinfo(PortAddr, ushort, uchar *, int);
1999 STATIC ushort AscInitGetConfig(ASC_DVC_VAR *);
2000 STATIC ushort AscInitSetConfig(ASC_DVC_VAR *);
2001 STATIC ushort AscInitAsc1000Driver(ASC_DVC_VAR *);
2002 STATIC void AscAsyncFix(ASC_DVC_VAR *, uchar,
2003 ASC_SCSI_INQUIRY *);
2004 STATIC int AscTagQueuingSafe(ASC_SCSI_INQUIRY *);
2005 STATIC void AscInquiryHandling(ASC_DVC_VAR *,
2006 uchar, ASC_SCSI_INQUIRY *);
2007 STATIC int AscExeScsiQueue(ASC_DVC_VAR *, ASC_SCSI_Q *);
2008 STATIC int AscISR(ASC_DVC_VAR *);
2009 STATIC uint AscGetNumOfFreeQueue(ASC_DVC_VAR *, uchar,
2011 STATIC int AscSgListToQueue(int);
2013 STATIC void AscEnableIsaDma(uchar);
2014 #endif /* CONFIG_ISA */
2015 STATIC ASC_DCNT AscGetMaxDmaCount(ushort);
2019 * --- Adv Library Constants and Macros
2022 #define ADV_LIB_VERSION_MAJOR 5
2023 #define ADV_LIB_VERSION_MINOR 14
2026 * Define Adv Library required special types.
2030 * Portable Data Types
2032 * Any instance where a 32-bit long or pointer type is assumed
2033 * for precision or HW defined structures, the following define
2034 * types must be used. In Linux the char, short, and int types
2035 * are all consistent at 8, 16, and 32 bits respectively. Pointers
2036 * and long types are 64 bits on Alpha and UltraSPARC.
2038 #define ADV_PADDR __u32 /* Physical address data type. */
2039 #define ADV_VADDR __u32 /* Virtual address data type. */
2040 #define ADV_DCNT __u32 /* Unsigned Data count type. */
2041 #define ADV_SDCNT __s32 /* Signed Data count type. */
2044 * These macros are used to convert a virtual address to a
2045 * 32-bit value. This currently can be used on Linux Alpha
2046 * which uses 64-bit virtual address but a 32-bit bus address.
2047 * This is likely to break in the future, but doing this now
2048 * will give us time to change the HW and FW to handle 64-bit
2051 #define ADV_VADDR_TO_U32 virt_to_bus
2052 #define ADV_U32_TO_VADDR bus_to_virt
2054 #define AdvPortAddr ulong /* Virtual memory address size */
2057 * Define Adv Library required memory access macros.
2059 #define ADV_MEM_READB(addr) readb(addr)
2060 #define ADV_MEM_READW(addr) readw(addr)
2061 #define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
2062 #define ADV_MEM_WRITEW(addr, word) writew(word, addr)
2063 #define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
2065 #define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 15)
2068 * For wide boards a CDB length maximum of 16 bytes
2071 #define ADV_MAX_CDB_LEN 16
2074 * Define total number of simultaneous maximum element scatter-gather
2075 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
2076 * maximum number of outstanding commands per wide host adapter. Each
2077 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
2078 * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
2079 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
2080 * structures or 255 scatter-gather elements.
2083 #define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
2086 * Define Adv Library required maximum number of scatter-gather
2087 * elements per request.
2089 #define ADV_MAX_SG_LIST 255
2091 /* Number of SG blocks needed. */
2092 #define ADV_NUM_SG_BLOCK \
2093 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK)
2095 /* Total contiguous memory needed for SG blocks. */
2096 #define ADV_SG_TOTAL_MEM_SIZE \
2097 (sizeof(ADV_SG_BLOCK) * ADV_NUM_SG_BLOCK)
2099 #define ADV_PAGE_SIZE PAGE_SIZE
2101 #define ADV_NUM_PAGE_CROSSING \
2102 ((ADV_SG_TOTAL_MEM_SIZE + (ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE)
2105 #define ADV_PCI_VENDOR_ID 0x10CD
2106 #define ADV_PCI_DEVICE_ID_REV_A 0x2300
2107 #define ADV_PCI_DEVID_38C0800_REV1 0x2500
2108 #define ADV_PCI_DEVID_38C1600_REV1 0x2700
2110 #define ADV_EEP_DVC_CFG_BEGIN (0x00)
2111 #define ADV_EEP_DVC_CFG_END (0x15)
2112 #define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
2113 #define ADV_EEP_MAX_WORD_ADDR (0x1E)
2115 #define ADV_EEP_DELAY_MS 100
2117 #define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
2118 #define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
2120 * For the ASC3550 Bit 13 is Termination Polarity control bit.
2121 * For later ICs Bit 13 controls whether the CIS (Card Information
2122 * Service Section) is loaded from EEPROM.
2124 #define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
2125 #define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
2129 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
2130 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
2131 * Function 0 will specify INT B.
2133 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
2134 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
2135 * Function 1 will specify INT A.
2137 #define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
2139 typedef struct adveep_3550_config
2141 /* Word Offset, Description */
2143 ushort cfg_lsw; /* 00 power up initialization */
2144 /* bit 13 set - Term Polarity Control */
2145 /* bit 14 set - BIOS Enable */
2146 /* bit 15 set - Big Endian Mode */
2147 ushort cfg_msw; /* 01 unused */
2148 ushort disc_enable; /* 02 disconnect enable */
2149 ushort wdtr_able; /* 03 Wide DTR able */
2150 ushort sdtr_able; /* 04 Synchronous DTR able */
2151 ushort start_motor; /* 05 send start up motor */
2152 ushort tagqng_able; /* 06 tag queuing able */
2153 ushort bios_scan; /* 07 BIOS device control */
2154 ushort scam_tolerant; /* 08 no scam */
2156 uchar adapter_scsi_id; /* 09 Host Adapter ID */
2157 uchar bios_boot_delay; /* power up wait */
2159 uchar scsi_reset_delay; /* 10 reset delay */
2160 uchar bios_id_lun; /* first boot device scsi id & lun */
2161 /* high nibble is lun */
2162 /* low nibble is scsi id */
2164 uchar termination; /* 11 0 - automatic */
2165 /* 1 - low off / high off */
2166 /* 2 - low off / high on */
2167 /* 3 - low on / high on */
2168 /* There is no low on / high off */
2170 uchar reserved1; /* reserved byte (not used) */
2172 ushort bios_ctrl; /* 12 BIOS control bits */
2173 /* bit 0 BIOS don't act as initiator. */
2174 /* bit 1 BIOS > 1 GB support */
2175 /* bit 2 BIOS > 2 Disk Support */
2176 /* bit 3 BIOS don't support removables */
2177 /* bit 4 BIOS support bootable CD */
2178 /* bit 5 BIOS scan enabled */
2179 /* bit 6 BIOS support multiple LUNs */
2180 /* bit 7 BIOS display of message */
2181 /* bit 8 SCAM disabled */
2182 /* bit 9 Reset SCSI bus during init. */
2184 /* bit 11 No verbose initialization. */
2185 /* bit 12 SCSI parity enabled */
2189 ushort ultra_able; /* 13 ULTRA speed able */
2190 ushort reserved2; /* 14 reserved */
2191 uchar max_host_qng; /* 15 maximum host queuing */
2192 uchar max_dvc_qng; /* maximum per device queuing */
2193 ushort dvc_cntl; /* 16 control bit for driver */
2194 ushort bug_fix; /* 17 control bit for bug fix */
2195 ushort serial_number_word1; /* 18 Board serial number word 1 */
2196 ushort serial_number_word2; /* 19 Board serial number word 2 */
2197 ushort serial_number_word3; /* 20 Board serial number word 3 */
2198 ushort check_sum; /* 21 EEP check sum */
2199 uchar oem_name[16]; /* 22 OEM name */
2200 ushort dvc_err_code; /* 30 last device driver error code */
2201 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
2202 ushort adv_err_addr; /* 32 last uc error address */
2203 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
2204 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
2205 ushort saved_adv_err_addr; /* 35 saved last uc error address */
2206 ushort num_of_err; /* 36 number of error */
2207 } ADVEEP_3550_CONFIG;
2209 typedef struct adveep_38C0800_config
2211 /* Word Offset, Description */
2213 ushort cfg_lsw; /* 00 power up initialization */
2214 /* bit 13 set - Load CIS */
2215 /* bit 14 set - BIOS Enable */
2216 /* bit 15 set - Big Endian Mode */
2217 ushort cfg_msw; /* 01 unused */
2218 ushort disc_enable; /* 02 disconnect enable */
2219 ushort wdtr_able; /* 03 Wide DTR able */
2220 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
2221 ushort start_motor; /* 05 send start up motor */
2222 ushort tagqng_able; /* 06 tag queuing able */
2223 ushort bios_scan; /* 07 BIOS device control */
2224 ushort scam_tolerant; /* 08 no scam */
2226 uchar adapter_scsi_id; /* 09 Host Adapter ID */
2227 uchar bios_boot_delay; /* power up wait */
2229 uchar scsi_reset_delay; /* 10 reset delay */
2230 uchar bios_id_lun; /* first boot device scsi id & lun */
2231 /* high nibble is lun */
2232 /* low nibble is scsi id */
2234 uchar termination_se; /* 11 0 - automatic */
2235 /* 1 - low off / high off */
2236 /* 2 - low off / high on */
2237 /* 3 - low on / high on */
2238 /* There is no low on / high off */
2240 uchar termination_lvd; /* 11 0 - automatic */
2241 /* 1 - low off / high off */
2242 /* 2 - low off / high on */
2243 /* 3 - low on / high on */
2244 /* There is no low on / high off */
2246 ushort bios_ctrl; /* 12 BIOS control bits */
2247 /* bit 0 BIOS don't act as initiator. */
2248 /* bit 1 BIOS > 1 GB support */
2249 /* bit 2 BIOS > 2 Disk Support */
2250 /* bit 3 BIOS don't support removables */
2251 /* bit 4 BIOS support bootable CD */
2252 /* bit 5 BIOS scan enabled */
2253 /* bit 6 BIOS support multiple LUNs */
2254 /* bit 7 BIOS display of message */
2255 /* bit 8 SCAM disabled */
2256 /* bit 9 Reset SCSI bus during init. */
2258 /* bit 11 No verbose initialization. */
2259 /* bit 12 SCSI parity enabled */
2263 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
2264 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
2265 uchar max_host_qng; /* 15 maximum host queueing */
2266 uchar max_dvc_qng; /* maximum per device queuing */
2267 ushort dvc_cntl; /* 16 control bit for driver */
2268 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
2269 ushort serial_number_word1; /* 18 Board serial number word 1 */
2270 ushort serial_number_word2; /* 19 Board serial number word 2 */
2271 ushort serial_number_word3; /* 20 Board serial number word 3 */
2272 ushort check_sum; /* 21 EEP check sum */
2273 uchar oem_name[16]; /* 22 OEM name */
2274 ushort dvc_err_code; /* 30 last device driver error code */
2275 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
2276 ushort adv_err_addr; /* 32 last uc error address */
2277 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
2278 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
2279 ushort saved_adv_err_addr; /* 35 saved last uc error address */
2280 ushort reserved36; /* 36 reserved */
2281 ushort reserved37; /* 37 reserved */
2282 ushort reserved38; /* 38 reserved */
2283 ushort reserved39; /* 39 reserved */
2284 ushort reserved40; /* 40 reserved */
2285 ushort reserved41; /* 41 reserved */
2286 ushort reserved42; /* 42 reserved */
2287 ushort reserved43; /* 43 reserved */
2288 ushort reserved44; /* 44 reserved */
2289 ushort reserved45; /* 45 reserved */
2290 ushort reserved46; /* 46 reserved */
2291 ushort reserved47; /* 47 reserved */
2292 ushort reserved48; /* 48 reserved */
2293 ushort reserved49; /* 49 reserved */
2294 ushort reserved50; /* 50 reserved */
2295 ushort reserved51; /* 51 reserved */
2296 ushort reserved52; /* 52 reserved */
2297 ushort reserved53; /* 53 reserved */
2298 ushort reserved54; /* 54 reserved */
2299 ushort reserved55; /* 55 reserved */
2300 ushort cisptr_lsw; /* 56 CIS PTR LSW */
2301 ushort cisprt_msw; /* 57 CIS PTR MSW */
2302 ushort subsysvid; /* 58 SubSystem Vendor ID */
2303 ushort subsysid; /* 59 SubSystem ID */
2304 ushort reserved60; /* 60 reserved */
2305 ushort reserved61; /* 61 reserved */
2306 ushort reserved62; /* 62 reserved */
2307 ushort reserved63; /* 63 reserved */
2308 } ADVEEP_38C0800_CONFIG;
2310 typedef struct adveep_38C1600_config
2312 /* Word Offset, Description */
2314 ushort cfg_lsw; /* 00 power up initialization */
2315 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */
2316 /* clear - Func. 0 INTA, Func. 1 INTB */
2317 /* bit 13 set - Load CIS */
2318 /* bit 14 set - BIOS Enable */
2319 /* bit 15 set - Big Endian Mode */
2320 ushort cfg_msw; /* 01 unused */
2321 ushort disc_enable; /* 02 disconnect enable */
2322 ushort wdtr_able; /* 03 Wide DTR able */
2323 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
2324 ushort start_motor; /* 05 send start up motor */
2325 ushort tagqng_able; /* 06 tag queuing able */
2326 ushort bios_scan; /* 07 BIOS device control */
2327 ushort scam_tolerant; /* 08 no scam */
2329 uchar adapter_scsi_id; /* 09 Host Adapter ID */
2330 uchar bios_boot_delay; /* power up wait */
2332 uchar scsi_reset_delay; /* 10 reset delay */
2333 uchar bios_id_lun; /* first boot device scsi id & lun */
2334 /* high nibble is lun */
2335 /* low nibble is scsi id */
2337 uchar termination_se; /* 11 0 - automatic */
2338 /* 1 - low off / high off */
2339 /* 2 - low off / high on */
2340 /* 3 - low on / high on */
2341 /* There is no low on / high off */
2343 uchar termination_lvd; /* 11 0 - automatic */
2344 /* 1 - low off / high off */
2345 /* 2 - low off / high on */
2346 /* 3 - low on / high on */
2347 /* There is no low on / high off */
2349 ushort bios_ctrl; /* 12 BIOS control bits */
2350 /* bit 0 BIOS don't act as initiator. */
2351 /* bit 1 BIOS > 1 GB support */
2352 /* bit 2 BIOS > 2 Disk Support */
2353 /* bit 3 BIOS don't support removables */
2354 /* bit 4 BIOS support bootable CD */
2355 /* bit 5 BIOS scan enabled */
2356 /* bit 6 BIOS support multiple LUNs */
2357 /* bit 7 BIOS display of message */
2358 /* bit 8 SCAM disabled */
2359 /* bit 9 Reset SCSI bus during init. */
2360 /* bit 10 Basic Integrity Checking disabled */
2361 /* bit 11 No verbose initialization. */
2362 /* bit 12 SCSI parity enabled */
2363 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
2366 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
2367 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
2368 uchar max_host_qng; /* 15 maximum host queueing */
2369 uchar max_dvc_qng; /* maximum per device queuing */
2370 ushort dvc_cntl; /* 16 control bit for driver */
2371 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
2372 ushort serial_number_word1; /* 18 Board serial number word 1 */
2373 ushort serial_number_word2; /* 19 Board serial number word 2 */
2374 ushort serial_number_word3; /* 20 Board serial number word 3 */
2375 ushort check_sum; /* 21 EEP check sum */
2376 uchar oem_name[16]; /* 22 OEM name */
2377 ushort dvc_err_code; /* 30 last device driver error code */
2378 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
2379 ushort adv_err_addr; /* 32 last uc error address */
2380 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
2381 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
2382 ushort saved_adv_err_addr; /* 35 saved last uc error address */
2383 ushort reserved36; /* 36 reserved */
2384 ushort reserved37; /* 37 reserved */
2385 ushort reserved38; /* 38 reserved */
2386 ushort reserved39; /* 39 reserved */
2387 ushort reserved40; /* 40 reserved */
2388 ushort reserved41; /* 41 reserved */
2389 ushort reserved42; /* 42 reserved */
2390 ushort reserved43; /* 43 reserved */
2391 ushort reserved44; /* 44 reserved */
2392 ushort reserved45; /* 45 reserved */
2393 ushort reserved46; /* 46 reserved */
2394 ushort reserved47; /* 47 reserved */
2395 ushort reserved48; /* 48 reserved */
2396 ushort reserved49; /* 49 reserved */
2397 ushort reserved50; /* 50 reserved */
2398 ushort reserved51; /* 51 reserved */
2399 ushort reserved52; /* 52 reserved */
2400 ushort reserved53; /* 53 reserved */
2401 ushort reserved54; /* 54 reserved */
2402 ushort reserved55; /* 55 reserved */
2403 ushort cisptr_lsw; /* 56 CIS PTR LSW */
2404 ushort cisprt_msw; /* 57 CIS PTR MSW */
2405 ushort subsysvid; /* 58 SubSystem Vendor ID */
2406 ushort subsysid; /* 59 SubSystem ID */
2407 ushort reserved60; /* 60 reserved */
2408 ushort reserved61; /* 61 reserved */
2409 ushort reserved62; /* 62 reserved */
2410 ushort reserved63; /* 63 reserved */
2411 } ADVEEP_38C1600_CONFIG;
2416 #define ASC_EEP_CMD_DONE 0x0200
2417 #define ASC_EEP_CMD_DONE_ERR 0x0001
2420 #define EEP_CFG_WORD_BIG_ENDIAN 0x8000
2423 #define BIOS_CTRL_BIOS 0x0001
2424 #define BIOS_CTRL_EXTENDED_XLAT 0x0002
2425 #define BIOS_CTRL_GT_2_DISK 0x0004
2426 #define BIOS_CTRL_BIOS_REMOVABLE 0x0008
2427 #define BIOS_CTRL_BOOTABLE_CD 0x0010
2428 #define BIOS_CTRL_MULTIPLE_LUN 0x0040
2429 #define BIOS_CTRL_DISPLAY_MSG 0x0080
2430 #define BIOS_CTRL_NO_SCAM 0x0100
2431 #define BIOS_CTRL_RESET_SCSI_BUS 0x0200
2432 #define BIOS_CTRL_INIT_VERBOSE 0x0800
2433 #define BIOS_CTRL_SCSI_PARITY 0x1000
2434 #define BIOS_CTRL_AIPP_DIS 0x2000
2436 #define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
2437 #define ADV_3550_IOLEN 0x40 /* I/O Port Range in bytes */
2439 #define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
2440 #define ADV_38C0800_IOLEN 0x100 /* I/O Port Range in bytes */
2443 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
2444 * a special 16K Adv Library and Microcode version. After the issue is
2445 * resolved, should restore 32K support.
2447 * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
2449 #define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
2450 #define ADV_38C1600_IOLEN 0x100 /* I/O Port Range 256 bytes */
2451 #define ADV_38C1600_MEMLEN 0x1000 /* Memory Range 4KB bytes */
2454 * Byte I/O register address from base of 'iop_base'.
2456 #define IOPB_INTR_STATUS_REG 0x00
2457 #define IOPB_CHIP_ID_1 0x01
2458 #define IOPB_INTR_ENABLES 0x02
2459 #define IOPB_CHIP_TYPE_REV 0x03
2460 #define IOPB_RES_ADDR_4 0x04
2461 #define IOPB_RES_ADDR_5 0x05
2462 #define IOPB_RAM_DATA 0x06
2463 #define IOPB_RES_ADDR_7 0x07
2464 #define IOPB_FLAG_REG 0x08
2465 #define IOPB_RES_ADDR_9 0x09
2466 #define IOPB_RISC_CSR 0x0A
2467 #define IOPB_RES_ADDR_B 0x0B
2468 #define IOPB_RES_ADDR_C 0x0C
2469 #define IOPB_RES_ADDR_D 0x0D
2470 #define IOPB_SOFT_OVER_WR 0x0E
2471 #define IOPB_RES_ADDR_F 0x0F
2472 #define IOPB_MEM_CFG 0x10
2473 #define IOPB_RES_ADDR_11 0x11
2474 #define IOPB_GPIO_DATA 0x12
2475 #define IOPB_RES_ADDR_13 0x13
2476 #define IOPB_FLASH_PAGE 0x14
2477 #define IOPB_RES_ADDR_15 0x15
2478 #define IOPB_GPIO_CNTL 0x16
2479 #define IOPB_RES_ADDR_17 0x17
2480 #define IOPB_FLASH_DATA 0x18
2481 #define IOPB_RES_ADDR_19 0x19
2482 #define IOPB_RES_ADDR_1A 0x1A
2483 #define IOPB_RES_ADDR_1B 0x1B
2484 #define IOPB_RES_ADDR_1C 0x1C
2485 #define IOPB_RES_ADDR_1D 0x1D
2486 #define IOPB_RES_ADDR_1E 0x1E
2487 #define IOPB_RES_ADDR_1F 0x1F
2488 #define IOPB_DMA_CFG0 0x20
2489 #define IOPB_DMA_CFG1 0x21
2490 #define IOPB_TICKLE 0x22
2491 #define IOPB_DMA_REG_WR 0x23
2492 #define IOPB_SDMA_STATUS 0x24
2493 #define IOPB_SCSI_BYTE_CNT 0x25
2494 #define IOPB_HOST_BYTE_CNT 0x26
2495 #define IOPB_BYTE_LEFT_TO_XFER 0x27
2496 #define IOPB_BYTE_TO_XFER_0 0x28
2497 #define IOPB_BYTE_TO_XFER_1 0x29
2498 #define IOPB_BYTE_TO_XFER_2 0x2A
2499 #define IOPB_BYTE_TO_XFER_3 0x2B
2500 #define IOPB_ACC_GRP 0x2C
2501 #define IOPB_RES_ADDR_2D 0x2D
2502 #define IOPB_DEV_ID 0x2E
2503 #define IOPB_RES_ADDR_2F 0x2F
2504 #define IOPB_SCSI_DATA 0x30
2505 #define IOPB_RES_ADDR_31 0x31
2506 #define IOPB_RES_ADDR_32 0x32
2507 #define IOPB_SCSI_DATA_HSHK 0x33
2508 #define IOPB_SCSI_CTRL 0x34
2509 #define IOPB_RES_ADDR_35 0x35
2510 #define IOPB_RES_ADDR_36 0x36
2511 #define IOPB_RES_ADDR_37 0x37
2512 #define IOPB_RAM_BIST 0x38
2513 #define IOPB_PLL_TEST 0x39
2514 #define IOPB_PCI_INT_CFG 0x3A
2515 #define IOPB_RES_ADDR_3B 0x3B
2516 #define IOPB_RFIFO_CNT 0x3C
2517 #define IOPB_RES_ADDR_3D 0x3D
2518 #define IOPB_RES_ADDR_3E 0x3E
2519 #define IOPB_RES_ADDR_3F 0x3F
2522 * Word I/O register address from base of 'iop_base'.
2524 #define IOPW_CHIP_ID_0 0x00 /* CID0 */
2525 #define IOPW_CTRL_REG 0x02 /* CC */
2526 #define IOPW_RAM_ADDR 0x04 /* LA */
2527 #define IOPW_RAM_DATA 0x06 /* LD */
2528 #define IOPW_RES_ADDR_08 0x08
2529 #define IOPW_RISC_CSR 0x0A /* CSR */
2530 #define IOPW_SCSI_CFG0 0x0C /* CFG0 */
2531 #define IOPW_SCSI_CFG1 0x0E /* CFG1 */
2532 #define IOPW_RES_ADDR_10 0x10
2533 #define IOPW_SEL_MASK 0x12 /* SM */
2534 #define IOPW_RES_ADDR_14 0x14
2535 #define IOPW_FLASH_ADDR 0x16 /* FA */
2536 #define IOPW_RES_ADDR_18 0x18
2537 #define IOPW_EE_CMD 0x1A /* EC */
2538 #define IOPW_EE_DATA 0x1C /* ED */
2539 #define IOPW_SFIFO_CNT 0x1E /* SFC */
2540 #define IOPW_RES_ADDR_20 0x20
2541 #define IOPW_Q_BASE 0x22 /* QB */
2542 #define IOPW_QP 0x24 /* QP */
2543 #define IOPW_IX 0x26 /* IX */
2544 #define IOPW_SP 0x28 /* SP */
2545 #define IOPW_PC 0x2A /* PC */
2546 #define IOPW_RES_ADDR_2C 0x2C
2547 #define IOPW_RES_ADDR_2E 0x2E
2548 #define IOPW_SCSI_DATA 0x30 /* SD */
2549 #define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
2550 #define IOPW_SCSI_CTRL 0x34 /* SC */
2551 #define IOPW_HSHK_CFG 0x36 /* HCFG */
2552 #define IOPW_SXFR_STATUS 0x36 /* SXS */
2553 #define IOPW_SXFR_CNTL 0x38 /* SXL */
2554 #define IOPW_SXFR_CNTH 0x3A /* SXH */
2555 #define IOPW_RES_ADDR_3C 0x3C
2556 #define IOPW_RFIFO_DATA 0x3E /* RFD */
2559 * Doubleword I/O register address from base of 'iop_base'.
2561 #define IOPDW_RES_ADDR_0 0x00
2562 #define IOPDW_RAM_DATA 0x04
2563 #define IOPDW_RES_ADDR_8 0x08
2564 #define IOPDW_RES_ADDR_C 0x0C
2565 #define IOPDW_RES_ADDR_10 0x10
2566 #define IOPDW_COMMA 0x14
2567 #define IOPDW_COMMB 0x18
2568 #define IOPDW_RES_ADDR_1C 0x1C
2569 #define IOPDW_SDMA_ADDR0 0x20
2570 #define IOPDW_SDMA_ADDR1 0x24
2571 #define IOPDW_SDMA_COUNT 0x28
2572 #define IOPDW_SDMA_ERROR 0x2C
2573 #define IOPDW_RDMA_ADDR0 0x30
2574 #define IOPDW_RDMA_ADDR1 0x34
2575 #define IOPDW_RDMA_COUNT 0x38
2576 #define IOPDW_RDMA_ERROR 0x3C
2578 #define ADV_CHIP_ID_BYTE 0x25
2579 #define ADV_CHIP_ID_WORD 0x04C1
2581 #define ADV_SC_SCSI_BUS_RESET 0x2000
2583 #define ADV_INTR_ENABLE_HOST_INTR 0x01
2584 #define ADV_INTR_ENABLE_SEL_INTR 0x02
2585 #define ADV_INTR_ENABLE_DPR_INTR 0x04
2586 #define ADV_INTR_ENABLE_RTA_INTR 0x08
2587 #define ADV_INTR_ENABLE_RMA_INTR 0x10
2588 #define ADV_INTR_ENABLE_RST_INTR 0x20
2589 #define ADV_INTR_ENABLE_DPE_INTR 0x40
2590 #define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
2592 #define ADV_INTR_STATUS_INTRA 0x01
2593 #define ADV_INTR_STATUS_INTRB 0x02
2594 #define ADV_INTR_STATUS_INTRC 0x04
2596 #define ADV_RISC_CSR_STOP (0x0000)
2597 #define ADV_RISC_TEST_COND (0x2000)
2598 #define ADV_RISC_CSR_RUN (0x4000)
2599 #define ADV_RISC_CSR_SINGLE_STEP (0x8000)
2601 #define ADV_CTRL_REG_HOST_INTR 0x0100
2602 #define ADV_CTRL_REG_SEL_INTR 0x0200
2603 #define ADV_CTRL_REG_DPR_INTR 0x0400
2604 #define ADV_CTRL_REG_RTA_INTR 0x0800
2605 #define ADV_CTRL_REG_RMA_INTR 0x1000
2606 #define ADV_CTRL_REG_RES_BIT14 0x2000
2607 #define ADV_CTRL_REG_DPE_INTR 0x4000
2608 #define ADV_CTRL_REG_POWER_DONE 0x8000
2609 #define ADV_CTRL_REG_ANY_INTR 0xFF00
2611 #define ADV_CTRL_REG_CMD_RESET 0x00C6
2612 #define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
2613 #define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
2614 #define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
2615 #define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
2617 #define ADV_TICKLE_NOP 0x00
2618 #define ADV_TICKLE_A 0x01
2619 #define ADV_TICKLE_B 0x02
2620 #define ADV_TICKLE_C 0x03
2622 #define ADV_SCSI_CTRL_RSTOUT 0x2000
2624 #define AdvIsIntPending(port) \
2625 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
2628 * SCSI_CFG0 Register bit definitions
2630 #define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
2631 #define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
2632 #define EVEN_PARITY 0x1000 /* Select Even Parity */
2633 #define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
2634 #define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
2635 #define PRIM_MODE 0x0100 /* Primitive SCSI mode */
2636 #define SCAM_EN 0x0080 /* Enable SCAM selection */
2637 #define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
2638 #define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
2639 #define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
2640 #define OUR_ID 0x000F /* SCSI ID */
2643 * SCSI_CFG1 Register bit definitions
2645 #define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
2646 #define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
2647 #define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
2648 #define FILTER_SEL 0x0C00 /* Filter Period Selection */
2649 #define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
2650 #define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
2651 #define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
2652 #define ACTIVE_DBL 0x0200 /* Disable Active Negation */
2653 #define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
2654 #define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
2655 #define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
2656 #define TERM_CTL 0x0030 /* External SCSI Termination Bits */
2657 #define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
2658 #define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
2659 #define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
2662 * Addendum for ASC-38C0800 Chip
2664 * The ASC-38C1600 Chip uses the same definitions except that the
2665 * bus mode override bits [12:10] have been moved to byte register
2666 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
2667 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
2668 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
2669 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
2670 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
2672 #define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
2673 #define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
2674 #define HVD 0x1000 /* HVD Device Detect */
2675 #define LVD 0x0800 /* LVD Device Detect */
2676 #define SE 0x0400 /* SE Device Detect */
2677 #define TERM_LVD 0x00C0 /* LVD Termination Bits */
2678 #define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
2679 #define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
2680 #define TERM_SE 0x0030 /* SE Termination Bits */
2681 #define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
2682 #define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
2683 #define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
2684 #define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
2685 #define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
2686 #define C_DET_SE 0x0003 /* SE Cable Detect Bits */
2687 #define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
2688 #define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
2691 #define CABLE_ILLEGAL_A 0x7
2692 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
2694 #define CABLE_ILLEGAL_B 0xB
2695 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
2698 * MEM_CFG Register bit definitions
2700 #define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
2701 #define FAST_EE_CLK 0x20 /* Diagnostic Bit */
2702 #define RAM_SZ 0x1C /* Specify size of RAM to RISC */
2703 #define RAM_SZ_2KB 0x00 /* 2 KB */
2704 #define RAM_SZ_4KB 0x04 /* 4 KB */
2705 #define RAM_SZ_8KB 0x08 /* 8 KB */
2706 #define RAM_SZ_16KB 0x0C /* 16 KB */
2707 #define RAM_SZ_32KB 0x10 /* 32 KB */
2708 #define RAM_SZ_64KB 0x14 /* 64 KB */
2711 * DMA_CFG0 Register bit definitions
2713 * This register is only accessible to the host.
2715 #define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
2716 #define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
2717 #define FIFO_THRESH_16B 0x00 /* 16 bytes */
2718 #define FIFO_THRESH_32B 0x20 /* 32 bytes */
2719 #define FIFO_THRESH_48B 0x30 /* 48 bytes */
2720 #define FIFO_THRESH_64B 0x40 /* 64 bytes */
2721 #define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
2722 #define FIFO_THRESH_96B 0x60 /* 96 bytes */
2723 #define FIFO_THRESH_112B 0x70 /* 112 bytes */
2724 #define START_CTL 0x0C /* DMA start conditions */
2725 #define START_CTL_TH 0x00 /* Wait threshold level (default) */
2726 #define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
2727 #define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
2728 #define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
2729 #define READ_CMD 0x03 /* Memory Read Method */
2730 #define READ_CMD_MR 0x00 /* Memory Read */
2731 #define READ_CMD_MRL 0x02 /* Memory Read Long */
2732 #define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
2735 * ASC-38C0800 RAM BIST Register bit definitions
2737 #define RAM_TEST_MODE 0x80
2738 #define PRE_TEST_MODE 0x40
2739 #define NORMAL_MODE 0x00
2740 #define RAM_TEST_DONE 0x10
2741 #define RAM_TEST_STATUS 0x0F
2742 #define RAM_TEST_HOST_ERROR 0x08
2743 #define RAM_TEST_INTRAM_ERROR 0x04
2744 #define RAM_TEST_RISC_ERROR 0x02
2745 #define RAM_TEST_SCSI_ERROR 0x01
2746 #define RAM_TEST_SUCCESS 0x00
2747 #define PRE_TEST_VALUE 0x05
2748 #define NORMAL_VALUE 0x00
2751 * ASC38C1600 Definitions
2753 * IOPB_PCI_INT_CFG Bit Field Definitions
2756 #define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
2759 * Bit 1 can be set to change the interrupt for the Function to operate in
2760 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
2761 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
2762 * mode, otherwise the operating mode is undefined.
2764 #define TOTEMPOLE 0x02
2767 * Bit 0 can be used to change the Int Pin for the Function. The value is
2768 * 0 by default for both Functions with Function 0 using INT A and Function
2769 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
2772 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
2773 * value specified in the PCI Configuration Space.
2780 * Adv Library Status Definitions
2784 #define ADV_NOERROR 1
2785 #define ADV_SUCCESS 1
2787 #define ADV_ERROR (-1)
2791 * ADV_DVC_VAR 'warn_code' values
2793 #define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
2794 #define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
2795 #define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
2796 #define ASC_WARN_SET_PCI_CONFIG_SPACE 0x0080 /* PCI config space set error */
2797 #define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
2799 #define ADV_MAX_TID 15 /* max. target identifier */
2800 #define ADV_MAX_LUN 7 /* max. logical unit number */
2803 * Error code values are set in ADV_DVC_VAR 'err_code'.
2805 #define ASC_IERR_WRITE_EEPROM 0x0001 /* write EEPROM error */
2806 #define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
2807 #define ASC_IERR_NO_CARRIER 0x0004 /* No more carrier memory. */
2808 #define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
2809 #define ASC_IERR_CHIP_VERSION 0x0040 /* wrong chip version */
2810 #define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
2811 #define ASC_IERR_HVD_DEVICE 0x0100 /* HVD attached to LVD connector. */
2812 #define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
2813 #define ASC_IERR_ILLEGAL_CONNECTION 0x0400 /* Illegal cable connection */
2814 #define ASC_IERR_SINGLE_END_DEVICE 0x0800 /* Single-end used w/differential */
2815 #define ASC_IERR_REVERSED_CABLE 0x1000 /* Narrow flat cable reversed */
2816 #define ASC_IERR_BIST_PRE_TEST 0x2000 /* BIST pre-test error */
2817 #define ASC_IERR_BIST_RAM_TEST 0x4000 /* BIST RAM test error */
2818 #define ASC_IERR_BAD_CHIPTYPE 0x8000 /* Invalid 'chip_type' setting. */
2821 * Fixed locations of microcode operating variables.
2823 #define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
2824 #define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
2825 #define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
2826 #define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
2827 #define ASC_MC_VERSION_NUM 0x003A /* microcode number */
2828 #define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
2829 #define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
2830 #define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
2831 #define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
2832 #define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
2833 #define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
2834 #define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
2835 #define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
2836 #define ASC_MC_CHIP_TYPE 0x009A
2837 #define ASC_MC_INTRB_CODE 0x009B
2838 #define ASC_MC_WDTR_ABLE 0x009C
2839 #define ASC_MC_SDTR_ABLE 0x009E
2840 #define ASC_MC_TAGQNG_ABLE 0x00A0
2841 #define ASC_MC_DISC_ENABLE 0x00A2
2842 #define ASC_MC_IDLE_CMD_STATUS 0x00A4
2843 #define ASC_MC_IDLE_CMD 0x00A6
2844 #define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
2845 #define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
2846 #define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
2847 #define ASC_MC_DEFAULT_MEM_CFG 0x00B0
2848 #define ASC_MC_DEFAULT_SEL_MASK 0x00B2
2849 #define ASC_MC_SDTR_DONE 0x00B6
2850 #define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
2851 #define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
2852 #define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
2853 #define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
2854 #define ASC_MC_WDTR_DONE 0x0124
2855 #define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
2856 #define ASC_MC_ICQ 0x0160
2857 #define ASC_MC_IRQ 0x0164
2858 #define ASC_MC_PPR_ABLE 0x017A
2861 * BIOS LRAM variable absolute offsets.
2863 #define BIOS_CODESEG 0x54
2864 #define BIOS_CODELEN 0x56
2865 #define BIOS_SIGNATURE 0x58
2866 #define BIOS_VERSION 0x5A
2869 * Microcode Control Flags
2871 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
2872 * and handled by the microcode.
2874 #define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
2875 #define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
2878 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
2880 #define HSHK_CFG_WIDE_XFR 0x8000
2881 #define HSHK_CFG_RATE 0x0F00
2882 #define HSHK_CFG_OFFSET 0x001F
2884 #define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
2885 #define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
2886 #define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
2887 #define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
2889 #define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
2890 #define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
2891 #define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
2892 #define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
2893 #define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
2895 #define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
2896 #define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
2897 #define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
2898 #define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
2899 #define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
2901 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
2902 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
2904 #define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
2905 #define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
2908 * All fields here are accessed by the board microcode and need to be
2911 typedef struct adv_carr_t
2913 ADV_VADDR carr_va; /* Carrier Virtual Address */
2914 ADV_PADDR carr_pa; /* Carrier Physical Address */
2915 ADV_VADDR areq_vpa; /* ASC_SCSI_REQ_Q Virtual or Physical Address */
2917 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer
2919 * next_vpa [3:1] Reserved Bits
2920 * next_vpa [0] Done Flag set in Response Queue.
2926 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
2928 #define ASC_NEXT_VPA_MASK 0xFFFFFFF0
2930 #define ASC_RQ_DONE 0x00000001
2931 #define ASC_RQ_GOOD 0x00000002
2932 #define ASC_CQ_STOPPER 0x00000000
2934 #define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
2936 #define ADV_CARRIER_NUM_PAGE_CROSSING \
2937 (((ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) + \
2938 (ADV_PAGE_SIZE - 1))/ADV_PAGE_SIZE)
2940 #define ADV_CARRIER_BUFSIZE \
2941 ((ADV_CARRIER_COUNT + ADV_CARRIER_NUM_PAGE_CROSSING) * sizeof(ADV_CARR_T))
2944 * ASC_SCSI_REQ_Q 'a_flag' definitions
2946 * The Adv Library should limit use to the lower nibble (4 bits) of
2947 * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
2949 #define ADV_POLL_REQUEST 0x01 /* poll for request completion */
2950 #define ADV_SCSIQ_DONE 0x02 /* request done */
2951 #define ADV_DONT_RETRY 0x08 /* don't do retry */
2953 #define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
2954 #define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
2955 #define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
2958 * Adapter temporary configuration structure
2960 * This structure can be discarded after initialization. Don't add
2961 * fields here needed after initialization.
2963 * Field naming convention:
2965 * *_enable indicates the field enables or disables a feature. The
2966 * value of the field is never reset.
2968 typedef struct adv_dvc_cfg {
2969 ushort disc_enable; /* enable disconnection */
2970 uchar chip_version; /* chip version */
2971 uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
2972 ushort lib_version; /* Adv Library version number */
2973 ushort control_flag; /* Microcode Control Flag */
2974 ushort mcode_date; /* Microcode date */
2975 ushort mcode_version; /* Microcode version */
2976 ushort pci_slot_info; /* high byte device/function number */
2977 /* bits 7-3 device num., bits 2-0 function num. */
2978 /* low byte bus num. */
2979 ushort serial1; /* EEPROM serial number word 1 */
2980 ushort serial2; /* EEPROM serial number word 2 */
2981 ushort serial3; /* EEPROM serial number word 3 */
2982 struct device *dev; /* pointer to the pci dev structure for this board */
2986 struct adv_scsi_req_q;
2988 typedef void (* ADV_ISR_CALLBACK)
2989 (struct adv_dvc_var *, struct adv_scsi_req_q *);
2991 typedef void (* ADV_ASYNC_CALLBACK)
2992 (struct adv_dvc_var *, uchar);
2995 * Adapter operation variable structure.
2997 * One structure is required per host adapter.
2999 * Field naming convention:
3001 * *_able indicates both whether a feature should be enabled or disabled
3002 * and whether a device isi capable of the feature. At initialization
3003 * this field may be set, but later if a device is found to be incapable
3004 * of the feature, the field is cleared.
3006 typedef struct adv_dvc_var {
3007 AdvPortAddr iop_base; /* I/O port address */
3008 ushort err_code; /* fatal error code */
3009 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
3010 ADV_ISR_CALLBACK isr_callback;
3011 ADV_ASYNC_CALLBACK async_callback;
3012 ushort wdtr_able; /* try WDTR for a device */
3013 ushort sdtr_able; /* try SDTR for a device */
3014 ushort ultra_able; /* try SDTR Ultra speed for a device */
3015 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
3016 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
3017 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
3018 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
3019 ushort tagqng_able; /* try tagged queuing with a device */
3020 ushort ppr_able; /* PPR message capable per TID bitmask. */
3021 uchar max_dvc_qng; /* maximum number of tagged commands per device */
3022 ushort start_motor; /* start motor command allowed */
3023 uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */
3024 uchar chip_no; /* should be assigned by caller */
3025 uchar max_host_qng; /* maximum number of Q'ed command allowed */
3026 uchar irq_no; /* IRQ number */
3027 ushort no_scam; /* scam_tolerant of EEPROM */
3028 struct asc_board *drv_ptr; /* driver pointer to private structure */
3029 uchar chip_scsi_id; /* chip SCSI target ID */
3031 uchar bist_err_code;
3032 ADV_CARR_T *carrier_buf;
3033 ADV_CARR_T *carr_freelist; /* Carrier free list. */
3034 ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */
3035 ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */
3036 ushort carr_pending_cnt; /* Count of pending carriers. */
3038 * Note: The following fields will not be used after initialization. The
3039 * driver may discard the buffer after initialization is done.
3041 ADV_DVC_CFG *cfg; /* temporary configuration structure */
3044 #define NO_OF_SG_PER_BLOCK 15
3046 typedef struct asc_sg_block {
3050 uchar sg_cnt; /* Valid entries in block. */
3051 ADV_PADDR sg_ptr; /* Pointer to next sg block. */
3053 ADV_PADDR sg_addr; /* SG element address. */
3054 ADV_DCNT sg_count; /* SG element count. */
3055 } sg_list[NO_OF_SG_PER_BLOCK];
3059 * ADV_SCSI_REQ_Q - microcode request structure
3061 * All fields in this structure up to byte 60 are used by the microcode.
3062 * The microcode makes assumptions about the size and ordering of fields
3063 * in this structure. Do not change the structure definition here without
3064 * coordinating the change with the microcode.
3066 * All fields accessed by microcode must be maintained in little_endian
3069 typedef struct adv_scsi_req_q {
3070 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
3072 uchar target_id; /* Device target identifier. */
3073 uchar target_lun; /* Device target logical unit number. */
3074 ADV_PADDR data_addr; /* Data buffer physical address. */
3075 ADV_DCNT data_cnt; /* Data count. Ucode sets to residual. */
3076 ADV_PADDR sense_addr;
3080 uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
3082 uchar done_status; /* Completion status. */
3083 uchar scsi_status; /* SCSI status byte. */
3084 uchar host_status; /* Ucode host status. */
3085 uchar sg_working_ix;
3086 uchar cdb[12]; /* SCSI CDB bytes 0-11. */
3087 ADV_PADDR sg_real_addr; /* SG list physical address. */
3088 ADV_PADDR scsiq_rptr;
3089 uchar cdb16[4]; /* SCSI CDB bytes 12-15. */
3090 ADV_VADDR scsiq_ptr;
3093 * End of microcode structure - 60 bytes. The rest of the structure
3094 * is used by the Adv Library and ignored by the microcode.
3097 ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
3098 char *vdata_addr; /* Data buffer virtual address. */
3100 uchar pad[2]; /* Pad out to a word boundary. */
3104 * Microcode idle loop commands
3106 #define IDLE_CMD_COMPLETED 0
3107 #define IDLE_CMD_STOP_CHIP 0x0001
3108 #define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
3109 #define IDLE_CMD_SEND_INT 0x0004
3110 #define IDLE_CMD_ABORT 0x0008
3111 #define IDLE_CMD_DEVICE_RESET 0x0010
3112 #define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
3113 #define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
3114 #define IDLE_CMD_SCSIREQ 0x0080
3116 #define IDLE_CMD_STATUS_SUCCESS 0x0001
3117 #define IDLE_CMD_STATUS_FAILURE 0x0002
3120 * AdvSendIdleCmd() flag definitions.
3122 #define ADV_NOWAIT 0x01
3125 * Wait loop time out values.
3127 #define SCSI_WAIT_10_SEC 10UL /* 10 seconds */
3128 #define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
3129 #define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
3130 #define SCSI_MS_PER_SEC 1000UL /* milliseconds per second */
3131 #define SCSI_MAX_RETRY 10 /* retry count */
3133 #define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
3134 #define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
3135 #define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
3136 #define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
3139 #define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
3142 * Device drivers must define the following functions.
3144 STATIC inline ulong DvcEnterCritical(void);
3145 STATIC inline void DvcLeaveCritical(ulong);
3146 STATIC void DvcSleepMilliSecond(ADV_DCNT);
3147 STATIC uchar DvcAdvReadPCIConfigByte(ADV_DVC_VAR *, ushort);
3148 STATIC void DvcAdvWritePCIConfigByte(ADV_DVC_VAR *, ushort, uchar);
3149 STATIC ADV_PADDR DvcGetPhyAddr(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *,
3150 uchar *, ASC_SDCNT *, int);
3151 STATIC void DvcDelayMicroSecond(ADV_DVC_VAR *, ushort);
3154 * Adv Library functions available to drivers.
3156 STATIC int AdvExeScsiQueue(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *);
3157 STATIC int AdvISR(ADV_DVC_VAR *);
3158 STATIC int AdvInitGetConfig(ADV_DVC_VAR *);
3159 STATIC int AdvInitAsc3550Driver(ADV_DVC_VAR *);
3160 STATIC int AdvInitAsc38C0800Driver(ADV_DVC_VAR *);
3161 STATIC int AdvInitAsc38C1600Driver(ADV_DVC_VAR *);
3162 STATIC int AdvResetChipAndSB(ADV_DVC_VAR *);
3163 STATIC int AdvResetSB(ADV_DVC_VAR *asc_dvc);
3166 * Internal Adv Library functions.
3168 STATIC int AdvSendIdleCmd(ADV_DVC_VAR *, ushort, ADV_DCNT);
3169 STATIC void AdvInquiryHandling(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *);
3170 STATIC int AdvInitFrom3550EEP(ADV_DVC_VAR *);
3171 STATIC int AdvInitFrom38C0800EEP(ADV_DVC_VAR *);
3172 STATIC int AdvInitFrom38C1600EEP(ADV_DVC_VAR *);
3173 STATIC ushort AdvGet3550EEPConfig(AdvPortAddr, ADVEEP_3550_CONFIG *);
3174 STATIC void AdvSet3550EEPConfig(AdvPortAddr, ADVEEP_3550_CONFIG *);
3175 STATIC ushort AdvGet38C0800EEPConfig(AdvPortAddr, ADVEEP_38C0800_CONFIG *);
3176 STATIC void AdvSet38C0800EEPConfig(AdvPortAddr, ADVEEP_38C0800_CONFIG *);
3177 STATIC ushort AdvGet38C1600EEPConfig(AdvPortAddr, ADVEEP_38C1600_CONFIG *);
3178 STATIC void AdvSet38C1600EEPConfig(AdvPortAddr, ADVEEP_38C1600_CONFIG *);
3179 STATIC void AdvWaitEEPCmd(AdvPortAddr);
3180 STATIC ushort AdvReadEEPWord(AdvPortAddr, int);
3183 * PCI Bus Definitions
3185 #define AscPCICmdRegBits_BusMastering 0x0007
3186 #define AscPCICmdRegBits_ParErrRespCtrl 0x0040
3188 /* Read byte from a register. */
3189 #define AdvReadByteRegister(iop_base, reg_off) \
3190 (ADV_MEM_READB((iop_base) + (reg_off)))
3192 /* Write byte to a register. */
3193 #define AdvWriteByteRegister(iop_base, reg_off, byte) \
3194 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
3196 /* Read word (2 bytes) from a register. */
3197 #define AdvReadWordRegister(iop_base, reg_off) \
3198 (ADV_MEM_READW((iop_base) + (reg_off)))
3200 /* Write word (2 bytes) to a register. */
3201 #define AdvWriteWordRegister(iop_base, reg_off, word) \
3202 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
3204 /* Write dword (4 bytes) to a register. */
3205 #define AdvWriteDWordRegister(iop_base, reg_off, dword) \
3206 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
3208 /* Read byte from LRAM. */
3209 #define AdvReadByteLram(iop_base, addr, byte) \
3211 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
3212 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
3215 /* Write byte to LRAM. */
3216 #define AdvWriteByteLram(iop_base, addr, byte) \
3217 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
3218 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
3220 /* Read word (2 bytes) from LRAM. */
3221 #define AdvReadWordLram(iop_base, addr, word) \
3223 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
3224 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
3227 /* Write word (2 bytes) to LRAM. */
3228 #define AdvWriteWordLram(iop_base, addr, word) \
3229 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
3230 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
3232 /* Write little-endian double word (4 bytes) to LRAM */
3233 /* Because of unspecified C language ordering don't use auto-increment. */
3234 #define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
3235 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
3236 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
3237 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
3238 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
3239 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
3240 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
3242 /* Read word (2 bytes) from LRAM assuming that the address is already set. */
3243 #define AdvReadWordAutoIncLram(iop_base) \
3244 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
3246 /* Write word (2 bytes) to LRAM assuming that the address is already set. */
3247 #define AdvWriteWordAutoIncLram(iop_base, word) \
3248 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
3252 * Define macro to check for Condor signature.
3254 * Evaluate to ADV_TRUE if a Condor chip is found the specified port
3255 * address 'iop_base'. Otherwise evalue to ADV_FALSE.
3257 #define AdvFindSignature(iop_base) \
3258 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
3259 ADV_CHIP_ID_BYTE) && \
3260 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
3261 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
3264 * Define macro to Return the version number of the chip at 'iop_base'.
3266 * The second parameter 'bus_type' is currently unused.
3268 #define AdvGetChipVersion(iop_base, bus_type) \
3269 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
3272 * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must
3273 * match the ASC_SCSI_REQ_Q 'srb_ptr' field.
3275 * If the request has not yet been sent to the device it will simply be
3276 * aborted from RISC memory. If the request is disconnected it will be
3277 * aborted on reselection by sending an Abort Message to the target ID.
3280 * ADV_TRUE(1) - Queue was successfully aborted.
3281 * ADV_FALSE(0) - Queue was not found on the active queue list.
3283 #define AdvAbortQueue(asc_dvc, scsiq) \
3284 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
3288 * Send a Bus Device Reset Message to the specified target ID.
3290 * All outstanding commands will be purged if sending the
3291 * Bus Device Reset Message is successful.
3294 * ADV_TRUE(1) - All requests on the target are purged.
3295 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
3298 #define AdvResetDevice(asc_dvc, target_id) \
3299 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
3300 (ADV_DCNT) (target_id))
3303 * SCSI Wide Type definition.
3305 #define ADV_SCSI_BIT_ID_TYPE ushort
3308 * AdvInitScsiTarget() 'cntl_flag' options.
3310 #define ADV_SCAN_LUN 0x01
3311 #define ADV_CAPINFO_NOLUN 0x02
3314 * Convert target id to target id bit mask.
3316 #define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
3319 * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values.
3322 #define QD_NO_STATUS 0x00 /* Request not completed yet. */
3323 #define QD_NO_ERROR 0x01
3324 #define QD_ABORTED_BY_HOST 0x02
3325 #define QD_WITH_ERROR 0x04
3327 #define QHSTA_NO_ERROR 0x00
3328 #define QHSTA_M_SEL_TIMEOUT 0x11
3329 #define QHSTA_M_DATA_OVER_RUN 0x12
3330 #define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
3331 #define QHSTA_M_QUEUE_ABORTED 0x15
3332 #define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
3333 #define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
3334 #define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
3335 #define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
3336 #define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
3337 #define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
3338 #define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
3339 /* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
3340 #define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
3341 #define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
3342 #define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
3343 #define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
3344 #define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
3345 #define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
3346 #define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
3347 #define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
3348 #define QHSTA_M_WTM_TIMEOUT 0x41
3349 #define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
3350 #define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
3351 #define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
3352 #define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
3353 #define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
3354 #define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
3358 * Default EEPROM Configuration structure defined in a_init.c.
3360 static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config;
3361 static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config;
3362 static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config;
3365 * DvcGetPhyAddr() flag arguments
3367 #define ADV_IS_SCSIQ_FLAG 0x01 /* 'addr' is ASC_SCSI_REQ_Q pointer */
3368 #define ADV_ASCGETSGLIST_VADDR 0x02 /* 'addr' is AscGetSGList() virtual addr */
3369 #define ADV_IS_SENSE_FLAG 0x04 /* 'addr' is sense virtual pointer */
3370 #define ADV_IS_DATA_FLAG 0x08 /* 'addr' is data virtual pointer */
3371 #define ADV_IS_SGLIST_FLAG 0x10 /* 'addr' is sglist virtual pointer */
3372 #define ADV_IS_CARRIER_FLAG 0x20 /* 'addr' is ADV_CARR_T pointer */
3374 /* Return the address that is aligned at the next doubleword >= to 'addr'. */
3375 #define ADV_8BALIGN(addr) (((ulong) (addr) + 0x7) & ~0x7)
3376 #define ADV_16BALIGN(addr) (((ulong) (addr) + 0xF) & ~0xF)
3377 #define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F)
3380 * Total contiguous memory needed for driver SG blocks.
3382 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
3383 * number of scatter-gather elements the driver supports in a
3387 #define ADV_SG_LIST_MAX_BYTE_SIZE \
3388 (sizeof(ADV_SG_BLOCK) * \
3389 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
3392 * Inquiry data structure and bitfield macros
3394 * Using bitfields to access the subchar data isn't portable across
3395 * endianness, so instead mask and shift. Only quantities of more
3396 * than 1 bit are shifted, since the others are just tested for true
3400 #define ADV_INQ_DVC_TYPE(inq) ((inq)->periph & 0x1f)
3401 #define ADV_INQ_QUALIFIER(inq) (((inq)->periph & 0xe0) >> 5)
3402 #define ADV_INQ_DVC_TYPE_MOD(inq) ((inq)->devtype & 0x7f)
3403 #define ADV_INQ_REMOVABLE(inq) ((inq)->devtype & 0x80)
3404 #define ADV_INQ_ANSI_VER(inq) ((inq)->ver & 0x07)
3405 #define ADV_INQ_ECMA_VER(inq) (((inq)->ver & 0x38) >> 3)
3406 #define ADV_INQ_ISO_VER(inq) (((inq)->ver & 0xc0) >> 6)
3407 #define ADV_INQ_RESPONSE_FMT(inq) ((inq)->byte3 & 0x0f)
3408 #define ADV_INQ_TERM_IO(inq) ((inq)->byte3 & 0x40)
3409 #define ADV_INQ_ASYNC_NOTIF(inq) ((inq)->byte3 & 0x80)
3410 #define ADV_INQ_SOFT_RESET(inq) ((inq)->flags & 0x01)
3411 #define ADV_INQ_CMD_QUEUE(inq) ((inq)->flags & 0x02)
3412 #define ADV_INQ_LINK_CMD(inq) ((inq)->flags & 0x08)
3413 #define ADV_INQ_SYNC(inq) ((inq)->flags & 0x10)
3414 #define ADV_INQ_WIDE16(inq) ((inq)->flags & 0x20)
3415 #define ADV_INQ_WIDE32(inq) ((inq)->flags & 0x40)
3416 #define ADV_INQ_REL_ADDR(inq) ((inq)->flags & 0x80)
3417 #define ADV_INQ_INFO_UNIT(inq) ((inq)->info & 0x01)
3418 #define ADV_INQ_QUICK_ARB(inq) ((inq)->info & 0x02)
3419 #define ADV_INQ_CLOCKING(inq) (((inq)->info & 0x0c) >> 2)
3422 uchar periph; /* peripheral device type [0:4] */
3423 /* peripheral qualifier [5:7] */
3424 uchar devtype; /* device type modifier (for SCSI I) [0:6] */
3425 /* RMB - removable medium bit [7] */
3426 uchar ver; /* ANSI approved version [0:2] */
3427 /* ECMA version [3:5] */
3428 /* ISO version [6:7] */
3429 uchar byte3; /* response data format [0:3] */
3434 /* reserved [4:5] */
3435 /* terminate I/O process bit (see 5.6.22) [6] */
3436 /* asynch. event notification (processor) [7] */
3437 uchar add_len; /* additional length */
3438 uchar res1; /* reserved */
3439 uchar res2; /* reserved */
3440 uchar flags; /* soft reset implemented [0] */
3441 /* command queuing [1] */
3443 /* linked command for this logical unit [3] */
3444 /* synchronous data transfer [4] */
3445 /* wide bus 16 bit data transfer [5] */
3446 /* wide bus 32 bit data transfer [6] */
3447 /* relative addressing mode [7] */
3448 uchar vendor_id[8]; /* vendor identification */
3449 uchar product_id[16]; /* product identification */
3450 uchar product_rev_level[4]; /* product revision level */
3451 uchar vendor_specific[20]; /* vendor specific */
3452 uchar info; /* information unit supported [0] */
3453 /* quick arbitrate supported [1] */
3454 /* clocking field [2:3] */
3455 /* reserved [4:7] */
3456 uchar res3; /* reserved */
3457 } ADV_SCSI_INQUIRY; /* 58 bytes */
3461 * --- Driver Constants and Macros
3464 #define ASC_NUM_BOARD_SUPPORTED 16
3465 #define ASC_NUM_IOPORT_PROBE 4
3466 #define ASC_NUM_BUS 4
3468 /* Reference Scsi_Host hostdata */
3469 #define ASC_BOARDP(host) ((asc_board_t *) &((host)->hostdata))
3471 /* asc_board_t flags */
3472 #define ASC_HOST_IN_RESET 0x01
3473 #define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */
3474 #define ASC_SELECT_QUEUE_DEPTHS 0x08
3476 #define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
3477 #define ASC_WIDE_BOARD(boardp) ((boardp)->flags & ASC_IS_WIDE_BOARD)
3479 #define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */
3481 #define ASC_INFO_SIZE 128 /* advansys_info() line size */
3483 #ifdef CONFIG_PROC_FS
3484 /* /proc/scsi/advansys/[0...] related definitions */
3485 #define ASC_PRTBUF_SIZE 2048
3486 #define ASC_PRTLINE_SIZE 160
3488 #define ASC_PRT_NEXT() \
3492 if (leftlen == 0) { \
3497 #endif /* CONFIG_PROC_FS */
3499 /* Asc Library return codes */
3502 #define ASC_NOERROR 1
3504 #define ASC_ERROR (-1)
3506 /* struct scsi_cmnd function return codes */
3507 #define STATUS_BYTE(byte) (byte)
3508 #define MSG_BYTE(byte) ((byte) << 8)
3509 #define HOST_BYTE(byte) ((byte) << 16)
3510 #define DRIVER_BYTE(byte) ((byte) << 24)
3513 * The following definitions and macros are OS independent interfaces to
3514 * the queue functions:
3515 * REQ - SCSI request structure
3516 * REQP - pointer to SCSI request structure
3517 * REQPTID(reqp) - reqp's target id
3518 * REQPNEXT(reqp) - reqp's next pointer
3519 * REQPNEXTP(reqp) - pointer to reqp's next pointer
3520 * REQPTIME(reqp) - reqp's time stamp value
3521 * REQTIMESTAMP() - system time stamp value
3523 typedef struct scsi_cmnd REQ, *REQP;
3524 #define REQPNEXT(reqp) ((REQP) ((reqp)->host_scribble))
3525 #define REQPNEXTP(reqp) ((REQP *) &((reqp)->host_scribble))
3526 #define REQPTID(reqp) ((reqp)->device->id)
3527 #define REQPTIME(reqp) ((reqp)->SCp.this_residual)
3528 #define REQTIMESTAMP() (jiffies)
3530 #define REQTIMESTAT(function, ascq, reqp, tid) \
3533 * If the request time stamp is less than the system time stamp, then \
3534 * maybe the system time stamp wrapped. Set the request time to zero.\
3536 if (REQPTIME(reqp) <= REQTIMESTAMP()) { \
3537 REQPTIME(reqp) = REQTIMESTAMP() - REQPTIME(reqp); \
3539 /* Indicate an error occurred with the assertion. */ \
3540 ASC_ASSERT(REQPTIME(reqp) <= REQTIMESTAMP()); \
3541 REQPTIME(reqp) = 0; \
3543 /* Handle first minimum time case without external initialization. */ \
3544 if (((ascq)->q_tot_cnt[tid] == 1) || \
3545 (REQPTIME(reqp) < (ascq)->q_min_tim[tid])) { \
3546 (ascq)->q_min_tim[tid] = REQPTIME(reqp); \
3547 ASC_DBG3(1, "%s: new q_min_tim[%d] %u\n", \
3548 (function), (tid), (ascq)->q_min_tim[tid]); \
3550 if (REQPTIME(reqp) > (ascq)->q_max_tim[tid]) { \
3551 (ascq)->q_max_tim[tid] = REQPTIME(reqp); \
3552 ASC_DBG3(1, "%s: new q_max_tim[%d] %u\n", \
3553 (function), tid, (ascq)->q_max_tim[tid]); \
3555 (ascq)->q_tot_tim[tid] += REQPTIME(reqp); \
3556 /* Reset the time stamp field. */ \
3557 REQPTIME(reqp) = 0; \
3560 /* asc_enqueue() flags */
3564 /* asc_dequeue_list() argument */
3565 #define ASC_TID_ALL (-1)
3567 /* Return non-zero, if the queue is empty. */
3568 #define ASC_QUEUE_EMPTY(ascq) ((ascq)->q_tidmask == 0)
3570 #define PCI_MAX_SLOT 0x1F
3571 #define PCI_MAX_BUS 0xFF
3572 #define PCI_IOADDRESS_MASK 0xFFFE
3573 #define ASC_PCI_VENDORID 0x10CD
3574 #define ASC_PCI_DEVICE_ID_CNT 6 /* PCI Device ID count. */
3575 #define ASC_PCI_DEVICE_ID_1100 0x1100
3576 #define ASC_PCI_DEVICE_ID_1200 0x1200
3577 #define ASC_PCI_DEVICE_ID_1300 0x1300
3578 #define ASC_PCI_DEVICE_ID_2300 0x2300 /* ASC-3550 */
3579 #define ASC_PCI_DEVICE_ID_2500 0x2500 /* ASC-38C0800 */
3580 #define ASC_PCI_DEVICE_ID_2700 0x2700 /* ASC-38C1600 */
3582 #ifndef ADVANSYS_STATS
3583 #define ASC_STATS(shp, counter)
3584 #define ASC_STATS_ADD(shp, counter, count)
3585 #else /* ADVANSYS_STATS */
3586 #define ASC_STATS(shp, counter) \
3587 (ASC_BOARDP(shp)->asc_stats.counter++)
3589 #define ASC_STATS_ADD(shp, counter, count) \
3590 (ASC_BOARDP(shp)->asc_stats.counter += (count))
3591 #endif /* ADVANSYS_STATS */
3593 #define ASC_CEILING(val, unit) (((val) + ((unit) - 1))/(unit))
3595 /* If the result wraps when calculating tenths, return 0. */
3596 #define ASC_TENTHS(num, den) \
3597 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
3598 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
3601 * Display a message to the console.
3603 #define ASC_PRINT(s) \
3605 printk("advansys: "); \
3609 #define ASC_PRINT1(s, a1) \
3611 printk("advansys: "); \
3612 printk((s), (a1)); \
3615 #define ASC_PRINT2(s, a1, a2) \
3617 printk("advansys: "); \
3618 printk((s), (a1), (a2)); \
3621 #define ASC_PRINT3(s, a1, a2, a3) \
3623 printk("advansys: "); \
3624 printk((s), (a1), (a2), (a3)); \
3627 #define ASC_PRINT4(s, a1, a2, a3, a4) \
3629 printk("advansys: "); \
3630 printk((s), (a1), (a2), (a3), (a4)); \
3634 #ifndef ADVANSYS_DEBUG
3636 #define ASC_DBG(lvl, s)
3637 #define ASC_DBG1(lvl, s, a1)
3638 #define ASC_DBG2(lvl, s, a1, a2)
3639 #define ASC_DBG3(lvl, s, a1, a2, a3)
3640 #define ASC_DBG4(lvl, s, a1, a2, a3, a4)
3641 #define ASC_DBG_PRT_SCSI_HOST(lvl, s)
3642 #define ASC_DBG_PRT_SCSI_CMND(lvl, s)
3643 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
3644 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
3645 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
3646 #define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
3647 #define ASC_DBG_PRT_HEX(lvl, name, start, length)
3648 #define ASC_DBG_PRT_CDB(lvl, cdb, len)
3649 #define ASC_DBG_PRT_SENSE(lvl, sense, len)
3650 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
3652 #else /* ADVANSYS_DEBUG */
3655 * Debugging Message Levels:
3657 * 1: High-Level Tracing
3658 * 2-N: Verbose Tracing
3661 #define ASC_DBG(lvl, s) \
3663 if (asc_dbglvl >= (lvl)) { \
3668 #define ASC_DBG1(lvl, s, a1) \
3670 if (asc_dbglvl >= (lvl)) { \
3671 printk((s), (a1)); \
3675 #define ASC_DBG2(lvl, s, a1, a2) \
3677 if (asc_dbglvl >= (lvl)) { \
3678 printk((s), (a1), (a2)); \
3682 #define ASC_DBG3(lvl, s, a1, a2, a3) \
3684 if (asc_dbglvl >= (lvl)) { \
3685 printk((s), (a1), (a2), (a3)); \
3689 #define ASC_DBG4(lvl, s, a1, a2, a3, a4) \
3691 if (asc_dbglvl >= (lvl)) { \
3692 printk((s), (a1), (a2), (a3), (a4)); \
3696 #define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
3698 if (asc_dbglvl >= (lvl)) { \
3699 asc_prt_scsi_host(s); \
3703 #define ASC_DBG_PRT_SCSI_CMND(lvl, s) \
3705 if (asc_dbglvl >= (lvl)) { \
3706 asc_prt_scsi_cmnd(s); \
3710 #define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
3712 if (asc_dbglvl >= (lvl)) { \
3713 asc_prt_asc_scsi_q(scsiqp); \
3717 #define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
3719 if (asc_dbglvl >= (lvl)) { \
3720 asc_prt_asc_qdone_info(qdone); \
3724 #define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
3726 if (asc_dbglvl >= (lvl)) { \
3727 asc_prt_adv_scsi_req_q(scsiqp); \
3731 #define ASC_DBG_PRT_HEX(lvl, name, start, length) \
3733 if (asc_dbglvl >= (lvl)) { \
3734 asc_prt_hex((name), (start), (length)); \
3738 #define ASC_DBG_PRT_CDB(lvl, cdb, len) \
3739 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
3741 #define ASC_DBG_PRT_SENSE(lvl, sense, len) \
3742 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
3744 #define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
3745 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
3746 #endif /* ADVANSYS_DEBUG */
3748 #ifndef ADVANSYS_ASSERT
3749 #define ASC_ASSERT(a)
3750 #else /* ADVANSYS_ASSERT */
3752 #define ASC_ASSERT(a) \
3755 printk("ASC_ASSERT() Failure: file %s, line %d\n", \
3756 __FILE__, __LINE__); \
3760 #endif /* ADVANSYS_ASSERT */
3764 * --- Driver Structures
3767 #ifdef ADVANSYS_STATS
3769 /* Per board statistics structure */
3771 /* Driver Entrypoint Statistics */
3772 ADV_DCNT queuecommand; /* # calls to advansys_queuecommand() */
3773 ADV_DCNT reset; /* # calls to advansys_eh_bus_reset() */
3774 ADV_DCNT biosparam; /* # calls to advansys_biosparam() */
3775 ADV_DCNT interrupt; /* # advansys_interrupt() calls */
3776 ADV_DCNT callback; /* # calls to asc/adv_isr_callback() */
3777 ADV_DCNT done; /* # calls to request's scsi_done function */
3778 ADV_DCNT build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
3779 ADV_DCNT adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
3780 ADV_DCNT adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
3781 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
3782 ADV_DCNT exe_noerror; /* # ASC_NOERROR returns. */
3783 ADV_DCNT exe_busy; /* # ASC_BUSY returns. */
3784 ADV_DCNT exe_error; /* # ASC_ERROR returns. */
3785 ADV_DCNT exe_unknown; /* # unknown returns. */
3786 /* Data Transfer Statistics */
3787 ADV_DCNT cont_cnt; /* # non-scatter-gather I/O requests received */
3788 ADV_DCNT cont_xfer; /* # contiguous transfer 512-bytes */
3789 ADV_DCNT sg_cnt; /* # scatter-gather I/O requests received */
3790 ADV_DCNT sg_elem; /* # scatter-gather elements */
3791 ADV_DCNT sg_xfer; /* # scatter-gather transfer 512-bytes */
3793 #endif /* ADVANSYS_STATS */
3796 * Request queuing structure
3798 typedef struct asc_queue {
3799 ADV_SCSI_BIT_ID_TYPE q_tidmask; /* queue mask */
3800 REQP q_first[ADV_MAX_TID+1]; /* first queued request */
3801 REQP q_last[ADV_MAX_TID+1]; /* last queued request */
3802 #ifdef ADVANSYS_STATS
3803 short q_cur_cnt[ADV_MAX_TID+1]; /* current queue count */
3804 short q_max_cnt[ADV_MAX_TID+1]; /* maximum queue count */
3805 ADV_DCNT q_tot_cnt[ADV_MAX_TID+1]; /* total enqueue count */
3806 ADV_DCNT q_tot_tim[ADV_MAX_TID+1]; /* total time queued */
3807 ushort q_max_tim[ADV_MAX_TID+1]; /* maximum time queued */
3808 ushort q_min_tim[ADV_MAX_TID+1]; /* minimum time queued */
3809 #endif /* ADVANSYS_STATS */
3813 * Adv Library Request Structures
3815 * The following two structures are used to process Wide Board requests.
3817 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
3818 * and microcode with the ADV_SCSI_REQ_Q field 'srb_ptr' pointing to the
3819 * adv_req_t. The adv_req_t structure 'cmndp' field in turn points to the
3820 * Mid-Level SCSI request structure.
3822 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
3823 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
3824 * up to 255 scatter-gather elements may be used per request or
3827 * Both structures must be 32 byte aligned.
3829 typedef struct adv_sgblk {
3830 ADV_SG_BLOCK sg_block; /* Sgblock structure. */
3831 uchar align[32]; /* Sgblock structure padding. */
3832 struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */
3835 typedef struct adv_req {
3836 ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */
3837 uchar align[32]; /* Request structure padding. */
3838 struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */
3839 adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */
3840 struct adv_req *next_reqp; /* Next Request Structure. */
3844 * Structure allocated for each board.
3846 * This structure is allocated by scsi_register() at the end
3847 * of the 'Scsi_Host' structure starting at the 'hostdata'
3848 * field. It is guaranteed to be allocated from DMA-able memory.
3850 typedef struct asc_board {
3851 int id; /* Board Id */
3852 uint flags; /* Board flags */
3854 ASC_DVC_VAR asc_dvc_var; /* Narrow board */
3855 ADV_DVC_VAR adv_dvc_var; /* Wide board */
3858 ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */
3859 ADV_DVC_CFG adv_dvc_cfg; /* Wide board */
3861 ushort asc_n_io_port; /* Number I/O ports. */
3862 asc_queue_t active; /* Active command queue */
3863 asc_queue_t waiting; /* Waiting command queue */
3864 asc_queue_t done; /* Done command queue */
3865 ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */
3866 struct scsi_device *device[ADV_MAX_TID+1]; /* Mid-Level Scsi Device */
3867 ushort reqcnt[ADV_MAX_TID+1]; /* Starvation request count */
3868 ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */
3869 ushort queue_full_cnt[ADV_MAX_TID+1]; /* Queue full count */
3871 ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */
3872 ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */
3873 ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */
3874 ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */
3876 ulong last_reset; /* Saved last reset time */
3877 spinlock_t lock; /* Board spinlock */
3878 #ifdef CONFIG_PROC_FS
3879 /* /proc/scsi/advansys/[0...] */
3880 char *prtbuf; /* /proc print buffer */
3881 #endif /* CONFIG_PROC_FS */
3882 #ifdef ADVANSYS_STATS
3883 struct asc_stats asc_stats; /* Board statistics */
3884 #endif /* ADVANSYS_STATS */
3886 * The following fields are used only for Narrow Boards.
3888 /* The following three structures must be in DMA-able memory. */
3889 ASC_SCSI_REQ_Q scsireqq;
3890 ASC_CAP_INFO cap_info;
3891 ASC_SCSI_INQUIRY inquiry;
3892 uchar sdtr_data[ASC_MAX_TID+1]; /* SDTR information */
3894 * The following fields are used only for Wide Boards.
3896 void *ioremap_addr; /* I/O Memory remap address. */
3897 ushort ioport; /* I/O Port address. */
3898 ADV_CARR_T *orig_carrp; /* ADV_CARR_T memory block. */
3899 adv_req_t *orig_reqp; /* adv_req_t memory block. */
3900 adv_req_t *adv_reqp; /* Request structures. */
3901 adv_sgblk_t *adv_sgblkp; /* Scatter-gather structures. */
3902 ushort bios_signature; /* BIOS Signature. */
3903 ushort bios_version; /* BIOS Version. */
3904 ushort bios_codeseg; /* BIOS Code Segment. */
3905 ushort bios_codelen; /* BIOS Code Segment Length. */
3909 * PCI configuration structures
3911 typedef struct _PCI_DATA_
3920 typedef struct _PCI_DEVICE_
3935 typedef struct _PCI_CONFIG_SPACE_
3947 ADV_PADDR baseAddress[6];
3949 ADV_PADDR optionRomAddr;
3950 ushort reserved2[4];
3962 /* Note: All driver global data should be initialized. */
3964 /* Number of boards detected in system. */
3965 STATIC int asc_board_count = 0;
3966 STATIC struct Scsi_Host *asc_host[ASC_NUM_BOARD_SUPPORTED] = { 0 };
3968 /* Overrun buffer used by all narrow boards. */
3969 STATIC uchar overrun_buf[ASC_OVERRUN_BSIZE] = { 0 };
3972 * Global structures required to issue a command.
3974 STATIC ASC_SCSI_Q asc_scsi_q = { { 0 } };
3975 STATIC ASC_SG_HEAD asc_sg_head = { 0 };
3977 /* List of supported bus types. */
3978 STATIC ushort asc_bus[ASC_NUM_BUS] __initdata = {
3986 * Used with the LILO 'advansys' option to eliminate or
3987 * limit I/O port probing at boot time, cf. advansys_setup().
3989 STATIC int asc_iopflag = ASC_FALSE;
3990 STATIC int asc_ioport[ASC_NUM_IOPORT_PROBE] = { 0, 0, 0, 0 };
3992 #ifdef ADVANSYS_DEBUG
3994 asc_bus_name[ASC_NUM_BUS] = {
4001 STATIC int asc_dbglvl = 3;
4002 #endif /* ADVANSYS_DEBUG */
4004 /* Declaration for Asc Library internal data referenced by driver. */
4005 STATIC PortAddr _asc_def_iop_base[];
4009 * --- Driver Function Prototypes
4011 * advansys.h contains function prototypes for functions global to Linux.
4014 STATIC irqreturn_t advansys_interrupt(int, void *, struct pt_regs *);
4015 STATIC int advansys_slave_configure(struct scsi_device *);
4016 STATIC void asc_scsi_done_list(struct scsi_cmnd *);
4017 STATIC int asc_execute_scsi_cmnd(struct scsi_cmnd *);
4018 STATIC int asc_build_req(asc_board_t *, struct scsi_cmnd *);
4019 STATIC int adv_build_req(asc_board_t *, struct scsi_cmnd *, ADV_SCSI_REQ_Q **);
4020 STATIC int adv_get_sglist(asc_board_t *, adv_req_t *, struct scsi_cmnd *, int);
4021 STATIC void asc_isr_callback(ASC_DVC_VAR *, ASC_QDONE_INFO *);
4022 STATIC void adv_isr_callback(ADV_DVC_VAR *, ADV_SCSI_REQ_Q *);
4023 STATIC void adv_async_callback(ADV_DVC_VAR *, uchar);
4024 STATIC void asc_enqueue(asc_queue_t *, REQP, int);
4025 STATIC REQP asc_dequeue(asc_queue_t *, int);
4026 STATIC REQP asc_dequeue_list(asc_queue_t *, REQP *, int);
4027 STATIC int asc_rmqueue(asc_queue_t *, REQP);
4028 STATIC void asc_execute_queue(asc_queue_t *);
4029 #ifdef CONFIG_PROC_FS
4030 STATIC int asc_proc_copy(off_t, off_t, char *, int , char *, int);
4031 STATIC int asc_prt_board_devices(struct Scsi_Host *, char *, int);
4032 STATIC int asc_prt_adv_bios(struct Scsi_Host *, char *, int);
4033 STATIC int asc_get_eeprom_string(ushort *serialnum, uchar *cp);
4034 STATIC int asc_prt_asc_board_eeprom(struct Scsi_Host *, char *, int);
4035 STATIC int asc_prt_adv_board_eeprom(struct Scsi_Host *, char *, int);
4036 STATIC int asc_prt_driver_conf(struct Scsi_Host *, char *, int);
4037 STATIC int asc_prt_asc_board_info(struct Scsi_Host *, char *, int);
4038 STATIC int asc_prt_adv_board_info(struct Scsi_Host *, char *, int);
4039 STATIC int asc_prt_line(char *, int, char *fmt, ...);
4040 #endif /* CONFIG_PROC_FS */
4042 /* Declaration for Asc Library internal functions referenced by driver. */
4043 STATIC int AscFindSignature(PortAddr);
4044 STATIC ushort AscGetEEPConfig(PortAddr, ASCEEP_CONFIG *, ushort);
4046 /* Statistics function prototypes. */
4047 #ifdef ADVANSYS_STATS
4048 #ifdef CONFIG_PROC_FS
4049 STATIC int asc_prt_board_stats(struct Scsi_Host *, char *, int);
4050 STATIC int asc_prt_target_stats(struct Scsi_Host *, int, char *, int);
4051 #endif /* CONFIG_PROC_FS */
4052 #endif /* ADVANSYS_STATS */
4054 /* Debug function prototypes. */
4055 #ifdef ADVANSYS_DEBUG
4056 STATIC void asc_prt_scsi_host(struct Scsi_Host *);
4057 STATIC void asc_prt_scsi_cmnd(struct scsi_cmnd *);
4058 STATIC void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *);
4059 STATIC void asc_prt_asc_dvc_var(ASC_DVC_VAR *);
4060 STATIC void asc_prt_asc_scsi_q(ASC_SCSI_Q *);
4061 STATIC void asc_prt_asc_qdone_info(ASC_QDONE_INFO *);
4062 STATIC void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *);
4063 STATIC void asc_prt_adv_dvc_var(ADV_DVC_VAR *);
4064 STATIC void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *);
4065 STATIC void asc_prt_adv_sgblock(int, ADV_SG_BLOCK *);
4066 STATIC void asc_prt_hex(char *f, uchar *, int);
4067 #endif /* ADVANSYS_DEBUG */
4071 * --- Linux 'Scsi_Host_Template' and advansys_setup() Functions
4074 #ifdef CONFIG_PROC_FS
4076 * advansys_proc_info() - /proc/scsi/advansys/[0-(ASC_NUM_BOARD_SUPPORTED-1)]
4078 * *buffer: I/O buffer
4079 * **start: if inout == FALSE pointer into buffer where user read should start
4080 * offset: current offset into a /proc/scsi/advansys/[0...] file
4081 * length: length of buffer
4082 * hostno: Scsi_Host host_no
4083 * inout: TRUE - user is writing; FALSE - user is reading
4085 * Return the number of bytes read from or written to a
4086 * /proc/scsi/advansys/[0...] file.
4088 * Note: This function uses the per board buffer 'prtbuf' which is
4089 * allocated when the board is initialized in advansys_detect(). The
4090 * buffer is ASC_PRTBUF_SIZE bytes. The function asc_proc_copy() is
4091 * used to write to the buffer. The way asc_proc_copy() is written
4092 * if 'prtbuf' is too small it will not be overwritten. Instead the
4093 * user just won't get all the available statistics.
4096 advansys_proc_info(struct Scsi_Host *shost, char *buffer, char **start,
4097 off_t offset, int length, int inout)
4099 struct Scsi_Host *shp;
4100 asc_board_t *boardp;
4109 #ifdef ADVANSYS_STATS
4111 #endif /* ADVANSYS_STATS */
4113 ASC_DBG(1, "advansys_proc_info: begin\n");
4116 * User write not supported.
4118 if (inout == TRUE) {
4123 * User read of /proc/scsi/advansys/[0...] file.
4126 /* Find the specified board. */
4127 for (i = 0; i < asc_board_count; i++) {
4128 if (asc_host[i]->host_no == shost->host_no) {
4132 if (i == asc_board_count) {
4137 boardp = ASC_BOARDP(shp);
4139 /* Copy read data starting at the beginning of the buffer. */
4147 * Get board configuration information.
4149 * advansys_info() returns the board string from its own static buffer.
4151 cp = (char *) advansys_info(shp);
4154 /* Copy board information. */
4155 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4159 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4166 * Display Wide Board BIOS Information.
4168 if (ASC_WIDE_BOARD(boardp)) {
4169 cp = boardp->prtbuf;
4170 cplen = asc_prt_adv_bios(shp, cp, ASC_PRTBUF_SIZE);
4171 ASC_ASSERT(cplen < ASC_PRTBUF_SIZE);
4172 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4176 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4184 * Display driver information for each device attached to the board.
4186 cp = boardp->prtbuf;
4187 cplen = asc_prt_board_devices(shp, cp, ASC_PRTBUF_SIZE);
4188 ASC_ASSERT(cplen < ASC_PRTBUF_SIZE);
4189 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4193 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4200 * Display EEPROM configuration for the board.
4202 cp = boardp->prtbuf;
4203 if (ASC_NARROW_BOARD(boardp)) {
4204 cplen = asc_prt_asc_board_eeprom(shp, cp, ASC_PRTBUF_SIZE);
4206 cplen = asc_prt_adv_board_eeprom(shp, cp, ASC_PRTBUF_SIZE);
4208 ASC_ASSERT(cplen < ASC_PRTBUF_SIZE);
4209 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4213 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4220 * Display driver configuration and information for the board.
4222 cp = boardp->prtbuf;
4223 cplen = asc_prt_driver_conf(shp, cp, ASC_PRTBUF_SIZE);
4224 ASC_ASSERT(cplen < ASC_PRTBUF_SIZE);
4225 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4229 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4235 #ifdef ADVANSYS_STATS
4237 * Display driver statistics for the board.
4239 cp = boardp->prtbuf;
4240 cplen = asc_prt_board_stats(shp, cp, ASC_PRTBUF_SIZE);
4241 ASC_ASSERT(cplen <= ASC_PRTBUF_SIZE);
4242 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4246 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4253 * Display driver statistics for each target.
4255 for (tgt_id = 0; tgt_id <= ADV_MAX_TID; tgt_id++) {
4256 cp = boardp->prtbuf;
4257 cplen = asc_prt_target_stats(shp, tgt_id, cp, ASC_PRTBUF_SIZE);
4258 ASC_ASSERT(cplen <= ASC_PRTBUF_SIZE);
4259 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4263 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4269 #endif /* ADVANSYS_STATS */
4272 * Display Asc Library dynamic configuration information
4275 cp = boardp->prtbuf;
4276 if (ASC_NARROW_BOARD(boardp)) {
4277 cplen = asc_prt_asc_board_info(shp, cp, ASC_PRTBUF_SIZE);
4279 cplen = asc_prt_adv_board_info(shp, cp, ASC_PRTBUF_SIZE);
4281 ASC_ASSERT(cplen < ASC_PRTBUF_SIZE);
4282 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen);
4286 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4292 ASC_DBG1(1, "advansys_proc_info: totcnt %d\n", totcnt);
4296 #endif /* CONFIG_PROC_FS */
4301 * Detect function for AdvanSys adapters.
4303 * Argument is a pointer to the host driver's scsi_hosts entry.
4305 * Return number of adapters found.
4307 * Note: Because this function is called during system initialization
4308 * it must not call SCSI mid-level functions including scsi_malloc()
4312 advansys_detect(struct scsi_host_template *tpnt)
4314 static int detect_called = ASC_FALSE;
4317 struct Scsi_Host *shp = NULL;
4318 asc_board_t *boardp = NULL;
4319 ASC_DVC_VAR *asc_dvc_varp = NULL;
4320 ADV_DVC_VAR *adv_dvc_varp = NULL;
4321 adv_sgblk_t *sgp = NULL;
4323 int share_irq = FALSE;
4325 struct device *dev = NULL;
4327 int pci_init_search = 0;
4328 struct pci_dev *pci_devicep[ASC_NUM_BOARD_SUPPORTED];
4329 int pci_card_cnt_max = 0;
4330 int pci_card_cnt = 0;
4331 struct pci_dev *pci_devp = NULL;
4332 int pci_device_id_cnt = 0;
4333 unsigned int pci_device_id[ASC_PCI_DEVICE_ID_CNT] = {
4334 ASC_PCI_DEVICE_ID_1100,
4335 ASC_PCI_DEVICE_ID_1200,
4336 ASC_PCI_DEVICE_ID_1300,
4337 ASC_PCI_DEVICE_ID_2300,
4338 ASC_PCI_DEVICE_ID_2500,
4339 ASC_PCI_DEVICE_ID_2700
4341 ADV_PADDR pci_memory_address;
4342 #endif /* CONFIG_PCI */
4343 int warn_code, err_code;
4346 if (detect_called == ASC_FALSE) {
4347 detect_called = ASC_TRUE;
4349 printk("AdvanSys SCSI: advansys_detect() multiple calls ignored\n");
4353 ASC_DBG(1, "advansys_detect: begin\n");
4355 asc_board_count = 0;
4358 * If I/O port probing has been modified, then verify and
4359 * clean-up the 'asc_ioport' list.
4361 if (asc_iopflag == ASC_TRUE) {
4362 for (ioport = 0; ioport < ASC_NUM_IOPORT_PROBE; ioport++) {
4363 ASC_DBG2(1, "advansys_detect: asc_ioport[%d] 0x%x\n",
4364 ioport, asc_ioport[ioport]);
4365 if (asc_ioport[ioport] != 0) {
4366 for (iop = 0; iop < ASC_IOADR_TABLE_MAX_IX; iop++) {
4367 if (_asc_def_iop_base[iop] == asc_ioport[ioport]) {
4371 if (iop == ASC_IOADR_TABLE_MAX_IX) {
4373 "AdvanSys SCSI: specified I/O Port 0x%X is invalid\n",
4374 asc_ioport[ioport]);
4375 asc_ioport[ioport] = 0;
4382 for (bus = 0; bus < ASC_NUM_BUS; bus++) {
4384 ASC_DBG2(1, "advansys_detect: bus search type %d (%s)\n",
4385 bus, asc_bus_name[bus]);
4388 while (asc_board_count < ASC_NUM_BOARD_SUPPORTED) {
4390 ASC_DBG1(2, "advansys_detect: asc_board_count %d\n",
4393 switch (asc_bus[bus]) {
4397 if (asc_iopflag == ASC_FALSE) {
4398 iop = AscSearchIOPortAddr(iop, asc_bus[bus]);
4401 * ISA and VL I/O port scanning has either been
4402 * eliminated or limited to selected ports on
4403 * the LILO command line, /etc/lilo.conf, or
4404 * by setting variables when the module was loaded.
4406 ASC_DBG(1, "advansys_detect: I/O port scanning modified\n");
4409 for (; ioport < ASC_NUM_IOPORT_PROBE; ioport++) {
4410 if ((iop = asc_ioport[ioport]) != 0) {
4416 "advansys_detect: probing I/O port 0x%x...\n",
4418 if (check_region(iop, ASC_IOADR_GAP) != 0) {
4420 "AdvanSys SCSI: specified I/O Port 0x%X is busy\n", iop);
4421 /* Don't try this I/O port twice. */
4422 asc_ioport[ioport] = 0;
4423 goto ioport_try_again;
4424 } else if (AscFindSignature(iop) == ASC_FALSE) {
4426 "AdvanSys SCSI: specified I/O Port 0x%X has no adapter\n", iop);
4427 /* Don't try this I/O port twice. */
4428 asc_ioport[ioport] = 0;
4429 goto ioport_try_again;
4432 * If this isn't an ISA board, then it must be
4433 * a VL board. If currently looking an ISA
4434 * board is being looked for then try for
4435 * another ISA board in 'asc_ioport'.
4437 if (asc_bus[bus] == ASC_IS_ISA &&
4438 (AscGetChipVersion(iop, ASC_IS_ISA) &
4439 ASC_CHIP_VER_ISA_BIT) == 0) {
4441 * Don't clear 'asc_ioport[ioport]'. Try
4442 * this board again for VL. Increment
4443 * 'ioport' past this board.
4446 goto ioport_try_again;
4450 * This board appears good, don't try the I/O port
4451 * again by clearing its value. Increment 'ioport'
4452 * for the next iteration.
4454 asc_ioport[ioport++] = 0;
4457 #endif /* CONFIG_ISA */
4462 iop = AscSearchIOPortAddr(iop, asc_bus[bus]);
4463 #endif /* CONFIG_ISA */
4468 if (pci_init_search == 0) {
4471 pci_init_search = 1;
4473 /* Find all PCI cards. */
4474 while (pci_device_id_cnt < ASC_PCI_DEVICE_ID_CNT) {
4475 if ((pci_devp = pci_find_device(ASC_PCI_VENDORID,
4476 pci_device_id[pci_device_id_cnt], pci_devp)) ==
4478 pci_device_id_cnt++;
4480 if (pci_enable_device(pci_devp) == 0) {
4481 pci_devicep[pci_card_cnt_max++] = pci_devp;
4487 * Sort PCI cards in ascending order by PCI Bus, Slot,
4488 * and Device Number.
4490 for (i = 0; i < pci_card_cnt_max - 1; i++)
4492 for (j = i + 1; j < pci_card_cnt_max; j++) {
4493 if ((pci_devicep[j]->bus->number <
4494 pci_devicep[i]->bus->number) ||
4495 ((pci_devicep[j]->bus->number ==
4496 pci_devicep[i]->bus->number) &&
4497 (pci_devicep[j]->devfn <
4498 pci_devicep[i]->devfn))) {
4499 pci_devp = pci_devicep[i];
4500 pci_devicep[i] = pci_devicep[j];
4501 pci_devicep[j] = pci_devp;
4511 if (pci_card_cnt == pci_card_cnt_max) {
4514 pci_devp = pci_devicep[pci_card_cnt];
4517 "advansys_detect: devfn %d, bus number %d\n",
4518 pci_devp->devfn, pci_devp->bus->number);
4519 iop = pci_resource_start(pci_devp, 0);
4521 "advansys_detect: vendorID %X, deviceID %X\n",
4522 pci_devp->vendor, pci_devp->device);
4523 ASC_DBG2(2, "advansys_detect: iop %X, irqLine %d\n",
4524 iop, pci_devp->irq);
4527 dev = &pci_devp->dev;
4529 #endif /* CONFIG_PCI */
4533 ASC_PRINT1("advansys_detect: unknown bus type: %d\n",
4537 ASC_DBG1(1, "advansys_detect: iop 0x%x\n", iop);
4540 * Adapter not found, try next bus type.
4549 * Register the adapter, get its configuration, and
4552 ASC_DBG(2, "advansys_detect: scsi_register()\n");
4553 shp = scsi_register(tpnt, sizeof(asc_board_t));
4559 scsi_set_device(shp, dev);
4561 /* Save a pointer to the Scsi_Host of each board found. */
4562 asc_host[asc_board_count++] = shp;
4564 /* Initialize private per board data */
4565 boardp = ASC_BOARDP(shp);
4566 memset(boardp, 0, sizeof(asc_board_t));
4567 boardp->id = asc_board_count - 1;
4569 /* Initialize spinlock. */
4570 spin_lock_init(&boardp->lock);
4573 * Handle both narrow and wide boards.
4575 * If a Wide board was detected, set the board structure
4576 * wide board flag. Set-up the board structure based on
4580 if (asc_bus[bus] == ASC_IS_PCI &&
4581 (pci_devp->device == ASC_PCI_DEVICE_ID_2300 ||
4582 pci_devp->device == ASC_PCI_DEVICE_ID_2500 ||
4583 pci_devp->device == ASC_PCI_DEVICE_ID_2700))
4585 boardp->flags |= ASC_IS_WIDE_BOARD;
4587 #endif /* CONFIG_PCI */
4589 if (ASC_NARROW_BOARD(boardp)) {
4590 ASC_DBG(1, "advansys_detect: narrow board\n");
4591 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
4592 asc_dvc_varp->bus_type = asc_bus[bus];
4593 asc_dvc_varp->drv_ptr = boardp;
4594 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
4595 asc_dvc_varp->cfg->overrun_buf = &overrun_buf[0];
4596 asc_dvc_varp->iop_base = iop;
4597 asc_dvc_varp->isr_callback = asc_isr_callback;
4599 ASC_DBG(1, "advansys_detect: wide board\n");
4600 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
4601 adv_dvc_varp->drv_ptr = boardp;
4602 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
4603 adv_dvc_varp->isr_callback = adv_isr_callback;
4604 adv_dvc_varp->async_callback = adv_async_callback;
4606 if (pci_devp->device == ASC_PCI_DEVICE_ID_2300)
4608 ASC_DBG(1, "advansys_detect: ASC-3550\n");
4609 adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
4610 } else if (pci_devp->device == ASC_PCI_DEVICE_ID_2500)
4612 ASC_DBG(1, "advansys_detect: ASC-38C0800\n");
4613 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
4616 ASC_DBG(1, "advansys_detect: ASC-38C1600\n");
4617 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
4619 #endif /* CONFIG_PCI */
4622 * Map the board's registers into virtual memory for
4623 * PCI slave access. Only memory accesses are used to
4624 * access the board's registers.
4626 * Note: The PCI register base address is not always
4627 * page aligned, but the address passed to ioremap()
4628 * must be page aligned. It is guaranteed that the
4629 * PCI register base address will not cross a page
4632 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
4634 iolen = ADV_3550_IOLEN;
4635 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
4637 iolen = ADV_38C0800_IOLEN;
4640 iolen = ADV_38C1600_IOLEN;
4643 pci_memory_address = pci_resource_start(pci_devp, 1);
4644 ASC_DBG1(1, "advansys_detect: pci_memory_address: 0x%lx\n",
4645 (ulong) pci_memory_address);
4646 if ((boardp->ioremap_addr =
4647 ioremap(pci_memory_address & PAGE_MASK,
4650 "advansys_detect: board %d: ioremap(%x, %d) returned NULL\n",
4651 boardp->id, pci_memory_address, iolen);
4652 scsi_unregister(shp);
4656 ASC_DBG1(1, "advansys_detect: ioremap_addr: 0x%lx\n",
4657 (ulong) boardp->ioremap_addr);
4658 adv_dvc_varp->iop_base = (AdvPortAddr)
4659 (boardp->ioremap_addr +
4660 (pci_memory_address - (pci_memory_address & PAGE_MASK)));
4661 ASC_DBG1(1, "advansys_detect: iop_base: 0x%lx\n",
4662 adv_dvc_varp->iop_base);
4663 #endif /* CONFIG_PCI */
4666 * Even though it isn't used to access wide boards, other
4667 * than for the debug line below, save I/O Port address so
4668 * that it can be reported.
4670 boardp->ioport = iop;
4673 "advansys_detect: iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n",
4674 (ushort) inp(iop + 1), (ushort) inpw(iop));
4677 #ifdef CONFIG_PROC_FS
4679 * Allocate buffer for printing information from
4680 * /proc/scsi/advansys/[0...].
4682 if ((boardp->prtbuf =
4683 kmalloc(ASC_PRTBUF_SIZE, GFP_ATOMIC)) == NULL) {
4685 "advansys_detect: board %d: kmalloc(%d, %d) returned NULL\n",
4686 boardp->id, ASC_PRTBUF_SIZE, GFP_ATOMIC);
4687 scsi_unregister(shp);
4691 #endif /* CONFIG_PROC_FS */
4693 if (ASC_NARROW_BOARD(boardp)) {
4694 asc_dvc_varp->cfg->dev = dev;
4696 * Set the board bus type and PCI IRQ before
4697 * calling AscInitGetConfig().
4699 switch (asc_dvc_varp->bus_type) {
4702 shp->unchecked_isa_dma = TRUE;
4706 shp->unchecked_isa_dma = FALSE;
4710 shp->unchecked_isa_dma = FALSE;
4713 #endif /* CONFIG_ISA */
4716 shp->irq = asc_dvc_varp->irq_no = pci_devp->irq;
4717 asc_dvc_varp->cfg->pci_slot_info =
4718 ASC_PCI_MKID(pci_devp->bus->number,
4719 PCI_SLOT(pci_devp->devfn),
4720 PCI_FUNC(pci_devp->devfn));
4721 shp->unchecked_isa_dma = FALSE;
4724 #endif /* CONFIG_PCI */
4727 "advansys_detect: board %d: unknown adapter type: %d\n",
4728 boardp->id, asc_dvc_varp->bus_type);
4729 shp->unchecked_isa_dma = TRUE;
4734 adv_dvc_varp->cfg->dev = dev;
4736 * For Wide boards set PCI information before calling
4737 * AdvInitGetConfig().
4740 shp->irq = adv_dvc_varp->irq_no = pci_devp->irq;
4741 adv_dvc_varp->cfg->pci_slot_info =
4742 ASC_PCI_MKID(pci_devp->bus->number,
4743 PCI_SLOT(pci_devp->devfn),
4744 PCI_FUNC(pci_devp->devfn));
4745 shp->unchecked_isa_dma = FALSE;
4747 #endif /* CONFIG_PCI */
4751 * Read the board configuration.
4753 if (ASC_NARROW_BOARD(boardp)) {
4755 * NOTE: AscInitGetConfig() may change the board's
4756 * bus_type value. The asc_bus[bus] value should no
4757 * longer be used. If the bus_type field must be
4758 * referenced only use the bit-wise AND operator "&".
4760 ASC_DBG(2, "advansys_detect: AscInitGetConfig()\n");
4761 switch(ret = AscInitGetConfig(asc_dvc_varp)) {
4762 case 0: /* No error */
4764 case ASC_WARN_IO_PORT_ROTATE:
4766 "AscInitGetConfig: board %d: I/O port address modified\n",
4769 case ASC_WARN_AUTO_CONFIG:
4771 "AscInitGetConfig: board %d: I/O port increment switch enabled\n",
4774 case ASC_WARN_EEPROM_CHKSUM:
4776 "AscInitGetConfig: board %d: EEPROM checksum error\n",
4779 case ASC_WARN_IRQ_MODIFIED:
4781 "AscInitGetConfig: board %d: IRQ modified\n",
4784 case ASC_WARN_CMD_QNG_CONFLICT:
4786 "AscInitGetConfig: board %d: tag queuing enabled w/o disconnects\n",
4791 "AscInitGetConfig: board %d: unknown warning: 0x%x\n",
4795 if ((err_code = asc_dvc_varp->err_code) != 0) {
4797 "AscInitGetConfig: board %d error: init_state 0x%x, err_code 0x%x\n",
4798 boardp->id, asc_dvc_varp->init_state,
4799 asc_dvc_varp->err_code);
4802 ASC_DBG(2, "advansys_detect: AdvInitGetConfig()\n");
4803 if ((ret = AdvInitGetConfig(adv_dvc_varp)) != 0) {
4804 ASC_PRINT2("AdvInitGetConfig: board %d: warning: 0x%x\n",
4807 if ((err_code = adv_dvc_varp->err_code) != 0) {
4809 "AdvInitGetConfig: board %d error: err_code 0x%x\n",
4810 boardp->id, adv_dvc_varp->err_code);
4814 if (err_code != 0) {
4815 #ifdef CONFIG_PROC_FS
4816 kfree(boardp->prtbuf);
4817 #endif /* CONFIG_PROC_FS */
4818 scsi_unregister(shp);
4824 * Save the EEPROM configuration so that it can be displayed
4825 * from /proc/scsi/advansys/[0...].
4827 if (ASC_NARROW_BOARD(boardp)) {
4832 * Set the adapter's target id bit in the 'init_tidmask' field.
4834 boardp->init_tidmask |=
4835 ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
4838 * Save EEPROM settings for the board.
4840 ep = &boardp->eep_config.asc_eep;
4842 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
4843 ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
4844 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
4845 ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
4846 ep->start_motor = asc_dvc_varp->start_motor;
4847 ep->cntl = asc_dvc_varp->dvc_cntl;
4848 ep->no_scam = asc_dvc_varp->no_scam;
4849 ep->max_total_qng = asc_dvc_varp->max_total_qng;
4850 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
4851 /* 'max_tag_qng' is set to the same value for every device. */
4852 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
4853 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
4854 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
4855 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
4856 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
4857 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
4858 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
4861 * Modify board configuration.
4863 ASC_DBG(2, "advansys_detect: AscInitSetConfig()\n");
4864 switch (ret = AscInitSetConfig(asc_dvc_varp)) {
4865 case 0: /* No error. */
4867 case ASC_WARN_IO_PORT_ROTATE:
4869 "AscInitSetConfig: board %d: I/O port address modified\n",
4872 case ASC_WARN_AUTO_CONFIG:
4874 "AscInitSetConfig: board %d: I/O port increment switch enabled\n",
4877 case ASC_WARN_EEPROM_CHKSUM:
4879 "AscInitSetConfig: board %d: EEPROM checksum error\n",
4882 case ASC_WARN_IRQ_MODIFIED:
4884 "AscInitSetConfig: board %d: IRQ modified\n",
4887 case ASC_WARN_CMD_QNG_CONFLICT:
4889 "AscInitSetConfig: board %d: tag queuing w/o disconnects\n",
4894 "AscInitSetConfig: board %d: unknown warning: 0x%x\n",
4898 if (asc_dvc_varp->err_code != 0) {
4900 "AscInitSetConfig: board %d error: init_state 0x%x, err_code 0x%x\n",
4901 boardp->id, asc_dvc_varp->init_state,
4902 asc_dvc_varp->err_code);
4903 #ifdef CONFIG_PROC_FS
4904 kfree(boardp->prtbuf);
4905 #endif /* CONFIG_PROC_FS */
4906 scsi_unregister(shp);
4912 * Finish initializing the 'Scsi_Host' structure.
4914 /* AscInitSetConfig() will set the IRQ for non-PCI boards. */
4915 if ((asc_dvc_varp->bus_type & ASC_IS_PCI) == 0) {
4916 shp->irq = asc_dvc_varp->irq_no;
4919 ADVEEP_3550_CONFIG *ep_3550;
4920 ADVEEP_38C0800_CONFIG *ep_38C0800;
4921 ADVEEP_38C1600_CONFIG *ep_38C1600;
4924 * Save Wide EEP Configuration Information.
4926 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
4928 ep_3550 = &boardp->eep_config.adv_3550_eep;
4930 ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
4931 ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
4932 ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
4933 ep_3550->termination = adv_dvc_varp->cfg->termination;
4934 ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
4935 ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
4936 ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
4937 ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
4938 ep_3550->ultra_able = adv_dvc_varp->ultra_able;
4939 ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
4940 ep_3550->start_motor = adv_dvc_varp->start_motor;
4941 ep_3550->scsi_reset_delay = adv_dvc_varp->scsi_reset_wait;
4942 ep_3550->serial_number_word1 =
4943 adv_dvc_varp->cfg->serial1;
4944 ep_3550->serial_number_word2 =
4945 adv_dvc_varp->cfg->serial2;
4946 ep_3550->serial_number_word3 =
4947 adv_dvc_varp->cfg->serial3;
4948 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
4950 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
4952 ep_38C0800->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
4953 ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
4954 ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
4955 ep_38C0800->termination_lvd =
4956 adv_dvc_varp->cfg->termination;
4957 ep_38C0800->disc_enable = adv_dvc_varp->cfg->disc_enable;
4958 ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
4959 ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
4960 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
4961 ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
4962 ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
4963 ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
4964 ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
4965 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
4966 ep_38C0800->start_motor = adv_dvc_varp->start_motor;
4967 ep_38C0800->scsi_reset_delay =
4968 adv_dvc_varp->scsi_reset_wait;
4969 ep_38C0800->serial_number_word1 =
4970 adv_dvc_varp->cfg->serial1;
4971 ep_38C0800->serial_number_word2 =
4972 adv_dvc_varp->cfg->serial2;
4973 ep_38C0800->serial_number_word3 =
4974 adv_dvc_varp->cfg->serial3;
4977 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
4979 ep_38C1600->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
4980 ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
4981 ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
4982 ep_38C1600->termination_lvd =
4983 adv_dvc_varp->cfg->termination;
4984 ep_38C1600->disc_enable = adv_dvc_varp->cfg->disc_enable;
4985 ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
4986 ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
4987 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
4988 ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
4989 ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
4990 ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
4991 ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
4992 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
4993 ep_38C1600->start_motor = adv_dvc_varp->start_motor;
4994 ep_38C1600->scsi_reset_delay =
4995 adv_dvc_varp->scsi_reset_wait;
4996 ep_38C1600->serial_number_word1 =
4997 adv_dvc_varp->cfg->serial1;
4998 ep_38C1600->serial_number_word2 =
4999 adv_dvc_varp->cfg->serial2;
5000 ep_38C1600->serial_number_word3 =
5001 adv_dvc_varp->cfg->serial3;
5005 * Set the adapter's target id bit in the 'init_tidmask' field.
5007 boardp->init_tidmask |=
5008 ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
5011 * Finish initializing the 'Scsi_Host' structure.
5013 shp->irq = adv_dvc_varp->irq_no;
5017 * Channels are numbered beginning with 0. For AdvanSys one host
5018 * structure supports one channel. Multi-channel boards have a
5019 * separate host structure for each channel.
5021 shp->max_channel = 0;
5022 if (ASC_NARROW_BOARD(boardp)) {
5023 shp->max_id = ASC_MAX_TID + 1;
5024 shp->max_lun = ASC_MAX_LUN + 1;
5026 shp->io_port = asc_dvc_varp->iop_base;
5027 boardp->asc_n_io_port = ASC_IOADR_GAP;
5028 shp->this_id = asc_dvc_varp->cfg->chip_scsi_id;
5030 /* Set maximum number of queues the adapter can handle. */
5031 shp->can_queue = asc_dvc_varp->max_total_qng;
5033 shp->max_id = ADV_MAX_TID + 1;
5034 shp->max_lun = ADV_MAX_LUN + 1;
5037 * Save the I/O Port address and length even though
5038 * I/O ports are not used to access Wide boards.
5039 * Instead the Wide boards are accessed with
5040 * PCI Memory Mapped I/O.
5043 boardp->asc_n_io_port = iolen;
5045 shp->this_id = adv_dvc_varp->chip_scsi_id;
5047 /* Set maximum number of queues the adapter can handle. */
5048 shp->can_queue = adv_dvc_varp->max_host_qng;
5052 * 'n_io_port' currently is one byte.
5054 * Set a value to 'n_io_port', but never referenced it because
5055 * it may be truncated.
5057 shp->n_io_port = boardp->asc_n_io_port <= 255 ?
5058 boardp->asc_n_io_port : 255;
5061 * Following v1.3.89, 'cmd_per_lun' is no longer needed
5062 * and should be set to zero.
5064 * But because of a bug introduced in v1.3.89 if the driver is
5065 * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level
5066 * SCSI function 'allocate_device' will panic. To allow the driver
5067 * to work as a module in these kernels set 'cmd_per_lun' to 1.
5069 * Note: This is wrong. cmd_per_lun should be set to the depth
5070 * you want on untagged devices always.
5073 shp->cmd_per_lun = 1;
5075 shp->cmd_per_lun = 0;
5079 * Set the maximum number of scatter-gather elements the
5080 * adapter can handle.
5082 if (ASC_NARROW_BOARD(boardp)) {
5084 * Allow two commands with 'sg_tablesize' scatter-gather
5085 * elements to be executed simultaneously. This value is
5086 * the theoretical hardware limit. It may be decreased
5090 (((asc_dvc_varp->max_total_qng - 2) / 2) *
5091 ASC_SG_LIST_PER_Q) + 1;
5093 shp->sg_tablesize = ADV_MAX_SG_LIST;
5097 * The value of 'sg_tablesize' can not exceed the SCSI
5098 * mid-level driver definition of SG_ALL. SG_ALL also
5099 * must not be exceeded, because it is used to define the
5100 * size of the scatter-gather table in 'struct asc_sg_head'.
5102 if (shp->sg_tablesize > SG_ALL) {
5103 shp->sg_tablesize = SG_ALL;
5106 ASC_DBG1(1, "advansys_detect: sg_tablesize: %d\n",
5109 /* BIOS start address. */
5110 if (ASC_NARROW_BOARD(boardp)) {
5112 ((ulong) AscGetChipBiosAddress(
5113 asc_dvc_varp->iop_base,
5114 asc_dvc_varp->bus_type));
5117 * Fill-in BIOS board variables. The Wide BIOS saves
5118 * information in LRAM that is used by the driver.
5120 AdvReadWordLram(adv_dvc_varp->iop_base, BIOS_SIGNATURE,
5121 boardp->bios_signature);
5122 AdvReadWordLram(adv_dvc_varp->iop_base, BIOS_VERSION,
5123 boardp->bios_version);
5124 AdvReadWordLram(adv_dvc_varp->iop_base, BIOS_CODESEG,
5125 boardp->bios_codeseg);
5126 AdvReadWordLram(adv_dvc_varp->iop_base, BIOS_CODELEN,
5127 boardp->bios_codelen);
5130 "advansys_detect: bios_signature 0x%x, bios_version 0x%x\n",
5131 boardp->bios_signature, boardp->bios_version);
5134 "advansys_detect: bios_codeseg 0x%x, bios_codelen 0x%x\n",
5135 boardp->bios_codeseg, boardp->bios_codelen);
5138 * If the BIOS saved a valid signature, then fill in
5139 * the BIOS code segment base address.
5141 if (boardp->bios_signature == 0x55AA) {
5143 * Convert x86 realmode code segment to a linear
5144 * address by shifting left 4.
5146 shp->base = ((ulong) boardp->bios_codeseg << 4);
5153 * Register Board Resources - I/O Port, DMA, IRQ
5157 * Register I/O port range.
5159 * For Wide boards the I/O ports are not used to access
5160 * the board, but request the region anyway.
5162 * 'shp->n_io_port' is not referenced, because it may be truncated.
5165 "advansys_detect: request_region port 0x%lx, len 0x%x\n",
5166 (ulong) shp->io_port, boardp->asc_n_io_port);
5167 if (request_region(shp->io_port, boardp->asc_n_io_port,
5168 "advansys") == NULL) {
5170 "advansys_detect: board %d: request_region() failed, port 0x%lx, len 0x%x\n",
5171 boardp->id, (ulong) shp->io_port, boardp->asc_n_io_port);
5172 #ifdef CONFIG_PROC_FS
5173 kfree(boardp->prtbuf);
5174 #endif /* CONFIG_PROC_FS */
5175 scsi_unregister(shp);
5180 /* Register DMA Channel for Narrow boards. */
5181 shp->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */
5183 if (ASC_NARROW_BOARD(boardp)) {
5184 /* Register DMA channel for ISA bus. */
5185 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
5186 shp->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
5188 request_dma(shp->dma_channel, "advansys")) != 0) {
5190 "advansys_detect: board %d: request_dma() %d failed %d\n",
5191 boardp->id, shp->dma_channel, ret);
5192 release_region(shp->io_port, boardp->asc_n_io_port);
5193 #ifdef CONFIG_PROC_FS
5194 kfree(boardp->prtbuf);
5195 #endif /* CONFIG_PROC_FS */
5196 scsi_unregister(shp);
5200 AscEnableIsaDma(shp->dma_channel);
5203 #endif /* CONFIG_ISA */
5205 /* Register IRQ Number. */
5206 ASC_DBG1(2, "advansys_detect: request_irq() %d\n", shp->irq);
5208 * If request_irq() fails with the SA_INTERRUPT flag set,
5209 * then try again without the SA_INTERRUPT flag set. This
5210 * allows IRQ sharing to work even with other drivers that
5211 * do not set the SA_INTERRUPT flag.
5213 * If SA_INTERRUPT is not set, then interrupts are enabled
5214 * before the driver interrupt function is called.
5216 if (((ret = request_irq(shp->irq, advansys_interrupt,
5217 SA_INTERRUPT | (share_irq == TRUE ? SA_SHIRQ : 0),
5218 "advansys", boardp)) != 0) &&
5219 ((ret = request_irq(shp->irq, advansys_interrupt,
5220 (share_irq == TRUE ? SA_SHIRQ : 0),
5221 "advansys", boardp)) != 0))
5223 if (ret == -EBUSY) {
5225 "advansys_detect: board %d: request_irq(): IRQ 0x%x already in use.\n",
5226 boardp->id, shp->irq);
5227 } else if (ret == -EINVAL) {
5229 "advansys_detect: board %d: request_irq(): IRQ 0x%x not valid.\n",
5230 boardp->id, shp->irq);
5233 "advansys_detect: board %d: request_irq(): IRQ 0x%x failed with %d\n",
5234 boardp->id, shp->irq, ret);
5236 release_region(shp->io_port, boardp->asc_n_io_port);
5237 iounmap(boardp->ioremap_addr);
5238 if (shp->dma_channel != NO_ISA_DMA) {
5239 free_dma(shp->dma_channel);
5241 #ifdef CONFIG_PROC_FS
5242 kfree(boardp->prtbuf);
5243 #endif /* CONFIG_PROC_FS */
5244 scsi_unregister(shp);
5250 * Initialize board RISC chip and enable interrupts.
5252 if (ASC_NARROW_BOARD(boardp)) {
5253 ASC_DBG(2, "advansys_detect: AscInitAsc1000Driver()\n");
5254 warn_code = AscInitAsc1000Driver(asc_dvc_varp);
5255 err_code = asc_dvc_varp->err_code;
5257 if (warn_code || err_code) {
5259 "advansys_detect: board %d error: init_state 0x%x, warn 0x%x, error 0x%x\n",
5260 boardp->id, asc_dvc_varp->init_state,
5261 warn_code, err_code);
5266 adv_req_t *reqp = NULL;
5270 * Allocate buffer carrier structures. The total size
5271 * is about 4 KB, so allocate all at once.
5274 (ADV_CARR_T *) kmalloc(ADV_CARRIER_BUFSIZE, GFP_ATOMIC);
5275 ASC_DBG1(1, "advansys_detect: carrp 0x%lx\n", (ulong) carrp);
5277 if (carrp == NULL) {
5282 * Allocate up to 'max_host_qng' request structures for
5283 * the Wide board. The total size is about 16 KB, so
5284 * allocate all at once. If the allocation fails decrement
5287 for (req_cnt = adv_dvc_varp->max_host_qng;
5288 req_cnt > 0; req_cnt--) {
5290 reqp = (adv_req_t *)
5291 kmalloc(sizeof(adv_req_t) * req_cnt, GFP_ATOMIC);
5294 "advansys_detect: reqp 0x%lx, req_cnt %d, bytes %lu\n",
5295 (ulong) reqp, req_cnt,
5296 (ulong) sizeof(adv_req_t) * req_cnt);
5308 * Allocate up to ADV_TOT_SG_BLOCK request structures for
5309 * the Wide board. Each structure is about 136 bytes.
5311 boardp->adv_sgblkp = NULL;
5312 for (sg_cnt = 0; sg_cnt < ADV_TOT_SG_BLOCK; sg_cnt++) {
5314 sgp = (adv_sgblk_t *)
5315 kmalloc(sizeof(adv_sgblk_t), GFP_ATOMIC);
5321 sgp->next_sgblkp = boardp->adv_sgblkp;
5322 boardp->adv_sgblkp = sgp;
5326 "advansys_detect: sg_cnt %d * %u = %u bytes\n",
5327 sg_cnt, sizeof(adv_sgblk_t),
5328 (unsigned) (sizeof(adv_sgblk_t) * sg_cnt));
5331 * If no request structures or scatter-gather structures could
5332 * be allocated, then return an error. Otherwise continue with
5339 "advansys_detect: board %d error: failed to kmalloc() carrier buffer.\n",
5341 err_code = ADV_ERROR;
5342 } else if (reqp == NULL) {
5345 "advansys_detect: board %d error: failed to kmalloc() adv_req_t buffer.\n",
5347 err_code = ADV_ERROR;
5348 } else if (boardp->adv_sgblkp == NULL) {
5352 "advansys_detect: board %d error: failed to kmalloc() adv_sgblk_t buffers.\n",
5354 err_code = ADV_ERROR;
5357 /* Save carrier buffer pointer. */
5358 boardp->orig_carrp = carrp;
5361 * Save original pointer for kfree() in case the
5362 * driver is built as a module and can be unloaded.
5364 boardp->orig_reqp = reqp;
5366 adv_dvc_varp->carrier_buf = carrp;
5369 * Point 'adv_reqp' to the request structures and
5370 * link them together.
5373 reqp[req_cnt].next_reqp = NULL;
5374 for (; req_cnt > 0; req_cnt--) {
5375 reqp[req_cnt - 1].next_reqp = &reqp[req_cnt];
5377 boardp->adv_reqp = &reqp[0];
5379 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
5382 "advansys_detect: AdvInitAsc3550Driver()\n");
5383 warn_code = AdvInitAsc3550Driver(adv_dvc_varp);
5384 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
5386 "advansys_detect: AdvInitAsc38C0800Driver()\n");
5387 warn_code = AdvInitAsc38C0800Driver(adv_dvc_varp);
5390 "advansys_detect: AdvInitAsc38C1600Driver()\n");
5391 warn_code = AdvInitAsc38C1600Driver(adv_dvc_varp);
5393 err_code = adv_dvc_varp->err_code;
5395 if (warn_code || err_code) {
5397 "advansys_detect: board %d error: warn 0x%x, error 0x%x\n",
5398 boardp->id, warn_code, err_code);
5403 if (err_code != 0) {
5404 release_region(shp->io_port, boardp->asc_n_io_port);
5405 if (ASC_WIDE_BOARD(boardp)) {
5406 iounmap(boardp->ioremap_addr);
5407 if (boardp->orig_carrp) {
5408 kfree(boardp->orig_carrp);
5409 boardp->orig_carrp = NULL;
5411 if (boardp->orig_reqp) {
5412 kfree(boardp->orig_reqp);
5413 boardp->orig_reqp = boardp->adv_reqp = NULL;
5415 while ((sgp = boardp->adv_sgblkp) != NULL)
5417 boardp->adv_sgblkp = sgp->next_sgblkp;
5421 if (shp->dma_channel != NO_ISA_DMA) {
5422 free_dma(shp->dma_channel);
5424 #ifdef CONFIG_PROC_FS
5425 kfree(boardp->prtbuf);
5426 #endif /* CONFIG_PROC_FS */
5427 free_irq(shp->irq, boardp);
5428 scsi_unregister(shp);
5432 ASC_DBG_PRT_SCSI_HOST(2, shp);
5436 ASC_DBG1(1, "advansys_detect: done: asc_board_count %d\n", asc_board_count);
5437 return asc_board_count;
5441 * advansys_release()
5443 * Release resources allocated for a single AdvanSys adapter.
5446 advansys_release(struct Scsi_Host *shp)
5448 asc_board_t *boardp;
5450 ASC_DBG(1, "advansys_release: begin\n");
5451 boardp = ASC_BOARDP(shp);
5452 free_irq(shp->irq, boardp);
5453 if (shp->dma_channel != NO_ISA_DMA) {
5454 ASC_DBG(1, "advansys_release: free_dma()\n");
5455 free_dma(shp->dma_channel);
5457 release_region(shp->io_port, boardp->asc_n_io_port);
5458 if (ASC_WIDE_BOARD(boardp)) {
5459 adv_sgblk_t *sgp = NULL;
5461 iounmap(boardp->ioremap_addr);
5462 if (boardp->orig_carrp) {
5463 kfree(boardp->orig_carrp);
5464 boardp->orig_carrp = NULL;
5466 if (boardp->orig_reqp) {
5467 kfree(boardp->orig_reqp);
5468 boardp->orig_reqp = boardp->adv_reqp = NULL;
5470 while ((sgp = boardp->adv_sgblkp) != NULL)
5472 boardp->adv_sgblkp = sgp->next_sgblkp;
5476 #ifdef CONFIG_PROC_FS
5477 ASC_ASSERT(boardp->prtbuf != NULL);
5478 kfree(boardp->prtbuf);
5479 #endif /* CONFIG_PROC_FS */
5480 scsi_unregister(shp);
5481 ASC_DBG(1, "advansys_release: end\n");
5488 * Return suitable for printing on the console with the argument
5489 * adapter's configuration information.
5491 * Note: The information line should not exceed ASC_INFO_SIZE bytes,
5492 * otherwise the static 'info' array will be overrun.
5495 advansys_info(struct Scsi_Host *shp)
5497 static char info[ASC_INFO_SIZE];
5498 asc_board_t *boardp;
5499 ASC_DVC_VAR *asc_dvc_varp;
5500 ADV_DVC_VAR *adv_dvc_varp;
5503 char *widename = NULL;
5505 boardp = ASC_BOARDP(shp);
5506 if (ASC_NARROW_BOARD(boardp)) {
5507 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
5508 ASC_DBG(1, "advansys_info: begin\n");
5509 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
5510 if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) == ASC_IS_ISAPNP) {
5511 busname = "ISA PnP";
5515 /* Don't reference 'shp->n_io_port'; It may be truncated. */
5517 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
5518 ASC_VERSION, busname,
5519 (ulong) shp->io_port,
5520 (ulong) shp->io_port + boardp->asc_n_io_port - 1,
5521 shp->irq, shp->dma_channel);
5523 if (asc_dvc_varp->bus_type & ASC_IS_VL) {
5525 } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
5527 } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
5528 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
5529 == ASC_IS_PCI_ULTRA) {
5530 busname = "PCI Ultra";
5536 ASC_PRINT2( "advansys_info: board %d: unknown bus type %d\n",
5537 boardp->id, asc_dvc_varp->bus_type);
5539 /* Don't reference 'shp->n_io_port'; It may be truncated. */
5541 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
5542 ASC_VERSION, busname,
5543 (ulong) shp->io_port,
5544 (ulong) shp->io_port + boardp->asc_n_io_port - 1,
5549 * Wide Adapter Information
5551 * Memory-mapped I/O is used instead of I/O space to access
5552 * the adapter, but display the I/O Port range. The Memory
5553 * I/O address is displayed through the driver /proc file.
5555 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
5556 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
5558 iolen = ADV_3550_IOLEN;
5559 widename = "Ultra-Wide";
5560 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
5562 iolen = ADV_38C0800_IOLEN;
5563 widename = "Ultra2-Wide";
5566 iolen = ADV_38C1600_IOLEN;
5567 widename = "Ultra3-Wide";
5569 sprintf(info, "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
5572 (ulong) adv_dvc_varp->iop_base,
5573 (ulong) adv_dvc_varp->iop_base + iolen - 1,
5576 ASC_ASSERT(strlen(info) < ASC_INFO_SIZE);
5577 ASC_DBG(1, "advansys_info: end\n");
5582 * advansys_queuecommand() - interrupt-driven I/O entrypoint.
5584 * This function always returns 0. Command return status is saved
5585 * in the 'scp' result field.
5588 advansys_queuecommand(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *))
5590 struct Scsi_Host *shp;
5591 asc_board_t *boardp;
5593 struct scsi_cmnd *done_scp;
5595 shp = scp->device->host;
5596 boardp = ASC_BOARDP(shp);
5597 ASC_STATS(shp, queuecommand);
5599 /* host_lock taken by mid-level prior to call but need to protect */
5600 /* against own ISR */
5601 spin_lock_irqsave(&boardp->lock, flags);
5604 * Block new commands while handling a reset or abort request.
5606 if (boardp->flags & ASC_HOST_IN_RESET) {
5608 "advansys_queuecommand: scp 0x%lx blocked for reset request\n",
5610 scp->result = HOST_BYTE(DID_RESET);
5613 * Add blocked requests to the board's 'done' queue. The queued
5614 * requests will be completed at the end of the abort or reset
5617 asc_enqueue(&boardp->done, scp, ASC_BACK);
5618 spin_unlock_irqrestore(&boardp->lock, flags);
5623 * Attempt to execute any waiting commands for the board.
5625 if (!ASC_QUEUE_EMPTY(&boardp->waiting)) {
5627 "advansys_queuecommand: before asc_execute_queue() waiting\n");
5628 asc_execute_queue(&boardp->waiting);
5632 * Save the function pointer to Linux mid-level 'done' function
5633 * and attempt to execute the command.
5635 * If ASC_NOERROR is returned the request has been added to the
5636 * board's 'active' queue and will be completed by the interrupt
5639 * If ASC_BUSY is returned add the request to the board's per
5640 * target waiting list. This is the first time the request has
5641 * been tried. Add it to the back of the waiting list. It will be
5644 * If an error occurred, the request will have been placed on the
5645 * board's 'done' queue and must be completed before returning.
5647 scp->scsi_done = done;
5648 switch (asc_execute_scsi_cmnd(scp)) {
5652 asc_enqueue(&boardp->waiting, scp, ASC_BACK);
5656 done_scp = asc_dequeue_list(&boardp->done, NULL, ASC_TID_ALL);
5657 /* Interrupts could be enabled here. */
5658 asc_scsi_done_list(done_scp);
5661 spin_unlock_irqrestore(&boardp->lock, flags);
5669 * Reset the bus associated with the command 'scp'.
5671 * This function runs its own thread. Interrupts must be blocked but
5672 * sleeping is allowed and no locking other than for host structures is
5673 * required. Returns SUCCESS or FAILED.
5676 advansys_reset(struct scsi_cmnd *scp)
5678 struct Scsi_Host *shp;
5679 asc_board_t *boardp;
5680 ASC_DVC_VAR *asc_dvc_varp;
5681 ADV_DVC_VAR *adv_dvc_varp;
5683 struct scsi_cmnd *done_scp = NULL, *last_scp = NULL;
5684 struct scsi_cmnd *tscp, *new_last_scp;
5688 ASC_DBG1(1, "advansys_reset: 0x%lx\n", (ulong) scp);
5690 #ifdef ADVANSYS_STATS
5691 if (scp->device->host != NULL) {
5692 ASC_STATS(scp->device->host, reset);
5694 #endif /* ADVANSYS_STATS */
5696 if ((shp = scp->device->host) == NULL) {
5697 scp->result = HOST_BYTE(DID_ERROR);
5701 boardp = ASC_BOARDP(shp);
5703 ASC_PRINT1("advansys_reset: board %d: SCSI bus reset started...\n",
5706 * Check for re-entrancy.
5708 spin_lock_irqsave(&boardp->lock, flags);
5709 if (boardp->flags & ASC_HOST_IN_RESET) {
5710 spin_unlock_irqrestore(&boardp->lock, flags);
5713 boardp->flags |= ASC_HOST_IN_RESET;
5714 spin_unlock_irqrestore(&boardp->lock, flags);
5716 if (ASC_NARROW_BOARD(boardp)) {
5720 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
5723 * Reset the chip and SCSI bus.
5725 ASC_DBG(1, "advansys_reset: before AscInitAsc1000Driver()\n");
5726 status = AscInitAsc1000Driver(asc_dvc_varp);
5728 /* Refer to ASC_IERR_* defintions for meaning of 'err_code'. */
5729 if (asc_dvc_varp->err_code) {
5731 "advansys_reset: board %d: SCSI bus reset error: 0x%x\n",
5732 boardp->id, asc_dvc_varp->err_code);
5734 } else if (status) {
5736 "advansys_reset: board %d: SCSI bus reset warning: 0x%x\n",
5737 boardp->id, status);
5740 "advansys_reset: board %d: SCSI bus reset successful.\n",
5744 ASC_DBG(1, "advansys_reset: after AscInitAsc1000Driver()\n");
5745 spin_lock_irqsave(&boardp->lock, flags);
5751 * If the suggest reset bus flags are set, then reset the bus.
5752 * Otherwise only reset the device.
5754 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
5757 * Reset the target's SCSI bus.
5759 ASC_DBG(1, "advansys_reset: before AdvResetChipAndSB()\n");
5760 switch (AdvResetChipAndSB(adv_dvc_varp)) {
5762 ASC_PRINT1("advansys_reset: board %d: SCSI bus reset successful.\n",
5767 ASC_PRINT1("advansys_reset: board %d: SCSI bus reset error.\n",
5772 spin_lock_irqsave(&boardp->lock, flags);
5773 (void) AdvISR(adv_dvc_varp);
5775 /* Board lock is held. */
5778 * Dequeue all board 'done' requests. A pointer to the last request
5779 * is returned in 'last_scp'.
5781 done_scp = asc_dequeue_list(&boardp->done, &last_scp, ASC_TID_ALL);
5784 * Dequeue all board 'active' requests for all devices and set
5785 * the request status to DID_RESET. A pointer to the last request
5786 * is returned in 'last_scp'.
5788 if (done_scp == NULL) {
5789 done_scp = asc_dequeue_list(&boardp->active, &last_scp, ASC_TID_ALL);
5790 for (tscp = done_scp; tscp; tscp = REQPNEXT(tscp)) {
5791 tscp->result = HOST_BYTE(DID_RESET);
5794 /* Append to 'done_scp' at the end with 'last_scp'. */
5795 ASC_ASSERT(last_scp != NULL);
5796 last_scp->host_scribble = (unsigned char *)asc_dequeue_list(
5797 &boardp->active, &new_last_scp, ASC_TID_ALL);
5798 if (new_last_scp != NULL) {
5799 ASC_ASSERT(REQPNEXT(last_scp) != NULL);
5800 for (tscp = REQPNEXT(last_scp); tscp; tscp = REQPNEXT(tscp)) {
5801 tscp->result = HOST_BYTE(DID_RESET);
5803 last_scp = new_last_scp;
5808 * Dequeue all 'waiting' requests and set the request status
5811 if (done_scp == NULL) {
5812 done_scp = asc_dequeue_list(&boardp->waiting, &last_scp, ASC_TID_ALL);
5813 for (tscp = done_scp; tscp; tscp = REQPNEXT(tscp)) {
5814 tscp->result = HOST_BYTE(DID_RESET);
5817 /* Append to 'done_scp' at the end with 'last_scp'. */
5818 ASC_ASSERT(last_scp != NULL);
5819 last_scp->host_scribble = (unsigned char *)asc_dequeue_list(
5820 &boardp->waiting, &new_last_scp, ASC_TID_ALL);
5821 if (new_last_scp != NULL) {
5822 ASC_ASSERT(REQPNEXT(last_scp) != NULL);
5823 for (tscp = REQPNEXT(last_scp); tscp; tscp = REQPNEXT(tscp)) {
5824 tscp->result = HOST_BYTE(DID_RESET);
5826 last_scp = new_last_scp;
5830 /* Save the time of the most recently completed reset. */
5831 boardp->last_reset = jiffies;
5833 /* Clear reset flag. */
5834 boardp->flags &= ~ASC_HOST_IN_RESET;
5835 spin_unlock_irqrestore(&boardp->lock, flags);
5838 * Complete all the 'done_scp' requests.
5840 if (done_scp != NULL) {
5841 asc_scsi_done_list(done_scp);
5844 ASC_DBG1(1, "advansys_reset: ret %d\n", ret);
5850 * advansys_biosparam()
5852 * Translate disk drive geometry if the "BIOS greater than 1 GB"
5853 * support is enabled for a drive.
5855 * ip (information pointer) is an int array with the following definition:
5861 advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
5862 sector_t capacity, int ip[])
5864 asc_board_t *boardp;
5866 ASC_DBG(1, "advansys_biosparam: begin\n");
5867 ASC_STATS(sdev->host, biosparam);
5868 boardp = ASC_BOARDP(sdev->host);
5869 if (ASC_NARROW_BOARD(boardp)) {
5870 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
5871 ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
5879 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
5880 BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
5888 ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
5889 ASC_DBG(1, "advansys_biosparam: end\n");
5896 * This function is called from init/main.c at boot time.
5897 * It it passed LILO parameters that can be set from the
5898 * LILO command line or in /etc/lilo.conf.
5900 * It is used by the AdvanSys driver to either disable I/O
5901 * port scanning or to limit scanning to 1 - 4 I/O ports.
5902 * Regardless of the option setting EISA and PCI boards
5903 * will still be searched for and detected. This option
5904 * only affects searching for ISA and VL boards.
5906 * If ADVANSYS_DEBUG is defined the driver debug level may
5907 * be set using the 5th (ASC_NUM_IOPORT_PROBE + 1) I/O Port.
5910 * 1. Eliminate I/O port scanning:
5911 * boot: linux advansys=
5913 * boot: linux advansys=0x0
5914 * 2. Limit I/O port scanning to one I/O port:
5915 * boot: linux advansys=0x110
5916 * 3. Limit I/O port scanning to four I/O ports:
5917 * boot: linux advansys=0x110,0x210,0x230,0x330
5918 * 4. If ADVANSYS_DEBUG, limit I/O port scanning to four I/O ports and
5919 * set the driver debug level to 2.
5920 * boot: linux advansys=0x110,0x210,0x230,0x330,0xdeb2
5922 * ints[0] - number of arguments
5923 * ints[1] - first argument
5924 * ints[2] - second argument
5928 advansys_setup(char *str, int *ints)
5932 if (asc_iopflag == ASC_TRUE) {
5933 printk("AdvanSys SCSI: 'advansys' LILO option may appear only once\n");
5937 asc_iopflag = ASC_TRUE;
5939 if (ints[0] > ASC_NUM_IOPORT_PROBE) {
5940 #ifdef ADVANSYS_DEBUG
5941 if ((ints[0] == ASC_NUM_IOPORT_PROBE + 1) &&
5942 (ints[ASC_NUM_IOPORT_PROBE + 1] >> 4 == 0xdeb)) {
5943 asc_dbglvl = ints[ASC_NUM_IOPORT_PROBE + 1] & 0xf;
5945 #endif /* ADVANSYS_DEBUG */
5946 printk("AdvanSys SCSI: only %d I/O ports accepted\n",
5947 ASC_NUM_IOPORT_PROBE);
5948 #ifdef ADVANSYS_DEBUG
5950 #endif /* ADVANSYS_DEBUG */
5953 #ifdef ADVANSYS_DEBUG
5954 ASC_DBG1(1, "advansys_setup: ints[0] %d\n", ints[0]);
5955 for (i = 1; i < ints[0]; i++) {
5956 ASC_DBG2(1, " ints[%d] 0x%x", i, ints[i]);
5959 #endif /* ADVANSYS_DEBUG */
5961 for (i = 1; i <= ints[0] && i <= ASC_NUM_IOPORT_PROBE; i++) {
5962 asc_ioport[i-1] = ints[i];
5963 ASC_DBG2(1, "advansys_setup: asc_ioport[%d] 0x%x\n",
5964 i - 1, asc_ioport[i-1]);
5970 * --- Loadable Driver Support
5973 static struct scsi_host_template driver_template = {
5974 .proc_name = "advansys",
5975 #ifdef CONFIG_PROC_FS
5976 .proc_info = advansys_proc_info,
5979 .detect = advansys_detect,
5980 .release = advansys_release,
5981 .info = advansys_info,
5982 .queuecommand = advansys_queuecommand,
5983 .eh_bus_reset_handler = advansys_reset,
5984 .bios_param = advansys_biosparam,
5985 .slave_configure = advansys_slave_configure,
5987 * Because the driver may control an ISA adapter 'unchecked_isa_dma'
5988 * must be set. The flag will be cleared in advansys_detect for non-ISA
5989 * adapters. Refer to the comment in scsi_module.c for more information.
5991 .unchecked_isa_dma = 1,
5993 * All adapters controlled by this driver are capable of large
5994 * scatter-gather lists. According to the mid-level SCSI documentation
5995 * this obviates any performance gain provided by setting
5996 * 'use_clustering'. But empirically while CPU utilization is increased
5997 * by enabling clustering, I/O throughput increases as well.
5999 .use_clustering = ENABLE_CLUSTERING,
6001 #include "scsi_module.c"
6005 * --- Miscellaneous Driver Functions
6009 * First-level interrupt handler.
6011 * 'dev_id' is a pointer to the interrupting adapter's asc_board_t. Because
6012 * all boards are currently checked for interrupts on each interrupt, 'dev_id'
6013 * is not referenced. 'dev_id' could be used to identify an interrupt passed
6014 * to the AdvanSys driver which is for a device sharing an interrupt with
6015 * an AdvanSys adapter.
6018 advansys_interrupt(int irq, void *dev_id, struct pt_regs *regs)
6022 asc_board_t *boardp;
6023 struct scsi_cmnd *done_scp = NULL, *last_scp = NULL;
6024 struct scsi_cmnd *new_last_scp;
6025 struct Scsi_Host *shp;
6027 ASC_DBG(1, "advansys_interrupt: begin\n");
6030 * Check for interrupts on all boards.
6031 * AscISR() will call asc_isr_callback().
6033 for (i = 0; i < asc_board_count; i++) {
6035 boardp = ASC_BOARDP(shp);
6036 ASC_DBG2(2, "advansys_interrupt: i %d, boardp 0x%lx\n",
6038 spin_lock_irqsave(&boardp->lock, flags);
6039 if (ASC_NARROW_BOARD(boardp)) {
6043 if (AscIsIntPending(shp->io_port)) {
6044 ASC_STATS(shp, interrupt);
6045 ASC_DBG(1, "advansys_interrupt: before AscISR()\n");
6046 AscISR(&boardp->dvc_var.asc_dvc_var);
6052 ASC_DBG(1, "advansys_interrupt: before AdvISR()\n");
6053 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
6054 ASC_STATS(shp, interrupt);
6059 * Start waiting requests and create a list of completed requests.
6061 * If a reset request is being performed for the board, the reset
6062 * handler will complete pending requests after it has completed.
6064 if ((boardp->flags & ASC_HOST_IN_RESET) == 0) {
6065 ASC_DBG2(1, "advansys_interrupt: done_scp 0x%lx, last_scp 0x%lx\n",
6066 (ulong) done_scp, (ulong) last_scp);
6068 /* Start any waiting commands for the board. */
6069 if (!ASC_QUEUE_EMPTY(&boardp->waiting)) {
6070 ASC_DBG(1, "advansys_interrupt: before asc_execute_queue()\n");
6071 asc_execute_queue(&boardp->waiting);
6075 * Add to the list of requests that must be completed.
6077 * 'done_scp' will always be NULL on the first iteration
6078 * of this loop. 'last_scp' is set at the same time as
6081 if (done_scp == NULL) {
6082 done_scp = asc_dequeue_list(&boardp->done, &last_scp,
6085 ASC_ASSERT(last_scp != NULL);
6086 last_scp->host_scribble = (unsigned char *)asc_dequeue_list(
6087 &boardp->done, &new_last_scp, ASC_TID_ALL);
6088 if (new_last_scp != NULL) {
6089 ASC_ASSERT(REQPNEXT(last_scp) != NULL);
6090 last_scp = new_last_scp;
6094 spin_unlock_irqrestore(&boardp->lock, flags);
6098 * If interrupts were enabled on entry, then they
6099 * are now enabled here.
6101 * Complete all requests on the done list.
6104 asc_scsi_done_list(done_scp);
6106 ASC_DBG(1, "advansys_interrupt: end\n");
6111 * Set the number of commands to queue per device for the
6112 * specified host adapter.
6115 advansys_slave_configure(struct scsi_device *device)
6117 asc_board_t *boardp;
6119 boardp = ASC_BOARDP(device->host);
6120 boardp->flags |= ASC_SELECT_QUEUE_DEPTHS;
6122 * Save a pointer to the device and set its initial/maximum
6123 * queue depth. Only save the pointer for a lun0 dev though.
6125 if(device->lun == 0)
6126 boardp->device[device->id] = device;
6127 if(device->tagged_supported) {
6128 if (ASC_NARROW_BOARD(boardp)) {
6129 scsi_adjust_queue_depth(device, MSG_ORDERED_TAG,
6130 boardp->dvc_var.asc_dvc_var.max_dvc_qng[device->id]);
6132 scsi_adjust_queue_depth(device, MSG_ORDERED_TAG,
6133 boardp->dvc_var.adv_dvc_var.max_dvc_qng);
6136 scsi_adjust_queue_depth(device, 0, device->host->cmd_per_lun);
6138 ASC_DBG4(1, "advansys_slave_configure: device 0x%lx, boardp 0x%lx, id %d, depth %d\n",
6139 (ulong) device, (ulong) boardp, device->id, device->queue_depth);
6144 * Complete all requests on the singly linked list pointed
6147 * Interrupts can be enabled on entry.
6150 asc_scsi_done_list(struct scsi_cmnd *scp)
6152 struct scsi_cmnd *tscp;
6154 ASC_DBG(2, "asc_scsi_done_list: begin\n");
6155 while (scp != NULL) {
6156 asc_board_t *boardp;
6159 ASC_DBG1(3, "asc_scsi_done_list: scp 0x%lx\n", (ulong) scp);
6160 tscp = REQPNEXT(scp);
6161 scp->host_scribble = NULL;
6163 boardp = ASC_BOARDP(scp->device->host);
6165 if (ASC_NARROW_BOARD(boardp))
6166 dev = boardp->dvc_cfg.asc_dvc_cfg.dev;
6168 dev = boardp->dvc_cfg.adv_dvc_cfg.dev;
6171 dma_unmap_sg(dev, (struct scatterlist *)scp->request_buffer,
6172 scp->use_sg, scp->sc_data_direction);
6173 else if (scp->request_bufflen)
6174 dma_unmap_single(dev, scp->SCp.dma_handle,
6175 scp->request_bufflen, scp->sc_data_direction);
6177 ASC_STATS(scp->device->host, done);
6178 ASC_ASSERT(scp->scsi_done != NULL);
6180 scp->scsi_done(scp);
6184 ASC_DBG(2, "asc_scsi_done_list: done\n");
6189 * Execute a single 'Scsi_Cmnd'.
6191 * The function 'done' is called when the request has been completed.
6195 * host - board controlling device
6196 * device - device to send command
6197 * target - target of device
6198 * lun - lun of device
6199 * cmd_len - length of SCSI CDB
6200 * cmnd - buffer for SCSI 8, 10, or 12 byte CDB
6201 * use_sg - if non-zero indicates scatter-gather request with use_sg elements
6203 * if (use_sg == 0) {
6204 * request_buffer - buffer address for request
6205 * request_bufflen - length of request buffer
6207 * request_buffer - pointer to scatterlist structure
6210 * sense_buffer - sense command buffer
6212 * result (4 bytes of an int):
6214 * 0 SCSI Status Byte Code
6215 * 1 SCSI One Byte Message Code
6217 * 3 Mid-Level Error Code
6219 * host driver fields:
6220 * SCp - Scsi_Pointer used for command processing status
6221 * scsi_done - used to save caller's done function
6222 * host_scribble - used for pointer to another struct scsi_cmnd
6224 * If this function returns ASC_NOERROR the request has been enqueued
6225 * on the board's 'active' queue and will be completed from the
6226 * interrupt handler.
6228 * If this function returns ASC_NOERROR the request has been enqueued
6229 * on the board's 'done' queue and must be completed by the caller.
6231 * If ASC_BUSY is returned the request will be enqueued by the
6232 * caller on the target's waiting queue and re-tried later.
6235 asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
6237 asc_board_t *boardp;
6238 ASC_DVC_VAR *asc_dvc_varp;
6239 ADV_DVC_VAR *adv_dvc_varp;
6240 ADV_SCSI_REQ_Q *adv_scsiqp;
6241 struct scsi_device *device;
6244 ASC_DBG2(1, "asc_execute_scsi_cmnd: scp 0x%lx, done 0x%lx\n",
6245 (ulong) scp, (ulong) scp->scsi_done);
6247 boardp = ASC_BOARDP(scp->device->host);
6248 device = boardp->device[scp->device->id];
6250 if (ASC_NARROW_BOARD(boardp)) {
6252 * Build and execute Narrow Board request.
6255 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
6258 * Build Asc Library request structure using the
6259 * global structures 'asc_scsi_req' and 'asc_sg_head'.
6261 * If an error is returned, then the request has been
6262 * queued on the board done queue. It will be completed
6265 * asc_build_req() can not return ASC_BUSY.
6267 if (asc_build_req(boardp, scp) == ASC_ERROR) {
6268 ASC_STATS(scp->device->host, build_error);
6273 * Execute the command. If there is no error, add the command
6274 * to the active queue.
6276 switch (ret = AscExeScsiQueue(asc_dvc_varp, &asc_scsi_q)) {
6278 ASC_STATS(scp->device->host, exe_noerror);
6280 * Increment monotonically increasing per device successful
6281 * request counter. Wrapping doesn't matter.
6283 boardp->reqcnt[scp->device->id]++;
6284 asc_enqueue(&boardp->active, scp, ASC_BACK);
6286 "asc_execute_scsi_cmnd: AscExeScsiQueue(), ASC_NOERROR\n");
6290 * Caller will enqueue request on the target's waiting queue
6293 ASC_STATS(scp->device->host, exe_busy);
6297 "asc_execute_scsi_cmnd: board %d: AscExeScsiQueue() ASC_ERROR, err_code 0x%x\n",
6298 boardp->id, asc_dvc_varp->err_code);
6299 ASC_STATS(scp->device->host, exe_error);
6300 scp->result = HOST_BYTE(DID_ERROR);
6301 asc_enqueue(&boardp->done, scp, ASC_BACK);
6305 "asc_execute_scsi_cmnd: board %d: AscExeScsiQueue() unknown, err_code 0x%x\n",
6306 boardp->id, asc_dvc_varp->err_code);
6307 ASC_STATS(scp->device->host, exe_unknown);
6308 scp->result = HOST_BYTE(DID_ERROR);
6309 asc_enqueue(&boardp->done, scp, ASC_BACK);
6314 * Build and execute Wide Board request.
6316 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
6319 * Build and get a pointer to an Adv Library request structure.
6321 * If the request is successfully built then send it below,
6322 * otherwise return with an error.
6324 switch (adv_build_req(boardp, scp, &adv_scsiqp)) {
6326 ASC_DBG(3, "asc_execute_scsi_cmnd: adv_build_req ASC_NOERROR\n");
6329 ASC_DBG(1, "asc_execute_scsi_cmnd: adv_build_req ASC_BUSY\n");
6331 * If busy is returned the request has not been enqueued.
6332 * It will be enqueued by the caller on the target's waiting
6333 * queue and retried later.
6335 * The asc_stats fields 'adv_build_noreq' and 'adv_build_nosg'
6336 * count wide board busy conditions. They are updated in
6337 * adv_build_req and adv_get_sglist, respectively.
6342 * If an error is returned, then the request has been
6343 * queued on the board done queue. It will be completed
6347 ASC_DBG(1, "asc_execute_scsi_cmnd: adv_build_req ASC_ERROR\n");
6348 ASC_STATS(scp->device->host, build_error);
6353 * Execute the command. If there is no error, add the command
6354 * to the active queue.
6356 switch (ret = AdvExeScsiQueue(adv_dvc_varp, adv_scsiqp)) {
6358 ASC_STATS(scp->device->host, exe_noerror);
6360 * Increment monotonically increasing per device successful
6361 * request counter. Wrapping doesn't matter.
6363 boardp->reqcnt[scp->device->id]++;
6364 asc_enqueue(&boardp->active, scp, ASC_BACK);
6366 "asc_execute_scsi_cmnd: AdvExeScsiQueue(), ASC_NOERROR\n");
6370 * Caller will enqueue request on the target's waiting queue
6373 ASC_STATS(scp->device->host, exe_busy);
6377 "asc_execute_scsi_cmnd: board %d: AdvExeScsiQueue() ASC_ERROR, err_code 0x%x\n",
6378 boardp->id, adv_dvc_varp->err_code);
6379 ASC_STATS(scp->device->host, exe_error);
6380 scp->result = HOST_BYTE(DID_ERROR);
6381 asc_enqueue(&boardp->done, scp, ASC_BACK);
6385 "asc_execute_scsi_cmnd: board %d: AdvExeScsiQueue() unknown, err_code 0x%x\n",
6386 boardp->id, adv_dvc_varp->err_code);
6387 ASC_STATS(scp->device->host, exe_unknown);
6388 scp->result = HOST_BYTE(DID_ERROR);
6389 asc_enqueue(&boardp->done, scp, ASC_BACK);
6394 ASC_DBG(1, "asc_execute_scsi_cmnd: end\n");
6399 * Build a request structure for the Asc Library (Narrow Board).
6401 * The global structures 'asc_scsi_q' and 'asc_sg_head' are
6402 * used to build the request.
6404 * If an error occurs, then queue the request on the board done
6405 * queue and return ASC_ERROR.
6408 asc_build_req(asc_board_t *boardp, struct scsi_cmnd *scp)
6410 struct device *dev = boardp->dvc_cfg.asc_dvc_cfg.dev;
6413 * Mutually exclusive access is required to 'asc_scsi_q' and
6414 * 'asc_sg_head' until after the request is started.
6416 memset(&asc_scsi_q, 0, sizeof(ASC_SCSI_Q));
6419 * Point the ASC_SCSI_Q to the 'struct scsi_cmnd'.
6421 asc_scsi_q.q2.srb_ptr = ASC_VADDR_TO_U32(scp);
6424 * Build the ASC_SCSI_Q request.
6426 * For narrow boards a CDB length maximum of 12 bytes
6429 if (scp->cmd_len > ASC_MAX_CDB_LEN) {
6431 "asc_build_req: board %d: cmd_len %d > ASC_MAX_CDB_LEN %d\n",
6432 boardp->id, scp->cmd_len, ASC_MAX_CDB_LEN);
6433 scp->result = HOST_BYTE(DID_ERROR);
6434 asc_enqueue(&boardp->done, scp, ASC_BACK);
6437 asc_scsi_q.cdbptr = &scp->cmnd[0];
6438 asc_scsi_q.q2.cdb_len = scp->cmd_len;
6439 asc_scsi_q.q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
6440 asc_scsi_q.q1.target_lun = scp->device->lun;
6441 asc_scsi_q.q2.target_ix = ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
6442 asc_scsi_q.q1.sense_addr = cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
6443 asc_scsi_q.q1.sense_len = sizeof(scp->sense_buffer);
6446 * If there are any outstanding requests for the current target,
6447 * then every 255th request send an ORDERED request. This heuristic
6448 * tries to retain the benefit of request sorting while preventing
6449 * request starvation. 255 is the max number of tags or pending commands
6450 * a device may have outstanding.
6452 * The request count is incremented below for every successfully
6456 if ((boardp->dvc_var.asc_dvc_var.cur_dvc_qng[scp->device->id] > 0) &&
6457 (boardp->reqcnt[scp->device->id] % 255) == 0) {
6458 asc_scsi_q.q2.tag_code = MSG_ORDERED_TAG;
6460 asc_scsi_q.q2.tag_code = MSG_SIMPLE_TAG;
6464 * Build ASC_SCSI_Q for a contiguous buffer or a scatter-gather
6467 if (scp->use_sg == 0) {
6469 * CDB request of single contiguous buffer.
6471 ASC_STATS(scp->device->host, cont_cnt);
6472 scp->SCp.dma_handle = scp->request_bufflen ?
6473 dma_map_single(dev, scp->request_buffer,
6474 scp->request_bufflen, scp->sc_data_direction) : 0;
6475 asc_scsi_q.q1.data_addr = cpu_to_le32(scp->SCp.dma_handle);
6476 asc_scsi_q.q1.data_cnt = cpu_to_le32(scp->request_bufflen);
6477 ASC_STATS_ADD(scp->device->host, cont_xfer,
6478 ASC_CEILING(scp->request_bufflen, 512));
6479 asc_scsi_q.q1.sg_queue_cnt = 0;
6480 asc_scsi_q.sg_head = NULL;
6483 * CDB scatter-gather request list.
6487 struct scatterlist *slp;
6489 slp = (struct scatterlist *)scp->request_buffer;
6490 use_sg = dma_map_sg(dev, slp, scp->use_sg, scp->sc_data_direction);
6492 if (use_sg > scp->device->host->sg_tablesize) {
6494 "asc_build_req: board %d: use_sg %d > sg_tablesize %d\n",
6495 boardp->id, use_sg, scp->device->host->sg_tablesize);
6496 dma_unmap_sg(dev, slp, scp->use_sg, scp->sc_data_direction);
6497 scp->result = HOST_BYTE(DID_ERROR);
6498 asc_enqueue(&boardp->done, scp, ASC_BACK);
6502 ASC_STATS(scp->device->host, sg_cnt);
6505 * Use global ASC_SG_HEAD structure and set the ASC_SCSI_Q
6506 * structure to point to it.
6508 memset(&asc_sg_head, 0, sizeof(ASC_SG_HEAD));
6510 asc_scsi_q.q1.cntl |= QC_SG_HEAD;
6511 asc_scsi_q.sg_head = &asc_sg_head;
6512 asc_scsi_q.q1.data_cnt = 0;
6513 asc_scsi_q.q1.data_addr = 0;
6514 /* This is a byte value, otherwise it would need to be swapped. */
6515 asc_sg_head.entry_cnt = asc_scsi_q.q1.sg_queue_cnt = use_sg;
6516 ASC_STATS_ADD(scp->device->host, sg_elem, asc_sg_head.entry_cnt);
6519 * Convert scatter-gather list into ASC_SG_HEAD list.
6521 for (sgcnt = 0; sgcnt < use_sg; sgcnt++, slp++) {
6522 asc_sg_head.sg_list[sgcnt].addr = cpu_to_le32(sg_dma_address(slp));
6523 asc_sg_head.sg_list[sgcnt].bytes = cpu_to_le32(sg_dma_len(slp));
6524 ASC_STATS_ADD(scp->device->host, sg_xfer, ASC_CEILING(sg_dma_len(slp), 512));
6528 ASC_DBG_PRT_ASC_SCSI_Q(2, &asc_scsi_q);
6529 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
6535 * Build a request structure for the Adv Library (Wide Board).
6537 * If an adv_req_t can not be allocated to issue the request,
6538 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
6540 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the
6541 * microcode for DMA addresses or math operations are byte swapped
6542 * to little-endian order.
6545 adv_build_req(asc_board_t *boardp, struct scsi_cmnd *scp,
6546 ADV_SCSI_REQ_Q **adv_scsiqpp)
6549 ADV_SCSI_REQ_Q *scsiqp;
6552 struct device *dev = boardp->dvc_cfg.adv_dvc_cfg.dev;
6555 * Allocate an adv_req_t structure from the board to execute
6558 if (boardp->adv_reqp == NULL) {
6559 ASC_DBG(1, "adv_build_req: no free adv_req_t\n");
6560 ASC_STATS(scp->device->host, adv_build_noreq);
6563 reqp = boardp->adv_reqp;
6564 boardp->adv_reqp = reqp->next_reqp;
6565 reqp->next_reqp = NULL;
6569 * Get 32-byte aligned ADV_SCSI_REQ_Q and ADV_SG_BLOCK pointers.
6571 scsiqp = (ADV_SCSI_REQ_Q *) ADV_32BALIGN(&reqp->scsi_req_q);
6574 * Initialize the structure.
6576 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
6579 * Set the ADV_SCSI_REQ_Q 'srb_ptr' to point to the adv_req_t structure.
6581 scsiqp->srb_ptr = ASC_VADDR_TO_U32(reqp);
6584 * Set the adv_req_t 'cmndp' to point to the struct scsi_cmnd structure.
6589 * Build the ADV_SCSI_REQ_Q request.
6593 * Set CDB length and copy it to the request structure.
6594 * For wide boards a CDB length maximum of 16 bytes
6597 if (scp->cmd_len > ADV_MAX_CDB_LEN) {
6599 "adv_build_req: board %d: cmd_len %d > ADV_MAX_CDB_LEN %d\n",
6600 boardp->id, scp->cmd_len, ADV_MAX_CDB_LEN);
6601 scp->result = HOST_BYTE(DID_ERROR);
6602 asc_enqueue(&boardp->done, scp, ASC_BACK);
6605 scsiqp->cdb_len = scp->cmd_len;
6606 /* Copy first 12 CDB bytes to cdb[]. */
6607 for (i = 0; i < scp->cmd_len && i < 12; i++) {
6608 scsiqp->cdb[i] = scp->cmnd[i];
6610 /* Copy last 4 CDB bytes, if present, to cdb16[]. */
6611 for (; i < scp->cmd_len; i++) {
6612 scsiqp->cdb16[i - 12] = scp->cmnd[i];
6615 scsiqp->target_id = scp->device->id;
6616 scsiqp->target_lun = scp->device->lun;
6618 scsiqp->sense_addr = cpu_to_le32(virt_to_bus(&scp->sense_buffer[0]));
6619 scsiqp->sense_len = sizeof(scp->sense_buffer);
6622 * Build ADV_SCSI_REQ_Q for a contiguous buffer or a scatter-gather
6626 scsiqp->data_cnt = cpu_to_le32(scp->request_bufflen);
6627 scsiqp->vdata_addr = scp->request_buffer;
6628 scsiqp->data_addr = cpu_to_le32(virt_to_bus(scp->request_buffer));
6630 if (scp->use_sg == 0) {
6632 * CDB request of single contiguous buffer.
6634 reqp->sgblkp = NULL;
6635 scsiqp->data_cnt = cpu_to_le32(scp->request_bufflen);
6636 if (scp->request_bufflen) {
6637 scsiqp->vdata_addr = scp->request_buffer;
6638 scp->SCp.dma_handle =
6639 dma_map_single(dev, scp->request_buffer,
6640 scp->request_bufflen, scp->sc_data_direction);
6642 scsiqp->vdata_addr = 0;
6643 scp->SCp.dma_handle = 0;
6645 scsiqp->data_addr = cpu_to_le32(scp->SCp.dma_handle);
6646 scsiqp->sg_list_ptr = NULL;
6647 scsiqp->sg_real_addr = 0;
6648 ASC_STATS(scp->device->host, cont_cnt);
6649 ASC_STATS_ADD(scp->device->host, cont_xfer,
6650 ASC_CEILING(scp->request_bufflen, 512));
6653 * CDB scatter-gather request list.
6655 struct scatterlist *slp;
6658 slp = (struct scatterlist *)scp->request_buffer;
6659 use_sg = dma_map_sg(dev, slp, scp->use_sg, scp->sc_data_direction);
6661 if (use_sg > ADV_MAX_SG_LIST) {
6663 "adv_build_req: board %d: use_sg %d > ADV_MAX_SG_LIST %d\n",
6664 boardp->id, use_sg, scp->device->host->sg_tablesize);
6665 dma_unmap_sg(dev, slp, scp->use_sg, scp->sc_data_direction);
6666 scp->result = HOST_BYTE(DID_ERROR);
6667 asc_enqueue(&boardp->done, scp, ASC_BACK);
6670 * Free the 'adv_req_t' structure by adding it back to the
6673 reqp->next_reqp = boardp->adv_reqp;
6674 boardp->adv_reqp = reqp;
6679 if ((ret = adv_get_sglist(boardp, reqp, scp, use_sg)) != ADV_SUCCESS) {
6681 * Free the adv_req_t structure by adding it back to the
6684 reqp->next_reqp = boardp->adv_reqp;
6685 boardp->adv_reqp = reqp;
6690 ASC_STATS(scp->device->host, sg_cnt);
6691 ASC_STATS_ADD(scp->device->host, sg_elem, use_sg);
6694 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
6695 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
6697 *adv_scsiqpp = scsiqp;
6703 * Build scatter-gather list for Adv Library (Wide Board).
6705 * Additional ADV_SG_BLOCK structures will need to be allocated
6706 * if the total number of scatter-gather elements exceeds
6707 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
6708 * assumed to be physically contiguous.
6711 * ADV_SUCCESS(1) - SG List successfully created
6712 * ADV_ERROR(-1) - SG List creation failed
6715 adv_get_sglist(asc_board_t *boardp, adv_req_t *reqp, struct scsi_cmnd *scp, int use_sg)
6717 adv_sgblk_t *sgblkp;
6718 ADV_SCSI_REQ_Q *scsiqp;
6719 struct scatterlist *slp;
6721 ADV_SG_BLOCK *sg_block, *prev_sg_block;
6722 ADV_PADDR sg_block_paddr;
6725 scsiqp = (ADV_SCSI_REQ_Q *) ADV_32BALIGN(&reqp->scsi_req_q);
6726 slp = (struct scatterlist *) scp->request_buffer;
6727 sg_elem_cnt = use_sg;
6728 prev_sg_block = NULL;
6729 reqp->sgblkp = NULL;
6734 * Allocate a 'adv_sgblk_t' structure from the board free
6735 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
6736 * (15) scatter-gather elements.
6738 if ((sgblkp = boardp->adv_sgblkp) == NULL) {
6739 ASC_DBG(1, "adv_get_sglist: no free adv_sgblk_t\n");
6740 ASC_STATS(scp->device->host, adv_build_nosg);
6743 * Allocation failed. Free 'adv_sgblk_t' structures already
6744 * allocated for the request.
6746 while ((sgblkp = reqp->sgblkp) != NULL)
6748 /* Remove 'sgblkp' from the request list. */
6749 reqp->sgblkp = sgblkp->next_sgblkp;
6751 /* Add 'sgblkp' to the board free list. */
6752 sgblkp->next_sgblkp = boardp->adv_sgblkp;
6753 boardp->adv_sgblkp = sgblkp;
6757 /* Complete 'adv_sgblk_t' board allocation. */
6758 boardp->adv_sgblkp = sgblkp->next_sgblkp;
6759 sgblkp->next_sgblkp = NULL;
6762 * Get 8 byte aligned virtual and physical addresses for
6763 * the allocated ADV_SG_BLOCK structure.
6765 sg_block = (ADV_SG_BLOCK *) ADV_8BALIGN(&sgblkp->sg_block);
6766 sg_block_paddr = virt_to_bus(sg_block);
6769 * Check if this is the first 'adv_sgblk_t' for the request.
6771 if (reqp->sgblkp == NULL)
6773 /* Request's first scatter-gather block. */
6774 reqp->sgblkp = sgblkp;
6777 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
6780 scsiqp->sg_list_ptr = sg_block;
6781 scsiqp->sg_real_addr = cpu_to_le32(sg_block_paddr);
6784 /* Request's second or later scatter-gather block. */
6785 sgblkp->next_sgblkp = reqp->sgblkp;
6786 reqp->sgblkp = sgblkp;
6789 * Point the previous ADV_SG_BLOCK structure to
6790 * the newly allocated ADV_SG_BLOCK structure.
6792 ASC_ASSERT(prev_sg_block != NULL);
6793 prev_sg_block->sg_ptr = cpu_to_le32(sg_block_paddr);
6797 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++)
6799 sg_block->sg_list[i].sg_addr = cpu_to_le32(sg_dma_address(slp));
6800 sg_block->sg_list[i].sg_count = cpu_to_le32(sg_dma_len(slp));
6801 ASC_STATS_ADD(scp->device->host, sg_xfer, ASC_CEILING(sg_dma_len(slp), 512));
6803 if (--sg_elem_cnt == 0)
6804 { /* Last ADV_SG_BLOCK and scatter-gather entry. */
6805 sg_block->sg_cnt = i + 1;
6806 sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */
6811 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
6812 prev_sg_block = sg_block;
6819 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
6821 * Interrupt callback function for the Narrow SCSI Asc Library.
6824 asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
6826 asc_board_t *boardp;
6827 struct scsi_cmnd *scp;
6828 struct Scsi_Host *shp;
6831 ASC_DBG2(1, "asc_isr_callback: asc_dvc_varp 0x%lx, qdonep 0x%lx\n",
6832 (ulong) asc_dvc_varp, (ulong) qdonep);
6833 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
6836 * Get the struct scsi_cmnd structure and Scsi_Host structure for the
6837 * command that has been completed.
6839 scp = (struct scsi_cmnd *) ASC_U32_TO_VADDR(qdonep->d2.srb_ptr);
6840 ASC_DBG1(1, "asc_isr_callback: scp 0x%lx\n", (ulong) scp);
6843 ASC_PRINT("asc_isr_callback: scp is NULL\n");
6846 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
6849 * If the request's host pointer is not valid, display a
6850 * message and return.
6852 shp = scp->device->host;
6853 for (i = 0; i < asc_board_count; i++) {
6854 if (asc_host[i] == shp) {
6858 if (i == asc_board_count) {
6860 "asc_isr_callback: scp 0x%lx has bad host pointer, host 0x%lx\n",
6861 (ulong) scp, (ulong) shp);
6865 ASC_STATS(shp, callback);
6866 ASC_DBG1(1, "asc_isr_callback: shp 0x%lx\n", (ulong) shp);
6869 * If the request isn't found on the active queue, it may
6870 * have been removed to handle a reset request.
6871 * Display a message and return.
6873 boardp = ASC_BOARDP(shp);
6874 ASC_ASSERT(asc_dvc_varp == &boardp->dvc_var.asc_dvc_var);
6875 if (asc_rmqueue(&boardp->active, scp) == ASC_FALSE) {
6877 "asc_isr_callback: board %d: scp 0x%lx not on active queue\n",
6878 boardp->id, (ulong) scp);
6883 * 'qdonep' contains the command's ending status.
6885 switch (qdonep->d3.done_stat) {
6887 ASC_DBG(2, "asc_isr_callback: QD_NO_ERROR\n");
6891 * If an INQUIRY command completed successfully, then call
6892 * the AscInquiryHandling() function to set-up the device.
6894 if (scp->cmnd[0] == INQUIRY && scp->device->lun == 0 &&
6895 (scp->request_bufflen - qdonep->remain_bytes) >= 8)
6897 AscInquiryHandling(asc_dvc_varp, scp->device->id & 0x7,
6898 (ASC_SCSI_INQUIRY *) scp->request_buffer);
6902 * Check for an underrun condition.
6904 * If there was no error and an underrun condition, then
6905 * then return the number of underrun bytes.
6907 if (scp->request_bufflen != 0 && qdonep->remain_bytes != 0 &&
6908 qdonep->remain_bytes <= scp->request_bufflen) {
6909 ASC_DBG1(1, "asc_isr_callback: underrun condition %u bytes\n",
6910 (unsigned) qdonep->remain_bytes);
6911 scp->resid = qdonep->remain_bytes;
6916 ASC_DBG(2, "asc_isr_callback: QD_WITH_ERROR\n");
6917 switch (qdonep->d3.host_stat) {
6918 case QHSTA_NO_ERROR:
6919 if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
6920 ASC_DBG(2, "asc_isr_callback: SAM_STAT_CHECK_CONDITION\n");
6921 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
6922 sizeof(scp->sense_buffer));
6924 * Note: The 'status_byte()' macro used by target drivers
6925 * defined in scsi.h shifts the status byte returned by
6926 * host drivers right by 1 bit. This is why target drivers
6927 * also use right shifted status byte definitions. For
6928 * instance target drivers use CHECK_CONDITION, defined to
6929 * 0x1, instead of the SCSI defined check condition value
6930 * of 0x2. Host drivers are supposed to return the status
6931 * byte as it is defined by SCSI.
6933 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
6934 STATUS_BYTE(qdonep->d3.scsi_stat);
6936 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
6941 /* QHSTA error occurred */
6942 ASC_DBG1(1, "asc_isr_callback: host_stat 0x%x\n",
6943 qdonep->d3.host_stat);
6944 scp->result = HOST_BYTE(DID_BAD_TARGET);
6949 case QD_ABORTED_BY_HOST:
6950 ASC_DBG(1, "asc_isr_callback: QD_ABORTED_BY_HOST\n");
6951 scp->result = HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.scsi_msg) |
6952 STATUS_BYTE(qdonep->d3.scsi_stat);
6956 ASC_DBG1(1, "asc_isr_callback: done_stat 0x%x\n", qdonep->d3.done_stat);
6957 scp->result = HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.scsi_msg) |
6958 STATUS_BYTE(qdonep->d3.scsi_stat);
6963 * If the 'init_tidmask' bit isn't already set for the target and the
6964 * current request finished normally, then set the bit for the target
6965 * to indicate that a device is present.
6967 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
6968 qdonep->d3.done_stat == QD_NO_ERROR &&
6969 qdonep->d3.host_stat == QHSTA_NO_ERROR) {
6970 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
6974 * Because interrupts may be enabled by the 'struct scsi_cmnd' done
6975 * function, add the command to the end of the board's done queue.
6976 * The done function for the command will be called from
6977 * advansys_interrupt().
6979 asc_enqueue(&boardp->done, scp, ASC_BACK);
6985 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
6987 * Callback function for the Wide SCSI Adv Library.
6990 adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
6992 asc_board_t *boardp;
6994 adv_sgblk_t *sgblkp;
6995 struct scsi_cmnd *scp;
6996 struct Scsi_Host *shp;
7001 ASC_DBG2(1, "adv_isr_callback: adv_dvc_varp 0x%lx, scsiqp 0x%lx\n",
7002 (ulong) adv_dvc_varp, (ulong) scsiqp);
7003 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
7006 * Get the adv_req_t structure for the command that has been
7007 * completed. The adv_req_t structure actually contains the
7008 * completed ADV_SCSI_REQ_Q structure.
7010 reqp = (adv_req_t *) ADV_U32_TO_VADDR(scsiqp->srb_ptr);
7011 ASC_DBG1(1, "adv_isr_callback: reqp 0x%lx\n", (ulong) reqp);
7013 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
7018 * Get the struct scsi_cmnd structure and Scsi_Host structure for the
7019 * command that has been completed.
7021 * Note: The adv_req_t request structure and adv_sgblk_t structure,
7022 * if any, are dropped, because a board structure pointer can not be
7026 ASC_DBG1(1, "adv_isr_callback: scp 0x%lx\n", (ulong) scp);
7028 ASC_PRINT("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
7031 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
7034 * If the request's host pointer is not valid, display a message
7037 shp = scp->device->host;
7038 for (i = 0; i < asc_board_count; i++) {
7039 if (asc_host[i] == shp) {
7044 * Note: If the host structure is not found, the adv_req_t request
7045 * structure and adv_sgblk_t structure, if any, is dropped.
7047 if (i == asc_board_count) {
7049 "adv_isr_callback: scp 0x%lx has bad host pointer, host 0x%lx\n",
7050 (ulong) scp, (ulong) shp);
7054 ASC_STATS(shp, callback);
7055 ASC_DBG1(1, "adv_isr_callback: shp 0x%lx\n", (ulong) shp);
7058 * If the request isn't found on the active queue, it may have been
7059 * removed to handle a reset request. Display a message and return.
7061 * Note: Because the structure may still be in use don't attempt
7062 * to free the adv_req_t and adv_sgblk_t, if any, structures.
7064 boardp = ASC_BOARDP(shp);
7065 ASC_ASSERT(adv_dvc_varp == &boardp->dvc_var.adv_dvc_var);
7066 if (asc_rmqueue(&boardp->active, scp) == ASC_FALSE) {
7068 "adv_isr_callback: board %d: scp 0x%lx not on active queue\n",
7069 boardp->id, (ulong) scp);
7074 * 'done_status' contains the command's ending status.
7076 switch (scsiqp->done_status) {
7078 ASC_DBG(2, "adv_isr_callback: QD_NO_ERROR\n");
7082 * Check for an underrun condition.
7084 * If there was no error and an underrun condition, then
7085 * then return the number of underrun bytes.
7087 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
7088 if (scp->request_bufflen != 0 && resid_cnt != 0 &&
7089 resid_cnt <= scp->request_bufflen) {
7090 ASC_DBG1(1, "adv_isr_callback: underrun condition %lu bytes\n",
7092 scp->resid = resid_cnt;
7097 ASC_DBG(2, "adv_isr_callback: QD_WITH_ERROR\n");
7098 switch (scsiqp->host_status) {
7099 case QHSTA_NO_ERROR:
7100 if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
7101 ASC_DBG(2, "adv_isr_callback: SAM_STAT_CHECK_CONDITION\n");
7102 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
7103 sizeof(scp->sense_buffer));
7105 * Note: The 'status_byte()' macro used by target drivers
7106 * defined in scsi.h shifts the status byte returned by
7107 * host drivers right by 1 bit. This is why target drivers
7108 * also use right shifted status byte definitions. For
7109 * instance target drivers use CHECK_CONDITION, defined to
7110 * 0x1, instead of the SCSI defined check condition value
7111 * of 0x2. Host drivers are supposed to return the status
7112 * byte as it is defined by SCSI.
7114 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
7115 STATUS_BYTE(scsiqp->scsi_status);
7117 scp->result = STATUS_BYTE(scsiqp->scsi_status);
7122 /* Some other QHSTA error occurred. */
7123 ASC_DBG1(1, "adv_isr_callback: host_status 0x%x\n",
7124 scsiqp->host_status);
7125 scp->result = HOST_BYTE(DID_BAD_TARGET);
7130 case QD_ABORTED_BY_HOST:
7131 ASC_DBG(1, "adv_isr_callback: QD_ABORTED_BY_HOST\n");
7132 scp->result = HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
7136 ASC_DBG1(1, "adv_isr_callback: done_status 0x%x\n", scsiqp->done_status);
7137 scp->result = HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
7142 * If the 'init_tidmask' bit isn't already set for the target and the
7143 * current request finished normally, then set the bit for the target
7144 * to indicate that a device is present.
7146 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
7147 scsiqp->done_status == QD_NO_ERROR &&
7148 scsiqp->host_status == QHSTA_NO_ERROR) {
7149 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
7153 * Because interrupts may be enabled by the 'struct scsi_cmnd' done
7154 * function, add the command to the end of the board's done queue.
7155 * The done function for the command will be called from
7156 * advansys_interrupt().
7158 asc_enqueue(&boardp->done, scp, ASC_BACK);
7161 * Free all 'adv_sgblk_t' structures allocated for the request.
7163 while ((sgblkp = reqp->sgblkp) != NULL)
7165 /* Remove 'sgblkp' from the request list. */
7166 reqp->sgblkp = sgblkp->next_sgblkp;
7168 /* Add 'sgblkp' to the board free list. */
7169 sgblkp->next_sgblkp = boardp->adv_sgblkp;
7170 boardp->adv_sgblkp = sgblkp;
7174 * Free the adv_req_t structure used with the command by adding
7175 * it back to the board free list.
7177 reqp->next_reqp = boardp->adv_reqp;
7178 boardp->adv_reqp = reqp;
7180 ASC_DBG(1, "adv_isr_callback: done\n");
7186 * adv_async_callback() - Adv Library asynchronous event callback function.
7189 adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
7193 case ADV_ASYNC_SCSI_BUS_RESET_DET:
7195 * The firmware detected a SCSI Bus reset.
7197 ASC_DBG(0, "adv_async_callback: ADV_ASYNC_SCSI_BUS_RESET_DET\n");
7200 case ADV_ASYNC_RDMA_FAILURE:
7202 * Handle RDMA failure by resetting the SCSI Bus and
7203 * possibly the chip if it is unresponsive. Log the error
7204 * with a unique code.
7206 ASC_DBG(0, "adv_async_callback: ADV_ASYNC_RDMA_FAILURE\n");
7207 AdvResetChipAndSB(adv_dvc_varp);
7210 case ADV_HOST_SCSI_BUS_RESET:
7212 * Host generated SCSI bus reset occurred.
7214 ASC_DBG(0, "adv_async_callback: ADV_HOST_SCSI_BUS_RESET\n");
7218 ASC_DBG1(0, "DvcAsyncCallBack: unknown code 0x%x\n", code);
7224 * Add a 'REQP' to the end of specified queue. Set 'tidmask'
7225 * to indicate a command is queued for the device.
7227 * 'flag' may be either ASC_FRONT or ASC_BACK.
7229 * 'REQPNEXT(reqp)' returns reqp's next pointer.
7232 asc_enqueue(asc_queue_t *ascq, REQP reqp, int flag)
7236 ASC_DBG3(3, "asc_enqueue: ascq 0x%lx, reqp 0x%lx, flag %d\n",
7237 (ulong) ascq, (ulong) reqp, flag);
7238 ASC_ASSERT(reqp != NULL);
7239 ASC_ASSERT(flag == ASC_FRONT || flag == ASC_BACK);
7240 tid = REQPTID(reqp);
7241 ASC_ASSERT(tid >= 0 && tid <= ADV_MAX_TID);
7242 if (flag == ASC_FRONT) {
7243 reqp->host_scribble = (unsigned char *)ascq->q_first[tid];
7244 ascq->q_first[tid] = reqp;
7245 /* If the queue was empty, set the last pointer. */
7246 if (ascq->q_last[tid] == NULL) {
7247 ascq->q_last[tid] = reqp;
7249 } else { /* ASC_BACK */
7250 if (ascq->q_last[tid] != NULL) {
7251 ascq->q_last[tid]->host_scribble = (unsigned char *)reqp;
7253 ascq->q_last[tid] = reqp;
7254 reqp->host_scribble = NULL;
7255 /* If the queue was empty, set the first pointer. */
7256 if (ascq->q_first[tid] == NULL) {
7257 ascq->q_first[tid] = reqp;
7260 /* The queue has at least one entry, set its bit. */
7261 ascq->q_tidmask |= ADV_TID_TO_TIDMASK(tid);
7262 #ifdef ADVANSYS_STATS
7263 /* Maintain request queue statistics. */
7264 ascq->q_tot_cnt[tid]++;
7265 ascq->q_cur_cnt[tid]++;
7266 if (ascq->q_cur_cnt[tid] > ascq->q_max_cnt[tid]) {
7267 ascq->q_max_cnt[tid] = ascq->q_cur_cnt[tid];
7268 ASC_DBG2(2, "asc_enqueue: new q_max_cnt[%d] %d\n",
7269 tid, ascq->q_max_cnt[tid]);
7271 REQPTIME(reqp) = REQTIMESTAMP();
7272 #endif /* ADVANSYS_STATS */
7273 ASC_DBG1(3, "asc_enqueue: reqp 0x%lx\n", (ulong) reqp);
7278 * Return first queued 'REQP' on the specified queue for
7279 * the specified target device. Clear the 'tidmask' bit for
7280 * the device if no more commands are left queued for it.
7282 * 'REQPNEXT(reqp)' returns reqp's next pointer.
7285 asc_dequeue(asc_queue_t *ascq, int tid)
7289 ASC_DBG2(3, "asc_dequeue: ascq 0x%lx, tid %d\n", (ulong) ascq, tid);
7290 ASC_ASSERT(tid >= 0 && tid <= ADV_MAX_TID);
7291 if ((reqp = ascq->q_first[tid]) != NULL) {
7292 ASC_ASSERT(ascq->q_tidmask & ADV_TID_TO_TIDMASK(tid));
7293 ascq->q_first[tid] = REQPNEXT(reqp);
7294 /* If the queue is empty, clear its bit and the last pointer. */
7295 if (ascq->q_first[tid] == NULL) {
7296 ascq->q_tidmask &= ~ADV_TID_TO_TIDMASK(tid);
7297 ASC_ASSERT(ascq->q_last[tid] == reqp);
7298 ascq->q_last[tid] = NULL;
7300 #ifdef ADVANSYS_STATS
7301 /* Maintain request queue statistics. */
7302 ascq->q_cur_cnt[tid]--;
7303 ASC_ASSERT(ascq->q_cur_cnt[tid] >= 0);
7304 REQTIMESTAT("asc_dequeue", ascq, reqp, tid);
7305 #endif /* ADVANSYS_STATS */
7307 ASC_DBG1(3, "asc_dequeue: reqp 0x%lx\n", (ulong) reqp);
7312 * Return a pointer to a singly linked list of all the requests queued
7313 * for 'tid' on the 'asc_queue_t' pointed to by 'ascq'.
7315 * If 'lastpp' is not NULL, '*lastpp' will be set to point to the
7316 * the last request returned in the singly linked list.
7318 * 'tid' should either be a valid target id or if it is ASC_TID_ALL,
7319 * then all queued requests are concatenated into one list and
7322 * Note: If 'lastpp' is used to append a new list to the end of
7323 * an old list, only change the old list last pointer if '*lastpp'
7324 * (or the function return value) is not NULL, i.e. use a temporary
7325 * variable for 'lastpp' and check its value after the function return
7326 * before assigning it to the list last pointer.
7328 * Unfortunately collecting queuing time statistics adds overhead to
7329 * the function that isn't inherent to the function's algorithm.
7332 asc_dequeue_list(asc_queue_t *ascq, REQP *lastpp, int tid)
7337 ASC_DBG2(3, "asc_dequeue_list: ascq 0x%lx, tid %d\n", (ulong) ascq, tid);
7338 ASC_ASSERT((tid == ASC_TID_ALL) || (tid >= 0 && tid <= ADV_MAX_TID));
7341 * If 'tid' is not ASC_TID_ALL, return requests only for
7342 * the specified 'tid'. If 'tid' is ASC_TID_ALL, return all
7343 * requests for all tids.
7345 if (tid != ASC_TID_ALL) {
7346 /* Return all requests for the specified 'tid'. */
7347 if ((ascq->q_tidmask & ADV_TID_TO_TIDMASK(tid)) == 0) {
7348 /* List is empty; Set first and last return pointers to NULL. */
7349 firstp = lastp = NULL;
7351 firstp = ascq->q_first[tid];
7352 lastp = ascq->q_last[tid];
7353 ascq->q_first[tid] = ascq->q_last[tid] = NULL;
7354 ascq->q_tidmask &= ~ADV_TID_TO_TIDMASK(tid);
7355 #ifdef ADVANSYS_STATS
7358 ascq->q_cur_cnt[tid] = 0;
7359 for (reqp = firstp; reqp; reqp = REQPNEXT(reqp)) {
7360 REQTIMESTAT("asc_dequeue_list", ascq, reqp, tid);
7363 #endif /* ADVANSYS_STATS */
7366 /* Return all requests for all tids. */
7367 firstp = lastp = NULL;
7368 for (i = 0; i <= ADV_MAX_TID; i++) {
7369 if (ascq->q_tidmask & ADV_TID_TO_TIDMASK(i)) {
7370 if (firstp == NULL) {
7371 firstp = ascq->q_first[i];
7372 lastp = ascq->q_last[i];
7374 ASC_ASSERT(lastp != NULL);
7375 lastp->host_scribble = (unsigned char *)ascq->q_first[i];
7376 lastp = ascq->q_last[i];
7378 ascq->q_first[i] = ascq->q_last[i] = NULL;
7379 ascq->q_tidmask &= ~ADV_TID_TO_TIDMASK(i);
7380 #ifdef ADVANSYS_STATS
7381 ascq->q_cur_cnt[i] = 0;
7382 #endif /* ADVANSYS_STATS */
7385 #ifdef ADVANSYS_STATS
7388 for (reqp = firstp; reqp; reqp = REQPNEXT(reqp)) {
7389 REQTIMESTAT("asc_dequeue_list", ascq, reqp, reqp->device->id);
7392 #endif /* ADVANSYS_STATS */
7397 ASC_DBG1(3, "asc_dequeue_list: firstp 0x%lx\n", (ulong) firstp);
7402 * Remove the specified 'REQP' from the specified queue for
7403 * the specified target device. Clear the 'tidmask' bit for the
7404 * device if no more commands are left queued for it.
7406 * 'REQPNEXT(reqp)' returns reqp's the next pointer.
7408 * Return ASC_TRUE if the command was found and removed,
7409 * otherwise return ASC_FALSE.
7412 asc_rmqueue(asc_queue_t *ascq, REQP reqp)
7416 int ret = ASC_FALSE;
7418 ASC_DBG2(3, "asc_rmqueue: ascq 0x%lx, reqp 0x%lx\n",
7419 (ulong) ascq, (ulong) reqp);
7420 ASC_ASSERT(reqp != NULL);
7422 tid = REQPTID(reqp);
7423 ASC_ASSERT(tid >= 0 && tid <= ADV_MAX_TID);
7426 * Handle the common case of 'reqp' being the first
7427 * entry on the queue.
7429 if (reqp == ascq->q_first[tid]) {
7431 ascq->q_first[tid] = REQPNEXT(reqp);
7432 /* If the queue is now empty, clear its bit and the last pointer. */
7433 if (ascq->q_first[tid] == NULL) {
7434 ascq->q_tidmask &= ~ADV_TID_TO_TIDMASK(tid);
7435 ASC_ASSERT(ascq->q_last[tid] == reqp);
7436 ascq->q_last[tid] = NULL;
7438 } else if (ascq->q_first[tid] != NULL) {
7439 ASC_ASSERT(ascq->q_last[tid] != NULL);
7441 * Because the case of 'reqp' being the first entry has been
7442 * handled above and it is known the queue is not empty, if
7443 * 'reqp' is found on the queue it is guaranteed the queue will
7444 * not become empty and that 'q_first[tid]' will not be changed.
7446 * Set 'prevp' to the first entry, 'currp' to the second entry,
7447 * and search for 'reqp'.
7449 for (prevp = ascq->q_first[tid], currp = REQPNEXT(prevp);
7450 currp; prevp = currp, currp = REQPNEXT(currp)) {
7451 if (currp == reqp) {
7453 prevp->host_scribble = (unsigned char *)REQPNEXT(currp);
7454 reqp->host_scribble = NULL;
7455 if (ascq->q_last[tid] == reqp) {
7456 ascq->q_last[tid] = prevp;
7462 #ifdef ADVANSYS_STATS
7463 /* Maintain request queue statistics. */
7464 if (ret == ASC_TRUE) {
7465 ascq->q_cur_cnt[tid]--;
7466 REQTIMESTAT("asc_rmqueue", ascq, reqp, tid);
7468 ASC_ASSERT(ascq->q_cur_cnt[tid] >= 0);
7469 #endif /* ADVANSYS_STATS */
7470 ASC_DBG2(3, "asc_rmqueue: reqp 0x%lx, ret %d\n", (ulong) reqp, ret);
7475 * Execute as many queued requests as possible for the specified queue.
7477 * Calls asc_execute_scsi_cmnd() to execute a REQP/struct scsi_cmnd.
7480 asc_execute_queue(asc_queue_t *ascq)
7482 ADV_SCSI_BIT_ID_TYPE scan_tidmask;
7486 ASC_DBG1(1, "asc_execute_queue: ascq 0x%lx\n", (ulong) ascq);
7488 * Execute queued commands for devices attached to
7489 * the current board in round-robin fashion.
7491 scan_tidmask = ascq->q_tidmask;
7493 for (i = 0; i <= ADV_MAX_TID; i++) {
7494 if (scan_tidmask & ADV_TID_TO_TIDMASK(i)) {
7495 if ((reqp = asc_dequeue(ascq, i)) == NULL) {
7496 scan_tidmask &= ~ADV_TID_TO_TIDMASK(i);
7497 } else if (asc_execute_scsi_cmnd((struct scsi_cmnd *) reqp)
7499 scan_tidmask &= ~ADV_TID_TO_TIDMASK(i);
7501 * The request returned ASC_BUSY. Enqueue at the front of
7502 * target's waiting list to maintain correct ordering.
7504 asc_enqueue(ascq, reqp, ASC_FRONT);
7508 } while (scan_tidmask);
7512 #ifdef CONFIG_PROC_FS
7514 * asc_prt_board_devices()
7516 * Print driver information for devices attached to the board.
7518 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
7519 * cf. asc_prt_line().
7521 * Return the number of characters copied into 'cp'. No more than
7522 * 'cplen' characters will be copied to 'cp'.
7525 asc_prt_board_devices(struct Scsi_Host *shp, char *cp, int cplen)
7527 asc_board_t *boardp;
7534 boardp = ASC_BOARDP(shp);
7538 len = asc_prt_line(cp, leftlen,
7539 "\nDevice Information for AdvanSys SCSI Host %d:\n", shp->host_no);
7542 if (ASC_NARROW_BOARD(boardp)) {
7543 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
7545 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
7548 len = asc_prt_line(cp, leftlen, "Target IDs Detected:");
7550 for (i = 0; i <= ADV_MAX_TID; i++) {
7551 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) {
7552 len = asc_prt_line(cp, leftlen, " %X,", i);
7556 len = asc_prt_line(cp, leftlen, " (%X=Host Adapter)\n", chip_scsi_id);
7563 * Display Wide Board BIOS Information.
7566 asc_prt_adv_bios(struct Scsi_Host *shp, char *cp, int cplen)
7568 asc_board_t *boardp;
7572 ushort major, minor, letter;
7574 boardp = ASC_BOARDP(shp);
7578 len = asc_prt_line(cp, leftlen, "\nROM BIOS Version: ");
7582 * If the BIOS saved a valid signature, then fill in
7583 * the BIOS code segment base address.
7585 if (boardp->bios_signature != 0x55AA) {
7586 len = asc_prt_line(cp, leftlen, "Disabled or Pre-3.1\n");
7588 len = asc_prt_line(cp, leftlen,
7589 "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n");
7591 len = asc_prt_line(cp, leftlen,
7592 "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
7595 major = (boardp->bios_version >> 12) & 0xF;
7596 minor = (boardp->bios_version >> 8) & 0xF;
7597 letter = (boardp->bios_version & 0xFF);
7599 len = asc_prt_line(cp, leftlen, "%d.%d%c\n",
7600 major, minor, letter >= 26 ? '?' : letter + 'A');
7604 * Current available ROM BIOS release is 3.1I for UW
7605 * and 3.2I for U2W. This code doesn't differentiate
7606 * UW and U2W boards.
7608 if (major < 3 || (major <= 3 && minor < 1) ||
7609 (major <= 3 && minor <= 1 && letter < ('I'- 'A'))) {
7610 len = asc_prt_line(cp, leftlen,
7611 "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n");
7613 len = asc_prt_line(cp, leftlen,
7614 "ftp://ftp.connectcom.net/pub\n");
7623 * Add serial number to information bar if signature AAh
7624 * is found in at bit 15-9 (7 bits) of word 1.
7626 * Serial Number consists fo 12 alpha-numeric digits.
7628 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits)
7629 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits)
7630 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits)
7631 * 5 - Product revision (A-J) Word0: " "
7633 * Signature Word1: 15-9 (7 bits)
7634 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
7635 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits)
7637 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
7639 * Note 1: Only production cards will have a serial number.
7641 * Note 2: Signature is most significant 7 bits (0xFE).
7643 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
7646 asc_get_eeprom_string(ushort *serialnum, uchar *cp)
7650 if ((serialnum[1] & 0xFE00) != ((ushort) 0xAA << 8)) {
7654 * First word - 6 digits.
7658 /* Product type - 1st digit. */
7659 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
7660 /* Product type is P=Prototype */
7665 /* Manufacturing location - 2nd digit. */
7666 *cp++ = 'A' + ((w & 0x1C00) >> 10);
7668 /* Product ID - 3rd, 4th digits. */
7670 *cp++ = '0' + (num / 100);
7672 *cp++ = '0' + (num / 10);
7674 /* Product revision - 5th digit. */
7675 *cp++ = 'A' + (num % 10);
7685 * If bit 15 of third word is set, then the
7686 * last digit of the year is greater than 7.
7688 if (serialnum[2] & 0x8000) {
7689 *cp++ = '8' + ((w & 0x1C0) >> 6);
7691 *cp++ = '0' + ((w & 0x1C0) >> 6);
7694 /* Week of year - 7th, 8th digits. */
7696 *cp++ = '0' + num / 10;
7703 w = serialnum[2] & 0x7FFF;
7705 /* Serial number - 9th digit. */
7706 *cp++ = 'A' + (w / 1000);
7708 /* 10th, 11th, 12th digits. */
7710 *cp++ = '0' + num / 100;
7712 *cp++ = '0' + num / 10;
7716 *cp = '\0'; /* Null Terminate the string. */
7722 * asc_prt_asc_board_eeprom()
7724 * Print board EEPROM configuration.
7726 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
7727 * cf. asc_prt_line().
7729 * Return the number of characters copied into 'cp'. No more than
7730 * 'cplen' characters will be copied to 'cp'.
7733 asc_prt_asc_board_eeprom(struct Scsi_Host *shp, char *cp, int cplen)
7735 asc_board_t *boardp;
7736 ASC_DVC_VAR *asc_dvc_varp;
7743 int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
7744 #endif /* CONFIG_ISA */
7745 uchar serialstr[13];
7747 boardp = ASC_BOARDP(shp);
7748 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
7749 ep = &boardp->eep_config.asc_eep;
7754 len = asc_prt_line(cp, leftlen,
7755 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n", shp->host_no);
7758 if (asc_get_eeprom_string((ushort *) &ep->adapter_info[0], serialstr) ==
7760 len = asc_prt_line(cp, leftlen, " Serial Number: %s\n", serialstr);
7763 if (ep->adapter_info[5] == 0xBB) {
7764 len = asc_prt_line(cp, leftlen,
7765 " Default Settings Used for EEPROM-less Adapter.\n");
7768 len = asc_prt_line(cp, leftlen,
7769 " Serial Number Signature Not Present.\n");
7774 len = asc_prt_line(cp, leftlen,
7775 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
7776 ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng, ep->max_tag_qng);
7779 len = asc_prt_line(cp, leftlen,
7780 " cntl 0x%x, no_scam 0x%x\n",
7781 ep->cntl, ep->no_scam);
7784 len = asc_prt_line(cp, leftlen,
7787 for (i = 0; i <= ASC_MAX_TID; i++) {
7788 len = asc_prt_line(cp, leftlen, " %d", i);
7791 len = asc_prt_line(cp, leftlen, "\n");
7794 len = asc_prt_line(cp, leftlen,
7797 for (i = 0; i <= ASC_MAX_TID; i++) {
7798 len = asc_prt_line(cp, leftlen, " %c",
7799 (ep->disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
7802 len = asc_prt_line(cp, leftlen, "\n");
7805 len = asc_prt_line(cp, leftlen,
7806 " Command Queuing: ");
7808 for (i = 0; i <= ASC_MAX_TID; i++) {
7809 len = asc_prt_line(cp, leftlen, " %c",
7810 (ep->use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
7813 len = asc_prt_line(cp, leftlen, "\n");
7816 len = asc_prt_line(cp, leftlen,
7819 for (i = 0; i <= ASC_MAX_TID; i++) {
7820 len = asc_prt_line(cp, leftlen, " %c",
7821 (ep->start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
7824 len = asc_prt_line(cp, leftlen, "\n");
7827 len = asc_prt_line(cp, leftlen,
7828 " Synchronous Transfer:");
7830 for (i = 0; i <= ASC_MAX_TID; i++) {
7831 len = asc_prt_line(cp, leftlen, " %c",
7832 (ep->init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
7835 len = asc_prt_line(cp, leftlen, "\n");
7839 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
7840 len = asc_prt_line(cp, leftlen,
7841 " Host ISA DMA speed: %d MB/S\n",
7842 isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
7845 #endif /* CONFIG_ISA */
7851 * asc_prt_adv_board_eeprom()
7853 * Print board EEPROM configuration.
7855 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
7856 * cf. asc_prt_line().
7858 * Return the number of characters copied into 'cp'. No more than
7859 * 'cplen' characters will be copied to 'cp'.
7862 asc_prt_adv_board_eeprom(struct Scsi_Host *shp, char *cp, int cplen)
7864 asc_board_t *boardp;
7865 ADV_DVC_VAR *adv_dvc_varp;
7871 uchar serialstr[13];
7872 ADVEEP_3550_CONFIG *ep_3550 = NULL;
7873 ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
7874 ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
7877 ushort sdtr_speed = 0;
7879 boardp = ASC_BOARDP(shp);
7880 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
7881 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
7883 ep_3550 = &boardp->eep_config.adv_3550_eep;
7884 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
7886 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
7889 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
7895 len = asc_prt_line(cp, leftlen,
7896 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n", shp->host_no);
7899 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
7901 wordp = &ep_3550->serial_number_word1;
7902 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
7904 wordp = &ep_38C0800->serial_number_word1;
7907 wordp = &ep_38C1600->serial_number_word1;
7910 if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE) {
7911 len = asc_prt_line(cp, leftlen, " Serial Number: %s\n", serialstr);
7914 len = asc_prt_line(cp, leftlen,
7915 " Serial Number Signature Not Present.\n");
7919 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
7921 len = asc_prt_line(cp, leftlen,
7922 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
7923 ep_3550->adapter_scsi_id, ep_3550->max_host_qng,
7924 ep_3550->max_dvc_qng);
7926 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
7928 len = asc_prt_line(cp, leftlen,
7929 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
7930 ep_38C0800->adapter_scsi_id, ep_38C0800->max_host_qng,
7931 ep_38C0800->max_dvc_qng);
7935 len = asc_prt_line(cp, leftlen,
7936 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
7937 ep_38C1600->adapter_scsi_id, ep_38C1600->max_host_qng,
7938 ep_38C1600->max_dvc_qng);
7941 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
7943 word = ep_3550->termination;
7944 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
7946 word = ep_38C0800->termination_lvd;
7949 word = ep_38C1600->termination_lvd;
7953 termstr = "Low Off/High Off";
7956 termstr = "Low Off/High On";
7959 termstr = "Low On/High On";
7963 termstr = "Automatic";
7967 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
7969 len = asc_prt_line(cp, leftlen,
7970 " termination: %u (%s), bios_ctrl: 0x%x\n",
7971 ep_3550->termination, termstr, ep_3550->bios_ctrl);
7973 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
7975 len = asc_prt_line(cp, leftlen,
7976 " termination: %u (%s), bios_ctrl: 0x%x\n",
7977 ep_38C0800->termination_lvd, termstr, ep_38C0800->bios_ctrl);
7981 len = asc_prt_line(cp, leftlen,
7982 " termination: %u (%s), bios_ctrl: 0x%x\n",
7983 ep_38C1600->termination_lvd, termstr, ep_38C1600->bios_ctrl);
7987 len = asc_prt_line(cp, leftlen,
7990 for (i = 0; i <= ADV_MAX_TID; i++) {
7991 len = asc_prt_line(cp, leftlen, " %X", i);
7994 len = asc_prt_line(cp, leftlen, "\n");
7997 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
7999 word = ep_3550->disc_enable;
8000 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
8002 word = ep_38C0800->disc_enable;
8005 word = ep_38C1600->disc_enable;
8007 len = asc_prt_line(cp, leftlen,
8010 for (i = 0; i <= ADV_MAX_TID; i++) {
8011 len = asc_prt_line(cp, leftlen, " %c",
8012 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8015 len = asc_prt_line(cp, leftlen, "\n");
8018 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
8020 word = ep_3550->tagqng_able;
8021 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
8023 word = ep_38C0800->tagqng_able;
8026 word = ep_38C1600->tagqng_able;
8028 len = asc_prt_line(cp, leftlen,
8029 " Command Queuing: ");
8031 for (i = 0; i <= ADV_MAX_TID; i++) {
8032 len = asc_prt_line(cp, leftlen, " %c",
8033 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8036 len = asc_prt_line(cp, leftlen, "\n");
8039 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
8041 word = ep_3550->start_motor;
8042 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
8044 word = ep_38C0800->start_motor;
8047 word = ep_38C1600->start_motor;
8049 len = asc_prt_line(cp, leftlen,
8052 for (i = 0; i <= ADV_MAX_TID; i++) {
8053 len = asc_prt_line(cp, leftlen, " %c",
8054 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8057 len = asc_prt_line(cp, leftlen, "\n");
8060 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
8062 len = asc_prt_line(cp, leftlen,
8063 " Synchronous Transfer:");
8065 for (i = 0; i <= ADV_MAX_TID; i++) {
8066 len = asc_prt_line(cp, leftlen, " %c",
8067 (ep_3550->sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8070 len = asc_prt_line(cp, leftlen, "\n");
8074 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
8076 len = asc_prt_line(cp, leftlen,
8077 " Ultra Transfer: ");
8079 for (i = 0; i <= ADV_MAX_TID; i++) {
8080 len = asc_prt_line(cp, leftlen, " %c",
8081 (ep_3550->ultra_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8084 len = asc_prt_line(cp, leftlen, "\n");
8088 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
8090 word = ep_3550->wdtr_able;
8091 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
8093 word = ep_38C0800->wdtr_able;
8096 word = ep_38C1600->wdtr_able;
8098 len = asc_prt_line(cp, leftlen,
8099 " Wide Transfer: ");
8101 for (i = 0; i <= ADV_MAX_TID; i++) {
8102 len = asc_prt_line(cp, leftlen, " %c",
8103 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8106 len = asc_prt_line(cp, leftlen, "\n");
8109 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
8110 adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600)
8112 len = asc_prt_line(cp, leftlen,
8113 " Synchronous Transfer Speed (Mhz):\n ");
8115 for (i = 0; i <= ADV_MAX_TID; i++) {
8120 sdtr_speed = adv_dvc_varp->sdtr_speed1;
8123 sdtr_speed = adv_dvc_varp->sdtr_speed2;
8126 sdtr_speed = adv_dvc_varp->sdtr_speed3;
8129 sdtr_speed = adv_dvc_varp->sdtr_speed4;
8131 switch (sdtr_speed & ADV_MAX_TID)
8133 case 0: speed_str = "Off"; break;
8134 case 1: speed_str = " 5"; break;
8135 case 2: speed_str = " 10"; break;
8136 case 3: speed_str = " 20"; break;
8137 case 4: speed_str = " 40"; break;
8138 case 5: speed_str = " 80"; break;
8139 default: speed_str = "Unk"; break;
8141 len = asc_prt_line(cp, leftlen, "%X:%s ", i, speed_str);
8145 len = asc_prt_line(cp, leftlen, "\n ");
8150 len = asc_prt_line(cp, leftlen, "\n");
8158 * asc_prt_driver_conf()
8160 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
8161 * cf. asc_prt_line().
8163 * Return the number of characters copied into 'cp'. No more than
8164 * 'cplen' characters will be copied to 'cp'.
8167 asc_prt_driver_conf(struct Scsi_Host *shp, char *cp, int cplen)
8169 asc_board_t *boardp;
8175 boardp = ASC_BOARDP(shp);
8180 len = asc_prt_line(cp, leftlen,
8181 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
8185 len = asc_prt_line(cp, leftlen,
8186 " host_busy %u, last_reset %u, max_id %u, max_lun %u, max_channel %u\n",
8187 shp->host_busy, shp->last_reset, shp->max_id, shp->max_lun,
8191 len = asc_prt_line(cp, leftlen,
8192 " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
8193 shp->unique_id, shp->can_queue, shp->this_id, shp->sg_tablesize,
8197 len = asc_prt_line(cp, leftlen,
8198 " unchecked_isa_dma %d, use_clustering %d\n",
8199 shp->unchecked_isa_dma, shp->use_clustering);
8202 len = asc_prt_line(cp, leftlen,
8203 " flags 0x%x, last_reset 0x%x, jiffies 0x%x, asc_n_io_port 0x%x\n",
8204 boardp->flags, boardp->last_reset, jiffies, boardp->asc_n_io_port);
8207 /* 'shp->n_io_port' may be truncated because it is only one byte. */
8208 len = asc_prt_line(cp, leftlen,
8209 " io_port 0x%x, n_io_port 0x%x\n",
8210 shp->io_port, shp->n_io_port);
8213 if (ASC_NARROW_BOARD(boardp)) {
8214 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
8216 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
8223 * asc_prt_asc_board_info()
8225 * Print dynamic board configuration information.
8227 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
8228 * cf. asc_prt_line().
8230 * Return the number of characters copied into 'cp'. No more than
8231 * 'cplen' characters will be copied to 'cp'.
8234 asc_prt_asc_board_info(struct Scsi_Host *shp, char *cp, int cplen)
8236 asc_board_t *boardp;
8244 int renegotiate = 0;
8246 boardp = ASC_BOARDP(shp);
8247 v = &boardp->dvc_var.asc_dvc_var;
8248 c = &boardp->dvc_cfg.asc_dvc_cfg;
8249 chip_scsi_id = c->chip_scsi_id;
8254 len = asc_prt_line(cp, leftlen,
8255 "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
8259 len = asc_prt_line(cp, leftlen,
8260 " chip_version %u, lib_version 0x%x, lib_serial_no %u, mcode_date 0x%x\n",
8261 c->chip_version, c->lib_version, c->lib_serial_no, c->mcode_date);
8264 len = asc_prt_line(cp, leftlen,
8265 " mcode_version 0x%x, err_code %u\n",
8266 c->mcode_version, v->err_code);
8269 /* Current number of commands waiting for the host. */
8270 len = asc_prt_line(cp, leftlen,
8271 " Total Command Pending: %d\n", v->cur_total_qng);
8274 len = asc_prt_line(cp, leftlen,
8275 " Command Queuing:");
8277 for (i = 0; i <= ASC_MAX_TID; i++) {
8278 if ((chip_scsi_id == i) ||
8279 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8282 len = asc_prt_line(cp, leftlen, " %X:%c",
8283 i, (v->use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8286 len = asc_prt_line(cp, leftlen, "\n");
8289 /* Current number of commands waiting for a device. */
8290 len = asc_prt_line(cp, leftlen,
8291 " Command Queue Pending:");
8293 for (i = 0; i <= ASC_MAX_TID; i++) {
8294 if ((chip_scsi_id == i) ||
8295 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8298 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->cur_dvc_qng[i]);
8301 len = asc_prt_line(cp, leftlen, "\n");
8304 /* Current limit on number of commands that can be sent to a device. */
8305 len = asc_prt_line(cp, leftlen,
8306 " Command Queue Limit:");
8308 for (i = 0; i <= ASC_MAX_TID; i++) {
8309 if ((chip_scsi_id == i) ||
8310 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8313 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->max_dvc_qng[i]);
8316 len = asc_prt_line(cp, leftlen, "\n");
8319 /* Indicate whether the device has returned queue full status. */
8320 len = asc_prt_line(cp, leftlen,
8321 " Command Queue Full:");
8323 for (i = 0; i <= ASC_MAX_TID; i++) {
8324 if ((chip_scsi_id == i) ||
8325 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8328 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i)) {
8329 len = asc_prt_line(cp, leftlen, " %X:Y-%d",
8330 i, boardp->queue_full_cnt[i]);
8332 len = asc_prt_line(cp, leftlen, " %X:N", i);
8336 len = asc_prt_line(cp, leftlen, "\n");
8339 len = asc_prt_line(cp, leftlen,
8340 " Synchronous Transfer:");
8342 for (i = 0; i <= ASC_MAX_TID; i++) {
8343 if ((chip_scsi_id == i) ||
8344 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8347 len = asc_prt_line(cp, leftlen, " %X:%c",
8348 i, (v->sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8351 len = asc_prt_line(cp, leftlen, "\n");
8354 for (i = 0; i <= ASC_MAX_TID; i++) {
8355 uchar syn_period_ix;
8357 if ((chip_scsi_id == i) ||
8358 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
8359 ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
8363 len = asc_prt_line(cp, leftlen, " %X:", i);
8366 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0)
8368 len = asc_prt_line(cp, leftlen, " Asynchronous");
8373 (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index - 1);
8375 len = asc_prt_line(cp, leftlen,
8376 " Transfer Period Factor: %d (%d.%d Mhz),",
8377 v->sdtr_period_tbl[syn_period_ix],
8378 250 / v->sdtr_period_tbl[syn_period_ix],
8379 ASC_TENTHS(250, v->sdtr_period_tbl[syn_period_ix]));
8382 len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
8383 boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET);
8387 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
8388 len = asc_prt_line(cp, leftlen, "*\n");
8392 len = asc_prt_line(cp, leftlen, "\n");
8399 len = asc_prt_line(cp, leftlen,
8400 " * = Re-negotiation pending before next command.\n");
8408 * asc_prt_adv_board_info()
8410 * Print dynamic board configuration information.
8412 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
8413 * cf. asc_prt_line().
8415 * Return the number of characters copied into 'cp'. No more than
8416 * 'cplen' characters will be copied to 'cp'.
8419 asc_prt_adv_board_info(struct Scsi_Host *shp, char *cp, int cplen)
8421 asc_board_t *boardp;
8428 AdvPortAddr iop_base;
8429 ushort chip_scsi_id;
8433 ushort sdtr_able, wdtr_able;
8434 ushort wdtr_done, sdtr_done;
8436 int renegotiate = 0;
8438 boardp = ASC_BOARDP(shp);
8439 v = &boardp->dvc_var.adv_dvc_var;
8440 c = &boardp->dvc_cfg.adv_dvc_cfg;
8441 iop_base = v->iop_base;
8442 chip_scsi_id = v->chip_scsi_id;
8447 len = asc_prt_line(cp, leftlen,
8448 "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
8452 len = asc_prt_line(cp, leftlen,
8453 " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
8455 AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1) & CABLE_DETECT,
8459 len = asc_prt_line(cp, leftlen,
8460 " chip_version %u, lib_version 0x%x, mcode_date 0x%x, mcode_version 0x%x\n",
8461 c->chip_version, c->lib_version, c->mcode_date, c->mcode_version);
8464 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
8465 len = asc_prt_line(cp, leftlen,
8466 " Queuing Enabled:");
8468 for (i = 0; i <= ADV_MAX_TID; i++) {
8469 if ((chip_scsi_id == i) ||
8470 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8474 len = asc_prt_line(cp, leftlen, " %X:%c",
8475 i, (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8478 len = asc_prt_line(cp, leftlen, "\n");
8481 len = asc_prt_line(cp, leftlen,
8484 for (i = 0; i <= ADV_MAX_TID; i++) {
8485 if ((chip_scsi_id == i) ||
8486 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8490 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i, lrambyte);
8492 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
8495 len = asc_prt_line(cp, leftlen, "\n");
8498 len = asc_prt_line(cp, leftlen,
8499 " Command Pending:");
8501 for (i = 0; i <= ADV_MAX_TID; i++) {
8502 if ((chip_scsi_id == i) ||
8503 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8507 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i, lrambyte);
8509 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte);
8512 len = asc_prt_line(cp, leftlen, "\n");
8515 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
8516 len = asc_prt_line(cp, leftlen,
8519 for (i = 0; i <= ADV_MAX_TID; i++) {
8520 if ((chip_scsi_id == i) ||
8521 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8525 len = asc_prt_line(cp, leftlen, " %X:%c",
8526 i, (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8529 len = asc_prt_line(cp, leftlen, "\n");
8532 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
8533 len = asc_prt_line(cp, leftlen,
8534 " Transfer Bit Width:");
8536 for (i = 0; i <= ADV_MAX_TID; i++) {
8537 if ((chip_scsi_id == i) ||
8538 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8542 AdvReadWordLram(iop_base, ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
8545 len = asc_prt_line(cp, leftlen, " %X:%d",
8546 i, (lramword & 0x8000) ? 16 : 8);
8549 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
8550 (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
8551 len = asc_prt_line(cp, leftlen, "*");
8556 len = asc_prt_line(cp, leftlen, "\n");
8559 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
8560 len = asc_prt_line(cp, leftlen,
8561 " Synchronous Enabled:");
8563 for (i = 0; i <= ADV_MAX_TID; i++) {
8564 if ((chip_scsi_id == i) ||
8565 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
8569 len = asc_prt_line(cp, leftlen, " %X:%c",
8570 i, (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
8573 len = asc_prt_line(cp, leftlen, "\n");
8576 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
8577 for (i = 0; i <= ADV_MAX_TID; i++) {
8579 AdvReadWordLram(iop_base, ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
8581 lramword &= ~0x8000;
8583 if ((chip_scsi_id == i) ||
8584 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
8585 ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
8589 len = asc_prt_line(cp, leftlen, " %X:", i);
8592 if ((lramword & 0x1F) == 0) /* Check for REQ/ACK Offset 0. */
8594 len = asc_prt_line(cp, leftlen, " Asynchronous");
8598 len = asc_prt_line(cp, leftlen, " Transfer Period Factor: ");
8601 if ((lramword & 0x1F00) == 0x1100) /* 80 Mhz */
8603 len = asc_prt_line(cp, leftlen, "9 (80.0 Mhz),");
8605 } else if ((lramword & 0x1F00) == 0x1000) /* 40 Mhz */
8607 len = asc_prt_line(cp, leftlen, "10 (40.0 Mhz),");
8609 } else /* 20 Mhz or below. */
8611 period = (((lramword >> 8) * 25) + 50)/4;
8613 if (period == 0) /* Should never happen. */
8615 len = asc_prt_line(cp, leftlen, "%d (? Mhz), ");
8619 len = asc_prt_line(cp, leftlen,
8621 period, 250/period, ASC_TENTHS(250, period));
8626 len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d",
8631 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
8632 len = asc_prt_line(cp, leftlen, "*\n");
8636 len = asc_prt_line(cp, leftlen, "\n");
8643 len = asc_prt_line(cp, leftlen,
8644 " * = Re-negotiation pending before next command.\n");
8654 * Copy proc information to a read buffer taking into account the current
8655 * read offset in the file and the remaining space in the read buffer.
8658 asc_proc_copy(off_t advoffset, off_t offset, char *curbuf, int leftlen,
8659 char *cp, int cplen)
8663 ASC_DBG3(2, "asc_proc_copy: offset %d, advoffset %d, cplen %d\n",
8664 (unsigned) offset, (unsigned) advoffset, cplen);
8665 if (offset <= advoffset) {
8666 /* Read offset below current offset, copy everything. */
8667 cnt = min(cplen, leftlen);
8668 ASC_DBG3(2, "asc_proc_copy: curbuf 0x%lx, cp 0x%lx, cnt %d\n",
8669 (ulong) curbuf, (ulong) cp, cnt);
8670 memcpy(curbuf, cp, cnt);
8671 } else if (offset < advoffset + cplen) {
8672 /* Read offset within current range, partial copy. */
8673 cnt = (advoffset + cplen) - offset;
8674 cp = (cp + cplen) - cnt;
8675 cnt = min(cnt, leftlen);
8676 ASC_DBG3(2, "asc_proc_copy: curbuf 0x%lx, cp 0x%lx, cnt %d\n",
8677 (ulong) curbuf, (ulong) cp, cnt);
8678 memcpy(curbuf, cp, cnt);
8686 * If 'cp' is NULL print to the console, otherwise print to a buffer.
8688 * Return 0 if printing to the console, otherwise return the number of
8689 * bytes written to the buffer.
8691 * Note: If any single line is greater than ASC_PRTLINE_SIZE bytes the stack
8692 * will be corrupted. 's[]' is defined to be ASC_PRTLINE_SIZE bytes.
8695 asc_prt_line(char *buf, int buflen, char *fmt, ...)
8699 char s[ASC_PRTLINE_SIZE];
8701 va_start(args, fmt);
8702 ret = vsprintf(s, fmt, args);
8703 ASC_ASSERT(ret < ASC_PRTLINE_SIZE);
8708 ret = min(buflen, ret);
8709 memcpy(buf, s, ret);
8714 #endif /* CONFIG_PROC_FS */
8718 * --- Functions Required by the Asc Library
8722 * Delay for 'n' milliseconds. Don't use the 'jiffies'
8723 * global variable which is incremented once every 5 ms
8724 * from a timer interrupt, because this function may be
8725 * called when interrupts are disabled.
8728 DvcSleepMilliSecond(ADV_DCNT n)
8730 ASC_DBG1(4, "DvcSleepMilliSecond: %lu\n", (ulong) n);
8735 * Currently and inline noop but leave as a placeholder.
8736 * Leave DvcEnterCritical() as a noop placeholder.
8739 DvcEnterCritical(void)
8745 * Critical sections are all protected by the board spinlock.
8746 * Leave DvcLeaveCritical() as a noop placeholder.
8749 DvcLeaveCritical(ulong flags)
8756 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8758 * Calling/Exit State:
8762 * Output an ASC_SCSI_Q structure to the chip
8765 DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8769 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
8770 AscSetChipLramAddr(iop_base, s_addr);
8771 for (i = 0; i < 2 * words; i += 2) {
8772 if (i == 4 || i == 20) {
8775 outpw(iop_base + IOP_RAM_DATA,
8776 ((ushort) outbuf[i + 1] << 8) | outbuf[i]);
8782 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
8784 * Calling/Exit State:
8788 * Input an ASC_QDONE_INFO structure from the chip
8791 DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
8796 AscSetChipLramAddr(iop_base, s_addr);
8797 for (i = 0; i < 2 * words; i += 2) {
8801 word = inpw(iop_base + IOP_RAM_DATA);
8802 inbuf[i] = word & 0xff;
8803 inbuf[i + 1] = (word >> 8) & 0xff;
8805 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
8809 * Read a PCI configuration byte.
8812 DvcReadPCIConfigByte(
8813 ASC_DVC_VAR *asc_dvc,
8818 pci_read_config_byte(to_pci_dev(asc_dvc->cfg->dev), offset, &byte_data);
8820 #else /* !defined(CONFIG_PCI) */
8822 #endif /* !defined(CONFIG_PCI) */
8826 * Write a PCI configuration byte.
8829 DvcWritePCIConfigByte(
8830 ASC_DVC_VAR *asc_dvc,
8835 pci_write_config_byte(to_pci_dev(asc_dvc->cfg->dev), offset, byte_data);
8836 #endif /* CONFIG_PCI */
8840 * Return the BIOS address of the adapter at the specified
8841 * I/O port and with the specified bus type.
8843 STATIC ushort __init
8844 AscGetChipBiosAddress(
8852 * The PCI BIOS is re-located by the motherboard BIOS. Because
8853 * of this the driver can not determine where a PCI BIOS is
8854 * loaded and executes.
8856 if (bus_type & ASC_IS_PCI)
8862 if((bus_type & ASC_IS_EISA) != 0)
8864 cfg_lsw = AscGetEisaChipCfg(iop_base);
8866 bios_addr = (ushort)(ASC_BIOS_MIN_ADDR +
8867 (cfg_lsw * ASC_BIOS_BANK_SIZE));
8870 #endif /* CONFIG_ISA */
8872 cfg_lsw = AscGetChipCfgLsw(iop_base);
8875 * ISA PnP uses the top bit as the 32K BIOS flag
8877 if (bus_type == ASC_IS_ISAPNP)
8882 bios_addr = (ushort)(((cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE) +
8889 * --- Functions Required by the Adv Library
8895 * Return the physical address of 'vaddr' and set '*lenp' to the
8896 * number of physically contiguous bytes that follow 'vaddr'.
8897 * 'flag' indicates the type of structure whose physical address
8898 * is being translated.
8900 * Note: Because Linux currently doesn't page the kernel and all
8901 * kernel buffers are physically contiguous, leave '*lenp' unchanged.
8904 DvcGetPhyAddr(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq,
8905 uchar *vaddr, ADV_SDCNT *lenp, int flag)
8909 paddr = virt_to_bus(vaddr);
8912 "DvcGetPhyAddr: vaddr 0x%lx, lenp 0x%lx *lenp %lu, paddr 0x%lx\n",
8913 (ulong) vaddr, (ulong) lenp, (ulong) *((ulong *) lenp), (ulong) paddr);
8919 * Read a PCI configuration byte.
8922 DvcAdvReadPCIConfigByte(
8923 ADV_DVC_VAR *asc_dvc,
8928 pci_read_config_byte(to_pci_dev(asc_dvc->cfg->dev), offset, &byte_data);
8930 #else /* CONFIG_PCI */
8932 #endif /* CONFIG_PCI */
8936 * Write a PCI configuration byte.
8939 DvcAdvWritePCIConfigByte(
8940 ADV_DVC_VAR *asc_dvc,
8945 pci_write_config_byte(to_pci_dev(asc_dvc->cfg->dev), offset, byte_data);
8946 #else /* CONFIG_PCI */
8948 #endif /* CONFIG_PCI */
8952 * --- Tracing and Debugging Functions
8955 #ifdef ADVANSYS_STATS
8956 #ifdef CONFIG_PROC_FS
8958 * asc_prt_board_stats()
8960 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
8961 * cf. asc_prt_line().
8963 * Return the number of characters copied into 'cp'. No more than
8964 * 'cplen' characters will be copied to 'cp'.
8967 asc_prt_board_stats(struct Scsi_Host *shp, char *cp, int cplen)
8972 struct asc_stats *s;
8973 asc_board_t *boardp;
8978 boardp = ASC_BOARDP(shp);
8979 s = &boardp->asc_stats;
8981 len = asc_prt_line(cp, leftlen,
8982 "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n", shp->host_no);
8985 len = asc_prt_line(cp, leftlen,
8986 " queuecommand %lu, reset %lu, biosparam %lu, interrupt %lu\n",
8987 s->queuecommand, s->reset, s->biosparam, s->interrupt);
8990 len = asc_prt_line(cp, leftlen,
8991 " callback %lu, done %lu, build_error %lu, build_noreq %lu, build_nosg %lu\n",
8992 s->callback, s->done, s->build_error, s->adv_build_noreq,
8996 len = asc_prt_line(cp, leftlen,
8997 " exe_noerror %lu, exe_busy %lu, exe_error %lu, exe_unknown %lu\n",
8998 s->exe_noerror, s->exe_busy, s->exe_error, s->exe_unknown);
9002 * Display data transfer statistics.
9004 if (s->cont_cnt > 0) {
9005 len = asc_prt_line(cp, leftlen, " cont_cnt %lu, ", s->cont_cnt);
9008 len = asc_prt_line(cp, leftlen, "cont_xfer %lu.%01lu kb ",
9010 ASC_TENTHS(s->cont_xfer, 2));
9013 /* Contiguous transfer average size */
9014 len = asc_prt_line(cp, leftlen, "avg_xfer %lu.%01lu kb\n",
9015 (s->cont_xfer/2)/s->cont_cnt,
9016 ASC_TENTHS((s->cont_xfer/2), s->cont_cnt));
9020 if (s->sg_cnt > 0) {
9022 len = asc_prt_line(cp, leftlen, " sg_cnt %lu, sg_elem %lu, ",
9023 s->sg_cnt, s->sg_elem);
9026 len = asc_prt_line(cp, leftlen, "sg_xfer %lu.%01lu kb\n",
9028 ASC_TENTHS(s->sg_xfer, 2));
9031 /* Scatter gather transfer statistics */
9032 len = asc_prt_line(cp, leftlen, " avg_num_elem %lu.%01lu, ",
9033 s->sg_elem/s->sg_cnt,
9034 ASC_TENTHS(s->sg_elem, s->sg_cnt));
9037 len = asc_prt_line(cp, leftlen, "avg_elem_size %lu.%01lu kb, ",
9038 (s->sg_xfer/2)/s->sg_elem,
9039 ASC_TENTHS((s->sg_xfer/2), s->sg_elem));
9042 len = asc_prt_line(cp, leftlen, "avg_xfer_size %lu.%01lu kb\n",
9043 (s->sg_xfer/2)/s->sg_cnt,
9044 ASC_TENTHS((s->sg_xfer/2), s->sg_cnt));
9049 * Display request queuing statistics.
9051 len = asc_prt_line(cp, leftlen,
9052 " Active and Waiting Request Queues (Time Unit: %d HZ):\n", HZ);
9060 * asc_prt_target_stats()
9062 * Note: no single line should be greater than ASC_PRTLINE_SIZE,
9063 * cf. asc_prt_line().
9065 * This is separated from asc_prt_board_stats because a full set
9066 * of targets will overflow ASC_PRTBUF_SIZE.
9068 * Return the number of characters copied into 'cp'. No more than
9069 * 'cplen' characters will be copied to 'cp'.
9072 asc_prt_target_stats(struct Scsi_Host *shp, int tgt_id, char *cp, int cplen)
9077 struct asc_stats *s;
9078 ushort chip_scsi_id;
9079 asc_board_t *boardp;
9080 asc_queue_t *active;
9081 asc_queue_t *waiting;
9086 boardp = ASC_BOARDP(shp);
9087 s = &boardp->asc_stats;
9089 active = &ASC_BOARDP(shp)->active;
9090 waiting = &ASC_BOARDP(shp)->waiting;
9092 if (ASC_NARROW_BOARD(boardp)) {
9093 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
9095 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
9098 if ((chip_scsi_id == tgt_id) ||
9099 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(tgt_id)) == 0)) {
9104 if (active->q_tot_cnt[tgt_id] > 0 || waiting->q_tot_cnt[tgt_id] > 0) {
9105 len = asc_prt_line(cp, leftlen, " target %d\n", tgt_id);
9108 len = asc_prt_line(cp, leftlen,
9109 " active: cnt [cur %d, max %d, tot %u], time [min %d, max %d, avg %lu.%01lu]\n",
9110 active->q_cur_cnt[tgt_id], active->q_max_cnt[tgt_id],
9111 active->q_tot_cnt[tgt_id],
9112 active->q_min_tim[tgt_id], active->q_max_tim[tgt_id],
9113 (active->q_tot_cnt[tgt_id] == 0) ? 0 :
9114 (active->q_tot_tim[tgt_id]/active->q_tot_cnt[tgt_id]),
9115 (active->q_tot_cnt[tgt_id] == 0) ? 0 :
9116 ASC_TENTHS(active->q_tot_tim[tgt_id],
9117 active->q_tot_cnt[tgt_id]));
9120 len = asc_prt_line(cp, leftlen,
9121 " waiting: cnt [cur %d, max %d, tot %u], time [min %u, max %u, avg %lu.%01lu]\n",
9122 waiting->q_cur_cnt[tgt_id], waiting->q_max_cnt[tgt_id],
9123 waiting->q_tot_cnt[tgt_id],
9124 waiting->q_min_tim[tgt_id], waiting->q_max_tim[tgt_id],
9125 (waiting->q_tot_cnt[tgt_id] == 0) ? 0 :
9126 (waiting->q_tot_tim[tgt_id]/waiting->q_tot_cnt[tgt_id]),
9127 (waiting->q_tot_cnt[tgt_id] == 0) ? 0 :
9128 ASC_TENTHS(waiting->q_tot_tim[tgt_id],
9129 waiting->q_tot_cnt[tgt_id]));
9136 #endif /* CONFIG_PROC_FS */
9137 #endif /* ADVANSYS_STATS */
9139 #ifdef ADVANSYS_DEBUG
9141 * asc_prt_scsi_host()
9144 asc_prt_scsi_host(struct Scsi_Host *s)
9146 asc_board_t *boardp;
9148 boardp = ASC_BOARDP(s);
9150 printk("Scsi_Host at addr 0x%lx\n", (ulong) s);
9152 " host_busy %u, host_no %d, last_reset %d,\n",
9153 s->host_busy, s->host_no,
9154 (unsigned) s->last_reset);
9157 " base 0x%lx, io_port 0x%lx, n_io_port %u, irq 0x%x,\n",
9158 (ulong) s->base, (ulong) s->io_port, s->n_io_port, s->irq);
9161 " dma_channel %d, this_id %d, can_queue %d,\n",
9162 s->dma_channel, s->this_id, s->can_queue);
9165 " cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
9166 s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
9168 if (ASC_NARROW_BOARD(boardp)) {
9169 asc_prt_asc_dvc_var(&ASC_BOARDP(s)->dvc_var.asc_dvc_var);
9170 asc_prt_asc_dvc_cfg(&ASC_BOARDP(s)->dvc_cfg.asc_dvc_cfg);
9172 asc_prt_adv_dvc_var(&ASC_BOARDP(s)->dvc_var.adv_dvc_var);
9173 asc_prt_adv_dvc_cfg(&ASC_BOARDP(s)->dvc_cfg.adv_dvc_cfg);
9178 * asc_prt_scsi_cmnd()
9181 asc_prt_scsi_cmnd(struct scsi_cmnd *s)
9183 printk("struct scsi_cmnd at addr 0x%lx\n", (ulong) s);
9186 " host 0x%lx, device 0x%lx, target %u, lun %u, channel %u,\n",
9187 (ulong) s->device->host, (ulong) s->device, s->device->id, s->device->lun,
9188 s->device->channel);
9190 asc_prt_hex(" CDB", s->cmnd, s->cmd_len);
9193 "sc_data_direction %u, resid %d\n",
9194 s->sc_data_direction, s->resid);
9197 " use_sg %u, sglist_len %u, abort_reason 0x%x\n",
9198 s->use_sg, s->sglist_len, s->abort_reason);
9201 " serial_number 0x%x, serial_number_at_timeout 0x%x, retries %d, allowed %d\n",
9202 (unsigned) s->serial_number, (unsigned) s->serial_number_at_timeout,
9203 s->retries, s->allowed);
9206 " timeout_per_command %d, timeout_total %d, timeout %d\n",
9207 s->timeout_per_command, s->timeout_total, s->timeout);
9210 " scsi_done 0x%lx, done 0x%lx, host_scribble 0x%lx, result 0x%x\n",
9211 (ulong) s->scsi_done, (ulong) s->done,
9212 (ulong) s->host_scribble, s->result);
9215 " tag %u, pid %u\n",
9216 (unsigned) s->tag, (unsigned) s->pid);
9220 * asc_prt_asc_dvc_var()
9223 asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
9225 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong) h);
9228 " iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl %d,\n",
9229 h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
9232 " bus_type %d, isr_callback 0x%lx, exe_callback 0x%lx, init_sdtr 0x%x,\n",
9233 h->bus_type, (ulong) h->isr_callback, (ulong) h->exe_callback,
9234 (unsigned) h->init_sdtr);
9237 " sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, chip_no 0x%x,\n",
9238 (unsigned) h->sdtr_done, (unsigned) h->use_tagged_qng,
9239 (unsigned) h->unit_not_ready, (unsigned) h->chip_no);
9242 " queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait %u,\n",
9243 (unsigned) h->queue_full_or_busy, (unsigned) h->start_motor,
9244 (unsigned) h->scsi_reset_wait);
9247 " is_in_int %u, max_total_qng %u, cur_total_qng %u, in_critical_cnt %u,\n",
9248 (unsigned) h->is_in_int, (unsigned) h->max_total_qng,
9249 (unsigned) h->cur_total_qng, (unsigned) h->in_critical_cnt);
9252 " last_q_shortage %u, init_state 0x%x, no_scam 0x%x, pci_fix_asyn_xfer 0x%x,\n",
9253 (unsigned) h->last_q_shortage, (unsigned) h->init_state,
9254 (unsigned) h->no_scam, (unsigned) h->pci_fix_asyn_xfer);
9257 " cfg 0x%lx, irq_no 0x%x\n",
9258 (ulong) h->cfg, (unsigned) h->irq_no);
9262 * asc_prt_asc_dvc_cfg()
9265 asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
9267 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong) h);
9270 " can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
9271 h->can_tagged_qng, h->cmd_qng_enabled);
9273 " disc_enable 0x%x, sdtr_enable 0x%x,\n",
9274 h->disc_enable, h->sdtr_enable);
9277 " chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, chip_version %d,\n",
9278 h->chip_scsi_id, h->isa_dma_speed, h->isa_dma_channel,
9282 " pci_device_id %d, lib_serial_no %u, lib_version %u, mcode_date 0x%x,\n",
9283 to_pci_dev(h->dev)->device, h->lib_serial_no, h->lib_version,
9287 " mcode_version %d, overrun_buf 0x%lx\n",
9288 h->mcode_version, (ulong) h->overrun_buf);
9292 * asc_prt_asc_scsi_q()
9295 asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
9300 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong) q);
9303 " target_ix 0x%x, target_lun %u, srb_ptr 0x%lx, tag_code 0x%x,\n",
9304 q->q2.target_ix, q->q1.target_lun,
9305 (ulong) q->q2.srb_ptr, q->q2.tag_code);
9308 " data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
9309 (ulong) le32_to_cpu(q->q1.data_addr),
9310 (ulong) le32_to_cpu(q->q1.data_cnt),
9311 (ulong) le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
9314 " cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
9315 (ulong) q->cdbptr, q->q2.cdb_len,
9316 (ulong) q->sg_head, q->q1.sg_queue_cnt);
9320 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong) sgp);
9321 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt, sgp->queue_cnt);
9322 for (i = 0; i < sgp->entry_cnt; i++) {
9323 printk(" [%u]: addr 0x%lx, bytes %lu\n",
9324 i, (ulong) le32_to_cpu(sgp->sg_list[i].addr),
9325 (ulong) le32_to_cpu(sgp->sg_list[i].bytes));
9332 * asc_prt_asc_qdone_info()
9335 asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
9337 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong) q);
9339 " srb_ptr 0x%lx, target_ix %u, cdb_len %u, tag_code %u,\n",
9340 (ulong) q->d2.srb_ptr, q->d2.target_ix, q->d2.cdb_len,
9343 " done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
9344 q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
9348 * asc_prt_adv_dvc_var()
9350 * Display an ADV_DVC_VAR structure.
9353 asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
9355 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong) h);
9358 " iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
9359 (ulong) h->iop_base, h->err_code, (unsigned) h->ultra_able);
9362 " isr_callback 0x%lx, sdtr_able 0x%x, wdtr_able 0x%x\n",
9363 (ulong) h->isr_callback, (unsigned) h->sdtr_able,
9364 (unsigned) h->wdtr_able);
9367 " start_motor 0x%x, scsi_reset_wait 0x%x, irq_no 0x%x,\n",
9368 (unsigned) h->start_motor,
9369 (unsigned) h->scsi_reset_wait, (unsigned) h->irq_no);
9372 " max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%lxn\n",
9373 (unsigned) h->max_host_qng, (unsigned) h->max_dvc_qng,
9374 (ulong) h->carr_freelist);
9377 " icq_sp 0x%lx, irq_sp 0x%lx\n",
9378 (ulong) h->icq_sp, (ulong) h->irq_sp);
9381 " no_scam 0x%x, tagqng_able 0x%x\n",
9382 (unsigned) h->no_scam, (unsigned) h->tagqng_able);
9385 " chip_scsi_id 0x%x, cfg 0x%lx\n",
9386 (unsigned) h->chip_scsi_id, (ulong) h->cfg);
9390 * asc_prt_adv_dvc_cfg()
9392 * Display an ADV_DVC_CFG structure.
9395 asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
9397 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong) h);
9400 " disc_enable 0x%x, termination 0x%x\n",
9401 h->disc_enable, h->termination);
9404 " chip_version 0x%x, mcode_date 0x%x\n",
9405 h->chip_version, h->mcode_date);
9408 " mcode_version 0x%x, pci_device_id 0x%x, lib_version %u\n",
9409 h->mcode_version, to_pci_dev(h->dev)->device, h->lib_version);
9412 " control_flag 0x%x, pci_slot_info 0x%x\n",
9413 h->control_flag, h->pci_slot_info);
9417 * asc_prt_adv_scsi_req_q()
9419 * Display an ADV_SCSI_REQ_Q structure.
9422 asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
9425 struct asc_sg_block *sg_ptr;
9427 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong) q);
9430 " target_id %u, target_lun %u, srb_ptr 0x%lx, a_flag 0x%x\n",
9431 q->target_id, q->target_lun, (ulong) q->srb_ptr, q->a_flag);
9433 printk(" cntl 0x%x, data_addr 0x%lx, vdata_addr 0x%lx\n",
9434 q->cntl, (ulong) le32_to_cpu(q->data_addr), (ulong) q->vdata_addr);
9437 " data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
9438 (ulong) le32_to_cpu(q->data_cnt),
9439 (ulong) le32_to_cpu(q->sense_addr), q->sense_len);
9442 " cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
9443 q->cdb_len, q->done_status, q->host_status, q->scsi_status);
9446 " sg_working_ix 0x%x, target_cmd %u\n",
9447 q->sg_working_ix, q->target_cmd);
9450 " scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
9451 (ulong) le32_to_cpu(q->scsiq_rptr),
9452 (ulong) le32_to_cpu(q->sg_real_addr), (ulong) q->sg_list_ptr);
9454 /* Display the request's ADV_SG_BLOCK structures. */
9455 if (q->sg_list_ptr != NULL)
9460 * 'sg_ptr' is a physical address. Convert it to a virtual
9461 * address by indexing 'sg_blk_cnt' into the virtual address
9462 * array 'sg_list_ptr'.
9464 * XXX - Assumes all SG physical blocks are virtually contiguous.
9466 sg_ptr = &(((ADV_SG_BLOCK *) (q->sg_list_ptr))[sg_blk_cnt]);
9467 asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
9468 if (sg_ptr->sg_ptr == 0)
9478 * asc_prt_adv_sgblock()
9480 * Display an ADV_SG_BLOCK structure.
9483 asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
9487 printk(" ASC_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
9488 (ulong) b, sgblockno);
9489 printk(" sg_cnt %u, sg_ptr 0x%lx\n",
9490 b->sg_cnt, (ulong) le32_to_cpu(b->sg_ptr));
9491 ASC_ASSERT(b->sg_cnt <= NO_OF_SG_PER_BLOCK);
9494 ASC_ASSERT(b->sg_cnt == NO_OF_SG_PER_BLOCK);
9496 for (i = 0; i < b->sg_cnt; i++) {
9497 printk(" [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
9498 i, (ulong) b->sg_list[i].sg_addr, (ulong) b->sg_list[i].sg_count);
9505 * Print hexadecimal output in 4 byte groupings 32 bytes
9506 * or 8 double-words per line.
9509 asc_prt_hex(char *f, uchar *s, int l)
9516 printk("%s: (%d bytes)\n", f, l);
9518 for (i = 0; i < l; i += 32) {
9520 /* Display a maximum of 8 double-words per line. */
9521 if ((k = (l - i) / 4) >= 8) {
9528 for (j = 0; j < k; j++) {
9529 printk(" %2.2X%2.2X%2.2X%2.2X",
9530 (unsigned) s[i+(j*4)], (unsigned) s[i+(j*4)+1],
9531 (unsigned) s[i+(j*4)+2], (unsigned) s[i+(j*4)+3]);
9540 (unsigned) s[i+(j*4)]);
9543 printk(" %2.2X%2.2X",
9544 (unsigned) s[i+(j*4)],
9545 (unsigned) s[i+(j*4)+1]);
9548 printk(" %2.2X%2.2X%2.2X",
9549 (unsigned) s[i+(j*4)+1],
9550 (unsigned) s[i+(j*4)+2],
9551 (unsigned) s[i+(j*4)+3]);
9558 #endif /* ADVANSYS_DEBUG */
9561 * --- Asc Library Functions
9564 STATIC ushort __init
9568 PortAddr eisa_cfg_iop;
9570 eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
9571 (PortAddr) (ASC_EISA_CFG_IOP_MASK);
9572 return (inpw(eisa_cfg_iop));
9583 if (AscGetChipScsiID(iop_base) == new_host_id) {
9584 return (new_host_id);
9586 cfg_lsw = AscGetChipCfgLsw(iop_base);
9588 cfg_lsw |= (ushort) ((new_host_id & ASC_MAX_TID) << 8);
9589 AscSetChipCfgLsw(iop_base, cfg_lsw);
9590 return (AscGetChipScsiID(iop_base));
9599 AscSetBank(iop_base, 1);
9600 sc = inp(iop_base + IOP_REG_SC);
9601 AscSetBank(iop_base, 0);
9611 if ((bus_type & ASC_IS_EISA) != 0) {
9614 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
9615 (PortAddr) ASC_EISA_REV_IOP_MASK;
9616 revision = inp(eisa_iop);
9617 return ((uchar) ((ASC_CHIP_MIN_VER_EISA - 1) + revision));
9619 return (AscGetChipVerNo(iop_base));
9622 STATIC ushort __init
9628 chip_ver = AscGetChipVerNo(iop_base);
9630 (chip_ver >= ASC_CHIP_MIN_VER_VL)
9631 && (chip_ver <= ASC_CHIP_MAX_VER_VL)
9634 ((iop_base & 0x0C30) == 0x0C30)
9635 || ((iop_base & 0x0C50) == 0x0C50)
9637 return (ASC_IS_EISA);
9641 if ((chip_ver >= ASC_CHIP_MIN_VER_ISA) &&
9642 (chip_ver <= ASC_CHIP_MAX_VER_ISA)) {
9643 if (chip_ver >= ASC_CHIP_MIN_VER_ISA_PNP) {
9644 return (ASC_IS_ISAPNP);
9646 return (ASC_IS_ISA);
9647 } else if ((chip_ver >= ASC_CHIP_MIN_VER_PCI) &&
9648 (chip_ver <= ASC_CHIP_MAX_VER_PCI)) {
9649 return (ASC_IS_PCI);
9663 ushort mcode_word_size;
9664 ushort mcode_chksum;
9666 /* Write the microcode buffer starting at LRAM address 0. */
9667 mcode_word_size = (ushort) (mcode_size >> 1);
9668 AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
9669 AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
9671 chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
9672 ASC_DBG1(1, "AscLoadMicroCode: chksum 0x%lx\n", (ulong) chksum);
9673 mcode_chksum = (ushort) AscMemSumLramWord(iop_base,
9674 (ushort) ASC_CODE_SEC_BEG,
9675 (ushort) ((mcode_size - s_addr - (ushort) ASC_CODE_SEC_BEG) / 2));
9676 ASC_DBG1(1, "AscLoadMicroCode: mcode_chksum 0x%lx\n",
9677 (ulong) mcode_chksum);
9678 AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
9679 AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
9690 ASC_DBG2(1, "AscFindSignature: AscGetChipSignatureByte(0x%x) 0x%x\n",
9691 iop_base, AscGetChipSignatureByte(iop_base));
9692 if (AscGetChipSignatureByte(iop_base) == (uchar) ASC_1000_ID1B) {
9693 ASC_DBG2(1, "AscFindSignature: AscGetChipSignatureWord(0x%x) 0x%x\n",
9694 iop_base, AscGetChipSignatureWord(iop_base));
9695 sig_word = AscGetChipSignatureWord(iop_base);
9696 if ((sig_word == (ushort) ASC_1000_ID0W) ||
9697 (sig_word == (ushort) ASC_1000_ID0W_FIX)) {
9704 STATIC PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] __initdata =
9706 0x100, ASC_IOADR_1, 0x120, ASC_IOADR_2, 0x140, ASC_IOADR_3, ASC_IOADR_4,
9707 ASC_IOADR_5, ASC_IOADR_6, ASC_IOADR_7, ASC_IOADR_8
9711 STATIC uchar _isa_pnp_inited __initdata = 0;
9713 STATIC PortAddr __init
9714 AscSearchIOPortAddr(
9718 if (bus_type & ASC_IS_VL) {
9719 while ((iop_beg = AscSearchIOPortAddr11(iop_beg)) != 0) {
9720 if (AscGetChipVersion(iop_beg, bus_type) <= ASC_CHIP_MAX_VER_VL) {
9726 if (bus_type & ASC_IS_ISA) {
9727 if (_isa_pnp_inited == 0) {
9728 AscSetISAPNPWaitForKey();
9731 while ((iop_beg = AscSearchIOPortAddr11(iop_beg)) != 0) {
9732 if ((AscGetChipVersion(iop_beg, bus_type) & ASC_CHIP_VER_ISA_BIT) != 0) {
9738 if (bus_type & ASC_IS_EISA) {
9739 if ((iop_beg = AscSearchIOPortAddrEISA(iop_beg)) != 0) {
9747 STATIC PortAddr __init
9748 AscSearchIOPortAddr11(
9755 for (i = 0; i < ASC_IOADR_TABLE_MAX_IX; i++) {
9756 if (_asc_def_iop_base[i] > s_addr) {
9760 for (; i < ASC_IOADR_TABLE_MAX_IX; i++) {
9761 iop_base = _asc_def_iop_base[i];
9762 if (check_region(iop_base, ASC_IOADR_GAP) != 0) {
9764 "AscSearchIOPortAddr11: check_region() failed I/O port 0x%x\n",
9768 ASC_DBG1(1, "AscSearchIOPortAddr11: probing I/O port 0x%x\n", iop_base);
9769 if (AscFindSignature(iop_base)) {
9777 AscSetISAPNPWaitForKey(void)
9779 outp(ASC_ISA_PNP_PORT_ADDR, 0x02);
9780 outp(ASC_ISA_PNP_PORT_WRITE, 0x02);
9783 #endif /* CONFIG_ISA */
9790 AscSetChipStatus(iop_base, CIW_IRQ_ACT);
9791 AscSetChipStatus(iop_base, 0);
9803 if ((bus_type & ASC_IS_EISA) != 0) {
9804 cfg_lsw = AscGetEisaChipCfg(iop_base);
9805 chip_irq = (uchar) (((cfg_lsw >> 8) & 0x07) + 10);
9806 if ((chip_irq == 13) || (chip_irq > 15)) {
9811 if ((bus_type & ASC_IS_VL) != 0) {
9812 cfg_lsw = AscGetChipCfgLsw(iop_base);
9813 chip_irq = (uchar) (((cfg_lsw >> 2) & 0x07));
9814 if ((chip_irq == 0) ||
9819 return ((uchar) (chip_irq + (ASC_MIN_IRQ_NO - 1)));
9821 cfg_lsw = AscGetChipCfgLsw(iop_base);
9822 chip_irq = (uchar) (((cfg_lsw >> 2) & 0x03));
9824 chip_irq += (uchar) 2;
9825 return ((uchar) (chip_irq + ASC_MIN_IRQ_NO));
9836 if ((bus_type & ASC_IS_VL) != 0) {
9838 if ((irq_no < ASC_MIN_IRQ_NO) || (irq_no > ASC_MAX_IRQ_NO)) {
9841 irq_no -= (uchar) ((ASC_MIN_IRQ_NO - 1));
9844 cfg_lsw = (ushort) (AscGetChipCfgLsw(iop_base) & 0xFFE3);
9845 cfg_lsw |= (ushort) 0x0010;
9846 AscSetChipCfgLsw(iop_base, cfg_lsw);
9847 AscToggleIRQAct(iop_base);
9848 cfg_lsw = (ushort) (AscGetChipCfgLsw(iop_base) & 0xFFE0);
9849 cfg_lsw |= (ushort) ((irq_no & 0x07) << 2);
9850 AscSetChipCfgLsw(iop_base, cfg_lsw);
9851 AscToggleIRQAct(iop_base);
9852 return (AscGetChipIRQ(iop_base, bus_type));
9854 if ((bus_type & (ASC_IS_ISA)) != 0) {
9856 irq_no -= (uchar) 2;
9857 irq_no -= (uchar) ASC_MIN_IRQ_NO;
9858 cfg_lsw = (ushort) (AscGetChipCfgLsw(iop_base) & 0xFFF3);
9859 cfg_lsw |= (ushort) ((irq_no & 0x03) << 2);
9860 AscSetChipCfgLsw(iop_base, cfg_lsw);
9861 return (AscGetChipIRQ(iop_base, bus_type));
9871 if (dma_channel < 4) {
9872 outp(0x000B, (ushort) (0xC0 | dma_channel));
9873 outp(0x000A, dma_channel);
9874 } else if (dma_channel < 8) {
9875 outp(0x00D6, (ushort) (0xC0 | (dma_channel - 4)));
9876 outp(0x00D4, (ushort) (dma_channel - 4));
9880 #endif /* CONFIG_ISA */
9884 ASC_DVC_VAR *asc_dvc
9891 ushort int_halt_code;
9892 ASC_SCSI_BIT_ID_TYPE scsi_busy;
9893 ASC_SCSI_BIT_ID_TYPE target_id;
9900 uchar q_cntl, tid_no;
9904 asc_board_t *boardp;
9906 ASC_ASSERT(asc_dvc->drv_ptr != NULL);
9907 boardp = asc_dvc->drv_ptr;
9909 iop_base = asc_dvc->iop_base;
9910 int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
9912 halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
9913 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
9914 target_ix = AscReadLramByte(iop_base,
9915 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_TARGET_IX));
9916 q_cntl = AscReadLramByte(iop_base,
9917 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_CNTL));
9918 tid_no = ASC_TIX_TO_TID(target_ix);
9919 target_id = (uchar) ASC_TID_TO_TARGET_ID(tid_no);
9920 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
9921 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
9925 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
9926 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
9927 AscSetChipSDTR(iop_base, 0, tid_no);
9928 boardp->sdtr_data[tid_no] = 0;
9930 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9932 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
9933 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
9934 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
9935 boardp->sdtr_data[tid_no] = asyn_sdtr;
9937 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
9939 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
9941 AscMemWordCopyPtrFromLram(iop_base,
9944 sizeof(EXT_MSG) >> 1);
9946 if (ext_msg.msg_type == MS_EXTEND &&
9947 ext_msg.msg_req == MS_SDTR_CODE &&
9948 ext_msg.msg_len == MS_SDTR_LEN) {
9950 if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
9952 sdtr_accept = FALSE;
9953 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
9955 if ((ext_msg.xfer_period <
9956 asc_dvc->sdtr_period_tbl[asc_dvc->host_init_sdtr_index]) ||
9957 (ext_msg.xfer_period >
9958 asc_dvc->sdtr_period_tbl[asc_dvc->max_sdtr_index])) {
9959 sdtr_accept = FALSE;
9960 ext_msg.xfer_period =
9961 asc_dvc->sdtr_period_tbl[asc_dvc->host_init_sdtr_index];
9964 sdtr_data = AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
9965 ext_msg.req_ack_offset);
9966 if ((sdtr_data == 0xFF)) {
9968 q_cntl |= QC_MSG_OUT;
9969 asc_dvc->init_sdtr &= ~target_id;
9970 asc_dvc->sdtr_done &= ~target_id;
9971 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
9972 boardp->sdtr_data[tid_no] = asyn_sdtr;
9975 if (ext_msg.req_ack_offset == 0) {
9977 q_cntl &= ~QC_MSG_OUT;
9978 asc_dvc->init_sdtr &= ~target_id;
9979 asc_dvc->sdtr_done &= ~target_id;
9980 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
9982 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
9984 q_cntl &= ~QC_MSG_OUT;
9985 asc_dvc->sdtr_done |= target_id;
9986 asc_dvc->init_sdtr |= target_id;
9987 asc_dvc->pci_fix_asyn_xfer &= ~target_id;
9988 sdtr_data = AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
9989 ext_msg.req_ack_offset);
9990 AscSetChipSDTR(iop_base, sdtr_data, tid_no);
9991 boardp->sdtr_data[tid_no] = sdtr_data;
9994 q_cntl |= QC_MSG_OUT;
9995 AscMsgOutSDTR(asc_dvc,
9996 ext_msg.xfer_period,
9997 ext_msg.req_ack_offset);
9998 asc_dvc->pci_fix_asyn_xfer &= ~target_id;
9999 sdtr_data = AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
10000 ext_msg.req_ack_offset);
10001 AscSetChipSDTR(iop_base, sdtr_data, tid_no);
10002 boardp->sdtr_data[tid_no] = sdtr_data;
10003 asc_dvc->sdtr_done |= target_id;
10004 asc_dvc->init_sdtr |= target_id;
10008 AscWriteLramByte(iop_base,
10009 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_CNTL),
10011 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10013 } else if (ext_msg.msg_type == MS_EXTEND &&
10014 ext_msg.msg_req == MS_WDTR_CODE &&
10015 ext_msg.msg_len == MS_WDTR_LEN) {
10017 ext_msg.wdtr_width = 0;
10018 AscMemWordCopyPtrToLram(iop_base,
10020 (uchar *) &ext_msg,
10021 sizeof(EXT_MSG) >> 1);
10022 q_cntl |= QC_MSG_OUT;
10023 AscWriteLramByte(iop_base,
10024 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_CNTL),
10026 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10030 ext_msg.msg_type = MESSAGE_REJECT;
10031 AscMemWordCopyPtrToLram(iop_base,
10033 (uchar *) &ext_msg,
10034 sizeof(EXT_MSG) >> 1);
10035 q_cntl |= QC_MSG_OUT;
10036 AscWriteLramByte(iop_base,
10037 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_CNTL),
10039 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10042 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
10044 q_cntl |= QC_REQ_SENSE;
10046 if ((asc_dvc->init_sdtr & target_id) != 0) {
10048 asc_dvc->sdtr_done &= ~target_id;
10050 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
10051 q_cntl |= QC_MSG_OUT;
10052 AscMsgOutSDTR(asc_dvc,
10053 asc_dvc->sdtr_period_tbl[(sdtr_data >> 4) &
10054 (uchar) (asc_dvc->max_sdtr_index - 1)],
10055 (uchar) (sdtr_data & (uchar) ASC_SYN_MAX_OFFSET));
10058 AscWriteLramByte(iop_base,
10059 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_CNTL),
10062 tag_code = AscReadLramByte(iop_base,
10063 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_TAG_CODE));
10066 (asc_dvc->pci_fix_asyn_xfer & target_id)
10067 && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
10070 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
10071 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
10074 AscWriteLramByte(iop_base,
10075 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_TAG_CODE),
10078 q_status = AscReadLramByte(iop_base,
10079 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_STATUS));
10080 q_status |= (QS_READY | QS_BUSY);
10081 AscWriteLramByte(iop_base,
10082 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_STATUS),
10085 scsi_busy = AscReadLramByte(iop_base,
10086 (ushort) ASCV_SCSIBUSY_B);
10087 scsi_busy &= ~target_id;
10088 AscWriteLramByte(iop_base, (ushort) ASCV_SCSIBUSY_B, scsi_busy);
10090 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10092 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
10094 AscMemWordCopyPtrFromLram(iop_base,
10096 (uchar *) &out_msg,
10097 sizeof(EXT_MSG) >> 1);
10099 if ((out_msg.msg_type == MS_EXTEND) &&
10100 (out_msg.msg_len == MS_SDTR_LEN) &&
10101 (out_msg.msg_req == MS_SDTR_CODE)) {
10103 asc_dvc->init_sdtr &= ~target_id;
10104 asc_dvc->sdtr_done &= ~target_id;
10105 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
10106 boardp->sdtr_data[tid_no] = asyn_sdtr;
10108 q_cntl &= ~QC_MSG_OUT;
10109 AscWriteLramByte(iop_base,
10110 (ushort) (halt_q_addr + (ushort) ASC_SCSIQ_B_CNTL),
10112 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10114 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
10116 scsi_status = AscReadLramByte(iop_base,
10117 (ushort) ((ushort) halt_q_addr + (ushort) ASC_SCSIQ_SCSI_STATUS));
10118 cur_dvc_qng = AscReadLramByte(iop_base,
10119 (ushort) ((ushort) ASC_QADR_BEG + (ushort) target_ix));
10120 if ((cur_dvc_qng > 0) &&
10121 (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
10123 scsi_busy = AscReadLramByte(iop_base,
10124 (ushort) ASCV_SCSIBUSY_B);
10125 scsi_busy |= target_id;
10126 AscWriteLramByte(iop_base,
10127 (ushort) ASCV_SCSIBUSY_B, scsi_busy);
10128 asc_dvc->queue_full_or_busy |= target_id;
10130 if (scsi_status == SAM_STAT_TASK_SET_FULL) {
10131 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
10133 asc_dvc->max_dvc_qng[tid_no] = cur_dvc_qng;
10135 AscWriteLramByte(iop_base,
10136 (ushort) ((ushort) ASCV_MAX_DVC_QNG_BEG +
10141 * Set the device queue depth to the number of
10142 * active requests when the QUEUE FULL condition
10145 boardp->queue_full |= target_id;
10146 boardp->queue_full_cnt[tid_no] = cur_dvc_qng;
10150 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10153 #if CC_VERY_LONG_SG_LIST
10154 else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC)
10159 uchar first_sg_wk_q_no;
10160 ASC_SCSI_Q *scsiq; /* Ptr to driver request. */
10161 ASC_SG_HEAD *sg_head; /* Ptr to driver SG request. */
10162 ASC_SG_LIST_Q scsi_sg_q; /* Structure written to queue. */
10163 ushort sg_list_dwords;
10164 ushort sg_entry_cnt;
10168 q_no = AscReadLramByte(iop_base, (ushort) ASCV_REQ_SG_LIST_QP);
10169 if (q_no == ASC_QLINK_END)
10174 q_addr = ASC_QNO_TO_QADDR(q_no);
10177 * Convert the request's SRB pointer to a host ASC_SCSI_REQ
10178 * structure pointer using a macro provided by the driver.
10179 * The ASC_SCSI_REQ pointer provides a pointer to the
10180 * host ASC_SG_HEAD structure.
10182 /* Read request's SRB pointer. */
10183 scsiq = (ASC_SCSI_Q *)
10185 ASC_U32_TO_VADDR(AscReadLramDWord(iop_base,
10186 (ushort) (q_addr + ASC_SCSIQ_D_SRBPTR))));
10189 * Get request's first and working SG queue.
10191 sg_wk_q_no = AscReadLramByte(iop_base,
10192 (ushort) (q_addr + ASC_SCSIQ_B_SG_WK_QP));
10194 first_sg_wk_q_no = AscReadLramByte(iop_base,
10195 (ushort) (q_addr + ASC_SCSIQ_B_FIRST_SG_WK_QP));
10198 * Reset request's working SG queue back to the
10201 AscWriteLramByte(iop_base,
10202 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_SG_WK_QP),
10205 sg_head = scsiq->sg_head;
10208 * Set sg_entry_cnt to the number of SG elements
10209 * that will be completed on this interrupt.
10211 * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
10212 * SG elements. The data_cnt and data_addr fields which
10213 * add 1 to the SG element capacity are not used when
10214 * restarting SG handling after a halt.
10216 if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1))
10218 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
10221 * Keep track of remaining number of SG elements that will
10222 * need to be handled on the next interrupt.
10224 scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1);
10227 sg_entry_cnt = scsiq->remain_sg_entry_cnt;
10228 scsiq->remain_sg_entry_cnt = 0;
10232 * Copy SG elements into the list of allocated SG queues.
10234 * Last index completed is saved in scsiq->next_sg_index.
10236 next_qp = first_sg_wk_q_no;
10237 q_addr = ASC_QNO_TO_QADDR(next_qp);
10238 scsi_sg_q.sg_head_qp = q_no;
10239 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
10240 for( i = 0; i < sg_head->queue_cnt; i++)
10242 scsi_sg_q.seq_no = i + 1;
10243 if (sg_entry_cnt > ASC_SG_LIST_PER_Q)
10245 sg_list_dwords = (uchar) (ASC_SG_LIST_PER_Q * 2);
10246 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
10248 * After very first SG queue RISC FW uses next
10249 * SG queue first element then checks sg_list_cnt
10250 * against zero and then decrements, so set
10251 * sg_list_cnt 1 less than number of SG elements
10252 * in each SG queue.
10254 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
10255 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q - 1;
10258 * This is the last SG queue in the list of
10259 * allocated SG queues. If there are more
10260 * SG elements than will fit in the allocated
10261 * queues, then set the QCSG_SG_XFER_MORE flag.
10263 if (scsiq->remain_sg_entry_cnt != 0)
10265 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
10268 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
10270 /* equals sg_entry_cnt * 2 */
10271 sg_list_dwords = sg_entry_cnt << 1;
10272 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
10273 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
10277 scsi_sg_q.q_no = next_qp;
10278 AscMemWordCopyPtrToLram(iop_base,
10279 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
10280 (uchar *) &scsi_sg_q,
10281 sizeof(ASC_SG_LIST_Q) >> 1);
10283 AscMemDWordCopyPtrToLram(iop_base,
10284 q_addr + ASC_SGQ_LIST_BEG,
10285 (uchar *) &sg_head->sg_list[scsiq->next_sg_index],
10288 scsiq->next_sg_index += ASC_SG_LIST_PER_Q;
10291 * If the just completed SG queue contained the
10292 * last SG element, then no more SG queues need
10295 if (scsi_sg_q.cntl & QCSG_SG_XFER_END)
10300 next_qp = AscReadLramByte( iop_base,
10301 ( ushort )( q_addr+ASC_SCSIQ_B_FWD ) );
10302 q_addr = ASC_QNO_TO_QADDR( next_qp );
10306 * Clear the halt condition so the RISC will be restarted
10307 * after the return.
10309 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
10312 #endif /* CC_VERY_LONG_SG_LIST */
10317 _AscCopyLramScsiDoneQ(
10320 ASC_QDONE_INFO * scsiq,
10321 ASC_DCNT max_dma_count
10325 uchar sg_queue_cnt;
10327 DvcGetQinfo(iop_base,
10328 q_addr + ASC_SCSIQ_DONE_INFO_BEG,
10330 (sizeof (ASC_SCSIQ_2) + sizeof (ASC_SCSIQ_3)) / 2);
10332 _val = AscReadLramWord(iop_base,
10333 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_STATUS));
10334 scsiq->q_status = (uchar) _val;
10335 scsiq->q_no = (uchar) (_val >> 8);
10336 _val = AscReadLramWord(iop_base,
10337 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_CNTL));
10338 scsiq->cntl = (uchar) _val;
10339 sg_queue_cnt = (uchar) (_val >> 8);
10340 _val = AscReadLramWord(iop_base,
10341 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_SENSE_LEN));
10342 scsiq->sense_len = (uchar) _val;
10343 scsiq->extra_bytes = (uchar) (_val >> 8);
10346 * Read high word of remain bytes from alternate location.
10348 scsiq->remain_bytes = (((ADV_DCNT) AscReadLramWord( iop_base,
10349 (ushort) (q_addr+ (ushort) ASC_SCSIQ_W_ALT_DC1))) << 16);
10351 * Read low word of remain bytes from original location.
10353 scsiq->remain_bytes += AscReadLramWord(iop_base,
10354 (ushort) (q_addr+ (ushort) ASC_SCSIQ_DW_REMAIN_XFER_CNT));
10356 scsiq->remain_bytes &= max_dma_count;
10357 return (sg_queue_cnt);
10362 ASC_DVC_VAR *asc_dvc
10368 uchar sg_queue_cnt;
10372 ASC_SCSI_BIT_ID_TYPE scsi_busy;
10373 ASC_SCSI_BIT_ID_TYPE target_id;
10377 uchar cur_target_qng;
10378 ASC_QDONE_INFO scsiq_buf;
10379 ASC_QDONE_INFO *scsiq;
10381 ASC_ISR_CALLBACK asc_isr_callback;
10383 iop_base = asc_dvc->iop_base;
10384 asc_isr_callback = asc_dvc->isr_callback;
10386 scsiq = (ASC_QDONE_INFO *) & scsiq_buf;
10387 done_q_tail = (uchar) AscGetVarDoneQTail(iop_base);
10388 q_addr = ASC_QNO_TO_QADDR(done_q_tail);
10389 next_qp = AscReadLramByte(iop_base,
10390 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_FWD));
10391 if (next_qp != ASC_QLINK_END) {
10392 AscPutVarDoneQTail(iop_base, next_qp);
10393 q_addr = ASC_QNO_TO_QADDR(next_qp);
10394 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
10395 asc_dvc->max_dma_count);
10396 AscWriteLramByte(iop_base,
10397 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_STATUS),
10398 (uchar) (scsiq->q_status & (uchar) ~ (QS_READY | QS_ABORTED)));
10399 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
10400 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
10401 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
10402 sg_q_addr = q_addr;
10403 sg_list_qp = next_qp;
10404 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
10405 sg_list_qp = AscReadLramByte(iop_base,
10406 (ushort) (sg_q_addr + (ushort) ASC_SCSIQ_B_FWD));
10407 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
10408 if (sg_list_qp == ASC_QLINK_END) {
10409 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_SG_Q_LINKS);
10410 scsiq->d3.done_stat = QD_WITH_ERROR;
10411 scsiq->d3.host_stat = QHSTA_D_QDONE_SG_LIST_CORRUPTED;
10412 goto FATAL_ERR_QDONE;
10414 AscWriteLramByte(iop_base,
10415 (ushort) (sg_q_addr + (ushort) ASC_SCSIQ_B_STATUS),
10418 n_q_used = sg_queue_cnt + 1;
10419 AscPutVarDoneQTail(iop_base, sg_list_qp);
10421 if (asc_dvc->queue_full_or_busy & target_id) {
10422 cur_target_qng = AscReadLramByte(iop_base,
10423 (ushort) ((ushort) ASC_QADR_BEG + (ushort) scsiq->d2.target_ix));
10424 if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
10425 scsi_busy = AscReadLramByte(iop_base,
10426 (ushort) ASCV_SCSIBUSY_B);
10427 scsi_busy &= ~target_id;
10428 AscWriteLramByte(iop_base,
10429 (ushort) ASCV_SCSIBUSY_B, scsi_busy);
10430 asc_dvc->queue_full_or_busy &= ~target_id;
10433 if (asc_dvc->cur_total_qng >= n_q_used) {
10434 asc_dvc->cur_total_qng -= n_q_used;
10435 if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
10436 asc_dvc->cur_dvc_qng[tid_no]--;
10439 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
10440 scsiq->d3.done_stat = QD_WITH_ERROR;
10441 goto FATAL_ERR_QDONE;
10443 if ((scsiq->d2.srb_ptr == 0UL) ||
10444 ((scsiq->q_status & QS_ABORTED) != 0)) {
10446 } else if (scsiq->q_status == QS_DONE) {
10447 false_overrun = FALSE;
10448 if (scsiq->extra_bytes != 0) {
10449 scsiq->remain_bytes += (ADV_DCNT) scsiq->extra_bytes;
10451 if (scsiq->d3.done_stat == QD_WITH_ERROR) {
10452 if (scsiq->d3.host_stat == QHSTA_M_DATA_OVER_RUN) {
10453 if ((scsiq->cntl & (QC_DATA_IN | QC_DATA_OUT)) == 0) {
10454 scsiq->d3.done_stat = QD_NO_ERROR;
10455 scsiq->d3.host_stat = QHSTA_NO_ERROR;
10456 } else if (false_overrun) {
10457 scsiq->d3.done_stat = QD_NO_ERROR;
10458 scsiq->d3.host_stat = QHSTA_NO_ERROR;
10460 } else if (scsiq->d3.host_stat ==
10461 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
10462 AscStopChip(iop_base);
10463 AscSetChipControl(iop_base,
10464 (uchar) (CC_SCSI_RESET | CC_HALT));
10465 DvcDelayNanoSecond(asc_dvc, 60000);
10466 AscSetChipControl(iop_base, CC_HALT);
10467 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
10468 AscSetChipStatus(iop_base, 0);
10469 AscSetChipControl(iop_base, 0);
10472 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
10473 (*asc_isr_callback) (asc_dvc, scsiq);
10475 if ((AscReadLramByte(iop_base,
10476 (ushort) (q_addr + (ushort) ASC_SCSIQ_CDB_BEG)) ==
10478 asc_dvc->unit_not_ready &= ~target_id;
10479 if (scsiq->d3.done_stat != QD_NO_ERROR) {
10480 asc_dvc->start_motor &= ~target_id;
10486 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
10488 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
10489 (*asc_isr_callback) (asc_dvc, scsiq);
10499 ASC_DVC_VAR *asc_dvc
10502 ASC_CS_TYPE chipstat;
10504 ushort saved_ram_addr;
10506 uchar saved_ctrl_reg;
10511 iop_base = asc_dvc->iop_base;
10512 int_pending = FALSE;
10514 if (AscIsIntPending(iop_base) == 0)
10516 return int_pending;
10519 if (((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0)
10520 || (asc_dvc->isr_callback == 0)
10524 if (asc_dvc->in_critical_cnt != 0) {
10525 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
10528 if (asc_dvc->is_in_int) {
10529 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
10532 asc_dvc->is_in_int = TRUE;
10533 ctrl_reg = AscGetChipControl(iop_base);
10534 saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
10535 CC_SINGLE_STEP | CC_DIAG | CC_TEST));
10536 chipstat = AscGetChipStatus(iop_base);
10537 if (chipstat & CSW_SCSI_RESET_LATCH) {
10538 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
10540 int_pending = TRUE;
10541 asc_dvc->sdtr_done = 0;
10542 saved_ctrl_reg &= (uchar) (~CC_HALT);
10543 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE) &&
10546 DvcSleepMilliSecond(100);
10548 AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
10549 AscSetChipControl(iop_base, CC_HALT);
10550 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
10551 AscSetChipStatus(iop_base, 0);
10552 chipstat = AscGetChipStatus(iop_base);
10555 saved_ram_addr = AscGetChipLramAddr(iop_base);
10556 host_flag = AscReadLramByte(iop_base,
10557 ASCV_HOST_FLAG_B) & (uchar) (~ASC_HOST_FLAG_IN_ISR);
10558 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
10559 (uchar) (host_flag | (uchar) ASC_HOST_FLAG_IN_ISR));
10560 if ((chipstat & CSW_INT_PENDING)
10563 AscAckInterrupt(iop_base);
10564 int_pending = TRUE;
10565 if ((chipstat & CSW_HALTED) &&
10566 (ctrl_reg & CC_SINGLE_STEP)) {
10567 if (AscIsrChipHalted(asc_dvc) == ERR) {
10568 goto ISR_REPORT_QDONE_FATAL_ERROR;
10570 saved_ctrl_reg &= (uchar) (~CC_HALT);
10573 ISR_REPORT_QDONE_FATAL_ERROR:
10574 if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
10575 while (((status = AscIsrQDone(asc_dvc)) & 0x01) != 0) {
10579 if ((status = AscIsrQDone(asc_dvc)) == 1) {
10582 } while (status == 0x11);
10584 if ((status & 0x80) != 0)
10588 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
10589 AscSetChipLramAddr(iop_base, saved_ram_addr);
10590 AscSetChipControl(iop_base, saved_ctrl_reg);
10591 asc_dvc->is_in_int = FALSE;
10592 return (int_pending);
10595 /* Microcode buffer is kept after initialization for error recovery. */
10596 STATIC uchar _asc_mcode_buf[] =
10598 0x01, 0x03, 0x01, 0x19, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10599 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10600 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10601 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10602 0x00, 0x00, 0x00, 0x00, 0xC3, 0x12, 0x0D, 0x05, 0x01, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00,
10603 0x00, 0x00, 0x00, 0x00, 0xFF, 0x80, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
10604 0x00, 0x00, 0x00, 0x23, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00,
10605 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE4, 0x88, 0x00, 0x00, 0x00, 0x00,
10606 0x80, 0x73, 0x48, 0x04, 0x36, 0x00, 0x00, 0xA2, 0xC2, 0x00, 0x80, 0x73, 0x03, 0x23, 0x36, 0x40,
10607 0xB6, 0x00, 0x36, 0x00, 0x05, 0xD6, 0x0C, 0xD2, 0x12, 0xDA, 0x00, 0xA2, 0xC2, 0x00, 0x92, 0x80,
10608 0x1E, 0x98, 0x50, 0x00, 0xF5, 0x00, 0x48, 0x98, 0xDF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80,
10609 0x4F, 0x00, 0xF5, 0x00, 0x48, 0x98, 0xEF, 0x23, 0x36, 0x60, 0xB6, 0x00, 0x92, 0x80, 0x80, 0x62,
10610 0x92, 0x80, 0x00, 0x46, 0x15, 0xEE, 0x13, 0xEA, 0x02, 0x01, 0x09, 0xD8, 0xCD, 0x04, 0x4D, 0x00,
10611 0x00, 0xA3, 0xD6, 0x00, 0xA6, 0x97, 0x7F, 0x23, 0x04, 0x61, 0x84, 0x01, 0xE6, 0x84, 0xD2, 0xC1,
10612 0x80, 0x73, 0xCD, 0x04, 0x4D, 0x00, 0x00, 0xA3, 0xDA, 0x01, 0xA6, 0x97, 0xC6, 0x81, 0xC2, 0x88,
10613 0x80, 0x73, 0x80, 0x77, 0x00, 0x01, 0x01, 0xA1, 0xFE, 0x00, 0x4F, 0x00, 0x84, 0x97, 0x07, 0xA6,
10614 0x08, 0x01, 0x00, 0x33, 0x03, 0x00, 0xC2, 0x88, 0x03, 0x03, 0x01, 0xDE, 0xC2, 0x88, 0xCE, 0x00,
10615 0x69, 0x60, 0xCE, 0x00, 0x02, 0x03, 0x4A, 0x60, 0x00, 0xA2, 0x78, 0x01, 0x80, 0x63, 0x07, 0xA6,
10616 0x24, 0x01, 0x78, 0x81, 0x03, 0x03, 0x80, 0x63, 0xE2, 0x00, 0x07, 0xA6, 0x34, 0x01, 0x00, 0x33,
10617 0x04, 0x00, 0xC2, 0x88, 0x03, 0x07, 0x02, 0x01, 0x04, 0xCA, 0x0D, 0x23, 0x68, 0x98, 0x4D, 0x04,
10618 0x04, 0x85, 0x05, 0xD8, 0x0D, 0x23, 0x68, 0x98, 0xCD, 0x04, 0x15, 0x23, 0xF8, 0x88, 0xFB, 0x23,
10619 0x02, 0x61, 0x82, 0x01, 0x80, 0x63, 0x02, 0x03, 0x06, 0xA3, 0x62, 0x01, 0x00, 0x33, 0x0A, 0x00,
10620 0xC2, 0x88, 0x4E, 0x00, 0x07, 0xA3, 0x6E, 0x01, 0x00, 0x33, 0x0B, 0x00, 0xC2, 0x88, 0xCD, 0x04,
10621 0x36, 0x2D, 0x00, 0x33, 0x1A, 0x00, 0xC2, 0x88, 0x50, 0x04, 0x88, 0x81, 0x06, 0xAB, 0x82, 0x01,
10622 0x88, 0x81, 0x4E, 0x00, 0x07, 0xA3, 0x92, 0x01, 0x50, 0x00, 0x00, 0xA3, 0x3C, 0x01, 0x00, 0x05,
10623 0x7C, 0x81, 0x46, 0x97, 0x02, 0x01, 0x05, 0xC6, 0x04, 0x23, 0xA0, 0x01, 0x15, 0x23, 0xA1, 0x01,
10624 0xBE, 0x81, 0xFD, 0x23, 0x02, 0x61, 0x82, 0x01, 0x0A, 0xDA, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA0,
10625 0xB4, 0x01, 0x80, 0x63, 0xCD, 0x04, 0x36, 0x2D, 0x00, 0x33, 0x1B, 0x00, 0xC2, 0x88, 0x06, 0x23,
10626 0x68, 0x98, 0xCD, 0x04, 0xE6, 0x84, 0x06, 0x01, 0x00, 0xA2, 0xD4, 0x01, 0x57, 0x60, 0x00, 0xA0,
10627 0xDA, 0x01, 0xE6, 0x84, 0x80, 0x23, 0xA0, 0x01, 0xE6, 0x84, 0x80, 0x73, 0x4B, 0x00, 0x06, 0x61,
10628 0x00, 0xA2, 0x00, 0x02, 0x04, 0x01, 0x0C, 0xDE, 0x02, 0x01, 0x03, 0xCC, 0x4F, 0x00, 0x84, 0x97,
10629 0xFC, 0x81, 0x08, 0x23, 0x02, 0x41, 0x82, 0x01, 0x4F, 0x00, 0x62, 0x97, 0x48, 0x04, 0x84, 0x80,
10630 0xF0, 0x97, 0x00, 0x46, 0x56, 0x00, 0x03, 0xC0, 0x01, 0x23, 0xE8, 0x00, 0x81, 0x73, 0x06, 0x29,
10631 0x03, 0x42, 0x06, 0xE2, 0x03, 0xEE, 0x6B, 0xEB, 0x11, 0x23, 0xF8, 0x88, 0x04, 0x98, 0xF0, 0x80,
10632 0x80, 0x73, 0x80, 0x77, 0x07, 0xA4, 0x2A, 0x02, 0x7C, 0x95, 0x06, 0xA6, 0x34, 0x02, 0x03, 0xA6,
10633 0x4C, 0x04, 0x46, 0x82, 0x04, 0x01, 0x03, 0xD8, 0xB4, 0x98, 0x6A, 0x96, 0x46, 0x82, 0xFE, 0x95,
10634 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0xB6, 0x2D, 0x02, 0xA6, 0x6C, 0x02, 0x07, 0xA6, 0x5A, 0x02,
10635 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x62, 0x02, 0xC2, 0x88, 0x7C, 0x95, 0x48, 0x82, 0x60, 0x96,
10636 0x48, 0x82, 0x04, 0x23, 0xA0, 0x01, 0x14, 0x23, 0xA1, 0x01, 0x3C, 0x84, 0x04, 0x01, 0x0C, 0xDC,
10637 0xE0, 0x23, 0x25, 0x61, 0xEF, 0x00, 0x14, 0x01, 0x4F, 0x04, 0xA8, 0x01, 0x6F, 0x00, 0xA5, 0x01,
10638 0x03, 0x23, 0xA4, 0x01, 0x06, 0x23, 0x9C, 0x01, 0x24, 0x2B, 0x1C, 0x01, 0x02, 0xA6, 0xAA, 0x02,
10639 0x07, 0xA6, 0x5A, 0x02, 0x06, 0xA6, 0x5E, 0x02, 0x03, 0xA6, 0x20, 0x04, 0x01, 0xA6, 0xB4, 0x02,
10640 0x00, 0xA6, 0xB4, 0x02, 0x00, 0x33, 0x12, 0x00, 0xC2, 0x88, 0x00, 0x0E, 0x80, 0x63, 0x00, 0x43,
10641 0x00, 0xA0, 0x8C, 0x02, 0x4D, 0x04, 0x04, 0x01, 0x0B, 0xDC, 0xE7, 0x23, 0x04, 0x61, 0x84, 0x01,
10642 0x10, 0x31, 0x12, 0x35, 0x14, 0x01, 0xEC, 0x00, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0xEA, 0x82,
10643 0x18, 0x23, 0x04, 0x61, 0x18, 0xA0, 0xE2, 0x02, 0x04, 0x01, 0xA2, 0xC8, 0x00, 0x33, 0x1F, 0x00,
10644 0xC2, 0x88, 0x08, 0x31, 0x0A, 0x35, 0x0C, 0x39, 0x0E, 0x3D, 0x7E, 0x98, 0xB6, 0x2D, 0x01, 0xA6,
10645 0x14, 0x03, 0x00, 0xA6, 0x14, 0x03, 0x07, 0xA6, 0x0C, 0x03, 0x06, 0xA6, 0x10, 0x03, 0x03, 0xA6,
10646 0x20, 0x04, 0x02, 0xA6, 0x6C, 0x02, 0x00, 0x33, 0x33, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0xEE, 0x82,
10647 0x60, 0x96, 0xEE, 0x82, 0x82, 0x98, 0x80, 0x42, 0x7E, 0x98, 0x64, 0xE4, 0x04, 0x01, 0x2D, 0xC8,
10648 0x31, 0x05, 0x07, 0x01, 0x00, 0xA2, 0x54, 0x03, 0x00, 0x43, 0x87, 0x01, 0x05, 0x05, 0x86, 0x98,
10649 0x7E, 0x98, 0x00, 0xA6, 0x16, 0x03, 0x07, 0xA6, 0x4C, 0x03, 0x03, 0xA6, 0x3C, 0x04, 0x06, 0xA6,
10650 0x50, 0x03, 0x01, 0xA6, 0x16, 0x03, 0x00, 0x33, 0x25, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x32, 0x83,
10651 0x60, 0x96, 0x32, 0x83, 0x04, 0x01, 0x10, 0xCE, 0x07, 0xC8, 0x05, 0x05, 0xEB, 0x04, 0x00, 0x33,
10652 0x00, 0x20, 0xC0, 0x20, 0x81, 0x62, 0x72, 0x83, 0x00, 0x01, 0x05, 0x05, 0xFF, 0xA2, 0x7A, 0x03,
10653 0xB1, 0x01, 0x08, 0x23, 0xB2, 0x01, 0x2E, 0x83, 0x05, 0x05, 0x15, 0x01, 0x00, 0xA2, 0x9A, 0x03,
10654 0xEC, 0x00, 0x6E, 0x00, 0x95, 0x01, 0x6C, 0x38, 0x00, 0x3F, 0x00, 0x00, 0x01, 0xA6, 0x96, 0x03,
10655 0x00, 0xA6, 0x96, 0x03, 0x10, 0x84, 0x80, 0x42, 0x7E, 0x98, 0x01, 0xA6, 0xA4, 0x03, 0x00, 0xA6,
10656 0xBC, 0x03, 0x10, 0x84, 0xA8, 0x98, 0x80, 0x42, 0x01, 0xA6, 0xA4, 0x03, 0x07, 0xA6, 0xB2, 0x03,
10657 0xD4, 0x83, 0x7C, 0x95, 0xA8, 0x83, 0x00, 0x33, 0x2F, 0x00, 0xC2, 0x88, 0xA8, 0x98, 0x80, 0x42,
10658 0x00, 0xA6, 0xBC, 0x03, 0x07, 0xA6, 0xCA, 0x03, 0xD4, 0x83, 0x7C, 0x95, 0xC0, 0x83, 0x00, 0x33,
10659 0x26, 0x00, 0xC2, 0x88, 0x38, 0x2B, 0x80, 0x32, 0x80, 0x36, 0x04, 0x23, 0xA0, 0x01, 0x12, 0x23,
10660 0xA1, 0x01, 0x10, 0x84, 0x07, 0xF0, 0x06, 0xA4, 0xF4, 0x03, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23,
10661 0x83, 0x03, 0x80, 0x63, 0x03, 0xA6, 0x0E, 0x04, 0x07, 0xA6, 0x06, 0x04, 0x06, 0xA6, 0x0A, 0x04,
10662 0x00, 0x33, 0x17, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0xF4, 0x83, 0x60, 0x96, 0xF4, 0x83, 0x20, 0x84,
10663 0x07, 0xF0, 0x06, 0xA4, 0x20, 0x04, 0x80, 0x6B, 0x80, 0x67, 0x05, 0x23, 0x83, 0x03, 0x80, 0x63,
10664 0xB6, 0x2D, 0x03, 0xA6, 0x3C, 0x04, 0x07, 0xA6, 0x34, 0x04, 0x06, 0xA6, 0x38, 0x04, 0x00, 0x33,
10665 0x30, 0x00, 0xC2, 0x88, 0x7C, 0x95, 0x20, 0x84, 0x60, 0x96, 0x20, 0x84, 0x1D, 0x01, 0x06, 0xCC,
10666 0x00, 0x33, 0x00, 0x84, 0xC0, 0x20, 0x00, 0x23, 0xEA, 0x00, 0x81, 0x62, 0xA2, 0x0D, 0x80, 0x63,
10667 0x07, 0xA6, 0x5A, 0x04, 0x00, 0x33, 0x18, 0x00, 0xC2, 0x88, 0x03, 0x03, 0x80, 0x63, 0xA3, 0x01,
10668 0x07, 0xA4, 0x64, 0x04, 0x23, 0x01, 0x00, 0xA2, 0x86, 0x04, 0x0A, 0xA0, 0x76, 0x04, 0xE0, 0x00,
10669 0x00, 0x33, 0x1D, 0x00, 0xC2, 0x88, 0x0B, 0xA0, 0x82, 0x04, 0xE0, 0x00, 0x00, 0x33, 0x1E, 0x00,
10670 0xC2, 0x88, 0x42, 0x23, 0xF8, 0x88, 0x00, 0x23, 0x22, 0xA3, 0xE6, 0x04, 0x08, 0x23, 0x22, 0xA3,
10671 0xA2, 0x04, 0x28, 0x23, 0x22, 0xA3, 0xAE, 0x04, 0x02, 0x23, 0x22, 0xA3, 0xC4, 0x04, 0x42, 0x23,
10672 0xF8, 0x88, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA0, 0xAE, 0x04, 0x45, 0x23, 0xF8, 0x88, 0x04, 0x98,
10673 0x00, 0xA2, 0xC0, 0x04, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x82, 0xC0, 0x20, 0x81, 0x62, 0xE8, 0x81,
10674 0x47, 0x23, 0xF8, 0x88, 0x04, 0x01, 0x0B, 0xDE, 0x04, 0x98, 0xB4, 0x98, 0x00, 0x33, 0x00, 0x81,
10675 0xC0, 0x20, 0x81, 0x62, 0x14, 0x01, 0x00, 0xA0, 0x00, 0x02, 0x43, 0x23, 0xF8, 0x88, 0x04, 0x23,
10676 0xA0, 0x01, 0x44, 0x23, 0xA1, 0x01, 0x80, 0x73, 0x4D, 0x00, 0x03, 0xA3, 0xF4, 0x04, 0x00, 0x33,
10677 0x27, 0x00, 0xC2, 0x88, 0x04, 0x01, 0x04, 0xDC, 0x02, 0x23, 0xA2, 0x01, 0x04, 0x23, 0xA0, 0x01,
10678 0x04, 0x98, 0x26, 0x95, 0x4B, 0x00, 0xF6, 0x00, 0x4F, 0x04, 0x4F, 0x00, 0x00, 0xA3, 0x22, 0x05,
10679 0x00, 0x05, 0x76, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x1C, 0x05, 0x0A, 0x85, 0x46, 0x97, 0xCD, 0x04,
10680 0x24, 0x85, 0x48, 0x04, 0x84, 0x80, 0x02, 0x01, 0x03, 0xDA, 0x80, 0x23, 0x82, 0x01, 0x34, 0x85,
10681 0x02, 0x23, 0xA0, 0x01, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0x40, 0x05, 0x1D, 0x01, 0x04, 0xD6,
10682 0xFF, 0x23, 0x86, 0x41, 0x4B, 0x60, 0xCB, 0x00, 0xFF, 0x23, 0x80, 0x01, 0x49, 0x00, 0x81, 0x01,
10683 0x04, 0x01, 0x02, 0xC8, 0x30, 0x01, 0x80, 0x01, 0xF7, 0x04, 0x03, 0x01, 0x49, 0x04, 0x80, 0x01,
10684 0xC9, 0x00, 0x00, 0x05, 0x00, 0x01, 0xFF, 0xA0, 0x60, 0x05, 0x77, 0x04, 0x01, 0x23, 0xEA, 0x00,
10685 0x5D, 0x00, 0xFE, 0xC7, 0x00, 0x62, 0x00, 0x23, 0xEA, 0x00, 0x00, 0x63, 0x07, 0xA4, 0xF8, 0x05,
10686 0x03, 0x03, 0x02, 0xA0, 0x8E, 0x05, 0xF4, 0x85, 0x00, 0x33, 0x2D, 0x00, 0xC2, 0x88, 0x04, 0xA0,
10687 0xB8, 0x05, 0x80, 0x63, 0x00, 0x23, 0xDF, 0x00, 0x4A, 0x00, 0x06, 0x61, 0x00, 0xA2, 0xA4, 0x05,
10688 0x1D, 0x01, 0x06, 0xD6, 0x02, 0x23, 0x02, 0x41, 0x82, 0x01, 0x50, 0x00, 0x62, 0x97, 0x04, 0x85,
10689 0x04, 0x23, 0x02, 0x41, 0x82, 0x01, 0x04, 0x85, 0x08, 0xA0, 0xBE, 0x05, 0xF4, 0x85, 0x03, 0xA0,
10690 0xC4, 0x05, 0xF4, 0x85, 0x01, 0xA0, 0xCE, 0x05, 0x88, 0x00, 0x80, 0x63, 0xCC, 0x86, 0x07, 0xA0,
10691 0xEE, 0x05, 0x5F, 0x00, 0x00, 0x2B, 0xDF, 0x08, 0x00, 0xA2, 0xE6, 0x05, 0x80, 0x67, 0x80, 0x63,
10692 0x01, 0xA2, 0x7A, 0x06, 0x7C, 0x85, 0x06, 0x23, 0x68, 0x98, 0x48, 0x23, 0xF8, 0x88, 0x07, 0x23,
10693 0x80, 0x00, 0x06, 0x87, 0x80, 0x63, 0x7C, 0x85, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63, 0x4A, 0x00,
10694 0x06, 0x61, 0x00, 0xA2, 0x36, 0x06, 0x1D, 0x01, 0x16, 0xD4, 0xC0, 0x23, 0x07, 0x41, 0x83, 0x03,
10695 0x80, 0x63, 0x06, 0xA6, 0x1C, 0x06, 0x00, 0x33, 0x37, 0x00, 0xC2, 0x88, 0x1D, 0x01, 0x01, 0xD6,
10696 0x20, 0x23, 0x63, 0x60, 0x83, 0x03, 0x80, 0x63, 0x02, 0x23, 0xDF, 0x00, 0x07, 0xA6, 0x7C, 0x05,
10697 0xEF, 0x04, 0x6F, 0x00, 0x00, 0x63, 0x4B, 0x00, 0x06, 0x41, 0xCB, 0x00, 0x52, 0x00, 0x06, 0x61,
10698 0x00, 0xA2, 0x4E, 0x06, 0x1D, 0x01, 0x03, 0xCA, 0xC0, 0x23, 0x07, 0x41, 0x00, 0x63, 0x1D, 0x01,
10699 0x04, 0xCC, 0x00, 0x33, 0x00, 0x83, 0xC0, 0x20, 0x81, 0x62, 0x80, 0x23, 0x07, 0x41, 0x00, 0x63,
10700 0x80, 0x67, 0x08, 0x23, 0x83, 0x03, 0x80, 0x63, 0x00, 0x63, 0x01, 0x23, 0xDF, 0x00, 0x06, 0xA6,
10701 0x84, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67, 0x80, 0x63, 0x00, 0x33, 0x00, 0x40, 0xC0, 0x20,
10702 0x81, 0x62, 0x00, 0x63, 0x00, 0x00, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6, 0x94, 0x06,
10703 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x00, 0x01, 0xA0, 0x14, 0x07, 0x00, 0x2B, 0x40, 0x0E, 0x80, 0x63,
10704 0x01, 0x00, 0x06, 0xA6, 0xAA, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x40, 0x0E, 0x80, 0x63, 0x00, 0x43,
10705 0x00, 0xA0, 0xA2, 0x06, 0x06, 0xA6, 0xBC, 0x06, 0x07, 0xA6, 0x7C, 0x05, 0x80, 0x67, 0x40, 0x0E,
10706 0x80, 0x63, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x23, 0xDF, 0x00, 0x00, 0x63, 0x07, 0xA6, 0xD6, 0x06,
10707 0x00, 0x33, 0x2A, 0x00, 0xC2, 0x88, 0x03, 0x03, 0x80, 0x63, 0x89, 0x00, 0x0A, 0x2B, 0x07, 0xA6,
10708 0xE8, 0x06, 0x00, 0x33, 0x29, 0x00, 0xC2, 0x88, 0x00, 0x43, 0x00, 0xA2, 0xF4, 0x06, 0xC0, 0x0E,
10709 0x80, 0x63, 0xDE, 0x86, 0xC0, 0x0E, 0x00, 0x33, 0x00, 0x80, 0xC0, 0x20, 0x81, 0x62, 0x04, 0x01,
10710 0x02, 0xDA, 0x80, 0x63, 0x7C, 0x85, 0x80, 0x7B, 0x80, 0x63, 0x06, 0xA6, 0x8C, 0x06, 0x00, 0x33,
10711 0x2C, 0x00, 0xC2, 0x88, 0x0C, 0xA2, 0x2E, 0x07, 0xFE, 0x95, 0x83, 0x03, 0x80, 0x63, 0x06, 0xA6,
10712 0x2C, 0x07, 0x07, 0xA6, 0x7C, 0x05, 0x00, 0x33, 0x3D, 0x00, 0xC2, 0x88, 0x00, 0x00, 0x80, 0x67,
10713 0x83, 0x03, 0x80, 0x63, 0x0C, 0xA0, 0x44, 0x07, 0x07, 0xA6, 0x7C, 0x05, 0xBF, 0x23, 0x04, 0x61,
10714 0x84, 0x01, 0xE6, 0x84, 0x00, 0x63, 0xF0, 0x04, 0x01, 0x01, 0xF1, 0x00, 0x00, 0x01, 0xF2, 0x00,
10715 0x01, 0x05, 0x80, 0x01, 0x72, 0x04, 0x71, 0x00, 0x81, 0x01, 0x70, 0x04, 0x80, 0x05, 0x81, 0x05,
10716 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04, 0x01, 0x01, 0xF1, 0x00, 0x70, 0x00, 0x81, 0x01,
10717 0x70, 0x04, 0x71, 0x00, 0x81, 0x01, 0x72, 0x00, 0x80, 0x01, 0x71, 0x04, 0x70, 0x00, 0x80, 0x01,
10718 0x70, 0x04, 0x00, 0x63, 0xF0, 0x04, 0xF2, 0x00, 0x72, 0x04, 0x00, 0x01, 0xF1, 0x00, 0x70, 0x00,
10719 0x80, 0x01, 0x70, 0x04, 0x71, 0x00, 0x80, 0x01, 0x72, 0x00, 0x81, 0x01, 0x71, 0x04, 0x70, 0x00,
10720 0x81, 0x01, 0x70, 0x04, 0x00, 0x63, 0x00, 0x23, 0xB3, 0x01, 0x83, 0x05, 0xA3, 0x01, 0xA2, 0x01,
10721 0xA1, 0x01, 0x01, 0x23, 0xA0, 0x01, 0x00, 0x01, 0xC8, 0x00, 0x03, 0xA1, 0xC4, 0x07, 0x00, 0x33,
10722 0x07, 0x00, 0xC2, 0x88, 0x80, 0x05, 0x81, 0x05, 0x04, 0x01, 0x11, 0xC8, 0x48, 0x00, 0xB0, 0x01,
10723 0xB1, 0x01, 0x08, 0x23, 0xB2, 0x01, 0x05, 0x01, 0x48, 0x04, 0x00, 0x43, 0x00, 0xA2, 0xE4, 0x07,
10724 0x00, 0x05, 0xDA, 0x87, 0x00, 0x01, 0xC8, 0x00, 0xFF, 0x23, 0x80, 0x01, 0x05, 0x05, 0x00, 0x63,
10725 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04, 0x00, 0x02, 0x80, 0x43, 0x76, 0x08, 0x80, 0x02,
10726 0x77, 0x04, 0x00, 0x63, 0xF7, 0x04, 0x1A, 0x09, 0xF6, 0x08, 0x6E, 0x04, 0x00, 0x02, 0x00, 0xA0,
10727 0x14, 0x08, 0x16, 0x88, 0x00, 0x43, 0x76, 0x08, 0x80, 0x02, 0x77, 0x04, 0x00, 0x63, 0xF3, 0x04,
10728 0x00, 0x23, 0xF4, 0x00, 0x74, 0x00, 0x80, 0x43, 0xF4, 0x00, 0xCF, 0x40, 0x00, 0xA2, 0x44, 0x08,
10729 0x74, 0x04, 0x02, 0x01, 0xF7, 0xC9, 0xF6, 0xD9, 0x00, 0x01, 0x01, 0xA1, 0x24, 0x08, 0x04, 0x98,
10730 0x26, 0x95, 0x24, 0x88, 0x73, 0x04, 0x00, 0x63, 0xF3, 0x04, 0x75, 0x04, 0x5A, 0x88, 0x02, 0x01,
10731 0x04, 0xD8, 0x46, 0x97, 0x04, 0x98, 0x26, 0x95, 0x4A, 0x88, 0x75, 0x00, 0x00, 0xA3, 0x64, 0x08,
10732 0x00, 0x05, 0x4E, 0x88, 0x73, 0x04, 0x00, 0x63, 0x80, 0x7B, 0x80, 0x63, 0x06, 0xA6, 0x76, 0x08,
10733 0x00, 0x33, 0x3E, 0x00, 0xC2, 0x88, 0x80, 0x67, 0x83, 0x03, 0x80, 0x63, 0x00, 0x63, 0x38, 0x2B,
10734 0x9C, 0x88, 0x38, 0x2B, 0x92, 0x88, 0x32, 0x09, 0x31, 0x05, 0x92, 0x98, 0x05, 0x05, 0xB2, 0x09,
10735 0x00, 0x63, 0x00, 0x32, 0x00, 0x36, 0x00, 0x3A, 0x00, 0x3E, 0x00, 0x63, 0x80, 0x32, 0x80, 0x36,
10736 0x80, 0x3A, 0x80, 0x3E, 0xB4, 0x3D, 0x00, 0x63, 0x38, 0x2B, 0x40, 0x32, 0x40, 0x36, 0x40, 0x3A,
10737 0x40, 0x3E, 0x00, 0x63, 0x5A, 0x20, 0xC9, 0x40, 0x00, 0xA0, 0xB4, 0x08, 0x5D, 0x00, 0xFE, 0xC3,
10738 0x00, 0x63, 0x80, 0x73, 0xE6, 0x20, 0x02, 0x23, 0xE8, 0x00, 0x82, 0x73, 0xFF, 0xFD, 0x80, 0x73,
10739 0x13, 0x23, 0xF8, 0x88, 0x66, 0x20, 0xC0, 0x20, 0x04, 0x23, 0xA0, 0x01, 0xA1, 0x23, 0xA1, 0x01,
10740 0x81, 0x62, 0xE2, 0x88, 0x80, 0x73, 0x80, 0x77, 0x68, 0x00, 0x00, 0xA2, 0x80, 0x00, 0x03, 0xC2,
10741 0xF1, 0xC7, 0x41, 0x23, 0xF8, 0x88, 0x11, 0x23, 0xA1, 0x01, 0x04, 0x23, 0xA0, 0x01, 0xE6, 0x84,
10744 STATIC ushort _asc_mcode_size = sizeof(_asc_mcode_buf);
10745 STATIC ADV_DCNT _asc_mcode_chksum = 0x012C453FUL;
10747 #define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16
10748 STATIC uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] =
10770 ASC_DVC_VAR *asc_dvc,
10775 ulong last_int_level;
10778 int disable_syn_offset_one_fix;
10781 ASC_EXE_CALLBACK asc_exe_callback;
10782 ushort sg_entry_cnt = 0;
10783 ushort sg_entry_cnt_minus_one = 0;
10790 ASC_SG_HEAD *sg_head;
10793 iop_base = asc_dvc->iop_base;
10794 sg_head = scsiq->sg_head;
10795 asc_exe_callback = asc_dvc->exe_callback;
10796 if (asc_dvc->err_code != 0)
10798 if (scsiq == (ASC_SCSI_Q *) 0L) {
10799 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_SCSIQ_NULL_PTR);
10802 scsiq->q1.q_no = 0;
10803 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
10804 scsiq->q1.extra_bytes = 0;
10807 target_ix = scsiq->q2.target_ix;
10808 tid_no = ASC_TIX_TO_TID(target_ix);
10810 if (scsiq->cdbptr[0] == REQUEST_SENSE) {
10811 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
10812 asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
10813 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
10814 AscMsgOutSDTR(asc_dvc,
10815 asc_dvc->sdtr_period_tbl[(sdtr_data >> 4) &
10816 (uchar) (asc_dvc->max_sdtr_index - 1)],
10817 (uchar) (sdtr_data & (uchar) ASC_SYN_MAX_OFFSET));
10818 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
10821 last_int_level = DvcEnterCritical();
10822 if (asc_dvc->in_critical_cnt != 0) {
10823 DvcLeaveCritical(last_int_level);
10824 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
10827 asc_dvc->in_critical_cnt++;
10828 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
10829 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
10830 asc_dvc->in_critical_cnt--;
10831 DvcLeaveCritical(last_int_level);
10834 #if !CC_VERY_LONG_SG_LIST
10835 if (sg_entry_cnt > ASC_MAX_SG_LIST)
10837 asc_dvc->in_critical_cnt--;
10838 DvcLeaveCritical(last_int_level);
10841 #endif /* !CC_VERY_LONG_SG_LIST */
10842 if (sg_entry_cnt == 1) {
10843 scsiq->q1.data_addr = (ADV_PADDR) sg_head->sg_list[0].addr;
10844 scsiq->q1.data_cnt = (ADV_DCNT) sg_head->sg_list[0].bytes;
10845 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
10847 sg_entry_cnt_minus_one = sg_entry_cnt - 1;
10849 scsi_cmd = scsiq->cdbptr[0];
10850 disable_syn_offset_one_fix = FALSE;
10851 if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
10852 !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
10853 if (scsiq->q1.cntl & QC_SG_HEAD) {
10855 for (i = 0; i < sg_entry_cnt; i++) {
10856 data_cnt += (ADV_DCNT) le32_to_cpu(sg_head->sg_list[i].bytes);
10859 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
10861 if (data_cnt != 0UL) {
10862 if (data_cnt < 512UL) {
10863 disable_syn_offset_one_fix = TRUE;
10865 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST; i++) {
10866 disable_cmd = _syn_offset_one_disable_cmd[i];
10867 if (disable_cmd == 0xFF) {
10870 if (scsi_cmd == disable_cmd) {
10871 disable_syn_offset_one_fix = TRUE;
10878 if (disable_syn_offset_one_fix) {
10879 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG;
10880 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
10881 ASC_TAG_FLAG_DISABLE_DISCONNECT);
10883 scsiq->q2.tag_code &= 0x27;
10885 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
10886 if (asc_dvc->bug_fix_cntl) {
10887 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
10888 if ((scsi_cmd == READ_6) ||
10889 (scsi_cmd == READ_10)) {
10891 (ADV_PADDR) le32_to_cpu(
10892 sg_head->sg_list[sg_entry_cnt_minus_one].addr) +
10893 (ADV_DCNT) le32_to_cpu(
10894 sg_head->sg_list[sg_entry_cnt_minus_one].bytes);
10895 extra_bytes = (uchar) ((ushort) addr & 0x0003);
10896 if ((extra_bytes != 0) &&
10897 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES)
10899 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES;
10900 scsiq->q1.extra_bytes = extra_bytes;
10901 data_cnt = le32_to_cpu(
10902 sg_head->sg_list[sg_entry_cnt_minus_one].bytes);
10903 data_cnt -= (ASC_DCNT) extra_bytes;
10904 sg_head->sg_list[sg_entry_cnt_minus_one].bytes =
10905 cpu_to_le32(data_cnt);
10910 sg_head->entry_to_copy = sg_head->entry_cnt;
10911 #if CC_VERY_LONG_SG_LIST
10913 * Set the sg_entry_cnt to the maximum possible. The rest of
10914 * the SG elements will be copied when the RISC completes the
10915 * SG elements that fit and halts.
10917 if (sg_entry_cnt > ASC_MAX_SG_LIST)
10919 sg_entry_cnt = ASC_MAX_SG_LIST;
10921 #endif /* CC_VERY_LONG_SG_LIST */
10922 n_q_required = AscSgListToQueue(sg_entry_cnt);
10923 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
10924 (uint) n_q_required) || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
10925 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
10926 n_q_required)) == 1) {
10927 asc_dvc->in_critical_cnt--;
10928 if (asc_exe_callback != 0) {
10929 (*asc_exe_callback) (asc_dvc, scsiq);
10931 DvcLeaveCritical(last_int_level);
10936 if (asc_dvc->bug_fix_cntl) {
10937 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
10938 if ((scsi_cmd == READ_6) ||
10939 (scsi_cmd == READ_10)) {
10940 addr = le32_to_cpu(scsiq->q1.data_addr) +
10941 le32_to_cpu(scsiq->q1.data_cnt);
10942 extra_bytes = (uchar) ((ushort) addr & 0x0003);
10943 if ((extra_bytes != 0) &&
10944 ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES)
10946 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
10947 if (((ushort) data_cnt & 0x01FF) == 0) {
10948 scsiq->q2.tag_code |= ASC_TAG_FLAG_EXTRA_BYTES;
10949 data_cnt -= (ASC_DCNT) extra_bytes;
10950 scsiq->q1.data_cnt = cpu_to_le32(data_cnt);
10951 scsiq->q1.extra_bytes = extra_bytes;
10958 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
10959 ((scsiq->q1.cntl & QC_URGENT) != 0)) {
10960 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
10961 n_q_required)) == 1) {
10962 asc_dvc->in_critical_cnt--;
10963 if (asc_exe_callback != 0) {
10964 (*asc_exe_callback) (asc_dvc, scsiq);
10966 DvcLeaveCritical(last_int_level);
10971 asc_dvc->in_critical_cnt--;
10972 DvcLeaveCritical(last_int_level);
10978 ASC_DVC_VAR *asc_dvc,
10990 iop_base = asc_dvc->iop_base;
10991 target_ix = scsiq->q2.target_ix;
10992 tid_no = ASC_TIX_TO_TID(target_ix);
10994 free_q_head = (uchar) AscGetVarFreeQHead(iop_base);
10995 if (n_q_required > 1) {
10996 if ((next_qp = AscAllocMultipleFreeQueue(iop_base,
10997 free_q_head, (uchar) (n_q_required)))
10998 != (uchar) ASC_QLINK_END) {
10999 asc_dvc->last_q_shortage = 0;
11000 scsiq->sg_head->queue_cnt = n_q_required - 1;
11001 scsiq->q1.q_no = free_q_head;
11002 if ((sta = AscPutReadySgListQueue(asc_dvc, scsiq,
11003 free_q_head)) == 1) {
11004 AscPutVarFreeQHead(iop_base, next_qp);
11005 asc_dvc->cur_total_qng += (uchar) (n_q_required);
11006 asc_dvc->cur_dvc_qng[tid_no]++;
11010 } else if (n_q_required == 1) {
11011 if ((next_qp = AscAllocFreeQueue(iop_base,
11012 free_q_head)) != ASC_QLINK_END) {
11013 scsiq->q1.q_no = free_q_head;
11014 if ((sta = AscPutReadyQueue(asc_dvc, scsiq,
11015 free_q_head)) == 1) {
11016 AscPutVarFreeQHead(iop_base, next_qp);
11017 asc_dvc->cur_total_qng++;
11018 asc_dvc->cur_dvc_qng[tid_no]++;
11033 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
11034 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
11036 return (n_sg_list_qs + 1);
11041 AscGetNumOfFreeQueue(
11042 ASC_DVC_VAR *asc_dvc,
11049 ASC_SCSI_BIT_ID_TYPE target_id;
11052 target_id = ASC_TIX_TO_TARGET_ID(target_ix);
11053 tid_no = ASC_TIX_TO_TID(target_ix);
11054 if ((asc_dvc->unit_not_ready & target_id) ||
11055 (asc_dvc->queue_full_or_busy & target_id)) {
11059 cur_used_qs = (uint) asc_dvc->cur_total_qng +
11060 (uint) asc_dvc->last_q_shortage +
11061 (uint) ASC_MIN_FREE_Q;
11063 cur_used_qs = (uint) asc_dvc->cur_total_qng +
11064 (uint) ASC_MIN_FREE_Q;
11066 if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
11067 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
11068 if (asc_dvc->cur_dvc_qng[tid_no] >=
11069 asc_dvc->max_dvc_qng[tid_no]) {
11072 return (cur_free_qs);
11075 if ((n_qs > asc_dvc->last_q_shortage) && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
11076 asc_dvc->last_q_shortage = n_qs;
11084 ASC_DVC_VAR *asc_dvc,
11092 uchar syn_period_ix;
11096 iop_base = asc_dvc->iop_base;
11097 if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
11098 ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
11099 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
11100 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
11101 syn_period_ix = (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
11102 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
11103 AscMsgOutSDTR(asc_dvc,
11104 asc_dvc->sdtr_period_tbl[syn_period_ix],
11106 scsiq->q1.cntl |= QC_MSG_OUT;
11108 q_addr = ASC_QNO_TO_QADDR(q_no);
11109 if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
11110 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG ;
11112 scsiq->q1.status = QS_FREE;
11113 AscMemWordCopyPtrToLram(iop_base,
11114 q_addr + ASC_SCSIQ_CDB_BEG,
11115 (uchar *) scsiq->cdbptr,
11116 scsiq->q2.cdb_len >> 1);
11118 DvcPutScsiQ(iop_base,
11119 q_addr + ASC_SCSIQ_CPY_BEG,
11120 (uchar *) &scsiq->q1.cntl,
11121 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
11122 AscWriteLramWord(iop_base,
11123 (ushort) (q_addr + (ushort) ASC_SCSIQ_B_STATUS),
11124 (ushort) (((ushort) scsiq->q1.q_no << 8) | (ushort) QS_READY));
11129 AscPutReadySgListQueue(
11130 ASC_DVC_VAR *asc_dvc,
11137 ASC_SG_HEAD *sg_head;
11138 ASC_SG_LIST_Q scsi_sg_q;
11139 ASC_DCNT saved_data_addr;
11140 ASC_DCNT saved_data_cnt;
11142 ushort sg_list_dwords;
11144 ushort sg_entry_cnt;
11148 iop_base = asc_dvc->iop_base;
11149 sg_head = scsiq->sg_head;
11150 saved_data_addr = scsiq->q1.data_addr;
11151 saved_data_cnt = scsiq->q1.data_cnt;
11152 scsiq->q1.data_addr = (ASC_PADDR) sg_head->sg_list[0].addr;
11153 scsiq->q1.data_cnt = (ASC_DCNT) sg_head->sg_list[0].bytes;
11154 #if CC_VERY_LONG_SG_LIST
11156 * If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST
11157 * then not all SG elements will fit in the allocated queues.
11158 * The rest of the SG elements will be copied when the RISC
11159 * completes the SG elements that fit and halts.
11161 if (sg_head->entry_cnt > ASC_MAX_SG_LIST)
11164 * Set sg_entry_cnt to be the number of SG elements that
11165 * will fit in the allocated SG queues. It is minus 1, because
11166 * the first SG element is handled above. ASC_MAX_SG_LIST is
11167 * already inflated by 1 to account for this. For example it
11168 * may be 50 which is 1 + 7 queues * 7 SG elements.
11170 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
11173 * Keep track of remaining number of SG elements that will
11174 * need to be handled from a_isr.c.
11176 scsiq->remain_sg_entry_cnt = sg_head->entry_cnt - ASC_MAX_SG_LIST;
11179 #endif /* CC_VERY_LONG_SG_LIST */
11181 * Set sg_entry_cnt to be the number of SG elements that
11182 * will fit in the allocated SG queues. It is minus 1, because
11183 * the first SG element is handled above.
11185 sg_entry_cnt = sg_head->entry_cnt - 1;
11186 #if CC_VERY_LONG_SG_LIST
11188 #endif /* CC_VERY_LONG_SG_LIST */
11189 if (sg_entry_cnt != 0) {
11190 scsiq->q1.cntl |= QC_SG_HEAD;
11191 q_addr = ASC_QNO_TO_QADDR(q_no);
11193 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
11194 scsi_sg_q.sg_head_qp = q_no;
11195 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
11196 for (i = 0; i < sg_head->queue_cnt; i++) {
11197 scsi_sg_q.seq_no = i + 1;
11198 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
11199 sg_list_dwords = (uchar) (ASC_SG_LIST_PER_Q * 2);
11200 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
11202 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q;
11203 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q;
11205 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
11206 scsi_sg_q.sg_cur_list_cnt = ASC_SG_LIST_PER_Q - 1;
11209 #if CC_VERY_LONG_SG_LIST
11211 * This is the last SG queue in the list of
11212 * allocated SG queues. If there are more
11213 * SG elements than will fit in the allocated
11214 * queues, then set the QCSG_SG_XFER_MORE flag.
11216 if (sg_head->entry_cnt > ASC_MAX_SG_LIST)
11218 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
11221 #endif /* CC_VERY_LONG_SG_LIST */
11222 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
11223 #if CC_VERY_LONG_SG_LIST
11225 #endif /* CC_VERY_LONG_SG_LIST */
11226 sg_list_dwords = sg_entry_cnt << 1;
11228 scsi_sg_q.sg_list_cnt = sg_entry_cnt;
11229 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt;
11231 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
11232 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
11236 next_qp = AscReadLramByte(iop_base,
11237 (ushort) (q_addr + ASC_SCSIQ_B_FWD));
11238 scsi_sg_q.q_no = next_qp;
11239 q_addr = ASC_QNO_TO_QADDR(next_qp);
11240 AscMemWordCopyPtrToLram(iop_base,
11241 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
11242 (uchar *) &scsi_sg_q,
11243 sizeof(ASC_SG_LIST_Q) >> 1);
11244 AscMemDWordCopyPtrToLram(iop_base,
11245 q_addr + ASC_SGQ_LIST_BEG,
11246 (uchar *) &sg_head->sg_list[sg_index],
11248 sg_index += ASC_SG_LIST_PER_Q;
11249 scsiq->next_sg_index = sg_index;
11252 scsiq->q1.cntl &= ~QC_SG_HEAD;
11254 sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
11255 scsiq->q1.data_addr = saved_data_addr;
11256 scsiq->q1.data_cnt = saved_data_cnt;
11261 AscSetRunChipSynRegAtID(
11269 if (AscHostReqRiscHalt(iop_base)) {
11270 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
11271 AscStartChip(iop_base);
11278 AscSetChipSynRegAtID(
11284 ASC_SCSI_BIT_ID_TYPE org_id;
11288 AscSetBank(iop_base, 1);
11289 org_id = AscReadChipDvcID(iop_base);
11290 for (i = 0; i <= ASC_MAX_TID; i++) {
11291 if (org_id == (0x01 << i))
11294 org_id = (ASC_SCSI_BIT_ID_TYPE) i;
11295 AscWriteChipDvcID(iop_base, id);
11296 if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
11297 AscSetBank(iop_base, 0);
11298 AscSetChipSyn(iop_base, sdtr_data);
11299 if (AscGetChipSyn(iop_base) != sdtr_data) {
11305 AscSetBank(iop_base, 1);
11306 AscWriteChipDvcID(iop_base, org_id);
11307 AscSetBank(iop_base, 0);
11313 ASC_DVC_VAR *asc_dvc
11321 iop_base = asc_dvc->iop_base;
11323 AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
11324 (ushort) (((int) (asc_dvc->max_total_qng + 2 + 1) * 64) >> 1)
11326 i = ASC_MIN_ACTIVE_QNO;
11327 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
11328 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_FWD),
11330 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_BWD),
11331 (uchar) (asc_dvc->max_total_qng));
11332 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_QNO),
11335 s_addr += ASC_QBLK_SIZE;
11336 for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
11337 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_FWD),
11339 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_BWD),
11341 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_QNO),
11344 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_FWD),
11345 (uchar) ASC_QLINK_END);
11346 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_BWD),
11347 (uchar) (asc_dvc->max_total_qng - 1));
11348 AscWriteLramByte(iop_base, (ushort) (s_addr + ASC_SCSIQ_B_QNO),
11349 (uchar) asc_dvc->max_total_qng);
11351 s_addr += ASC_QBLK_SIZE;
11352 for (; i <= (uchar) (asc_dvc->max_total_qng + 3);
11353 i++, s_addr += ASC_QBLK_SIZE) {
11354 AscWriteLramByte(iop_base,
11355 (ushort) (s_addr + (ushort) ASC_SCSIQ_B_FWD), i);
11356 AscWriteLramByte(iop_base,
11357 (ushort) (s_addr + (ushort) ASC_SCSIQ_B_BWD), i);
11358 AscWriteLramByte(iop_base,
11359 (ushort) (s_addr + (ushort) ASC_SCSIQ_B_QNO), i);
11361 return (warn_code);
11366 ASC_DVC_VAR *asc_dvc
11373 iop_base = asc_dvc->iop_base;
11374 AscPutRiscVarFreeQHead(iop_base, 1);
11375 AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
11376 AscPutVarFreeQHead(iop_base, 1);
11377 AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
11378 AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
11379 (uchar) ((int) asc_dvc->max_total_qng + 1));
11380 AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
11381 (uchar) ((int) asc_dvc->max_total_qng + 2));
11382 AscWriteLramByte(iop_base, (ushort) ASCV_TOTAL_READY_Q_B,
11383 asc_dvc->max_total_qng);
11384 AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
11385 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
11386 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
11387 AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
11388 AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
11389 AscPutQDoneInProgress(iop_base, 0);
11390 lram_addr = ASC_QADR_BEG;
11391 for (i = 0; i < 32; i++, lram_addr += 2) {
11392 AscWriteLramWord(iop_base, lram_addr, 0);
11398 AscSetLibErrorCode(
11399 ASC_DVC_VAR *asc_dvc,
11403 if (asc_dvc->err_code == 0) {
11404 asc_dvc->err_code = err_code;
11405 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
11414 ASC_DVC_VAR *asc_dvc,
11420 uchar sdtr_period_index;
11423 iop_base = asc_dvc->iop_base;
11424 sdtr_buf.msg_type = MS_EXTEND;
11425 sdtr_buf.msg_len = MS_SDTR_LEN;
11426 sdtr_buf.msg_req = MS_SDTR_CODE;
11427 sdtr_buf.xfer_period = sdtr_period;
11428 sdtr_offset &= ASC_SYN_MAX_OFFSET;
11429 sdtr_buf.req_ack_offset = sdtr_offset;
11430 if ((sdtr_period_index =
11431 AscGetSynPeriodIndex(asc_dvc, sdtr_period)) <=
11432 asc_dvc->max_sdtr_index) {
11433 AscMemWordCopyPtrToLram(iop_base,
11435 (uchar *) &sdtr_buf,
11436 sizeof (EXT_MSG) >> 1);
11437 return ((sdtr_period_index << 4) | sdtr_offset);
11440 sdtr_buf.req_ack_offset = 0;
11441 AscMemWordCopyPtrToLram(iop_base,
11443 (uchar *) &sdtr_buf,
11444 sizeof (EXT_MSG) >> 1);
11451 ASC_DVC_VAR *asc_dvc,
11457 uchar sdtr_period_ix;
11459 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
11461 (sdtr_period_ix > asc_dvc->max_sdtr_index)
11465 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
11476 AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
11477 AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
11482 AscGetSynPeriodIndex(
11483 ASC_DVC_VAR *asc_dvc,
11487 uchar *period_table;
11492 period_table = asc_dvc->sdtr_period_tbl;
11493 max_index = (int) asc_dvc->max_sdtr_index;
11494 min_index = (int)asc_dvc->host_init_sdtr_index;
11495 if ((syn_time <= period_table[max_index])) {
11496 for (i = min_index; i < (max_index - 1); i++) {
11497 if (syn_time <= period_table[i]) {
11498 return ((uchar) i);
11501 return ((uchar) max_index);
11503 return ((uchar) (max_index + 1));
11517 q_addr = ASC_QNO_TO_QADDR(free_q_head);
11518 q_status = (uchar) AscReadLramByte(iop_base,
11519 (ushort) (q_addr + ASC_SCSIQ_B_STATUS));
11520 next_qp = AscReadLramByte(iop_base,
11521 (ushort) (q_addr + ASC_SCSIQ_B_FWD));
11522 if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END)) {
11525 return (ASC_QLINK_END);
11529 AscAllocMultipleFreeQueue(
11537 for (i = 0; i < n_free_q; i++) {
11538 if ((free_q_head = AscAllocFreeQueue(iop_base, free_q_head))
11539 == ASC_QLINK_END) {
11540 return (ASC_QLINK_END);
11543 return (free_q_head);
11547 AscHostReqRiscHalt(
11553 uchar saved_stop_code;
11555 if (AscIsChipHalted(iop_base))
11557 saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
11558 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
11559 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP
11562 if (AscIsChipHalted(iop_base)) {
11566 DvcSleepMilliSecond(100);
11567 } while (count++ < 20);
11568 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
11579 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
11580 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
11581 ASC_STOP_REQ_RISC_STOP);
11584 AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
11585 ASC_STOP_ACK_RISC_STOP) {
11588 DvcSleepMilliSecond(100);
11589 } while (count++ < 20);
11595 DvcDelayMicroSecond(ADV_DVC_VAR *asc_dvc, ushort micro_sec)
11601 DvcDelayNanoSecond(ASC_DVC_VAR *asc_dvc, ASC_DCNT nano_sec)
11603 udelay((nano_sec + 999)/1000);
11607 STATIC ASC_DCNT __init
11608 AscGetEisaProductID(
11612 ushort product_id_high, product_id_low;
11613 ASC_DCNT product_id;
11615 eisa_iop = ASC_GET_EISA_SLOT(iop_base) | ASC_EISA_PID_IOP_MASK;
11616 product_id_low = inpw(eisa_iop);
11617 product_id_high = inpw(eisa_iop + 2);
11618 product_id = ((ASC_DCNT) product_id_high << 16) |
11619 (ASC_DCNT) product_id_low;
11620 return (product_id);
11623 STATIC PortAddr __init
11624 AscSearchIOPortAddrEISA(
11627 ASC_DCNT eisa_product_id;
11629 if (iop_base == 0) {
11630 iop_base = ASC_EISA_MIN_IOP_ADDR;
11632 if (iop_base == ASC_EISA_MAX_IOP_ADDR)
11634 if ((iop_base & 0x0050) == 0x0050) {
11635 iop_base += ASC_EISA_BIG_IOP_GAP;
11637 iop_base += ASC_EISA_SMALL_IOP_GAP;
11640 while (iop_base <= ASC_EISA_MAX_IOP_ADDR) {
11641 eisa_product_id = AscGetEisaProductID(iop_base);
11642 if ((eisa_product_id == ASC_EISA_ID_740) ||
11643 (eisa_product_id == ASC_EISA_ID_750)) {
11644 if (AscFindSignature(iop_base)) {
11645 inpw(iop_base + 4);
11649 if (iop_base == ASC_EISA_MAX_IOP_ADDR)
11651 if ((iop_base & 0x0050) == 0x0050) {
11652 iop_base += ASC_EISA_BIG_IOP_GAP;
11654 iop_base += ASC_EISA_SMALL_IOP_GAP;
11659 #endif /* CONFIG_ISA */
11666 AscSetChipControl(iop_base, 0);
11667 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
11680 cc_val = AscGetChipControl(iop_base) & (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
11681 AscSetChipControl(iop_base, (uchar) (cc_val | CC_HALT));
11682 AscSetChipIH(iop_base, INS_HALT);
11683 AscSetChipIH(iop_base, INS_RFLAG_WTM);
11684 if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
11695 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
11696 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
11709 AscSetBank(iop_base, 1);
11710 AscWriteChipIH(iop_base, ins_code);
11711 AscSetBank(iop_base, 0);
11726 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
11727 if (loop++ > 0x7FFF) {
11730 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
11731 host_flag = AscReadLramByte(iop_base, ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
11732 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
11733 (uchar) (host_flag | ASC_HOST_FLAG_ACK_INT));
11734 AscSetChipStatus(iop_base, CIW_INT_ACK);
11736 while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
11737 AscSetChipStatus(iop_base, CIW_INT_ACK);
11742 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
11747 AscDisableInterrupt(
11753 cfg = AscGetChipCfgLsw(iop_base);
11754 AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
11759 AscEnableInterrupt(
11765 cfg = AscGetChipCfgLsw(iop_base);
11766 AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
11780 val = AscGetChipControl(iop_base) &
11781 (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET | CC_CHIP_RESET));
11783 val |= CC_BANK_ONE;
11784 } else if (bank == 2) {
11785 val |= CC_DIAG | CC_BANK_ONE;
11787 val &= ~CC_BANK_ONE;
11789 AscSetChipControl(iop_base, val);
11794 AscResetChipAndScsiBus(
11795 ASC_DVC_VAR *asc_dvc
11801 iop_base = asc_dvc->iop_base;
11802 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE) && (i-- > 0))
11804 DvcSleepMilliSecond(100);
11806 AscStopChip(iop_base);
11807 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
11808 DvcDelayNanoSecond(asc_dvc, 60000);
11809 AscSetChipIH(iop_base, INS_RFLAG_WTM);
11810 AscSetChipIH(iop_base, INS_HALT);
11811 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
11812 AscSetChipControl(iop_base, CC_HALT);
11813 DvcSleepMilliSecond(200);
11814 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
11815 AscSetChipStatus(iop_base, 0);
11816 return (AscIsChipHalted(iop_base));
11819 STATIC ASC_DCNT __init
11823 if (bus_type & ASC_IS_ISA)
11824 return (ASC_MAX_ISA_DMA_COUNT);
11825 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
11826 return (ASC_MAX_VL_DMA_COUNT);
11827 return (ASC_MAX_PCI_DMA_COUNT);
11831 STATIC ushort __init
11832 AscGetIsaDmaChannel(
11837 channel = AscGetChipCfgLsw(iop_base) & 0x0003;
11838 if (channel == 0x03)
11840 else if (channel == 0x00)
11842 return (channel + 4);
11845 STATIC ushort __init
11846 AscSetIsaDmaChannel(
11848 ushort dma_channel)
11853 if ((dma_channel >= 5) && (dma_channel <= 7)) {
11854 if (dma_channel == 7)
11857 value = dma_channel - 4;
11858 cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
11860 AscSetChipCfgLsw(iop_base, cfg_lsw);
11861 return (AscGetIsaDmaChannel(iop_base));
11866 STATIC uchar __init
11871 speed_value &= 0x07;
11872 AscSetBank(iop_base, 1);
11873 AscWriteChipDmaSpeed(iop_base, speed_value);
11874 AscSetBank(iop_base, 0);
11875 return (AscGetIsaDmaSpeed(iop_base));
11878 STATIC uchar __init
11885 AscSetBank(iop_base, 1);
11886 speed_value = AscReadChipDmaSpeed(iop_base);
11887 speed_value &= 0x07;
11888 AscSetBank(iop_base, 0);
11889 return (speed_value);
11891 #endif /* CONFIG_ISA */
11893 STATIC ushort __init
11894 AscReadPCIConfigWord(
11895 ASC_DVC_VAR *asc_dvc,
11896 ushort pci_config_offset)
11900 lsb = DvcReadPCIConfigByte(asc_dvc, pci_config_offset);
11901 msb = DvcReadPCIConfigByte(asc_dvc, pci_config_offset + 1);
11902 return ((ushort) ((msb << 8) | lsb));
11905 STATIC ushort __init
11907 ASC_DVC_VAR *asc_dvc
11912 ushort PCIDeviceID;
11913 ushort PCIVendorID;
11914 uchar PCIRevisionID;
11915 uchar prevCmdRegBits;
11918 iop_base = asc_dvc->iop_base;
11919 asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
11920 if (asc_dvc->err_code != 0) {
11923 if (asc_dvc->bus_type == ASC_IS_PCI) {
11924 PCIVendorID = AscReadPCIConfigWord(asc_dvc,
11925 AscPCIConfigVendorIDRegister);
11927 PCIDeviceID = AscReadPCIConfigWord(asc_dvc,
11928 AscPCIConfigDeviceIDRegister);
11930 PCIRevisionID = DvcReadPCIConfigByte(asc_dvc,
11931 AscPCIConfigRevisionIDRegister);
11933 if (PCIVendorID != ASC_PCI_VENDORID) {
11934 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
11936 prevCmdRegBits = DvcReadPCIConfigByte(asc_dvc,
11937 AscPCIConfigCommandRegister);
11939 if ((prevCmdRegBits & AscPCICmdRegBits_IOMemBusMaster) !=
11940 AscPCICmdRegBits_IOMemBusMaster) {
11941 DvcWritePCIConfigByte(asc_dvc,
11942 AscPCIConfigCommandRegister,
11944 AscPCICmdRegBits_IOMemBusMaster));
11946 if ((DvcReadPCIConfigByte(asc_dvc,
11947 AscPCIConfigCommandRegister)
11948 & AscPCICmdRegBits_IOMemBusMaster)
11949 != AscPCICmdRegBits_IOMemBusMaster) {
11950 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
11953 if ((PCIDeviceID == ASC_PCI_DEVICEID_1200A) ||
11954 (PCIDeviceID == ASC_PCI_DEVICEID_1200B)) {
11955 DvcWritePCIConfigByte(asc_dvc,
11956 AscPCIConfigLatencyTimer, 0x00);
11957 if (DvcReadPCIConfigByte(asc_dvc, AscPCIConfigLatencyTimer)
11959 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
11961 } else if (PCIDeviceID == ASC_PCI_DEVICEID_ULTRA) {
11962 if (DvcReadPCIConfigByte(asc_dvc,
11963 AscPCIConfigLatencyTimer) < 0x20) {
11964 DvcWritePCIConfigByte(asc_dvc,
11965 AscPCIConfigLatencyTimer, 0x20);
11967 if (DvcReadPCIConfigByte(asc_dvc,
11968 AscPCIConfigLatencyTimer) < 0x20) {
11969 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
11975 if (AscFindSignature(iop_base)) {
11976 warn_code |= AscInitAscDvcVar(asc_dvc);
11977 warn_code |= AscInitFromEEP(asc_dvc);
11978 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
11979 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT) {
11980 asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
11983 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
11988 STATIC ushort __init
11990 ASC_DVC_VAR *asc_dvc
11993 ushort warn_code = 0;
11995 asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
11996 if (asc_dvc->err_code != 0)
11998 if (AscFindSignature(asc_dvc->iop_base)) {
11999 warn_code |= AscInitFromAscDvcVar(asc_dvc);
12000 asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
12002 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
12004 return (warn_code);
12007 STATIC ushort __init
12008 AscInitFromAscDvcVar(
12009 ASC_DVC_VAR *asc_dvc
12015 ushort pci_device_id = 0;
12017 iop_base = asc_dvc->iop_base;
12019 if (asc_dvc->cfg->dev)
12020 pci_device_id = to_pci_dev(asc_dvc->cfg->dev)->device;
12023 cfg_msw = AscGetChipCfgMsw(iop_base);
12024 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
12025 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK));
12026 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
12027 AscSetChipCfgMsw(iop_base, cfg_msw);
12029 if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
12030 asc_dvc->cfg->cmd_qng_enabled) {
12031 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
12032 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
12034 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
12035 warn_code |= ASC_WARN_AUTO_CONFIG;
12037 if ((asc_dvc->bus_type & (ASC_IS_ISA | ASC_IS_VL)) != 0) {
12038 if (AscSetChipIRQ(iop_base, asc_dvc->irq_no, asc_dvc->bus_type)
12039 != asc_dvc->irq_no) {
12040 asc_dvc->err_code |= ASC_IERR_SET_IRQ_NO;
12043 if (asc_dvc->bus_type & ASC_IS_PCI) {
12045 AscSetChipCfgMsw(iop_base, cfg_msw);
12046 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
12048 if ((pci_device_id == ASC_PCI_DEVICE_ID_REV_A) ||
12049 (pci_device_id == ASC_PCI_DEVICE_ID_REV_B)) {
12050 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
12051 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
12054 } else if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
12055 if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
12056 == ASC_CHIP_VER_ASYN_BUG) {
12057 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
12060 if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
12061 asc_dvc->cfg->chip_scsi_id) {
12062 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
12065 if (asc_dvc->bus_type & ASC_IS_ISA) {
12066 AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
12067 AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
12069 #endif /* CONFIG_ISA */
12070 return (warn_code);
12074 AscInitAsc1000Driver(
12075 ASC_DVC_VAR *asc_dvc
12081 iop_base = asc_dvc->iop_base;
12083 if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
12084 !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
12085 AscResetChipAndScsiBus(asc_dvc);
12086 DvcSleepMilliSecond((ASC_DCNT)
12087 ((ushort) asc_dvc->scsi_reset_wait * 1000));
12089 asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
12090 if (asc_dvc->err_code != 0)
12092 if (!AscFindSignature(asc_dvc->iop_base)) {
12093 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
12094 return (warn_code);
12096 AscDisableInterrupt(iop_base);
12097 warn_code |= AscInitLram(asc_dvc);
12098 if (asc_dvc->err_code != 0)
12100 ASC_DBG1(1, "AscInitAsc1000Driver: _asc_mcode_chksum 0x%lx\n",
12101 (ulong) _asc_mcode_chksum);
12102 if (AscLoadMicroCode(iop_base, 0, _asc_mcode_buf,
12103 _asc_mcode_size) != _asc_mcode_chksum) {
12104 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
12105 return (warn_code);
12107 warn_code |= AscInitMicroCodeVar(asc_dvc);
12108 asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
12109 AscEnableInterrupt(iop_base);
12110 return (warn_code);
12113 STATIC ushort __init
12115 ASC_DVC_VAR *asc_dvc)
12120 uchar chip_version;
12122 iop_base = asc_dvc->iop_base;
12124 asc_dvc->err_code = 0;
12125 if ((asc_dvc->bus_type &
12126 (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
12127 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
12129 AscSetChipControl(iop_base, CC_HALT);
12130 AscSetChipStatus(iop_base, 0);
12131 asc_dvc->bug_fix_cntl = 0;
12132 asc_dvc->pci_fix_asyn_xfer = 0;
12133 asc_dvc->pci_fix_asyn_xfer_always = 0;
12134 /* asc_dvc->init_state initalized in AscInitGetConfig(). */
12135 asc_dvc->sdtr_done = 0;
12136 asc_dvc->cur_total_qng = 0;
12137 asc_dvc->is_in_int = 0;
12138 asc_dvc->in_critical_cnt = 0;
12139 asc_dvc->last_q_shortage = 0;
12140 asc_dvc->use_tagged_qng = 0;
12141 asc_dvc->no_scam = 0;
12142 asc_dvc->unit_not_ready = 0;
12143 asc_dvc->queue_full_or_busy = 0;
12144 asc_dvc->redo_scam = 0;
12146 asc_dvc->host_init_sdtr_index = 0;
12147 asc_dvc->cfg->can_tagged_qng = 0;
12148 asc_dvc->cfg->cmd_qng_enabled = 0;
12149 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
12150 asc_dvc->init_sdtr = 0;
12151 asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
12152 asc_dvc->scsi_reset_wait = 3;
12153 asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
12154 asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
12155 asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
12156 asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
12157 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
12158 asc_dvc->cfg->lib_serial_no = ASC_LIB_SERIAL_NUMBER;
12159 asc_dvc->cfg->lib_version = (ASC_LIB_VERSION_MAJOR << 8) |
12160 ASC_LIB_VERSION_MINOR;
12161 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
12162 asc_dvc->cfg->chip_version = chip_version;
12163 asc_dvc->sdtr_period_tbl[0] = SYN_XFER_NS_0;
12164 asc_dvc->sdtr_period_tbl[1] = SYN_XFER_NS_1;
12165 asc_dvc->sdtr_period_tbl[2] = SYN_XFER_NS_2;
12166 asc_dvc->sdtr_period_tbl[3] = SYN_XFER_NS_3;
12167 asc_dvc->sdtr_period_tbl[4] = SYN_XFER_NS_4;
12168 asc_dvc->sdtr_period_tbl[5] = SYN_XFER_NS_5;
12169 asc_dvc->sdtr_period_tbl[6] = SYN_XFER_NS_6;
12170 asc_dvc->sdtr_period_tbl[7] = SYN_XFER_NS_7;
12171 asc_dvc->max_sdtr_index = 7;
12172 if ((asc_dvc->bus_type & ASC_IS_PCI) &&
12173 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
12174 asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
12175 asc_dvc->sdtr_period_tbl[0] = SYN_ULTRA_XFER_NS_0;
12176 asc_dvc->sdtr_period_tbl[1] = SYN_ULTRA_XFER_NS_1;
12177 asc_dvc->sdtr_period_tbl[2] = SYN_ULTRA_XFER_NS_2;
12178 asc_dvc->sdtr_period_tbl[3] = SYN_ULTRA_XFER_NS_3;
12179 asc_dvc->sdtr_period_tbl[4] = SYN_ULTRA_XFER_NS_4;
12180 asc_dvc->sdtr_period_tbl[5] = SYN_ULTRA_XFER_NS_5;
12181 asc_dvc->sdtr_period_tbl[6] = SYN_ULTRA_XFER_NS_6;
12182 asc_dvc->sdtr_period_tbl[7] = SYN_ULTRA_XFER_NS_7;
12183 asc_dvc->sdtr_period_tbl[8] = SYN_ULTRA_XFER_NS_8;
12184 asc_dvc->sdtr_period_tbl[9] = SYN_ULTRA_XFER_NS_9;
12185 asc_dvc->sdtr_period_tbl[10] = SYN_ULTRA_XFER_NS_10;
12186 asc_dvc->sdtr_period_tbl[11] = SYN_ULTRA_XFER_NS_11;
12187 asc_dvc->sdtr_period_tbl[12] = SYN_ULTRA_XFER_NS_12;
12188 asc_dvc->sdtr_period_tbl[13] = SYN_ULTRA_XFER_NS_13;
12189 asc_dvc->sdtr_period_tbl[14] = SYN_ULTRA_XFER_NS_14;
12190 asc_dvc->sdtr_period_tbl[15] = SYN_ULTRA_XFER_NS_15;
12191 asc_dvc->max_sdtr_index = 15;
12192 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150)
12194 AscSetExtraControl(iop_base,
12195 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
12196 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
12197 AscSetExtraControl(iop_base,
12198 (SEC_ACTIVE_NEGATE | SEC_ENABLE_FILTER));
12201 if (asc_dvc->bus_type == ASC_IS_PCI) {
12202 AscSetExtraControl(iop_base, (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
12205 asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
12206 if (AscGetChipBusType(iop_base) == ASC_IS_ISAPNP) {
12207 AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
12208 asc_dvc->bus_type = ASC_IS_ISAPNP;
12211 if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
12212 asc_dvc->cfg->isa_dma_channel = (uchar) AscGetIsaDmaChannel(iop_base);
12214 #endif /* CONFIG_ISA */
12215 for (i = 0; i <= ASC_MAX_TID; i++) {
12216 asc_dvc->cur_dvc_qng[i] = 0;
12217 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
12218 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *) 0L;
12219 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *) 0L;
12220 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
12222 return (warn_code);
12225 STATIC ushort __init
12226 AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
12228 ASCEEP_CONFIG eep_config_buf;
12229 ASCEEP_CONFIG *eep_config;
12233 ushort cfg_msw, cfg_lsw;
12237 iop_base = asc_dvc->iop_base;
12239 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
12240 AscStopQueueExe(iop_base);
12241 if ((AscStopChip(iop_base) == FALSE) ||
12242 (AscGetChipScsiCtrl(iop_base) != 0)) {
12243 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
12244 AscResetChipAndScsiBus(asc_dvc);
12245 DvcSleepMilliSecond((ASC_DCNT)
12246 ((ushort) asc_dvc->scsi_reset_wait * 1000));
12248 if (AscIsChipHalted(iop_base) == FALSE) {
12249 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
12250 return (warn_code);
12252 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
12253 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
12254 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
12255 return (warn_code);
12257 eep_config = (ASCEEP_CONFIG *) &eep_config_buf;
12258 cfg_msw = AscGetChipCfgMsw(iop_base);
12259 cfg_lsw = AscGetChipCfgLsw(iop_base);
12260 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
12261 cfg_msw &= (~(ASC_CFG_MSW_CLR_MASK));
12262 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
12263 AscSetChipCfgMsw(iop_base, cfg_msw);
12265 chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
12266 ASC_DBG1(1, "AscInitFromEEP: chksum 0x%x\n", chksum);
12270 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
12271 warn_code |= ASC_WARN_AUTO_CONFIG;
12272 if (asc_dvc->cfg->chip_version == 3) {
12273 if (eep_config->cfg_lsw != cfg_lsw) {
12274 warn_code |= ASC_WARN_EEPROM_RECOVER;
12275 eep_config->cfg_lsw = AscGetChipCfgLsw(iop_base);
12277 if (eep_config->cfg_msw != cfg_msw) {
12278 warn_code |= ASC_WARN_EEPROM_RECOVER;
12279 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
12283 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
12284 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
12285 ASC_DBG1(1, "AscInitFromEEP: eep_config->chksum 0x%x\n",
12286 eep_config->chksum);
12287 if (chksum != eep_config->chksum) {
12288 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
12289 ASC_CHIP_VER_PCI_ULTRA_3050 )
12292 "AscInitFromEEP: chksum error ignored; EEPROM-less board\n");
12293 eep_config->init_sdtr = 0xFF;
12294 eep_config->disc_enable = 0xFF;
12295 eep_config->start_motor = 0xFF;
12296 eep_config->use_cmd_qng = 0;
12297 eep_config->max_total_qng = 0xF0;
12298 eep_config->max_tag_qng = 0x20;
12299 eep_config->cntl = 0xBFFF;
12300 ASC_EEP_SET_CHIP_ID(eep_config, 7);
12301 eep_config->no_scam = 0;
12302 eep_config->adapter_info[0] = 0;
12303 eep_config->adapter_info[1] = 0;
12304 eep_config->adapter_info[2] = 0;
12305 eep_config->adapter_info[3] = 0;
12306 eep_config->adapter_info[4] = 0;
12307 /* Indicate EEPROM-less board. */
12308 eep_config->adapter_info[5] = 0xBB;
12311 "AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
12313 warn_code |= ASC_WARN_EEPROM_CHKSUM;
12316 asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
12317 asc_dvc->cfg->disc_enable = eep_config->disc_enable;
12318 asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
12319 asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
12320 asc_dvc->start_motor = eep_config->start_motor;
12321 asc_dvc->dvc_cntl = eep_config->cntl;
12322 asc_dvc->no_scam = eep_config->no_scam;
12323 asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
12324 asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
12325 asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
12326 asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
12327 asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
12328 asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
12329 if (!AscTestExternalLram(asc_dvc)) {
12330 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA)) {
12331 eep_config->max_total_qng = ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
12332 eep_config->max_tag_qng = ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
12334 eep_config->cfg_msw |= 0x0800;
12336 AscSetChipCfgMsw(iop_base, cfg_msw);
12337 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
12338 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
12342 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
12343 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
12345 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
12346 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
12348 if (eep_config->max_tag_qng > eep_config->max_total_qng) {
12349 eep_config->max_tag_qng = eep_config->max_total_qng;
12351 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
12352 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
12354 asc_dvc->max_total_qng = eep_config->max_total_qng;
12355 if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
12356 eep_config->use_cmd_qng) {
12357 eep_config->disc_enable = eep_config->use_cmd_qng;
12358 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
12360 if (asc_dvc->bus_type & (ASC_IS_ISA | ASC_IS_VL | ASC_IS_EISA)) {
12361 asc_dvc->irq_no = AscGetChipIRQ(iop_base, asc_dvc->bus_type);
12363 ASC_EEP_SET_CHIP_ID(eep_config, ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
12364 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
12365 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
12366 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
12367 asc_dvc->host_init_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
12370 for (i = 0; i <= ASC_MAX_TID; i++) {
12371 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
12372 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
12373 asc_dvc->cfg->sdtr_period_offset[i] =
12374 (uchar) (ASC_DEF_SDTR_OFFSET |
12375 (asc_dvc->host_init_sdtr_index << 4));
12377 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
12379 if ((i = AscSetEEPConfig(iop_base, eep_config, asc_dvc->bus_type)) !=
12382 "AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n", i);
12384 ASC_PRINT("AscInitFromEEP: Succesfully re-wrote EEPROM.");
12387 return (warn_code);
12391 AscInitMicroCodeVar(
12392 ASC_DVC_VAR *asc_dvc
12398 ASC_PADDR phy_addr;
12401 iop_base = asc_dvc->iop_base;
12403 for (i = 0; i <= ASC_MAX_TID; i++) {
12404 AscPutMCodeInitSDTRAtID(iop_base, i,
12405 asc_dvc->cfg->sdtr_period_offset[i]
12409 AscInitQLinkVar(asc_dvc);
12410 AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
12411 asc_dvc->cfg->disc_enable);
12412 AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
12413 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
12415 /* Align overrun buffer on an 8 byte boundary. */
12416 phy_addr = virt_to_bus(asc_dvc->cfg->overrun_buf);
12417 phy_addr = cpu_to_le32((phy_addr + 7) & ~0x7);
12418 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
12419 (uchar *) &phy_addr, 1);
12420 phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE - 8);
12421 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
12422 (uchar *) &phy_size, 1);
12424 asc_dvc->cfg->mcode_date =
12425 AscReadLramWord(iop_base, (ushort) ASCV_MC_DATE_W);
12426 asc_dvc->cfg->mcode_version =
12427 AscReadLramWord(iop_base, (ushort) ASCV_MC_VER_W);
12429 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
12430 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
12431 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
12432 return (warn_code);
12434 if (AscStartChip(iop_base) != 1) {
12435 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
12436 return (warn_code);
12439 return (warn_code);
12443 AscTestExternalLram(
12444 ASC_DVC_VAR *asc_dvc)
12451 iop_base = asc_dvc->iop_base;
12453 q_addr = ASC_QNO_TO_QADDR(241);
12454 saved_word = AscReadLramWord(iop_base, q_addr);
12455 AscSetChipLramAddr(iop_base, q_addr);
12456 AscSetChipLramData(iop_base, 0x55AA);
12457 DvcSleepMilliSecond(10);
12458 AscSetChipLramAddr(iop_base, q_addr);
12459 if (AscGetChipLramData(iop_base) == 0x55AA) {
12461 AscWriteLramWord(iop_base, q_addr, saved_word);
12477 AscSetChipEEPCmd(iop_base, cmd_reg);
12478 DvcSleepMilliSecond(1);
12479 read_back = AscGetChipEEPCmd(iop_base);
12480 if (read_back == cmd_reg) {
12483 if (retry++ > ASC_EEP_MAX_RETRY) {
12490 AscWriteEEPDataReg(
12500 AscSetChipEEPData(iop_base, data_reg);
12501 DvcSleepMilliSecond(1);
12502 read_back = AscGetChipEEPData(iop_base);
12503 if (read_back == data_reg) {
12506 if (retry++ > ASC_EEP_MAX_RETRY) {
12513 AscWaitEEPRead(void)
12515 DvcSleepMilliSecond(1);
12520 AscWaitEEPWrite(void)
12522 DvcSleepMilliSecond(20);
12526 STATIC ushort __init
12534 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
12536 cmd_reg = addr | ASC_EEP_CMD_READ;
12537 AscWriteEEPCmdReg(iop_base, cmd_reg);
12539 read_wval = AscGetChipEEPData(iop_base);
12541 return (read_wval);
12544 STATIC ushort __init
12552 read_wval = AscReadEEPWord(iop_base, addr);
12553 if (read_wval != word_val) {
12554 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
12556 AscWriteEEPDataReg(iop_base, word_val);
12558 AscWriteEEPCmdReg(iop_base,
12559 (uchar) ((uchar) ASC_EEP_CMD_WRITE | addr));
12561 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
12563 return (AscReadEEPWord(iop_base, addr));
12565 return (read_wval);
12568 STATIC ushort __init
12571 ASCEEP_CONFIG * cfg_buf, ushort bus_type)
12578 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
12581 wbuf = (ushort *) cfg_buf;
12583 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
12584 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
12585 *wbuf = AscReadEEPWord(iop_base, (uchar) s_addr);
12588 if (bus_type & ASC_IS_VL) {
12589 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
12590 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
12592 cfg_beg = ASC_EEP_DVC_CFG_BEG;
12593 cfg_end = ASC_EEP_MAX_DVC_ADDR;
12595 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
12596 wval = AscReadEEPWord( iop_base, ( uchar )s_addr ) ;
12597 if (s_addr <= uchar_end_in_config) {
12599 * Swap all char fields - must unswap bytes already swapped
12600 * by AscReadEEPWord().
12602 *wbuf = le16_to_cpu(wval);
12604 /* Don't swap word field at the end - cntl field. */
12607 sum += wval; /* Checksum treats all EEPROM data as words. */
12610 * Read the checksum word which will be compared against 'sum'
12611 * by the caller. Word field already swapped.
12613 *wbuf = AscReadEEPWord(iop_base, (uchar) s_addr);
12618 AscSetEEPConfigOnce(
12620 ASCEEP_CONFIG * cfg_buf, ushort bus_type)
12629 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
12632 wbuf = (ushort *) cfg_buf;
12635 /* Write two config words; AscWriteEEPWord() will swap bytes. */
12636 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
12638 if (*wbuf != AscWriteEEPWord(iop_base, (uchar) s_addr, *wbuf)) {
12642 if (bus_type & ASC_IS_VL) {
12643 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
12644 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
12646 cfg_beg = ASC_EEP_DVC_CFG_BEG;
12647 cfg_end = ASC_EEP_MAX_DVC_ADDR;
12649 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
12650 if (s_addr <= uchar_end_in_config) {
12652 * This is a char field. Swap char fields before they are
12653 * swapped again by AscWriteEEPWord().
12655 word = cpu_to_le16(*wbuf);
12656 if (word != AscWriteEEPWord( iop_base, (uchar) s_addr, word)) {
12660 /* Don't swap word field at the end - cntl field. */
12661 if (*wbuf != AscWriteEEPWord(iop_base, (uchar) s_addr, *wbuf)) {
12665 sum += *wbuf; /* Checksum calculated from word values. */
12667 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
12669 if (sum != AscWriteEEPWord(iop_base, (uchar) s_addr, sum)) {
12673 /* Read EEPROM back again. */
12674 wbuf = (ushort *) cfg_buf;
12676 * Read two config words; Byte-swapping done by AscReadEEPWord().
12678 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
12679 if (*wbuf != AscReadEEPWord(iop_base, (uchar) s_addr)) {
12683 if (bus_type & ASC_IS_VL) {
12684 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
12685 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
12687 cfg_beg = ASC_EEP_DVC_CFG_BEG;
12688 cfg_end = ASC_EEP_MAX_DVC_ADDR;
12690 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
12691 if (s_addr <= uchar_end_in_config) {
12693 * Swap all char fields. Must unswap bytes already swapped
12694 * by AscReadEEPWord().
12696 word = le16_to_cpu(AscReadEEPWord(iop_base, (uchar) s_addr));
12698 /* Don't swap word field at the end - cntl field. */
12699 word = AscReadEEPWord(iop_base, (uchar) s_addr);
12701 if (*wbuf != word) {
12705 /* Read checksum; Byte swapping not needed. */
12706 if (AscReadEEPWord(iop_base, (uchar) s_addr) != sum) {
12715 ASCEEP_CONFIG * cfg_buf, ushort bus_type
12723 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
12727 if (++retry > ASC_EEP_MAX_RETRY) {
12736 ASC_DVC_VAR *asc_dvc,
12738 ASC_SCSI_INQUIRY *inq)
12741 ASC_SCSI_BIT_ID_TYPE tid_bits;
12743 dvc_type = ASC_INQ_DVC_TYPE(inq);
12744 tid_bits = ASC_TIX_TO_TARGET_ID(tid_no);
12746 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN)
12748 if (!(asc_dvc->init_sdtr & tid_bits))
12750 if ((dvc_type == TYPE_ROM) &&
12751 (AscCompareString((uchar *) inq->vendor_id,
12752 (uchar *) "HP ", 3) == 0))
12754 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
12756 asc_dvc->pci_fix_asyn_xfer |= tid_bits;
12757 if ((dvc_type == TYPE_PROCESSOR) ||
12758 (dvc_type == TYPE_SCANNER) ||
12759 (dvc_type == TYPE_ROM) ||
12760 (dvc_type == TYPE_TAPE))
12762 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
12765 if (asc_dvc->pci_fix_asyn_xfer & tid_bits)
12767 AscSetRunChipSynRegAtID(asc_dvc->iop_base, tid_no,
12768 ASYN_SDTR_DATA_FIX_PCI_REV_AB);
12776 AscTagQueuingSafe(ASC_SCSI_INQUIRY *inq)
12778 if ((inq->add_len >= 32) &&
12779 (AscCompareString((uchar *) inq->vendor_id,
12780 (uchar *) "QUANTUM XP34301", 15) == 0) &&
12781 (AscCompareString((uchar *) inq->product_rev_level,
12782 (uchar *) "1071", 4) == 0))
12790 AscInquiryHandling(ASC_DVC_VAR *asc_dvc,
12791 uchar tid_no, ASC_SCSI_INQUIRY *inq)
12793 ASC_SCSI_BIT_ID_TYPE tid_bit = ASC_TIX_TO_TARGET_ID(tid_no);
12794 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr, orig_use_tagged_qng;
12796 orig_init_sdtr = asc_dvc->init_sdtr;
12797 orig_use_tagged_qng = asc_dvc->use_tagged_qng;
12799 asc_dvc->init_sdtr &= ~tid_bit;
12800 asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
12801 asc_dvc->use_tagged_qng &= ~tid_bit;
12803 if (ASC_INQ_RESPONSE_FMT(inq) >= 2 || ASC_INQ_ANSI_VER(inq) >= 2) {
12804 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && ASC_INQ_SYNC(inq)) {
12805 asc_dvc->init_sdtr |= tid_bit;
12807 if ((asc_dvc->cfg->cmd_qng_enabled & tid_bit) &&
12808 ASC_INQ_CMD_QUEUE(inq)) {
12809 if (AscTagQueuingSafe(inq)) {
12810 asc_dvc->use_tagged_qng |= tid_bit;
12811 asc_dvc->cfg->can_tagged_qng |= tid_bit;
12815 if (orig_use_tagged_qng != asc_dvc->use_tagged_qng) {
12816 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
12817 asc_dvc->cfg->disc_enable);
12818 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
12819 asc_dvc->use_tagged_qng);
12820 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
12821 asc_dvc->cfg->can_tagged_qng);
12823 asc_dvc->max_dvc_qng[tid_no] =
12824 asc_dvc->cfg->max_tag_qng[tid_no];
12825 AscWriteLramByte(asc_dvc->iop_base,
12826 (ushort) (ASCV_MAX_DVC_QNG_BEG + tid_no),
12827 asc_dvc->max_dvc_qng[tid_no]);
12829 if (orig_init_sdtr != asc_dvc->init_sdtr) {
12830 AscAsyncFix(asc_dvc, tid_no, inq);
12845 for (i = 0; i < len; i++) {
12846 diff = (int) (str1[i] - str2[i]);
12862 if (isodd_word(addr)) {
12863 AscSetChipLramAddr(iop_base, addr - 1);
12864 word_data = AscGetChipLramData(iop_base);
12865 byte_data = (uchar) ((word_data >> 8) & 0xFF);
12867 AscSetChipLramAddr(iop_base, addr);
12868 word_data = AscGetChipLramData(iop_base);
12869 byte_data = (uchar) (word_data & 0xFF);
12871 return (byte_data);
12881 AscSetChipLramAddr(iop_base, addr);
12882 word_data = AscGetChipLramData(iop_base);
12883 return (word_data);
12886 #if CC_VERY_LONG_SG_LIST
12893 ushort val_low, val_high;
12894 ASC_DCNT dword_data;
12896 AscSetChipLramAddr(iop_base, addr);
12897 val_low = AscGetChipLramData(iop_base);
12898 val_high = AscGetChipLramData(iop_base);
12899 dword_data = ((ASC_DCNT) val_high << 16) | (ASC_DCNT) val_low;
12900 return (dword_data);
12902 #endif /* CC_VERY_LONG_SG_LIST */
12911 AscSetChipLramAddr(iop_base, addr);
12912 AscSetChipLramData(iop_base, word_val);
12925 if (isodd_word(addr)) {
12927 word_data = AscReadLramWord(iop_base, addr);
12928 word_data &= 0x00FF;
12929 word_data |= (((ushort) byte_val << 8) & 0xFF00);
12931 word_data = AscReadLramWord(iop_base, addr);
12932 word_data &= 0xFF00;
12933 word_data |= ((ushort) byte_val & 0x00FF);
12935 AscWriteLramWord(iop_base, addr, word_data);
12940 * Copy 2 bytes to LRAM.
12942 * The source data is assumed to be in little-endian order in memory
12943 * and is maintained in little-endian order when written to LRAM.
12946 AscMemWordCopyPtrToLram(
12955 AscSetChipLramAddr(iop_base, s_addr);
12956 for (i = 0; i < 2 * words; i += 2) {
12958 * On a little-endian system the second argument below
12959 * produces a little-endian ushort which is written to
12960 * LRAM in little-endian order. On a big-endian system
12961 * the second argument produces a big-endian ushort which
12962 * is "transparently" byte-swapped by outpw() and written
12963 * in little-endian order to LRAM.
12965 outpw(iop_base + IOP_RAM_DATA,
12966 ((ushort) s_buffer[i + 1] << 8) | s_buffer[i]);
12972 * Copy 4 bytes to LRAM.
12974 * The source data is assumed to be in little-endian order in memory
12975 * and is maintained in little-endian order when writen to LRAM.
12978 AscMemDWordCopyPtrToLram(
12987 AscSetChipLramAddr(iop_base, s_addr);
12988 for (i = 0; i < 4 * dwords; i += 4) {
12989 outpw(iop_base + IOP_RAM_DATA,
12990 ((ushort) s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */
12991 outpw(iop_base + IOP_RAM_DATA,
12992 ((ushort) s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */
12998 * Copy 2 bytes from LRAM.
13000 * The source data is assumed to be in little-endian order in LRAM
13001 * and is maintained in little-endian order when written to memory.
13004 AscMemWordCopyPtrFromLram(
13014 AscSetChipLramAddr(iop_base, s_addr);
13015 for (i = 0; i < 2 * words; i += 2) {
13016 word = inpw(iop_base + IOP_RAM_DATA);
13017 d_buffer[i] = word & 0xff;
13018 d_buffer[i + 1] = (word >> 8) & 0xff;
13034 for (i = 0; i < words; i++, s_addr += 2) {
13035 sum += AscReadLramWord(iop_base, s_addr);
13050 AscSetChipLramAddr(iop_base, s_addr);
13051 for (i = 0; i < words; i++) {
13052 AscSetChipLramData(iop_base, set_wval);
13059 * --- Adv Library Functions
13064 /* Microcode buffer is kept after initialization for error recovery. */
13065 STATIC unsigned char _adv_asc3550_buf[] = {
13066 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0x16, 0x18, 0xe4, 0x00, 0xfc, 0x01, 0x00, 0x48, 0xe4,
13067 0xbe, 0x18, 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00, 0x00, 0xfa, 0xff, 0xff, 0x28, 0x0e, 0x9e, 0xe7,
13068 0xff, 0x00, 0x82, 0xe7, 0x00, 0xea, 0x00, 0xf6, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0, 0x01, 0xf6,
13069 0x01, 0xfa, 0x08, 0x00, 0x03, 0x00, 0x04, 0x00, 0x18, 0xf4, 0x10, 0x00, 0x00, 0xec, 0x85, 0xf0,
13070 0xbc, 0x00, 0xd5, 0xf0, 0x8e, 0x0c, 0x38, 0x54, 0x00, 0xe6, 0x1e, 0xf0, 0x86, 0xf0, 0xb4, 0x00,
13071 0x98, 0x57, 0xd0, 0x01, 0x0c, 0x1c, 0x3e, 0x1c, 0x0c, 0x00, 0xbb, 0x00, 0xaa, 0x18, 0x02, 0x80,
13072 0x32, 0xf0, 0x01, 0xfc, 0x88, 0x0c, 0xc6, 0x12, 0x02, 0x13, 0x18, 0x40, 0x00, 0x57, 0x01, 0xea,
13073 0x3c, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12, 0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00,
13074 0xc0, 0x00, 0x01, 0x01, 0x3e, 0x01, 0xda, 0x0f, 0x22, 0x10, 0x08, 0x12, 0x02, 0x4a, 0xb9, 0x54,
13075 0x03, 0x58, 0x1b, 0x80, 0x30, 0xe4, 0x4b, 0xe4, 0x20, 0x00, 0x32, 0x00, 0x3e, 0x00, 0x80, 0x00,
13076 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01, 0x70, 0x01, 0x72, 0x01, 0x74, 0x01, 0x76, 0x01,
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13303 0x5c, 0x01, 0x08, 0x25, 0x32, 0x1f, 0x44, 0x30, 0x2e, 0xd6, 0x07, 0x06, 0x21, 0x44, 0x01, 0xfe,
13304 0x8e, 0x13, 0xfe, 0x42, 0x58, 0xfe, 0x82, 0x14, 0xfe, 0xa4, 0x14, 0x87, 0xfe, 0x4a, 0xf4, 0x0b,
13305 0x16, 0x44, 0xfe, 0x4a, 0xf4, 0x06, 0xfe, 0x0c, 0x12, 0x2f, 0x07, 0x9a, 0x85, 0x02, 0x5b, 0x05,
13306 0x3f, 0xb4, 0x0c, 0x3f, 0x5e, 0x2b, 0x01, 0x08, 0x26, 0x5c, 0x01, 0xfe, 0xd8, 0x14, 0x02, 0x5c,
13307 0x13, 0x06, 0x65, 0xfe, 0xca, 0x12, 0x26, 0xfe, 0xe0, 0x12, 0x72, 0xf1, 0x01, 0x08, 0x23, 0x72,
13308 0x03, 0x8f, 0xfe, 0xdc, 0x12, 0x25, 0xfe, 0xdc, 0x12, 0x1f, 0xfe, 0xca, 0x12, 0x5e, 0x2b, 0x01,
13309 0x08, 0xfe, 0xd5, 0x10, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0x1c, 0xfe, 0xff, 0x7f,
13310 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x03, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0x1c,
13311 0x3d, 0xfe, 0x30, 0x56, 0xfe, 0x00, 0x5c, 0x03, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b,
13312 0x03, 0x13, 0x6c, 0xff, 0x02, 0x00, 0x57, 0x48, 0x8b, 0xfe, 0x0b, 0x58, 0x03, 0x0a, 0x50, 0x01,
13313 0x82, 0x0a, 0x3f, 0x01, 0x82, 0x03, 0xfc, 0x1c, 0x10, 0xff, 0x03, 0x00, 0x54, 0xfe, 0x00, 0xf4,
13314 0x19, 0x48, 0xfe, 0x00, 0x7d, 0xfe, 0x01, 0x7d, 0xfe, 0x02, 0x7d, 0xfe, 0x03, 0x7c, 0x63, 0x27,
13315 0x0c, 0x52, 0x18, 0x53, 0xbe, 0x56, 0xbf, 0x57, 0x03, 0xfe, 0x62, 0x08, 0xfe, 0x82, 0x4a, 0xfe,
13316 0xe1, 0x1a, 0xfe, 0x83, 0x5a, 0x74, 0x03, 0x01, 0xfe, 0x14, 0x18, 0xfe, 0x42, 0x48, 0x5f, 0x60,
13317 0x89, 0x01, 0x08, 0x1f, 0xfe, 0xa2, 0x14, 0x30, 0x2e, 0xd8, 0x01, 0x08, 0x1f, 0xfe, 0xa2, 0x14,
13318 0x30, 0x2e, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59, 0x05, 0xc6, 0x28, 0xfe, 0xcc, 0x12, 0x49, 0x04,
13319 0x1b, 0xfe, 0xc4, 0x13, 0x23, 0x62, 0x1b, 0xe2, 0x4b, 0xc3, 0x64, 0xfe, 0xe8, 0x13, 0x3b, 0x13,
13320 0x06, 0x17, 0xc3, 0x78, 0xdb, 0xfe, 0x78, 0x10, 0xff, 0x02, 0x83, 0x55, 0xa1, 0xff, 0x02, 0x83,
13321 0x55, 0x62, 0x1a, 0xa4, 0xbb, 0xfe, 0x30, 0x00, 0x8e, 0xe4, 0x17, 0x2c, 0x13, 0x06, 0xfe, 0x56,
13322 0x10, 0x62, 0x0b, 0xe1, 0xbb, 0xfe, 0x64, 0x00, 0x8e, 0xe4, 0x0a, 0xfe, 0x64, 0x00, 0x17, 0x93,
13323 0x13, 0x06, 0xfe, 0x28, 0x10, 0x62, 0x06, 0xfe, 0x60, 0x13, 0xbb, 0xfe, 0xc8, 0x00, 0x8e, 0xe4,
13324 0x0a, 0xfe, 0xc8, 0x00, 0x17, 0x4d, 0x13, 0x06, 0x83, 0xbb, 0xfe, 0x90, 0x01, 0xba, 0xfe, 0x4e,
13325 0x14, 0x89, 0xfe, 0x12, 0x10, 0xfe, 0x43, 0xf4, 0x94, 0xfe, 0x56, 0xf0, 0xfe, 0x60, 0x14, 0xfe,
13326 0x04, 0xf4, 0x6c, 0xfe, 0x43, 0xf4, 0x93, 0xfe, 0xf3, 0x10, 0xf9, 0x01, 0xfe, 0x22, 0x13, 0x1c,
13327 0x3d, 0xfe, 0x10, 0x13, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4, 0x69, 0xba, 0xfe, 0x9c, 0x14, 0xb7,
13328 0x69, 0xfe, 0x1c, 0x10, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4, 0x19, 0xba, 0xfe, 0x9c, 0x14, 0xb7,
13329 0x19, 0x83, 0x60, 0x23, 0xfe, 0x4d, 0xf4, 0x00, 0xdf, 0x89, 0x13, 0x06, 0xfe, 0xb4, 0x56, 0xfe,
13330 0xc3, 0x58, 0x03, 0x60, 0x13, 0x0b, 0x03, 0x15, 0x06, 0x01, 0x08, 0x26, 0xe5, 0x15, 0x0b, 0x01,
13331 0x08, 0x26, 0xe5, 0x15, 0x1a, 0x01, 0x08, 0x26, 0xe5, 0x72, 0xfe, 0x89, 0x49, 0x01, 0x08, 0x03,
13332 0x15, 0x06, 0x01, 0x08, 0x26, 0xa6, 0x15, 0x1a, 0x01, 0x08, 0x26, 0xa6, 0x15, 0x06, 0x01, 0x08,
13333 0x26, 0xa6, 0xfe, 0x89, 0x49, 0x01, 0x08, 0x26, 0xa6, 0x72, 0xfe, 0x89, 0x4a, 0x01, 0x08, 0x03,
13334 0x60, 0x03, 0x1e, 0xcc, 0x07, 0x06, 0xfe, 0x44, 0x13, 0xad, 0x12, 0xcc, 0xfe, 0x49, 0xf4, 0x00,
13335 0x3b, 0x72, 0x9f, 0x5e, 0xfe, 0x01, 0xec, 0xfe, 0x27, 0x01, 0xf1, 0x01, 0x08, 0x2f, 0x07, 0xfe,
13336 0xe3, 0x00, 0xfe, 0x20, 0x13, 0x1f, 0xfe, 0x5a, 0x15, 0x23, 0x12, 0xcd, 0x01, 0x43, 0x1e, 0xcd,
13337 0x07, 0x06, 0x45, 0x09, 0x4a, 0x06, 0x35, 0x03, 0x0a, 0x42, 0x01, 0x0e, 0xed, 0x88, 0x07, 0x10,
13338 0xa4, 0x0a, 0x80, 0x01, 0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03, 0x0a, 0x80, 0x01, 0x0e, 0x88,
13339 0xfe, 0x80, 0xe7, 0x10, 0x07, 0x10, 0x84, 0xfe, 0x45, 0x58, 0x01, 0xe3, 0x88, 0x03, 0x0a, 0x42,
13340 0x01, 0x0e, 0x88, 0x0a, 0x51, 0x01, 0x9e, 0x03, 0x0a, 0x42, 0x01, 0x0e, 0xfe, 0x80, 0x80, 0xf2,
13341 0xfe, 0x49, 0xe4, 0x10, 0xa4, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x0a, 0x51, 0x01, 0x82, 0x03, 0x17,
13342 0x10, 0x71, 0x66, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x24, 0x1c, 0xfe,
13343 0x1d, 0xf7, 0x1d, 0x90, 0xfe, 0xf6, 0x15, 0x01, 0xfe, 0xfc, 0x16, 0xe0, 0x91, 0x1d, 0x66, 0xfe,
13344 0x2c, 0x01, 0xfe, 0x2f, 0x19, 0x03, 0xae, 0x21, 0xfe, 0xe6, 0x15, 0xfe, 0xda, 0x10, 0x17, 0x10,
13345 0x71, 0x05, 0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x19, 0xfe, 0x18, 0x58, 0x05, 0xfe, 0x66, 0x01,
13346 0xfe, 0x19, 0x58, 0x91, 0x19, 0xfe, 0x3c, 0x90, 0xfe, 0x30, 0xf4, 0x06, 0xfe, 0x3c, 0x50, 0x66,
13347 0xfe, 0x38, 0x00, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0x19, 0x90, 0xfe, 0x40, 0x16, 0xfe, 0xb6,
13348 0x14, 0x34, 0x03, 0xae, 0x21, 0xfe, 0x18, 0x16, 0xfe, 0x9c, 0x10, 0x17, 0x10, 0x71, 0xfe, 0x83,
13349 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x1d, 0xf7, 0x38, 0x90, 0xfe, 0x62, 0x16, 0xfe,
13350 0x94, 0x14, 0xfe, 0x10, 0x13, 0x91, 0x38, 0x66, 0x1b, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00,
13351 0x03, 0xae, 0x21, 0xfe, 0x56, 0x16, 0xfe, 0x6c, 0x10, 0x17, 0x10, 0x71, 0xfe, 0x30, 0xbc, 0xfe,
13352 0xb2, 0xbc, 0x91, 0xc5, 0x66, 0x1b, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0xc5, 0x90, 0xfe, 0x9a,
13353 0x16, 0xfe, 0x5c, 0x14, 0x34, 0x03, 0xae, 0x21, 0xfe, 0x86, 0x16, 0xfe, 0x42, 0x10, 0xfe, 0x02,
13354 0xf6, 0x10, 0x71, 0xfe, 0x18, 0xfe, 0x54, 0xfe, 0x19, 0xfe, 0x55, 0xfc, 0xfe, 0x1d, 0xf7, 0x4f,
13355 0x90, 0xfe, 0xc0, 0x16, 0xfe, 0x36, 0x14, 0xfe, 0x1c, 0x13, 0x91, 0x4f, 0x47, 0xfe, 0x83, 0x58,
13356 0xfe, 0xaf, 0x19, 0xfe, 0x80, 0xe7, 0x10, 0xfe, 0x81, 0xe7, 0x10, 0x11, 0xfe, 0xdd, 0x00, 0x63,
13357 0x27, 0x03, 0x63, 0x27, 0xfe, 0x12, 0x45, 0x21, 0xfe, 0xb0, 0x16, 0x14, 0x06, 0x37, 0x95, 0xa9,
13358 0x02, 0x29, 0xfe, 0x39, 0xf0, 0xfe, 0x04, 0x17, 0x23, 0x03, 0xfe, 0x7e, 0x18, 0x1c, 0x1a, 0x5d,
13359 0x13, 0x0d, 0x03, 0x71, 0x05, 0xcb, 0x1c, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10, 0x78, 0x2c,
13360 0x46, 0x2f, 0x07, 0x2d, 0xfe, 0x3c, 0x13, 0xfe, 0x82, 0x14, 0xfe, 0x42, 0x13, 0x3c, 0x8a, 0x0a,
13361 0x42, 0x01, 0x0e, 0xb0, 0xfe, 0x3e, 0x12, 0xf0, 0xfe, 0x45, 0x48, 0x01, 0xe3, 0xfe, 0x00, 0xcc,
13362 0xb0, 0xfe, 0xf3, 0x13, 0x3d, 0x75, 0x07, 0x10, 0xa3, 0x0a, 0x80, 0x01, 0x0e, 0xf2, 0x01, 0x6f,
13363 0xfe, 0x16, 0x10, 0x07, 0x7e, 0x85, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12, 0xf6, 0xfe, 0xd6, 0xf0,
13364 0xfe, 0x24, 0x17, 0x17, 0x0b, 0x03, 0xfe, 0x9c, 0xe7, 0x0b, 0x0f, 0xfe, 0x15, 0x00, 0x59, 0x76,
13365 0x27, 0x01, 0xda, 0x17, 0x06, 0x03, 0x3c, 0x8a, 0x09, 0x4a, 0x1d, 0x35, 0x11, 0x2d, 0x01, 0x6f,
13366 0x17, 0x06, 0x03, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x79, 0xc7, 0x68, 0xc8, 0xfe, 0x48, 0x55,
13367 0x34, 0xfe, 0xc9, 0x55, 0x03, 0x1e, 0x98, 0x73, 0x12, 0x98, 0x03, 0x0a, 0x99, 0x01, 0x0e, 0xf0,
13368 0x0a, 0x40, 0x01, 0x0e, 0xfe, 0x49, 0x44, 0x16, 0xfe, 0xf0, 0x17, 0x73, 0x75, 0x03, 0x0a, 0x42,
13369 0x01, 0x0e, 0x07, 0x10, 0x45, 0x0a, 0x51, 0x01, 0x9e, 0x0a, 0x40, 0x01, 0x0e, 0x73, 0x75, 0x03,
13370 0xfe, 0x4e, 0xe4, 0x1a, 0x64, 0xfe, 0x24, 0x18, 0x05, 0xfe, 0x90, 0x00, 0xfe, 0x3a, 0x45, 0x5b,
13371 0xfe, 0x4e, 0xe4, 0xc2, 0x64, 0xfe, 0x36, 0x18, 0x05, 0xfe, 0x92, 0x00, 0xfe, 0x02, 0xe6, 0x1b,
13372 0xdc, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x64, 0xfe, 0x48, 0x18, 0x05, 0xfe, 0x94, 0x00, 0xfe,
13373 0x02, 0xe6, 0x19, 0xfe, 0x08, 0x10, 0x05, 0xfe, 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x2c, 0xfe, 0x4e,
13374 0x45, 0xfe, 0x0c, 0x12, 0xaf, 0xff, 0x04, 0x68, 0x54, 0xde, 0x1c, 0x69, 0x03, 0x07, 0x7a, 0xfe,
13375 0x5a, 0xf0, 0xfe, 0x74, 0x18, 0x24, 0xfe, 0x09, 0x00, 0xfe, 0x34, 0x10, 0x07, 0x1b, 0xfe, 0x5a,
13376 0xf0, 0xfe, 0x82, 0x18, 0x24, 0xc3, 0xfe, 0x26, 0x10, 0x07, 0x1a, 0x5d, 0x24, 0x2c, 0xdc, 0x07,
13377 0x0b, 0x5d, 0x24, 0x93, 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x5d, 0x24, 0x4d, 0x9f, 0xad, 0x03, 0x14,
13378 0xfe, 0x09, 0x00, 0x01, 0x33, 0xfe, 0x04, 0xfe, 0x7d, 0x05, 0x7f, 0xf9, 0x03, 0x25, 0xfe, 0xca,
13379 0x18, 0xfe, 0x14, 0xf0, 0x08, 0x65, 0xfe, 0xc6, 0x18, 0x03, 0xff, 0x1a, 0x00, 0x00,
13382 STATIC unsigned short _adv_asc3550_size =
13383 sizeof(_adv_asc3550_buf); /* 0x13AD */
13384 STATIC ADV_DCNT _adv_asc3550_chksum =
13385 0x04D52DDDUL; /* Expanded little-endian checksum. */
13387 /* Microcode buffer is kept after initialization for error recovery. */
13388 STATIC unsigned char _adv_asc38C0800_buf[] = {
13389 0x00, 0x00, 0x00, 0xf2, 0x00, 0xf0, 0x00, 0xfc, 0x00, 0x16, 0x18, 0xe4, 0x01, 0x00, 0x48, 0xe4,
13390 0x18, 0x80, 0x03, 0xf6, 0x02, 0x00, 0xce, 0x19, 0x00, 0xfa, 0xff, 0xff, 0x1c, 0x0f, 0x00, 0xf6,
13391 0x9e, 0xe7, 0xff, 0x00, 0x82, 0xe7, 0x00, 0xea, 0x01, 0xfa, 0x01, 0xe6, 0x09, 0xe7, 0x55, 0xf0,
13392 0x01, 0xf6, 0x03, 0x00, 0x04, 0x00, 0x10, 0x00, 0x1e, 0xf0, 0x85, 0xf0, 0x18, 0xf4, 0x08, 0x00,
13393 0xbc, 0x00, 0x38, 0x54, 0x00, 0xec, 0xd5, 0xf0, 0x82, 0x0d, 0x00, 0xe6, 0x86, 0xf0, 0xb1, 0xf0,
13394 0x98, 0x57, 0x01, 0xfc, 0xb4, 0x00, 0xd4, 0x01, 0x0c, 0x1c, 0x3e, 0x1c, 0x3c, 0x00, 0xbb, 0x00,
13395 0x00, 0x10, 0xba, 0x19, 0x02, 0x80, 0x32, 0xf0, 0x7c, 0x0d, 0x02, 0x13, 0xba, 0x13, 0x18, 0x40,
13396 0x00, 0x57, 0x01, 0xea, 0x02, 0xfc, 0x03, 0xfc, 0x3e, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x74, 0x01,
13397 0x76, 0x01, 0xb9, 0x54, 0x3e, 0x57, 0x00, 0x80, 0x03, 0xe6, 0xb6, 0x00, 0xc0, 0x00, 0x01, 0x01,
13398 0x3e, 0x01, 0x7a, 0x01, 0xca, 0x08, 0xce, 0x10, 0x16, 0x11, 0x04, 0x12, 0x08, 0x12, 0x02, 0x4a,
13399 0xbb, 0x55, 0x3c, 0x56, 0x03, 0x58, 0x1b, 0x80, 0x30, 0xe4, 0x4b, 0xe4, 0x5d, 0xf0, 0x02, 0xfa,
13400 0x20, 0x00, 0x32, 0x00, 0x40, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01, 0x68, 0x01, 0x6a, 0x01,
13401 0x70, 0x01, 0x72, 0x01, 0x78, 0x01, 0x7c, 0x01, 0x62, 0x0a, 0x86, 0x0d, 0x06, 0x13, 0x4c, 0x1c,
13402 0x04, 0x80, 0x4a, 0xe4, 0x02, 0xee, 0x5b, 0xf0, 0x03, 0xf7, 0x0c, 0x00, 0x0f, 0x00, 0x47, 0x00,
13403 0xbe, 0x00, 0x00, 0x01, 0x20, 0x11, 0x5c, 0x16, 0x32, 0x1c, 0x38, 0x1c, 0x4e, 0x1c, 0x10, 0x44,
13404 0x00, 0x4c, 0x04, 0xea, 0x5c, 0xf0, 0xa7, 0xf0, 0x04, 0xf6, 0x03, 0xfa, 0x05, 0x00, 0x34, 0x00,
13405 0x36, 0x00, 0x98, 0x00, 0xcc, 0x00, 0x20, 0x01, 0x4e, 0x01, 0x4a, 0x0b, 0x42, 0x0c, 0x12, 0x0f,
13406 0x0c, 0x10, 0x22, 0x11, 0x0a, 0x12, 0x04, 0x13, 0x30, 0x1c, 0x02, 0x48, 0x00, 0x4e, 0x42, 0x54,
13407 0x44, 0x55, 0xbd, 0x56, 0x06, 0x83, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0, 0x59, 0xf0, 0xb8, 0xf0,
13408 0x4b, 0xf4, 0x06, 0xf7, 0x0e, 0xf7, 0x04, 0xfc, 0x05, 0xfc, 0x06, 0x00, 0x19, 0x00, 0x33, 0x00,
13409 0x9b, 0x00, 0xa4, 0x00, 0xb5, 0x00, 0xba, 0x00, 0xd0, 0x00, 0xe1, 0x00, 0xe7, 0x00, 0xe2, 0x03,
13410 0x08, 0x0f, 0x02, 0x10, 0x04, 0x10, 0x0a, 0x10, 0x0a, 0x13, 0x0c, 0x13, 0x12, 0x13, 0x24, 0x14,
13411 0x34, 0x14, 0x04, 0x16, 0x08, 0x16, 0xa4, 0x17, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c, 0x08, 0x44,
13412 0x38, 0x44, 0x91, 0x44, 0x0a, 0x45, 0x48, 0x46, 0x01, 0x48, 0x68, 0x54, 0x3a, 0x55, 0x83, 0x55,
13413 0xe5, 0x55, 0xb0, 0x57, 0x01, 0x58, 0x83, 0x59, 0x05, 0xe6, 0x0b, 0xf0, 0x0c, 0xf0, 0x04, 0xf8,
13414 0x05, 0xf8, 0x07, 0x00, 0x0a, 0x00, 0x1c, 0x00, 0x1e, 0x00, 0x9e, 0x00, 0xa8, 0x00, 0xaa, 0x00,
13415 0xb9, 0x00, 0xe0, 0x00, 0x22, 0x01, 0x26, 0x01, 0x79, 0x01, 0x7e, 0x01, 0xc4, 0x01, 0xc6, 0x01,
13416 0x80, 0x02, 0x5e, 0x03, 0xee, 0x04, 0x9a, 0x06, 0xf8, 0x07, 0x62, 0x08, 0x68, 0x08, 0x69, 0x08,
13417 0xd6, 0x08, 0xe9, 0x09, 0xfa, 0x0b, 0x2e, 0x0f, 0x12, 0x10, 0x1a, 0x10, 0xed, 0x10, 0xf1, 0x10,
13418 0x2a, 0x11, 0x06, 0x12, 0x0c, 0x12, 0x3e, 0x12, 0x10, 0x13, 0x16, 0x13, 0x1e, 0x13, 0x46, 0x14,
13419 0x76, 0x14, 0x82, 0x14, 0x36, 0x15, 0xca, 0x15, 0x6b, 0x18, 0xbe, 0x18, 0xca, 0x18, 0xe6, 0x19,
13420 0x12, 0x1c, 0x46, 0x1c, 0x9c, 0x32, 0x00, 0x40, 0x0e, 0x47, 0xfe, 0x9c, 0xf0, 0x2b, 0x02, 0xfe,
13421 0xac, 0x0d, 0xff, 0x10, 0x00, 0x00, 0xd7, 0xfe, 0xe8, 0x19, 0x00, 0xd6, 0xfe, 0x84, 0x01, 0xff,
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13652 0x0f, 0x71, 0xff, 0x02, 0x00, 0x57, 0x52, 0x93, 0x04, 0x0f, 0x71, 0xff, 0x02, 0x00, 0x57, 0x52,
13653 0x93, 0xfe, 0x0b, 0x58, 0x04, 0x09, 0x5c, 0x01, 0x87, 0x09, 0x45, 0x01, 0x87, 0x04, 0xfe, 0x03,
13654 0xa1, 0x1e, 0x11, 0xff, 0x03, 0x00, 0x54, 0xfe, 0x00, 0xf4, 0x1f, 0x52, 0xfe, 0x00, 0x7d, 0xfe,
13655 0x01, 0x7d, 0xfe, 0x02, 0x7d, 0xfe, 0x03, 0x7c, 0x6a, 0x2a, 0x0c, 0x5e, 0x14, 0x5f, 0x57, 0x3f,
13656 0x7d, 0x40, 0x04, 0xdd, 0xfe, 0x82, 0x4a, 0xfe, 0xe1, 0x1a, 0xfe, 0x83, 0x5a, 0x8d, 0x04, 0x01,
13657 0xfe, 0x0c, 0x19, 0xfe, 0x42, 0x48, 0x50, 0x51, 0x91, 0x01, 0x0b, 0x1d, 0xfe, 0x96, 0x15, 0x33,
13658 0x31, 0xe1, 0x01, 0x0b, 0x1d, 0xfe, 0x96, 0x15, 0x33, 0x31, 0xfe, 0xe8, 0x0a, 0xfe, 0xc1, 0x59,
13659 0x03, 0xcd, 0x28, 0xfe, 0xcc, 0x12, 0x53, 0x05, 0x1a, 0xfe, 0xc4, 0x13, 0x21, 0x69, 0x1a, 0xee,
13660 0x55, 0xca, 0x6b, 0xfe, 0xdc, 0x14, 0x4d, 0x0f, 0x06, 0x18, 0xca, 0x7c, 0x30, 0xfe, 0x78, 0x10,
13661 0xff, 0x02, 0x83, 0x55, 0xab, 0xff, 0x02, 0x83, 0x55, 0x69, 0x19, 0xae, 0x98, 0xfe, 0x30, 0x00,
13662 0x96, 0xf2, 0x18, 0x6d, 0x0f, 0x06, 0xfe, 0x56, 0x10, 0x69, 0x0a, 0xed, 0x98, 0xfe, 0x64, 0x00,
13663 0x96, 0xf2, 0x09, 0xfe, 0x64, 0x00, 0x18, 0x9e, 0x0f, 0x06, 0xfe, 0x28, 0x10, 0x69, 0x06, 0xfe,
13664 0x60, 0x13, 0x98, 0xfe, 0xc8, 0x00, 0x96, 0xf2, 0x09, 0xfe, 0xc8, 0x00, 0x18, 0x59, 0x0f, 0x06,
13665 0x88, 0x98, 0xfe, 0x90, 0x01, 0x7a, 0xfe, 0x42, 0x15, 0x91, 0xe4, 0xfe, 0x43, 0xf4, 0x9f, 0xfe,
13666 0x56, 0xf0, 0xfe, 0x54, 0x15, 0xfe, 0x04, 0xf4, 0x71, 0xfe, 0x43, 0xf4, 0x9e, 0xfe, 0xf3, 0x10,
13667 0xfe, 0x40, 0x5c, 0x01, 0xfe, 0x16, 0x14, 0x1e, 0x43, 0xec, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4,
13668 0x6e, 0x7a, 0xfe, 0x90, 0x15, 0xc4, 0x6e, 0xfe, 0x1c, 0x10, 0xfe, 0x00, 0x17, 0xfe, 0x4d, 0xe4,
13669 0xcc, 0x7a, 0xfe, 0x90, 0x15, 0xc4, 0xcc, 0x88, 0x51, 0x21, 0xfe, 0x4d, 0xf4, 0x00, 0xe9, 0x91,
13670 0x0f, 0x06, 0xfe, 0xb4, 0x56, 0xfe, 0xc3, 0x58, 0x04, 0x51, 0x0f, 0x0a, 0x04, 0x16, 0x06, 0x01,
13671 0x0b, 0x26, 0xf3, 0x16, 0x0a, 0x01, 0x0b, 0x26, 0xf3, 0x16, 0x19, 0x01, 0x0b, 0x26, 0xf3, 0x76,
13672 0xfe, 0x89, 0x49, 0x01, 0x0b, 0x04, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xb1, 0x16, 0x19, 0x01, 0x0b,
13673 0x26, 0xb1, 0x16, 0x06, 0x01, 0x0b, 0x26, 0xb1, 0xfe, 0x89, 0x49, 0x01, 0x0b, 0x26, 0xb1, 0x76,
13674 0xfe, 0x89, 0x4a, 0x01, 0x0b, 0x04, 0x51, 0x04, 0x22, 0xd3, 0x07, 0x06, 0xfe, 0x48, 0x13, 0xb8,
13675 0x13, 0xd3, 0xfe, 0x49, 0xf4, 0x00, 0x4d, 0x76, 0xa9, 0x67, 0xfe, 0x01, 0xec, 0xfe, 0x27, 0x01,
13676 0xfe, 0x89, 0x48, 0xff, 0x02, 0x00, 0x10, 0x27, 0xfe, 0x2e, 0x16, 0x32, 0x07, 0xfe, 0xe3, 0x00,
13677 0xfe, 0x20, 0x13, 0x1d, 0xfe, 0x52, 0x16, 0x21, 0x13, 0xd4, 0x01, 0x4b, 0x22, 0xd4, 0x07, 0x06,
13678 0x4e, 0x08, 0x54, 0x06, 0x37, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfb, 0x8e, 0x07, 0x11, 0xae, 0x09,
13679 0x84, 0x01, 0x0e, 0x8e, 0x09, 0x5d, 0x01, 0xa8, 0x04, 0x09, 0x84, 0x01, 0x0e, 0x8e, 0xfe, 0x80,
13680 0xe7, 0x11, 0x07, 0x11, 0x8a, 0xfe, 0x45, 0x58, 0x01, 0xf0, 0x8e, 0x04, 0x09, 0x48, 0x01, 0x0e,
13681 0x8e, 0x09, 0x5d, 0x01, 0xa8, 0x04, 0x09, 0x48, 0x01, 0x0e, 0xfe, 0x80, 0x80, 0xfe, 0x80, 0x4c,
13682 0xfe, 0x49, 0xe4, 0x11, 0xae, 0x09, 0x84, 0x01, 0x0e, 0xfe, 0x80, 0x4c, 0x09, 0x5d, 0x01, 0x87,
13683 0x04, 0x18, 0x11, 0x75, 0x6c, 0xfe, 0x60, 0x01, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x24,
13684 0x1c, 0xfe, 0x1d, 0xf7, 0x1b, 0x97, 0xfe, 0xee, 0x16, 0x01, 0xfe, 0xf4, 0x17, 0xad, 0x9a, 0x1b,
13685 0x6c, 0xfe, 0x2c, 0x01, 0xfe, 0x2f, 0x19, 0x04, 0xb9, 0x23, 0xfe, 0xde, 0x16, 0xfe, 0xda, 0x10,
13686 0x18, 0x11, 0x75, 0x03, 0xfe, 0x64, 0x01, 0xfe, 0x00, 0xf4, 0x1f, 0xfe, 0x18, 0x58, 0x03, 0xfe,
13687 0x66, 0x01, 0xfe, 0x19, 0x58, 0x9a, 0x1f, 0xfe, 0x3c, 0x90, 0xfe, 0x30, 0xf4, 0x06, 0xfe, 0x3c,
13688 0x50, 0x6c, 0xfe, 0x38, 0x00, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0x1f, 0x97, 0xfe, 0x38, 0x17,
13689 0xfe, 0xb6, 0x14, 0x35, 0x04, 0xb9, 0x23, 0xfe, 0x10, 0x17, 0xfe, 0x9c, 0x10, 0x18, 0x11, 0x75,
13690 0xfe, 0x83, 0x5a, 0xfe, 0x18, 0xdf, 0xfe, 0x19, 0xde, 0xfe, 0x1d, 0xf7, 0x2e, 0x97, 0xfe, 0x5a,
13691 0x17, 0xfe, 0x94, 0x14, 0xec, 0x9a, 0x2e, 0x6c, 0x1a, 0xfe, 0xaf, 0x19, 0xfe, 0x98, 0xe7, 0x00,
13692 0x04, 0xb9, 0x23, 0xfe, 0x4e, 0x17, 0xfe, 0x6c, 0x10, 0x18, 0x11, 0x75, 0xfe, 0x30, 0xbc, 0xfe,
13693 0xb2, 0xbc, 0x9a, 0xcb, 0x6c, 0x1a, 0xfe, 0x0f, 0x79, 0xfe, 0x1c, 0xf7, 0xcb, 0x97, 0xfe, 0x92,
13694 0x17, 0xfe, 0x5c, 0x14, 0x35, 0x04, 0xb9, 0x23, 0xfe, 0x7e, 0x17, 0xfe, 0x42, 0x10, 0xfe, 0x02,
13695 0xf6, 0x11, 0x75, 0xfe, 0x18, 0xfe, 0x60, 0xfe, 0x19, 0xfe, 0x61, 0xfe, 0x03, 0xa1, 0xfe, 0x1d,
13696 0xf7, 0x5b, 0x97, 0xfe, 0xb8, 0x17, 0xfe, 0x36, 0x14, 0xfe, 0x1c, 0x13, 0x9a, 0x5b, 0x41, 0xfe,
13697 0x83, 0x58, 0xfe, 0xaf, 0x19, 0xfe, 0x80, 0xe7, 0x11, 0xfe, 0x81, 0xe7, 0x11, 0x12, 0xfe, 0xdd,
13698 0x00, 0x6a, 0x2a, 0x04, 0x6a, 0x2a, 0xfe, 0x12, 0x45, 0x23, 0xfe, 0xa8, 0x17, 0x15, 0x06, 0x39,
13699 0xa0, 0xb4, 0x02, 0x2b, 0xfe, 0x39, 0xf0, 0xfe, 0xfc, 0x17, 0x21, 0x04, 0xfe, 0x7e, 0x18, 0x1e,
13700 0x19, 0x66, 0x0f, 0x0d, 0x04, 0x75, 0x03, 0xd2, 0x1e, 0x06, 0xfe, 0xef, 0x12, 0xfe, 0xe1, 0x10,
13701 0x7c, 0x6f, 0x4f, 0x32, 0x07, 0x2f, 0xfe, 0x3c, 0x13, 0xf1, 0xfe, 0x42, 0x13, 0x42, 0x92, 0x09,
13702 0x48, 0x01, 0x0e, 0xbb, 0xeb, 0xfe, 0x41, 0x48, 0xfe, 0x45, 0x48, 0x01, 0xf0, 0xfe, 0x00, 0xcc,
13703 0xbb, 0xfe, 0xf3, 0x13, 0x43, 0x78, 0x07, 0x11, 0xac, 0x09, 0x84, 0x01, 0x0e, 0xfe, 0x80, 0x4c,
13704 0x01, 0x73, 0xfe, 0x16, 0x10, 0x07, 0x82, 0x8b, 0xfe, 0x40, 0x14, 0xfe, 0x24, 0x12, 0xfe, 0x14,
13705 0x56, 0xfe, 0xd6, 0xf0, 0xfe, 0x1c, 0x18, 0x18, 0x0a, 0x04, 0xfe, 0x9c, 0xe7, 0x0a, 0x10, 0xfe,
13706 0x15, 0x00, 0x64, 0x79, 0x2a, 0x01, 0xe3, 0x18, 0x06, 0x04, 0x42, 0x92, 0x08, 0x54, 0x1b, 0x37,
13707 0x12, 0x2f, 0x01, 0x73, 0x18, 0x06, 0x04, 0xfe, 0x38, 0x90, 0xfe, 0xba, 0x90, 0x3a, 0xce, 0x3b,
13708 0xcf, 0xfe, 0x48, 0x55, 0x35, 0xfe, 0xc9, 0x55, 0x04, 0x22, 0xa3, 0x77, 0x13, 0xa3, 0x04, 0x09,
13709 0xa4, 0x01, 0x0e, 0xfe, 0x41, 0x48, 0x09, 0x46, 0x01, 0x0e, 0xfe, 0x49, 0x44, 0x17, 0xfe, 0xe8,
13710 0x18, 0x77, 0x78, 0x04, 0x09, 0x48, 0x01, 0x0e, 0x07, 0x11, 0x4e, 0x09, 0x5d, 0x01, 0xa8, 0x09,
13711 0x46, 0x01, 0x0e, 0x77, 0x78, 0x04, 0xfe, 0x4e, 0xe4, 0x19, 0x6b, 0xfe, 0x1c, 0x19, 0x03, 0xfe,
13712 0x90, 0x00, 0xfe, 0x3a, 0x45, 0xfe, 0x2c, 0x10, 0xfe, 0x4e, 0xe4, 0xc9, 0x6b, 0xfe, 0x2e, 0x19,
13713 0x03, 0xfe, 0x92, 0x00, 0xfe, 0x02, 0xe6, 0x1a, 0xe5, 0xfe, 0x4e, 0xe4, 0xfe, 0x0b, 0x00, 0x6b,
13714 0xfe, 0x40, 0x19, 0x03, 0xfe, 0x94, 0x00, 0xfe, 0x02, 0xe6, 0x1f, 0xfe, 0x08, 0x10, 0x03, 0xfe,
13715 0x96, 0x00, 0xfe, 0x02, 0xe6, 0x6d, 0xfe, 0x4e, 0x45, 0xea, 0xba, 0xff, 0x04, 0x68, 0x54, 0xe7,
13716 0x1e, 0x6e, 0xfe, 0x08, 0x1c, 0xfe, 0x67, 0x19, 0xfe, 0x0a, 0x1c, 0xfe, 0x1a, 0xf4, 0xfe, 0x00,
13717 0x04, 0xea, 0xfe, 0x48, 0xf4, 0x19, 0x7a, 0xfe, 0x74, 0x19, 0x0f, 0x19, 0x04, 0x07, 0x7e, 0xfe,
13718 0x5a, 0xf0, 0xfe, 0x84, 0x19, 0x25, 0xfe, 0x09, 0x00, 0xfe, 0x34, 0x10, 0x07, 0x1a, 0xfe, 0x5a,
13719 0xf0, 0xfe, 0x92, 0x19, 0x25, 0xca, 0xfe, 0x26, 0x10, 0x07, 0x19, 0x66, 0x25, 0x6d, 0xe5, 0x07,
13720 0x0a, 0x66, 0x25, 0x9e, 0xfe, 0x0e, 0x10, 0x07, 0x06, 0x66, 0x25, 0x59, 0xa9, 0xb8, 0x04, 0x15,
13721 0xfe, 0x09, 0x00, 0x01, 0x36, 0xfe, 0x04, 0xfe, 0x81, 0x03, 0x83, 0xfe, 0x40, 0x5c, 0x04, 0x1c,
13722 0xf7, 0xfe, 0x14, 0xf0, 0x0b, 0x27, 0xfe, 0xd6, 0x19, 0x1c, 0xf7, 0x7b, 0xf7, 0xfe, 0x82, 0xf0,
13723 0xfe, 0xda, 0x19, 0x04, 0xff, 0xcc, 0x00, 0x00,
13726 STATIC unsigned short _adv_asc38C0800_size =
13727 sizeof(_adv_asc38C0800_buf); /* 0x14E1 */
13728 STATIC ADV_DCNT _adv_asc38C0800_chksum =
13729 0x050D3FD8UL; /* Expanded little-endian checksum. */
13731 /* Microcode buffer is kept after initialization for error recovery. */
13732 STATIC unsigned char _adv_asc38C1600_buf[] = {
13733 0x00, 0x00, 0x00, 0xf2, 0x00, 0x16, 0x00, 0xfc, 0x00, 0x10, 0x00, 0xf0, 0x18, 0xe4, 0x01, 0x00,
13734 0x04, 0x1e, 0x48, 0xe4, 0x03, 0xf6, 0xf7, 0x13, 0x2e, 0x1e, 0x02, 0x00, 0x07, 0x17, 0xc0, 0x5f,
13735 0x00, 0xfa, 0xff, 0xff, 0x04, 0x00, 0x00, 0xf6, 0x09, 0xe7, 0x82, 0xe7, 0x85, 0xf0, 0x86, 0xf0,
13736 0x4e, 0x10, 0x9e, 0xe7, 0xff, 0x00, 0x55, 0xf0, 0x01, 0xf6, 0x03, 0x00, 0x98, 0x57, 0x01, 0xe6,
13737 0x00, 0xea, 0x00, 0xec, 0x01, 0xfa, 0x18, 0xf4, 0x08, 0x00, 0xf0, 0x1d, 0x38, 0x54, 0x32, 0xf0,
13738 0x10, 0x00, 0xc2, 0x0e, 0x1e, 0xf0, 0xd5, 0xf0, 0xbc, 0x00, 0x4b, 0xe4, 0x00, 0xe6, 0xb1, 0xf0,
13739 0xb4, 0x00, 0x02, 0x13, 0x3e, 0x1c, 0xc8, 0x47, 0x3e, 0x00, 0xd8, 0x01, 0x06, 0x13, 0x0c, 0x1c,
13740 0x5e, 0x1e, 0x00, 0x57, 0xc8, 0x57, 0x01, 0xfc, 0xbc, 0x0e, 0xa2, 0x12, 0xb9, 0x54, 0x00, 0x80,
13741 0x62, 0x0a, 0x5a, 0x12, 0xc8, 0x15, 0x3e, 0x1e, 0x18, 0x40, 0xbd, 0x56, 0x03, 0xe6, 0x01, 0xea,
13742 0x5c, 0xf0, 0x0f, 0x00, 0x20, 0x00, 0x6c, 0x01, 0x6e, 0x01, 0x04, 0x12, 0x04, 0x13, 0xbb, 0x55,
13743 0x3c, 0x56, 0x3e, 0x57, 0x03, 0x58, 0x4a, 0xe4, 0x40, 0x00, 0xb6, 0x00, 0xbb, 0x00, 0xc0, 0x00,
13744 0x00, 0x01, 0x01, 0x01, 0x3e, 0x01, 0x58, 0x0a, 0x44, 0x10, 0x0a, 0x12, 0x4c, 0x1c, 0x4e, 0x1c,
13745 0x02, 0x4a, 0x30, 0xe4, 0x05, 0xe6, 0x0c, 0x00, 0x3c, 0x00, 0x80, 0x00, 0x24, 0x01, 0x3c, 0x01,
13746 0x68, 0x01, 0x6a, 0x01, 0x70, 0x01, 0x72, 0x01, 0x74, 0x01, 0x76, 0x01, 0x78, 0x01, 0x7c, 0x01,
13747 0xc6, 0x0e, 0x0c, 0x10, 0xac, 0x12, 0xae, 0x12, 0x16, 0x1a, 0x32, 0x1c, 0x6e, 0x1e, 0x02, 0x48,
13748 0x3a, 0x55, 0xc9, 0x57, 0x02, 0xee, 0x5b, 0xf0, 0x03, 0xf7, 0x06, 0xf7, 0x03, 0xfc, 0x06, 0x00,
13749 0x1e, 0x00, 0xbe, 0x00, 0xe1, 0x00, 0x0c, 0x12, 0x18, 0x1a, 0x70, 0x1a, 0x30, 0x1c, 0x38, 0x1c,
13750 0x10, 0x44, 0x00, 0x4c, 0xb0, 0x57, 0x40, 0x5c, 0x4d, 0xe4, 0x04, 0xea, 0x5d, 0xf0, 0xa7, 0xf0,
13751 0x04, 0xf6, 0x02, 0xfc, 0x05, 0x00, 0x09, 0x00, 0x19, 0x00, 0x32, 0x00, 0x33, 0x00, 0x34, 0x00,
13752 0x36, 0x00, 0x98, 0x00, 0x9e, 0x00, 0xcc, 0x00, 0x20, 0x01, 0x4e, 0x01, 0x79, 0x01, 0x3c, 0x09,
13753 0x68, 0x0d, 0x02, 0x10, 0x04, 0x10, 0x3a, 0x10, 0x08, 0x12, 0x0a, 0x13, 0x40, 0x16, 0x50, 0x16,
13754 0x00, 0x17, 0x4a, 0x19, 0x00, 0x4e, 0x00, 0x54, 0x01, 0x58, 0x00, 0xdc, 0x05, 0xf0, 0x09, 0xf0,
13755 0x59, 0xf0, 0xb8, 0xf0, 0x48, 0xf4, 0x0e, 0xf7, 0x0a, 0x00, 0x9b, 0x00, 0x9c, 0x00, 0xa4, 0x00,
13756 0xb5, 0x00, 0xba, 0x00, 0xd0, 0x00, 0xe7, 0x00, 0xf0, 0x03, 0x69, 0x08, 0xe9, 0x09, 0x5c, 0x0c,
13757 0xb6, 0x12, 0xbc, 0x19, 0xd8, 0x1b, 0x20, 0x1c, 0x34, 0x1c, 0x36, 0x1c, 0x42, 0x1d, 0x08, 0x44,
13758 0x38, 0x44, 0x91, 0x44, 0x0a, 0x45, 0x48, 0x46, 0x89, 0x48, 0x68, 0x54, 0x83, 0x55, 0x83, 0x59,
13759 0x31, 0xe4, 0x02, 0xe6, 0x07, 0xf0, 0x08, 0xf0, 0x0b, 0xf0, 0x0c, 0xf0, 0x4b, 0xf4, 0x04, 0xf8,
13760 0x05, 0xf8, 0x02, 0xfa, 0x03, 0xfa, 0x04, 0xfc, 0x05, 0xfc, 0x07, 0x00, 0xa8, 0x00, 0xaa, 0x00,
13761 0xb9, 0x00, 0xe0, 0x00, 0xe5, 0x00, 0x22, 0x01, 0x26, 0x01, 0x60, 0x01, 0x7a, 0x01, 0x82, 0x01,
13762 0xc8, 0x01, 0xca, 0x01, 0x86, 0x02, 0x6a, 0x03, 0x18, 0x05, 0xb2, 0x07, 0x68, 0x08, 0x10, 0x0d,
13763 0x06, 0x10, 0x0a, 0x10, 0x0e, 0x10, 0x12, 0x10, 0x60, 0x10, 0xed, 0x10, 0xf3, 0x10, 0x06, 0x12,
13764 0x10, 0x12, 0x1e, 0x12, 0x0c, 0x13, 0x0e, 0x13, 0x10, 0x13, 0xfe, 0x9c, 0xf0, 0x35, 0x05, 0xfe,
13765 0xec, 0x0e, 0xff, 0x10, 0x00, 0x00, 0xe9, 0xfe, 0x34, 0x1f, 0x00, 0xe8, 0xfe, 0x88, 0x01, 0xff,
13766 0x03, 0x00, 0x00, 0xfe, 0x93, 0x15, 0xfe, 0x0f, 0x05, 0xff, 0x38, 0x00, 0x00, 0xfe, 0x57, 0x24,
13767 0x00, 0xfe, 0x4c, 0x00, 0x65, 0xff, 0x04, 0x00, 0x00, 0x1a, 0xff, 0x09, 0x00, 0x00, 0xff, 0x08,
13768 0x01, 0x01, 0xff, 0x08, 0xff, 0xff, 0xff, 0x27, 0x00, 0x00, 0xff, 0x10, 0xff, 0xff, 0xff, 0x13,
13769 0x00, 0x00, 0xfe, 0x78, 0x56, 0xfe, 0x34, 0x12, 0xff, 0x21, 0x00, 0x00, 0xfe, 0x04, 0xf7, 0xe8,
13770 0x37, 0x7d, 0x0d, 0x01, 0xfe, 0x4a, 0x11, 0xfe, 0x04, 0xf7, 0xe8, 0x7d, 0x0d, 0x51, 0x37, 0xfe,
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14109 0x00, 0x04, 0x83, 0xb2, 0x1d, 0x48, 0xfe, 0xaa, 0x1d, 0x13, 0x1d, 0x02, 0x09, 0x92, 0xfe, 0x5a,
14110 0xf0, 0xfe, 0xba, 0x1d, 0x2e, 0x93, 0xfe, 0x34, 0x10, 0x09, 0x12, 0xfe, 0x5a, 0xf0, 0xfe, 0xc8,
14111 0x1d, 0x2e, 0xb4, 0xfe, 0x26, 0x10, 0x09, 0x1d, 0x36, 0x2e, 0x63, 0xfe, 0x1a, 0x10, 0x09, 0x0d,
14112 0x36, 0x2e, 0x94, 0xf2, 0x09, 0x07, 0x36, 0x2e, 0x95, 0xa1, 0xc8, 0x02, 0x1f, 0x93, 0x01, 0x42,
14113 0xfe, 0x04, 0xfe, 0x99, 0x03, 0x9c, 0x8b, 0x02, 0x2a, 0xfe, 0x1c, 0x1e, 0xfe, 0x14, 0xf0, 0x08,
14114 0x2f, 0xfe, 0x0c, 0x1e, 0x2a, 0xfe, 0x1c, 0x1e, 0x8f, 0xfe, 0x1c, 0x1e, 0xfe, 0x82, 0xf0, 0xfe,
14115 0x10, 0x1e, 0x02, 0x0f, 0x3f, 0x04, 0xfe, 0x80, 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x18,
14116 0x80, 0x04, 0xfe, 0x98, 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x02, 0x80, 0x04, 0xfe, 0x82,
14117 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06, 0x80, 0x04, 0xfe, 0x86, 0x83, 0x33, 0x0b, 0x0e,
14118 0x02, 0x0f, 0xfe, 0x1b, 0x80, 0x04, 0xfe, 0x9b, 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x04,
14119 0x80, 0x04, 0xfe, 0x84, 0x83, 0x33, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x80, 0x80, 0x04, 0xfe, 0x80,
14120 0x83, 0xfe, 0xc9, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x19, 0x81, 0x04, 0xfe, 0x99, 0x83, 0xfe,
14121 0xca, 0x47, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x06, 0x83, 0x04, 0xfe, 0x86, 0x83, 0xfe, 0xce, 0x47,
14122 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x2c, 0x90, 0x04, 0xfe, 0xac, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
14123 0xfe, 0xae, 0x90, 0x04, 0xfe, 0xae, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x08, 0x90, 0x04,
14124 0xfe, 0x88, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x8a, 0x90, 0x04, 0xfe, 0x8a, 0x93, 0x79,
14125 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x0c, 0x90, 0x04, 0xfe, 0x8c, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x0f,
14126 0xfe, 0x8e, 0x90, 0x04, 0xfe, 0x8e, 0x93, 0x79, 0x0b, 0x0e, 0x02, 0x0f, 0xfe, 0x3c, 0x90, 0x04,
14127 0xfe, 0xbc, 0x93, 0x3a, 0x0b, 0x0e, 0x02, 0x8b, 0x0f, 0xfe, 0x03, 0x80, 0x04, 0xfe, 0x83, 0x83,
14128 0x33, 0x0b, 0x77, 0x0e, 0xa8, 0x02, 0xff, 0x66, 0x00, 0x00,
14131 STATIC unsigned short _adv_asc38C1600_size =
14132 sizeof(_adv_asc38C1600_buf); /* 0x1673 */
14133 STATIC ADV_DCNT _adv_asc38C1600_chksum =
14134 0x0604EF77UL; /* Expanded little-endian checksum. */
14138 * EEPROM Configuration.
14140 * All drivers should use this structure to set the default EEPROM
14141 * configuration. The BIOS now uses this structure when it is built.
14142 * Additional structure information can be found in a_condor.h where
14143 * the structure is defined.
14145 * The *_Field_IsChar structs are needed to correct for endianness.
14146 * These values are read from the board 16 bits at a time directly
14147 * into the structs. Because some fields are char, the values will be
14148 * in the wrong order. The *_Field_IsChar tells when to flip the
14149 * bytes. Data read and written to PCI memory is automatically swapped
14150 * on big-endian platforms so char fields read as words are actually being
14151 * unswapped on big-endian platforms.
14153 STATIC ADVEEP_3550_CONFIG
14154 Default_3550_EEPROM_Config __initdata = {
14155 ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
14156 0x0000, /* cfg_msw */
14157 0xFFFF, /* disc_enable */
14158 0xFFFF, /* wdtr_able */
14159 0xFFFF, /* sdtr_able */
14160 0xFFFF, /* start_motor */
14161 0xFFFF, /* tagqng_able */
14162 0xFFFF, /* bios_scan */
14163 0, /* scam_tolerant */
14164 7, /* adapter_scsi_id */
14165 0, /* bios_boot_delay */
14166 3, /* scsi_reset_delay */
14167 0, /* bios_id_lun */
14168 0, /* termination */
14170 0xFFE7, /* bios_ctrl */
14171 0xFFFF, /* ultra_able */
14173 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */
14174 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
14177 0, /* serial_number_word1 */
14178 0, /* serial_number_word2 */
14179 0, /* serial_number_word3 */
14181 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }, /* oem_name[16] */
14182 0, /* dvc_err_code */
14183 0, /* adv_err_code */
14184 0, /* adv_err_addr */
14185 0, /* saved_dvc_err_code */
14186 0, /* saved_adv_err_code */
14187 0, /* saved_adv_err_addr */
14191 STATIC ADVEEP_3550_CONFIG
14192 ADVEEP_3550_Config_Field_IsChar __initdata = {
14195 0, /* -disc_enable */
14198 0, /* start_motor */
14199 0, /* tagqng_able */
14201 0, /* scam_tolerant */
14202 1, /* adapter_scsi_id */
14203 1, /* bios_boot_delay */
14204 1, /* scsi_reset_delay */
14205 1, /* bios_id_lun */
14206 1, /* termination */
14209 0, /* ultra_able */
14211 1, /* max_host_qng */
14212 1, /* max_dvc_qng */
14215 0, /* serial_number_word1 */
14216 0, /* serial_number_word2 */
14217 0, /* serial_number_word3 */
14219 { 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 }, /* oem_name[16] */
14220 0, /* dvc_err_code */
14221 0, /* adv_err_code */
14222 0, /* adv_err_addr */
14223 0, /* saved_dvc_err_code */
14224 0, /* saved_adv_err_code */
14225 0, /* saved_adv_err_addr */
14229 STATIC ADVEEP_38C0800_CONFIG
14230 Default_38C0800_EEPROM_Config __initdata = {
14231 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
14232 0x0000, /* 01 cfg_msw */
14233 0xFFFF, /* 02 disc_enable */
14234 0xFFFF, /* 03 wdtr_able */
14235 0x4444, /* 04 sdtr_speed1 */
14236 0xFFFF, /* 05 start_motor */
14237 0xFFFF, /* 06 tagqng_able */
14238 0xFFFF, /* 07 bios_scan */
14239 0, /* 08 scam_tolerant */
14240 7, /* 09 adapter_scsi_id */
14241 0, /* bios_boot_delay */
14242 3, /* 10 scsi_reset_delay */
14243 0, /* bios_id_lun */
14244 0, /* 11 termination_se */
14245 0, /* termination_lvd */
14246 0xFFE7, /* 12 bios_ctrl */
14247 0x4444, /* 13 sdtr_speed2 */
14248 0x4444, /* 14 sdtr_speed3 */
14249 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
14250 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
14251 0, /* 16 dvc_cntl */
14252 0x4444, /* 17 sdtr_speed4 */
14253 0, /* 18 serial_number_word1 */
14254 0, /* 19 serial_number_word2 */
14255 0, /* 20 serial_number_word3 */
14256 0, /* 21 check_sum */
14257 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }, /* 22-29 oem_name[16] */
14258 0, /* 30 dvc_err_code */
14259 0, /* 31 adv_err_code */
14260 0, /* 32 adv_err_addr */
14261 0, /* 33 saved_dvc_err_code */
14262 0, /* 34 saved_adv_err_code */
14263 0, /* 35 saved_adv_err_addr */
14264 0, /* 36 reserved */
14265 0, /* 37 reserved */
14266 0, /* 38 reserved */
14267 0, /* 39 reserved */
14268 0, /* 40 reserved */
14269 0, /* 41 reserved */
14270 0, /* 42 reserved */
14271 0, /* 43 reserved */
14272 0, /* 44 reserved */
14273 0, /* 45 reserved */
14274 0, /* 46 reserved */
14275 0, /* 47 reserved */
14276 0, /* 48 reserved */
14277 0, /* 49 reserved */
14278 0, /* 50 reserved */
14279 0, /* 51 reserved */
14280 0, /* 52 reserved */
14281 0, /* 53 reserved */
14282 0, /* 54 reserved */
14283 0, /* 55 reserved */
14284 0, /* 56 cisptr_lsw */
14285 0, /* 57 cisprt_msw */
14286 ADV_PCI_VENDOR_ID, /* 58 subsysvid */
14287 ADV_PCI_DEVID_38C0800_REV1, /* 59 subsysid */
14288 0, /* 60 reserved */
14289 0, /* 61 reserved */
14290 0, /* 62 reserved */
14291 0 /* 63 reserved */
14294 STATIC ADVEEP_38C0800_CONFIG
14295 ADVEEP_38C0800_Config_Field_IsChar __initdata = {
14296 0, /* 00 cfg_lsw */
14297 0, /* 01 cfg_msw */
14298 0, /* 02 disc_enable */
14299 0, /* 03 wdtr_able */
14300 0, /* 04 sdtr_speed1 */
14301 0, /* 05 start_motor */
14302 0, /* 06 tagqng_able */
14303 0, /* 07 bios_scan */
14304 0, /* 08 scam_tolerant */
14305 1, /* 09 adapter_scsi_id */
14306 1, /* bios_boot_delay */
14307 1, /* 10 scsi_reset_delay */
14308 1, /* bios_id_lun */
14309 1, /* 11 termination_se */
14310 1, /* termination_lvd */
14311 0, /* 12 bios_ctrl */
14312 0, /* 13 sdtr_speed2 */
14313 0, /* 14 sdtr_speed3 */
14314 1, /* 15 max_host_qng */
14315 1, /* max_dvc_qng */
14316 0, /* 16 dvc_cntl */
14317 0, /* 17 sdtr_speed4 */
14318 0, /* 18 serial_number_word1 */
14319 0, /* 19 serial_number_word2 */
14320 0, /* 20 serial_number_word3 */
14321 0, /* 21 check_sum */
14322 { 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 }, /* 22-29 oem_name[16] */
14323 0, /* 30 dvc_err_code */
14324 0, /* 31 adv_err_code */
14325 0, /* 32 adv_err_addr */
14326 0, /* 33 saved_dvc_err_code */
14327 0, /* 34 saved_adv_err_code */
14328 0, /* 35 saved_adv_err_addr */
14329 0, /* 36 reserved */
14330 0, /* 37 reserved */
14331 0, /* 38 reserved */
14332 0, /* 39 reserved */
14333 0, /* 40 reserved */
14334 0, /* 41 reserved */
14335 0, /* 42 reserved */
14336 0, /* 43 reserved */
14337 0, /* 44 reserved */
14338 0, /* 45 reserved */
14339 0, /* 46 reserved */
14340 0, /* 47 reserved */
14341 0, /* 48 reserved */
14342 0, /* 49 reserved */
14343 0, /* 50 reserved */
14344 0, /* 51 reserved */
14345 0, /* 52 reserved */
14346 0, /* 53 reserved */
14347 0, /* 54 reserved */
14348 0, /* 55 reserved */
14349 0, /* 56 cisptr_lsw */
14350 0, /* 57 cisprt_msw */
14351 0, /* 58 subsysvid */
14352 0, /* 59 subsysid */
14353 0, /* 60 reserved */
14354 0, /* 61 reserved */
14355 0, /* 62 reserved */
14356 0 /* 63 reserved */
14359 STATIC ADVEEP_38C1600_CONFIG
14360 Default_38C1600_EEPROM_Config __initdata = {
14361 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
14362 0x0000, /* 01 cfg_msw */
14363 0xFFFF, /* 02 disc_enable */
14364 0xFFFF, /* 03 wdtr_able */
14365 0x5555, /* 04 sdtr_speed1 */
14366 0xFFFF, /* 05 start_motor */
14367 0xFFFF, /* 06 tagqng_able */
14368 0xFFFF, /* 07 bios_scan */
14369 0, /* 08 scam_tolerant */
14370 7, /* 09 adapter_scsi_id */
14371 0, /* bios_boot_delay */
14372 3, /* 10 scsi_reset_delay */
14373 0, /* bios_id_lun */
14374 0, /* 11 termination_se */
14375 0, /* termination_lvd */
14376 0xFFE7, /* 12 bios_ctrl */
14377 0x5555, /* 13 sdtr_speed2 */
14378 0x5555, /* 14 sdtr_speed3 */
14379 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
14380 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
14381 0, /* 16 dvc_cntl */
14382 0x5555, /* 17 sdtr_speed4 */
14383 0, /* 18 serial_number_word1 */
14384 0, /* 19 serial_number_word2 */
14385 0, /* 20 serial_number_word3 */
14386 0, /* 21 check_sum */
14387 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }, /* 22-29 oem_name[16] */
14388 0, /* 30 dvc_err_code */
14389 0, /* 31 adv_err_code */
14390 0, /* 32 adv_err_addr */
14391 0, /* 33 saved_dvc_err_code */
14392 0, /* 34 saved_adv_err_code */
14393 0, /* 35 saved_adv_err_addr */
14394 0, /* 36 reserved */
14395 0, /* 37 reserved */
14396 0, /* 38 reserved */
14397 0, /* 39 reserved */
14398 0, /* 40 reserved */
14399 0, /* 41 reserved */
14400 0, /* 42 reserved */
14401 0, /* 43 reserved */
14402 0, /* 44 reserved */
14403 0, /* 45 reserved */
14404 0, /* 46 reserved */
14405 0, /* 47 reserved */
14406 0, /* 48 reserved */
14407 0, /* 49 reserved */
14408 0, /* 50 reserved */
14409 0, /* 51 reserved */
14410 0, /* 52 reserved */
14411 0, /* 53 reserved */
14412 0, /* 54 reserved */
14413 0, /* 55 reserved */
14414 0, /* 56 cisptr_lsw */
14415 0, /* 57 cisprt_msw */
14416 ADV_PCI_VENDOR_ID, /* 58 subsysvid */
14417 ADV_PCI_DEVID_38C1600_REV1, /* 59 subsysid */
14418 0, /* 60 reserved */
14419 0, /* 61 reserved */
14420 0, /* 62 reserved */
14421 0 /* 63 reserved */
14424 STATIC ADVEEP_38C1600_CONFIG
14425 ADVEEP_38C1600_Config_Field_IsChar __initdata = {
14426 0, /* 00 cfg_lsw */
14427 0, /* 01 cfg_msw */
14428 0, /* 02 disc_enable */
14429 0, /* 03 wdtr_able */
14430 0, /* 04 sdtr_speed1 */
14431 0, /* 05 start_motor */
14432 0, /* 06 tagqng_able */
14433 0, /* 07 bios_scan */
14434 0, /* 08 scam_tolerant */
14435 1, /* 09 adapter_scsi_id */
14436 1, /* bios_boot_delay */
14437 1, /* 10 scsi_reset_delay */
14438 1, /* bios_id_lun */
14439 1, /* 11 termination_se */
14440 1, /* termination_lvd */
14441 0, /* 12 bios_ctrl */
14442 0, /* 13 sdtr_speed2 */
14443 0, /* 14 sdtr_speed3 */
14444 1, /* 15 max_host_qng */
14445 1, /* max_dvc_qng */
14446 0, /* 16 dvc_cntl */
14447 0, /* 17 sdtr_speed4 */
14448 0, /* 18 serial_number_word1 */
14449 0, /* 19 serial_number_word2 */
14450 0, /* 20 serial_number_word3 */
14451 0, /* 21 check_sum */
14452 { 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 }, /* 22-29 oem_name[16] */
14453 0, /* 30 dvc_err_code */
14454 0, /* 31 adv_err_code */
14455 0, /* 32 adv_err_addr */
14456 0, /* 33 saved_dvc_err_code */
14457 0, /* 34 saved_adv_err_code */
14458 0, /* 35 saved_adv_err_addr */
14459 0, /* 36 reserved */
14460 0, /* 37 reserved */
14461 0, /* 38 reserved */
14462 0, /* 39 reserved */
14463 0, /* 40 reserved */
14464 0, /* 41 reserved */
14465 0, /* 42 reserved */
14466 0, /* 43 reserved */
14467 0, /* 44 reserved */
14468 0, /* 45 reserved */
14469 0, /* 46 reserved */
14470 0, /* 47 reserved */
14471 0, /* 48 reserved */
14472 0, /* 49 reserved */
14473 0, /* 50 reserved */
14474 0, /* 51 reserved */
14475 0, /* 52 reserved */
14476 0, /* 53 reserved */
14477 0, /* 54 reserved */
14478 0, /* 55 reserved */
14479 0, /* 56 cisptr_lsw */
14480 0, /* 57 cisprt_msw */
14481 0, /* 58 subsysvid */
14482 0, /* 59 subsysid */
14483 0, /* 60 reserved */
14484 0, /* 61 reserved */
14485 0, /* 62 reserved */
14486 0 /* 63 reserved */
14490 * Initialize the ADV_DVC_VAR structure.
14492 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
14494 * For a non-fatal error return a warning code. If there are no warnings
14495 * then 0 is returned.
14498 AdvInitGetConfig(ADV_DVC_VAR *asc_dvc)
14501 AdvPortAddr iop_base;
14506 asc_dvc->err_code = 0;
14507 iop_base = asc_dvc->iop_base;
14510 * PCI Command Register
14512 * Note: AscPCICmdRegBits_BusMastering definition (0x0007) includes
14513 * I/O Space Control, Memory Space Control and Bus Master Control bits.
14516 if (((pci_cmd_reg = DvcAdvReadPCIConfigByte(asc_dvc,
14517 AscPCIConfigCommandRegister))
14518 & AscPCICmdRegBits_BusMastering)
14519 != AscPCICmdRegBits_BusMastering)
14521 pci_cmd_reg |= AscPCICmdRegBits_BusMastering;
14523 DvcAdvWritePCIConfigByte(asc_dvc,
14524 AscPCIConfigCommandRegister, pci_cmd_reg);
14526 if (((DvcAdvReadPCIConfigByte(asc_dvc, AscPCIConfigCommandRegister))
14527 & AscPCICmdRegBits_BusMastering)
14528 != AscPCICmdRegBits_BusMastering)
14530 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
14535 * PCI Latency Timer
14537 * If the "latency timer" register is 0x20 or above, then we don't need
14538 * to change it. Otherwise, set it to 0x20 (i.e. set it to 0x20 if it
14539 * comes up less than 0x20).
14541 if (DvcAdvReadPCIConfigByte(asc_dvc, AscPCIConfigLatencyTimer) < 0x20) {
14542 DvcAdvWritePCIConfigByte(asc_dvc, AscPCIConfigLatencyTimer, 0x20);
14543 if (DvcAdvReadPCIConfigByte(asc_dvc, AscPCIConfigLatencyTimer) < 0x20)
14545 warn_code |= ASC_WARN_SET_PCI_CONFIG_SPACE;
14550 * Save the state of the PCI Configuration Command Register
14551 * "Parity Error Response Control" Bit. If the bit is clear (0),
14552 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
14553 * DMA parity errors.
14555 asc_dvc->cfg->control_flag = 0;
14556 if (((DvcAdvReadPCIConfigByte(asc_dvc, AscPCIConfigCommandRegister)
14557 & AscPCICmdRegBits_ParErrRespCtrl)) == 0)
14559 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
14562 asc_dvc->cfg->lib_version = (ADV_LIB_VERSION_MAJOR << 8) |
14563 ADV_LIB_VERSION_MINOR;
14564 asc_dvc->cfg->chip_version =
14565 AdvGetChipVersion(iop_base, asc_dvc->bus_type);
14567 ASC_DBG2(1, "AdvInitGetConfig: iopb_chip_id_1: 0x%x 0x%x\n",
14568 (ushort) AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
14569 (ushort) ADV_CHIP_ID_BYTE);
14571 ASC_DBG2(1, "AdvInitGetConfig: iopw_chip_id_0: 0x%x 0x%x\n",
14572 (ushort) AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
14573 (ushort) ADV_CHIP_ID_WORD);
14576 * Reset the chip to start and allow register writes.
14578 if (AdvFindSignature(iop_base) == 0)
14580 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
14585 * The caller must set 'chip_type' to a valid setting.
14587 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
14588 asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
14589 asc_dvc->chip_type != ADV_CHIP_ASC38C1600)
14591 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
14598 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
14599 ADV_CTRL_REG_CMD_RESET);
14600 DvcSleepMilliSecond(100);
14601 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
14602 ADV_CTRL_REG_CMD_WR_IO_REG);
14604 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600)
14606 if ((status = AdvInitFrom38C1600EEP(asc_dvc)) == ADV_ERROR)
14610 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800)
14612 if ((status = AdvInitFrom38C0800EEP(asc_dvc)) == ADV_ERROR)
14618 if ((status = AdvInitFrom3550EEP(asc_dvc)) == ADV_ERROR)
14623 warn_code |= status;
14630 * Initialize the ASC-3550.
14632 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
14634 * For a non-fatal error return a warning code. If there are no warnings
14635 * then 0 is returned.
14637 * Needed after initialization for error recovery.
14640 AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
14642 AdvPortAddr iop_base;
14650 int adv_asc3550_expanded_size;
14652 ADV_DCNT contig_len;
14653 ADV_SDCNT buf_size;
14654 ADV_PADDR carr_paddr;
14658 ushort bios_mem[ASC_MC_BIOSLEN/2]; /* BIOS RISC Memory 0x40-0x8F. */
14659 ushort wdtr_able = 0, sdtr_able, tagqng_able;
14660 uchar max_cmd[ADV_MAX_TID + 1];
14662 /* If there is already an error, don't continue. */
14663 if (asc_dvc->err_code != 0)
14669 * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
14671 if (asc_dvc->chip_type != ADV_CHIP_ASC3550)
14673 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
14678 iop_base = asc_dvc->iop_base;
14681 * Save the RISC memory BIOS region before writing the microcode.
14682 * The BIOS may already be loaded and using its RISC LRAM region
14683 * so its region must be saved and restored.
14685 * Note: This code makes the assumption, which is currently true,
14686 * that a chip reset does not clear RISC LRAM.
14688 for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
14690 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
14694 * Save current per TID negotiated values.
14696 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 0x55AA)
14698 ushort bios_version, major, minor;
14700 bios_version = bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM)/2];
14701 major = (bios_version >> 12) & 0xF;
14702 minor = (bios_version >> 8) & 0xF;
14703 if (major < 3 || (major == 3 && minor == 1))
14705 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
14706 AdvReadWordLram(iop_base, 0x120, wdtr_able);
14709 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
14712 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
14713 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
14714 for (tid = 0; tid <= ADV_MAX_TID; tid++)
14716 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
14721 * Load the Microcode
14723 * Write the microcode image to RISC memory starting at address 0.
14725 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
14726 /* Assume the following compressed format of the microcode buffer:
14728 * 254 word (508 byte) table indexed by byte code followed
14729 * by the following byte codes:
14732 * 00: Emit word 0 in table.
14733 * 01: Emit word 1 in table.
14735 * FD: Emit word 253 in table.
14738 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
14739 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
14742 for (i = 253 * 2; i < _adv_asc3550_size; i++)
14744 if (_adv_asc3550_buf[i] == 0xff)
14746 for (j = 0; j < _adv_asc3550_buf[i + 1]; j++)
14748 AdvWriteWordAutoIncLram(iop_base, (((ushort)
14749 _adv_asc3550_buf[i + 3] << 8) |
14750 _adv_asc3550_buf[i + 2]));
14754 } else if (_adv_asc3550_buf[i] == 0xfe)
14756 AdvWriteWordAutoIncLram(iop_base, (((ushort)
14757 _adv_asc3550_buf[i + 2] << 8) |
14758 _adv_asc3550_buf[i + 1]));
14763 AdvWriteWordAutoIncLram(iop_base, (((ushort)
14764 _adv_asc3550_buf[(_adv_asc3550_buf[i] * 2) + 1] << 8) |
14765 _adv_asc3550_buf[_adv_asc3550_buf[i] * 2]));
14771 * Set 'word' for later use to clear the rest of memory and save
14772 * the expanded mcode size.
14775 adv_asc3550_expanded_size = word;
14778 * Clear the rest of ASC-3550 Internal RAM (8KB).
14780 for (; word < ADV_3550_MEMSIZE; word += 2)
14782 AdvWriteWordAutoIncLram(iop_base, 0);
14786 * Verify the microcode checksum.
14789 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
14791 for (word = 0; word < adv_asc3550_expanded_size; word += 2)
14793 sum += AdvReadWordAutoIncLram(iop_base);
14796 if (sum != _adv_asc3550_chksum)
14798 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
14803 * Restore the RISC memory BIOS region.
14805 for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
14807 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
14811 * Calculate and write the microcode code checksum to the microcode
14812 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
14814 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
14815 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
14817 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
14818 for (word = begin_addr; word < end_addr; word += 2)
14820 code_sum += AdvReadWordAutoIncLram(iop_base);
14822 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
14825 * Read and save microcode version and date.
14827 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, asc_dvc->cfg->mcode_date);
14828 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, asc_dvc->cfg->mcode_version);
14831 * Set the chip type to indicate the ASC3550.
14833 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
14836 * If the PCI Configuration Command Register "Parity Error Response
14837 * Control" Bit was clear (0), then set the microcode variable
14838 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
14839 * to ignore DMA parity errors.
14841 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR)
14843 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
14844 word |= CONTROL_FLAG_IGNORE_PERR;
14845 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
14849 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
14850 * threshold of 128 bytes. This register is only accessible to the host.
14852 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
14853 START_CTL_EMFU | READ_CMD_MRM);
14856 * Microcode operating variables for WDTR, SDTR, and command tag
14857 * queuing will be set in AdvInquiryHandling() based on what a
14858 * device reports it is capable of in Inquiry byte 7.
14860 * If SCSI Bus Resets have been disabled, then directly set
14861 * SDTR and WDTR from the EEPROM configuration. This will allow
14862 * the BIOS and warm boot to work without a SCSI bus hang on
14863 * the Inquiry caused by host and target mismatched DTR values.
14864 * Without the SCSI Bus Reset, before an Inquiry a device can't
14865 * be assumed to be in Asynchronous, Narrow mode.
14867 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0)
14869 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, asc_dvc->wdtr_able);
14870 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, asc_dvc->sdtr_able);
14874 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
14875 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
14876 * bitmask. These values determine the maximum SDTR speed negotiated
14879 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
14880 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
14881 * without determining here whether the device supports SDTR.
14883 * 4-bit speed SDTR speed name
14884 * =========== ===============
14885 * 0000b (0x0) SDTR disabled
14886 * 0001b (0x1) 5 Mhz
14887 * 0010b (0x2) 10 Mhz
14888 * 0011b (0x3) 20 Mhz (Ultra)
14889 * 0100b (0x4) 40 Mhz (LVD/Ultra2)
14890 * 0101b (0x5) 80 Mhz (LVD2/Ultra3)
14891 * 0110b (0x6) Undefined
14893 * 1111b (0xF) Undefined
14896 for (tid = 0; tid <= ADV_MAX_TID; tid++)
14898 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able)
14900 /* Set Ultra speed for TID 'tid'. */
14901 word |= (0x3 << (4 * (tid % 4)));
14904 /* Set Fast speed for TID 'tid'. */
14905 word |= (0x2 << (4 * (tid % 4)));
14907 if (tid == 3) /* Check if done with sdtr_speed1. */
14909 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
14911 } else if (tid == 7) /* Check if done with sdtr_speed2. */
14913 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
14915 } else if (tid == 11) /* Check if done with sdtr_speed3. */
14917 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
14919 } else if (tid == 15) /* Check if done with sdtr_speed4. */
14921 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
14927 * Set microcode operating variable for the disconnect per TID bitmask.
14929 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, asc_dvc->cfg->disc_enable);
14932 * Set SCSI_CFG0 Microcode Default Value.
14934 * The microcode will set the SCSI_CFG0 register using this value
14935 * after it is started below.
14937 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
14938 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
14939 asc_dvc->chip_scsi_id);
14942 * Determine SCSI_CFG1 Microcode Default Value.
14944 * The microcode will set the SCSI_CFG1 register using this value
14945 * after it is started below.
14948 /* Read current SCSI_CFG1 Register value. */
14949 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
14952 * If all three connectors are in use, return an error.
14954 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
14955 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0)
14957 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
14962 * If the internal narrow cable is reversed all of the SCSI_CTRL
14963 * register signals will be set. Check for and return an error if
14964 * this condition is found.
14966 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07)
14968 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
14973 * If this is a differential board and a single-ended device
14974 * is attached to one of the connectors, return an error.
14976 if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0)
14978 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
14983 * If automatic termination control is enabled, then set the
14984 * termination value based on a table listed in a_condor.h.
14986 * If manual termination was specified with an EEPROM setting
14987 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
14988 * is ready to be 'ored' into SCSI_CFG1.
14990 if (asc_dvc->cfg->termination == 0)
14993 * The software always controls termination by setting TERM_CTL_SEL.
14994 * If TERM_CTL_SEL were set to 0, the hardware would set termination.
14996 asc_dvc->cfg->termination |= TERM_CTL_SEL;
14998 switch(scsi_cfg1 & CABLE_DETECT)
15000 /* TERM_CTL_H: on, TERM_CTL_L: on */
15001 case 0x3: case 0x7: case 0xB: case 0xD: case 0xE: case 0xF:
15002 asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
15005 /* TERM_CTL_H: on, TERM_CTL_L: off */
15006 case 0x1: case 0x5: case 0x9: case 0xA: case 0xC:
15007 asc_dvc->cfg->termination |= TERM_CTL_H;
15010 /* TERM_CTL_H: off, TERM_CTL_L: off */
15011 case 0x2: case 0x6:
15017 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
15019 scsi_cfg1 &= ~TERM_CTL;
15022 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
15023 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
15024 * referenced, because the hardware internally inverts
15025 * the Termination High and Low bits if TERM_POL is set.
15027 scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
15030 * Set SCSI_CFG1 Microcode Default Value
15032 * Set filter value and possibly modified termination control
15033 * bits in the Microcode SCSI_CFG1 Register Value.
15035 * The microcode will set the SCSI_CFG1 register using this value
15036 * after it is started below.
15038 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
15039 FLTR_DISABLE | scsi_cfg1);
15042 * Set MEM_CFG Microcode Default Value
15044 * The microcode will set the MEM_CFG register using this value
15045 * after it is started below.
15047 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
15050 * ASC-3550 has 8KB internal memory.
15052 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
15053 BIOS_EN | RAM_SZ_8KB);
15056 * Set SEL_MASK Microcode Default Value
15058 * The microcode will set the SEL_MASK register using this value
15059 * after it is started below.
15061 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
15062 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
15065 * Build carrier freelist.
15067 * Driver must have already allocated memory and set 'carrier_buf'.
15069 ASC_ASSERT(asc_dvc->carrier_buf != NULL);
15071 carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
15072 asc_dvc->carr_freelist = NULL;
15073 if (carrp == (ADV_CARR_T *) asc_dvc->carrier_buf)
15075 buf_size = ADV_CARRIER_BUFSIZE;
15078 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
15083 * Get physical address of the carrier 'carrp'.
15085 contig_len = sizeof(ADV_CARR_T);
15086 carr_paddr = cpu_to_le32(DvcGetPhyAddr(asc_dvc, NULL, (uchar *) carrp,
15087 (ADV_SDCNT *) &contig_len, ADV_IS_CARRIER_FLAG));
15089 buf_size -= sizeof(ADV_CARR_T);
15092 * If the current carrier is not physically contiguous, then
15093 * maybe there was a page crossing. Try the next carrier aligned
15096 if (contig_len < sizeof(ADV_CARR_T))
15102 carrp->carr_pa = carr_paddr;
15103 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
15106 * Insert the carrier at the beginning of the freelist.
15108 carrp->next_vpa = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
15109 asc_dvc->carr_freelist = carrp;
15113 while (buf_size > 0);
15116 * Set-up the Host->RISC Initiator Command Queue (ICQ).
15119 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL)
15121 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
15124 asc_dvc->carr_freelist = (ADV_CARR_T *)
15125 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
15128 * The first command issued will be placed in the stopper carrier.
15130 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
15133 * Set RISC ICQ physical address start value.
15135 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
15138 * Set-up the RISC->Host Initiator Response Queue (IRQ).
15140 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL)
15142 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
15145 asc_dvc->carr_freelist = (ADV_CARR_T *)
15146 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
15149 * The first command completed by the RISC will be placed in
15152 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
15153 * completed the RISC will set the ASC_RQ_STOPPER bit.
15155 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
15158 * Set RISC IRQ physical address start value.
15160 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
15161 asc_dvc->carr_pending_cnt = 0;
15163 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
15164 (ADV_INTR_ENABLE_HOST_INTR | ADV_INTR_ENABLE_GLOBAL_INTR));
15166 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
15167 AdvWriteWordRegister(iop_base, IOPW_PC, word);
15169 /* finally, finally, gentlemen, start your engine */
15170 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
15173 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
15174 * Resets should be performed. The RISC has to be running
15175 * to issue a SCSI Bus Reset.
15177 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS)
15180 * If the BIOS Signature is present in memory, restore the
15181 * BIOS Handshake Configuration Table and do not perform
15182 * a SCSI Bus Reset.
15184 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 0x55AA)
15187 * Restore per TID negotiated values.
15189 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
15190 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
15191 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
15192 for (tid = 0; tid <= ADV_MAX_TID; tid++)
15194 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
15199 if (AdvResetSB(asc_dvc) != ADV_TRUE)
15201 warn_code = ASC_WARN_BUSRESET_ERROR;
15210 * Initialize the ASC-38C0800.
15212 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
15214 * For a non-fatal error return a warning code. If there are no warnings
15215 * then 0 is returned.
15217 * Needed after initialization for error recovery.
15220 AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
15222 AdvPortAddr iop_base;
15230 int adv_asc38C0800_expanded_size;
15232 ADV_DCNT contig_len;
15233 ADV_SDCNT buf_size;
15234 ADV_PADDR carr_paddr;
15239 ushort bios_mem[ASC_MC_BIOSLEN/2]; /* BIOS RISC Memory 0x40-0x8F. */
15240 ushort wdtr_able, sdtr_able, tagqng_able;
15241 uchar max_cmd[ADV_MAX_TID + 1];
15243 /* If there is already an error, don't continue. */
15244 if (asc_dvc->err_code != 0)
15250 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
15252 if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800)
15254 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
15259 iop_base = asc_dvc->iop_base;
15262 * Save the RISC memory BIOS region before writing the microcode.
15263 * The BIOS may already be loaded and using its RISC LRAM region
15264 * so its region must be saved and restored.
15266 * Note: This code makes the assumption, which is currently true,
15267 * that a chip reset does not clear RISC LRAM.
15269 for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
15271 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
15275 * Save current per TID negotiated values.
15277 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
15278 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
15279 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
15280 for (tid = 0; tid <= ADV_MAX_TID; tid++)
15282 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
15287 * RAM BIST (RAM Built-In Self Test)
15289 * Address : I/O base + offset 0x38h register (byte).
15290 * Function: Bit 7-6(RW) : RAM mode
15291 * Normal Mode : 0x00
15292 * Pre-test Mode : 0x40
15293 * RAM Test Mode : 0x80
15295 * Bit 4(RO) : Done bit
15296 * Bit 3-0(RO) : Status
15297 * Host Error : 0x08
15298 * Int_RAM Error : 0x04
15299 * RISC Error : 0x02
15300 * SCSI Error : 0x01
15303 * Note: RAM BIST code should be put right here, before loading the
15304 * microcode and after saving the RISC memory BIOS region.
15310 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
15311 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
15312 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
15313 * to NORMAL_MODE, return an error too.
15315 for (i = 0; i < 2; i++)
15317 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
15318 DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */
15319 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
15320 if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) != PRE_TEST_VALUE)
15322 asc_dvc->err_code |= ASC_IERR_BIST_PRE_TEST;
15326 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
15327 DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */
15328 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
15331 asc_dvc->err_code |= ASC_IERR_BIST_PRE_TEST;
15337 * LRAM Test - It takes about 1.5 ms to run through the test.
15339 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
15340 * If Done bit not set or Status not 0, save register byte, set the
15341 * err_code, and return an error.
15343 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
15344 DvcSleepMilliSecond(10); /* Wait for 10ms before checking status. */
15346 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
15347 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0)
15349 /* Get here if Done bit not set or Status not 0. */
15350 asc_dvc->bist_err_code = byte; /* for BIOS display message */
15351 asc_dvc->err_code |= ASC_IERR_BIST_RAM_TEST;
15355 /* We need to reset back to normal mode after LRAM test passes. */
15356 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
15359 * Load the Microcode
15361 * Write the microcode image to RISC memory starting at address 0.
15364 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
15366 /* Assume the following compressed format of the microcode buffer:
15368 * 254 word (508 byte) table indexed by byte code followed
15369 * by the following byte codes:
15372 * 00: Emit word 0 in table.
15373 * 01: Emit word 1 in table.
15375 * FD: Emit word 253 in table.
15378 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
15379 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
15382 for (i = 253 * 2; i < _adv_asc38C0800_size; i++)
15384 if (_adv_asc38C0800_buf[i] == 0xff)
15386 for (j = 0; j < _adv_asc38C0800_buf[i + 1]; j++)
15388 AdvWriteWordAutoIncLram(iop_base, (((ushort)
15389 _adv_asc38C0800_buf[i + 3] << 8) |
15390 _adv_asc38C0800_buf[i + 2]));
15394 } else if (_adv_asc38C0800_buf[i] == 0xfe)
15396 AdvWriteWordAutoIncLram(iop_base, (((ushort)
15397 _adv_asc38C0800_buf[i + 2] << 8) |
15398 _adv_asc38C0800_buf[i + 1]));
15403 AdvWriteWordAutoIncLram(iop_base, (((ushort)
15404 _adv_asc38C0800_buf[(_adv_asc38C0800_buf[i] * 2) + 1] << 8) |
15405 _adv_asc38C0800_buf[_adv_asc38C0800_buf[i] * 2]));
15411 * Set 'word' for later use to clear the rest of memory and save
15412 * the expanded mcode size.
15415 adv_asc38C0800_expanded_size = word;
15418 * Clear the rest of ASC-38C0800 Internal RAM (16KB).
15420 for (; word < ADV_38C0800_MEMSIZE; word += 2)
15422 AdvWriteWordAutoIncLram(iop_base, 0);
15426 * Verify the microcode checksum.
15429 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
15431 for (word = 0; word < adv_asc38C0800_expanded_size; word += 2)
15433 sum += AdvReadWordAutoIncLram(iop_base);
15435 ASC_DBG2(1, "AdvInitAsc38C0800Driver: word %d, i %d\n", word, i);
15438 "AdvInitAsc38C0800Driver: sum 0x%lx, _adv_asc38C0800_chksum 0x%lx\n",
15439 (ulong) sum, (ulong) _adv_asc38C0800_chksum);
15441 if (sum != _adv_asc38C0800_chksum)
15443 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
15448 * Restore the RISC memory BIOS region.
15450 for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
15452 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
15456 * Calculate and write the microcode code checksum to the microcode
15457 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
15459 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
15460 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
15462 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
15463 for (word = begin_addr; word < end_addr; word += 2)
15465 code_sum += AdvReadWordAutoIncLram(iop_base);
15467 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
15470 * Read microcode version and date.
15472 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, asc_dvc->cfg->mcode_date);
15473 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, asc_dvc->cfg->mcode_version);
15476 * Set the chip type to indicate the ASC38C0800.
15478 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
15481 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
15482 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
15483 * cable detection and then we are able to read C_DET[3:0].
15485 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
15486 * Microcode Default Value' section below.
15488 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
15489 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1, scsi_cfg1 | DIS_TERM_DRV);
15492 * If the PCI Configuration Command Register "Parity Error Response
15493 * Control" Bit was clear (0), then set the microcode variable
15494 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
15495 * to ignore DMA parity errors.
15497 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR)
15499 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
15500 word |= CONTROL_FLAG_IGNORE_PERR;
15501 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
15505 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
15506 * bits for the default FIFO threshold.
15508 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
15510 * For DMA Errata #4 set the BC_THRESH_ENB bit.
15512 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
15513 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
15516 * Microcode operating variables for WDTR, SDTR, and command tag
15517 * queuing will be set in AdvInquiryHandling() based on what a
15518 * device reports it is capable of in Inquiry byte 7.
15520 * If SCSI Bus Resets have been disabled, then directly set
15521 * SDTR and WDTR from the EEPROM configuration. This will allow
15522 * the BIOS and warm boot to work without a SCSI bus hang on
15523 * the Inquiry caused by host and target mismatched DTR values.
15524 * Without the SCSI Bus Reset, before an Inquiry a device can't
15525 * be assumed to be in Asynchronous, Narrow mode.
15527 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0)
15529 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, asc_dvc->wdtr_able);
15530 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, asc_dvc->sdtr_able);
15534 * Set microcode operating variables for DISC and SDTR_SPEED1,
15535 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
15536 * configuration values.
15538 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
15539 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
15540 * without determining here whether the device supports SDTR.
15542 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, asc_dvc->cfg->disc_enable);
15543 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
15544 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
15545 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
15546 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
15549 * Set SCSI_CFG0 Microcode Default Value.
15551 * The microcode will set the SCSI_CFG0 register using this value
15552 * after it is started below.
15554 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
15555 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
15556 asc_dvc->chip_scsi_id);
15559 * Determine SCSI_CFG1 Microcode Default Value.
15561 * The microcode will set the SCSI_CFG1 register using this value
15562 * after it is started below.
15565 /* Read current SCSI_CFG1 Register value. */
15566 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
15569 * If the internal narrow cable is reversed all of the SCSI_CTRL
15570 * register signals will be set. Check for and return an error if
15571 * this condition is found.
15573 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07)
15575 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
15580 * All kind of combinations of devices attached to one of four connectors
15581 * are acceptable except HVD device attached. For example, LVD device can
15582 * be attached to SE connector while SE device attached to LVD connector.
15583 * If LVD device attached to SE connector, it only runs up to Ultra speed.
15585 * If an HVD device is attached to one of LVD connectors, return an error.
15586 * However, there is no way to detect HVD device attached to SE connectors.
15588 if (scsi_cfg1 & HVD)
15590 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
15595 * If either SE or LVD automatic termination control is enabled, then
15596 * set the termination value based on a table listed in a_condor.h.
15598 * If manual termination was specified with an EEPROM setting then
15599 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready to
15600 * be 'ored' into SCSI_CFG1.
15602 if ((asc_dvc->cfg->termination & TERM_SE) == 0)
15604 /* SE automatic termination control is enabled. */
15605 switch(scsi_cfg1 & C_DET_SE)
15607 /* TERM_SE_HI: on, TERM_SE_LO: on */
15608 case 0x1: case 0x2: case 0x3:
15609 asc_dvc->cfg->termination |= TERM_SE;
15612 /* TERM_SE_HI: on, TERM_SE_LO: off */
15614 asc_dvc->cfg->termination |= TERM_SE_HI;
15619 if ((asc_dvc->cfg->termination & TERM_LVD) == 0)
15621 /* LVD automatic termination control is enabled. */
15622 switch(scsi_cfg1 & C_DET_LVD)
15624 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
15625 case 0x4: case 0x8: case 0xC:
15626 asc_dvc->cfg->termination |= TERM_LVD;
15629 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
15636 * Clear any set TERM_SE and TERM_LVD bits.
15638 scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
15641 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
15643 scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
15646 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE bits
15647 * and set possibly modified termination control bits in the Microcode
15648 * SCSI_CFG1 Register Value.
15650 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
15653 * Set SCSI_CFG1 Microcode Default Value
15655 * Set possibly modified termination control and reset DIS_TERM_DRV
15656 * bits in the Microcode SCSI_CFG1 Register Value.
15658 * The microcode will set the SCSI_CFG1 register using this value
15659 * after it is started below.
15661 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
15664 * Set MEM_CFG Microcode Default Value
15666 * The microcode will set the MEM_CFG register using this value
15667 * after it is started below.
15669 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
15672 * ASC-38C0800 has 16KB internal memory.
15674 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
15675 BIOS_EN | RAM_SZ_16KB);
15678 * Set SEL_MASK Microcode Default Value
15680 * The microcode will set the SEL_MASK register using this value
15681 * after it is started below.
15683 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
15684 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
15687 * Build the carrier freelist.
15689 * Driver must have already allocated memory and set 'carrier_buf'.
15691 ASC_ASSERT(asc_dvc->carrier_buf != NULL);
15693 carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
15694 asc_dvc->carr_freelist = NULL;
15695 if (carrp == (ADV_CARR_T *) asc_dvc->carrier_buf)
15697 buf_size = ADV_CARRIER_BUFSIZE;
15700 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
15705 * Get physical address for the carrier 'carrp'.
15707 contig_len = sizeof(ADV_CARR_T);
15708 carr_paddr = cpu_to_le32(DvcGetPhyAddr(asc_dvc, NULL, (uchar *) carrp,
15709 (ADV_SDCNT *) &contig_len, ADV_IS_CARRIER_FLAG));
15711 buf_size -= sizeof(ADV_CARR_T);
15714 * If the current carrier is not physically contiguous, then
15715 * maybe there was a page crossing. Try the next carrier aligned
15718 if (contig_len < sizeof(ADV_CARR_T))
15724 carrp->carr_pa = carr_paddr;
15725 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
15728 * Insert the carrier at the beginning of the freelist.
15730 carrp->next_vpa = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
15731 asc_dvc->carr_freelist = carrp;
15735 while (buf_size > 0);
15738 * Set-up the Host->RISC Initiator Command Queue (ICQ).
15741 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL)
15743 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
15746 asc_dvc->carr_freelist = (ADV_CARR_T *)
15747 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
15750 * The first command issued will be placed in the stopper carrier.
15752 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
15755 * Set RISC ICQ physical address start value.
15756 * carr_pa is LE, must be native before write
15758 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
15761 * Set-up the RISC->Host Initiator Response Queue (IRQ).
15763 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL)
15765 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
15768 asc_dvc->carr_freelist = (ADV_CARR_T *)
15769 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
15772 * The first command completed by the RISC will be placed in
15775 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
15776 * completed the RISC will set the ASC_RQ_STOPPER bit.
15778 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
15781 * Set RISC IRQ physical address start value.
15783 * carr_pa is LE, must be native before write *
15785 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
15786 asc_dvc->carr_pending_cnt = 0;
15788 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
15789 (ADV_INTR_ENABLE_HOST_INTR | ADV_INTR_ENABLE_GLOBAL_INTR));
15791 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
15792 AdvWriteWordRegister(iop_base, IOPW_PC, word);
15794 /* finally, finally, gentlemen, start your engine */
15795 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
15798 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
15799 * Resets should be performed. The RISC has to be running
15800 * to issue a SCSI Bus Reset.
15802 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS)
15805 * If the BIOS Signature is present in memory, restore the
15806 * BIOS Handshake Configuration Table and do not perform
15807 * a SCSI Bus Reset.
15809 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 0x55AA)
15812 * Restore per TID negotiated values.
15814 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
15815 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
15816 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
15817 for (tid = 0; tid <= ADV_MAX_TID; tid++)
15819 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
15824 if (AdvResetSB(asc_dvc) != ADV_TRUE)
15826 warn_code = ASC_WARN_BUSRESET_ERROR;
15835 * Initialize the ASC-38C1600.
15837 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
15839 * For a non-fatal error return a warning code. If there are no warnings
15840 * then 0 is returned.
15842 * Needed after initialization for error recovery.
15845 AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
15847 AdvPortAddr iop_base;
15855 int adv_asc38C1600_expanded_size;
15857 ADV_DCNT contig_len;
15858 ADV_SDCNT buf_size;
15859 ADV_PADDR carr_paddr;
15864 ushort bios_mem[ASC_MC_BIOSLEN/2]; /* BIOS RISC Memory 0x40-0x8F. */
15865 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
15866 uchar max_cmd[ASC_MAX_TID + 1];
15868 /* If there is already an error, don't continue. */
15869 if (asc_dvc->err_code != 0)
15875 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
15877 if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600)
15879 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
15884 iop_base = asc_dvc->iop_base;
15887 * Save the RISC memory BIOS region before writing the microcode.
15888 * The BIOS may already be loaded and using its RISC LRAM region
15889 * so its region must be saved and restored.
15891 * Note: This code makes the assumption, which is currently true,
15892 * that a chip reset does not clear RISC LRAM.
15894 for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
15896 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
15900 * Save current per TID negotiated values.
15902 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
15903 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
15904 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
15905 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
15906 for (tid = 0; tid <= ASC_MAX_TID; tid++)
15908 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
15913 * RAM BIST (Built-In Self Test)
15915 * Address : I/O base + offset 0x38h register (byte).
15916 * Function: Bit 7-6(RW) : RAM mode
15917 * Normal Mode : 0x00
15918 * Pre-test Mode : 0x40
15919 * RAM Test Mode : 0x80
15921 * Bit 4(RO) : Done bit
15922 * Bit 3-0(RO) : Status
15923 * Host Error : 0x08
15924 * Int_RAM Error : 0x04
15925 * RISC Error : 0x02
15926 * SCSI Error : 0x01
15929 * Note: RAM BIST code should be put right here, before loading the
15930 * microcode and after saving the RISC memory BIOS region.
15936 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
15937 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
15938 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
15939 * to NORMAL_MODE, return an error too.
15941 for (i = 0; i < 2; i++)
15943 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
15944 DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */
15945 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
15946 if ((byte & RAM_TEST_DONE) == 0 || (byte & 0x0F) != PRE_TEST_VALUE)
15948 asc_dvc->err_code |= ASC_IERR_BIST_PRE_TEST;
15952 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
15953 DvcSleepMilliSecond(10); /* Wait for 10ms before reading back. */
15954 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
15957 asc_dvc->err_code |= ASC_IERR_BIST_PRE_TEST;
15963 * LRAM Test - It takes about 1.5 ms to run through the test.
15965 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
15966 * If Done bit not set or Status not 0, save register byte, set the
15967 * err_code, and return an error.
15969 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
15970 DvcSleepMilliSecond(10); /* Wait for 10ms before checking status. */
15972 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
15973 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0)
15975 /* Get here if Done bit not set or Status not 0. */
15976 asc_dvc->bist_err_code = byte; /* for BIOS display message */
15977 asc_dvc->err_code |= ASC_IERR_BIST_RAM_TEST;
15981 /* We need to reset back to normal mode after LRAM test passes. */
15982 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
15985 * Load the Microcode
15987 * Write the microcode image to RISC memory starting at address 0.
15990 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
15993 * Assume the following compressed format of the microcode buffer:
15995 * 254 word (508 byte) table indexed by byte code followed
15996 * by the following byte codes:
15999 * 00: Emit word 0 in table.
16000 * 01: Emit word 1 in table.
16002 * FD: Emit word 253 in table.
16005 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
16006 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
16009 for (i = 253 * 2; i < _adv_asc38C1600_size; i++)
16011 if (_adv_asc38C1600_buf[i] == 0xff)
16013 for (j = 0; j < _adv_asc38C1600_buf[i + 1]; j++)
16015 AdvWriteWordAutoIncLram(iop_base, (((ushort)
16016 _adv_asc38C1600_buf[i + 3] << 8) |
16017 _adv_asc38C1600_buf[i + 2]));
16021 } else if (_adv_asc38C1600_buf[i] == 0xfe)
16023 AdvWriteWordAutoIncLram(iop_base, (((ushort)
16024 _adv_asc38C1600_buf[i + 2] << 8) |
16025 _adv_asc38C1600_buf[i + 1]));
16030 AdvWriteWordAutoIncLram(iop_base, (((ushort)
16031 _adv_asc38C1600_buf[(_adv_asc38C1600_buf[i] * 2) + 1] << 8) |
16032 _adv_asc38C1600_buf[_adv_asc38C1600_buf[i] * 2]));
16038 * Set 'word' for later use to clear the rest of memory and save
16039 * the expanded mcode size.
16042 adv_asc38C1600_expanded_size = word;
16045 * Clear the rest of ASC-38C1600 Internal RAM (32KB).
16047 for (; word < ADV_38C1600_MEMSIZE; word += 2)
16049 AdvWriteWordAutoIncLram(iop_base, 0);
16053 * Verify the microcode checksum.
16056 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
16058 for (word = 0; word < adv_asc38C1600_expanded_size; word += 2)
16060 sum += AdvReadWordAutoIncLram(iop_base);
16063 if (sum != _adv_asc38C1600_chksum)
16065 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
16070 * Restore the RISC memory BIOS region.
16072 for (i = 0; i < ASC_MC_BIOSLEN/2; i++)
16074 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), bios_mem[i]);
16078 * Calculate and write the microcode code checksum to the microcode
16079 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
16081 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
16082 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
16084 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
16085 for (word = begin_addr; word < end_addr; word += 2)
16087 code_sum += AdvReadWordAutoIncLram(iop_base);
16089 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
16092 * Read microcode version and date.
16094 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, asc_dvc->cfg->mcode_date);
16095 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, asc_dvc->cfg->mcode_version);
16098 * Set the chip type to indicate the ASC38C1600.
16100 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
16103 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
16104 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
16105 * cable detection and then we are able to read C_DET[3:0].
16107 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
16108 * Microcode Default Value' section below.
16110 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
16111 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1, scsi_cfg1 | DIS_TERM_DRV);
16114 * If the PCI Configuration Command Register "Parity Error Response
16115 * Control" Bit was clear (0), then set the microcode variable
16116 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
16117 * to ignore DMA parity errors.
16119 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR)
16121 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
16122 word |= CONTROL_FLAG_IGNORE_PERR;
16123 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
16127 * If the BIOS control flag AIPP (Asynchronous Information
16128 * Phase Protection) disable bit is not set, then set the firmware
16129 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
16130 * AIPP checking and encoding.
16132 if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0)
16134 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
16135 word |= CONTROL_FLAG_ENABLE_AIPP;
16136 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
16140 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
16141 * and START_CTL_TH [3:2].
16143 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
16144 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
16147 * Microcode operating variables for WDTR, SDTR, and command tag
16148 * queuing will be set in AdvInquiryHandling() based on what a
16149 * device reports it is capable of in Inquiry byte 7.
16151 * If SCSI Bus Resets have been disabled, then directly set
16152 * SDTR and WDTR from the EEPROM configuration. This will allow
16153 * the BIOS and warm boot to work without a SCSI bus hang on
16154 * the Inquiry caused by host and target mismatched DTR values.
16155 * Without the SCSI Bus Reset, before an Inquiry a device can't
16156 * be assumed to be in Asynchronous, Narrow mode.
16158 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0)
16160 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, asc_dvc->wdtr_able);
16161 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, asc_dvc->sdtr_able);
16165 * Set microcode operating variables for DISC and SDTR_SPEED1,
16166 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
16167 * configuration values.
16169 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
16170 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
16171 * without determining here whether the device supports SDTR.
16173 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, asc_dvc->cfg->disc_enable);
16174 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
16175 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
16176 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
16177 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
16180 * Set SCSI_CFG0 Microcode Default Value.
16182 * The microcode will set the SCSI_CFG0 register using this value
16183 * after it is started below.
16185 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
16186 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
16187 asc_dvc->chip_scsi_id);
16190 * Calculate SCSI_CFG1 Microcode Default Value.
16192 * The microcode will set the SCSI_CFG1 register using this value
16193 * after it is started below.
16195 * Each ASC-38C1600 function has only two cable detect bits.
16196 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
16198 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
16201 * If the cable is reversed all of the SCSI_CTRL register signals
16202 * will be set. Check for and return an error if this condition is
16205 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07)
16207 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
16212 * Each ASC-38C1600 function has two connectors. Only an HVD device
16213 * can not be connected to either connector. An LVD device or SE device
16214 * may be connected to either connecor. If an SE device is connected,
16215 * then at most Ultra speed (20 Mhz) can be used on both connectors.
16217 * If an HVD device is attached, return an error.
16219 if (scsi_cfg1 & HVD)
16221 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
16226 * Each function in the ASC-38C1600 uses only the SE cable detect and
16227 * termination because there are two connectors for each function. Each
16228 * function may use either LVD or SE mode. Corresponding the SE automatic
16229 * termination control EEPROM bits are used for each function. Each
16230 * function has its own EEPROM. If SE automatic control is enabled for
16231 * the function, then set the termination value based on a table listed
16234 * If manual termination is specified in the EEPROM for the function,
16235 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
16236 * ready to be 'ored' into SCSI_CFG1.
16238 if ((asc_dvc->cfg->termination & TERM_SE) == 0)
16240 /* SE automatic termination control is enabled. */
16241 switch(scsi_cfg1 & C_DET_SE)
16243 /* TERM_SE_HI: on, TERM_SE_LO: on */
16244 case 0x1: case 0x2: case 0x3:
16245 asc_dvc->cfg->termination |= TERM_SE;
16249 if (ASC_PCI_ID2FUNC(asc_dvc->cfg->pci_slot_info) == 0)
16251 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
16255 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
16256 asc_dvc->cfg->termination |= TERM_SE_HI;
16263 * Clear any set TERM_SE bits.
16265 scsi_cfg1 &= ~TERM_SE;
16268 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
16270 scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
16273 * Clear Big Endian and Terminator Polarity bits and set possibly
16274 * modified termination control bits in the Microcode SCSI_CFG1
16277 * Big Endian bit is not used even on big endian machines.
16279 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
16282 * Set SCSI_CFG1 Microcode Default Value
16284 * Set possibly modified termination control bits in the Microcode
16285 * SCSI_CFG1 Register Value.
16287 * The microcode will set the SCSI_CFG1 register using this value
16288 * after it is started below.
16290 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
16293 * Set MEM_CFG Microcode Default Value
16295 * The microcode will set the MEM_CFG register using this value
16296 * after it is started below.
16298 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
16301 * ASC-38C1600 has 32KB internal memory.
16303 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
16304 * out a special 16K Adv Library and Microcode version. After the issue
16305 * resolved, we should turn back to the 32K support. Both a_condor.h and
16306 * mcode.sas files also need to be updated.
16308 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
16309 * BIOS_EN | RAM_SZ_32KB);
16311 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG, BIOS_EN | RAM_SZ_16KB);
16314 * Set SEL_MASK Microcode Default Value
16316 * The microcode will set the SEL_MASK register using this value
16317 * after it is started below.
16319 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
16320 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
16323 * Build the carrier freelist.
16325 * Driver must have already allocated memory and set 'carrier_buf'.
16328 ASC_ASSERT(asc_dvc->carrier_buf != NULL);
16330 carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf);
16331 asc_dvc->carr_freelist = NULL;
16332 if (carrp == (ADV_CARR_T *) asc_dvc->carrier_buf)
16334 buf_size = ADV_CARRIER_BUFSIZE;
16337 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T);
16342 * Get physical address for the carrier 'carrp'.
16344 contig_len = sizeof(ADV_CARR_T);
16345 carr_paddr = cpu_to_le32(DvcGetPhyAddr(asc_dvc, NULL, (uchar *) carrp,
16346 (ADV_SDCNT *) &contig_len, ADV_IS_CARRIER_FLAG));
16348 buf_size -= sizeof(ADV_CARR_T);
16351 * If the current carrier is not physically contiguous, then
16352 * maybe there was a page crossing. Try the next carrier aligned
16355 if (contig_len < sizeof(ADV_CARR_T))
16361 carrp->carr_pa = carr_paddr;
16362 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp));
16365 * Insert the carrier at the beginning of the freelist.
16367 carrp->next_vpa = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
16368 asc_dvc->carr_freelist = carrp;
16372 while (buf_size > 0);
16375 * Set-up the Host->RISC Initiator Command Queue (ICQ).
16377 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL)
16379 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
16382 asc_dvc->carr_freelist = (ADV_CARR_T *)
16383 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa));
16386 * The first command issued will be placed in the stopper carrier.
16388 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
16391 * Set RISC ICQ physical address start value. Initialize the
16392 * COMMA register to the same value otherwise the RISC will
16393 * prematurely detect a command is available.
16395 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
16396 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
16397 le32_to_cpu(asc_dvc->icq_sp->carr_pa));
16400 * Set-up the RISC->Host Initiator Response Queue (IRQ).
16402 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL)
16404 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
16407 asc_dvc->carr_freelist = (ADV_CARR_T *)
16408 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa));
16411 * The first command completed by the RISC will be placed in
16414 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is
16415 * completed the RISC will set the ASC_RQ_STOPPER bit.
16417 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
16420 * Set RISC IRQ physical address start value.
16422 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
16423 asc_dvc->carr_pending_cnt = 0;
16425 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
16426 (ADV_INTR_ENABLE_HOST_INTR | ADV_INTR_ENABLE_GLOBAL_INTR));
16427 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
16428 AdvWriteWordRegister(iop_base, IOPW_PC, word);
16430 /* finally, finally, gentlemen, start your engine */
16431 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
16434 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
16435 * Resets should be performed. The RISC has to be running
16436 * to issue a SCSI Bus Reset.
16438 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS)
16441 * If the BIOS Signature is present in memory, restore the
16442 * per TID microcode operating variables.
16444 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM)/2] == 0x55AA)
16447 * Restore per TID negotiated values.
16449 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
16450 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
16451 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
16452 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
16453 for (tid = 0; tid <= ASC_MAX_TID; tid++)
16455 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
16460 if (AdvResetSB(asc_dvc) != ADV_TRUE)
16462 warn_code = ASC_WARN_BUSRESET_ERROR;
16471 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
16472 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
16473 * all of this is done.
16475 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
16477 * For a non-fatal error return a warning code. If there are no warnings
16478 * then 0 is returned.
16480 * Note: Chip is stopped on entry.
16483 AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
16485 AdvPortAddr iop_base;
16487 ADVEEP_3550_CONFIG eep_config;
16490 iop_base = asc_dvc->iop_base;
16495 * Read the board's EEPROM configuration.
16497 * Set default values if a bad checksum is found.
16499 if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum)
16501 warn_code |= ASC_WARN_EEPROM_CHKSUM;
16504 * Set EEPROM default values.
16506 for (i = 0; i < sizeof(ADVEEP_3550_CONFIG); i++)
16508 *((uchar *) &eep_config + i) =
16509 *((uchar *) &Default_3550_EEPROM_Config + i);
16513 * Assume the 6 byte board serial number that was read
16514 * from EEPROM is correct even if the EEPROM checksum
16517 eep_config.serial_number_word3 =
16518 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
16520 eep_config.serial_number_word2 =
16521 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
16523 eep_config.serial_number_word1 =
16524 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
16526 AdvSet3550EEPConfig(iop_base, &eep_config);
16529 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
16530 * EEPROM configuration that was read.
16532 * This is the mapping of EEPROM fields to Adv Library fields.
16534 asc_dvc->wdtr_able = eep_config.wdtr_able;
16535 asc_dvc->sdtr_able = eep_config.sdtr_able;
16536 asc_dvc->ultra_able = eep_config.ultra_able;
16537 asc_dvc->tagqng_able = eep_config.tagqng_able;
16538 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
16539 asc_dvc->max_host_qng = eep_config.max_host_qng;
16540 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
16541 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
16542 asc_dvc->start_motor = eep_config.start_motor;
16543 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
16544 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
16545 asc_dvc->no_scam = eep_config.scam_tolerant;
16546 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
16547 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
16548 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
16551 * Set the host maximum queuing (max. 253, min. 16) and the per device
16552 * maximum queuing (max. 63, min. 4).
16554 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG)
16556 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
16557 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG)
16559 /* If the value is zero, assume it is uninitialized. */
16560 if (eep_config.max_host_qng == 0)
16562 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
16565 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
16569 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG)
16571 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
16572 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG)
16574 /* If the value is zero, assume it is uninitialized. */
16575 if (eep_config.max_dvc_qng == 0)
16577 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
16580 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
16585 * If 'max_dvc_qng' is greater than 'max_host_qng', then
16586 * set 'max_dvc_qng' to 'max_host_qng'.
16588 if (eep_config.max_dvc_qng > eep_config.max_host_qng)
16590 eep_config.max_dvc_qng = eep_config.max_host_qng;
16594 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
16595 * values based on possibly adjusted EEPROM values.
16597 asc_dvc->max_host_qng = eep_config.max_host_qng;
16598 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
16602 * If the EEPROM 'termination' field is set to automatic (0), then set
16603 * the ADV_DVC_CFG 'termination' field to automatic also.
16605 * If the termination is specified with a non-zero 'termination'
16606 * value check that a legal value is set and set the ADV_DVC_CFG
16607 * 'termination' field appropriately.
16609 if (eep_config.termination == 0)
16611 asc_dvc->cfg->termination = 0; /* auto termination */
16614 /* Enable manual control with low off / high off. */
16615 if (eep_config.termination == 1)
16617 asc_dvc->cfg->termination = TERM_CTL_SEL;
16619 /* Enable manual control with low off / high on. */
16620 } else if (eep_config.termination == 2)
16622 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
16624 /* Enable manual control with low on / high on. */
16625 } else if (eep_config.termination == 3)
16627 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
16631 * The EEPROM 'termination' field contains a bad value. Use
16632 * automatic termination instead.
16634 asc_dvc->cfg->termination = 0;
16635 warn_code |= ASC_WARN_EEPROM_TERMINATION;
16643 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
16644 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
16645 * all of this is done.
16647 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
16649 * For a non-fatal error return a warning code. If there are no warnings
16650 * then 0 is returned.
16652 * Note: Chip is stopped on entry.
16655 AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
16657 AdvPortAddr iop_base;
16659 ADVEEP_38C0800_CONFIG eep_config;
16661 uchar tid, termination;
16662 ushort sdtr_speed = 0;
16664 iop_base = asc_dvc->iop_base;
16669 * Read the board's EEPROM configuration.
16671 * Set default values if a bad checksum is found.
16673 if (AdvGet38C0800EEPConfig(iop_base, &eep_config) != eep_config.check_sum)
16675 warn_code |= ASC_WARN_EEPROM_CHKSUM;
16678 * Set EEPROM default values.
16680 for (i = 0; i < sizeof(ADVEEP_38C0800_CONFIG); i++)
16682 *((uchar *) &eep_config + i) =
16683 *((uchar *) &Default_38C0800_EEPROM_Config + i);
16687 * Assume the 6 byte board serial number that was read
16688 * from EEPROM is correct even if the EEPROM checksum
16691 eep_config.serial_number_word3 =
16692 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
16694 eep_config.serial_number_word2 =
16695 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
16697 eep_config.serial_number_word1 =
16698 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
16700 AdvSet38C0800EEPConfig(iop_base, &eep_config);
16703 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
16704 * EEPROM configuration that was read.
16706 * This is the mapping of EEPROM fields to Adv Library fields.
16708 asc_dvc->wdtr_able = eep_config.wdtr_able;
16709 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
16710 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
16711 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
16712 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
16713 asc_dvc->tagqng_able = eep_config.tagqng_able;
16714 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
16715 asc_dvc->max_host_qng = eep_config.max_host_qng;
16716 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
16717 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
16718 asc_dvc->start_motor = eep_config.start_motor;
16719 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
16720 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
16721 asc_dvc->no_scam = eep_config.scam_tolerant;
16722 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
16723 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
16724 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
16727 * For every Target ID if any of its 'sdtr_speed[1234]' bits
16728 * are set, then set an 'sdtr_able' bit for it.
16730 asc_dvc->sdtr_able = 0;
16731 for (tid = 0; tid <= ADV_MAX_TID; tid++)
16735 sdtr_speed = asc_dvc->sdtr_speed1;
16736 } else if (tid == 4)
16738 sdtr_speed = asc_dvc->sdtr_speed2;
16739 } else if (tid == 8)
16741 sdtr_speed = asc_dvc->sdtr_speed3;
16742 } else if (tid == 12)
16744 sdtr_speed = asc_dvc->sdtr_speed4;
16746 if (sdtr_speed & ADV_MAX_TID)
16748 asc_dvc->sdtr_able |= (1 << tid);
16754 * Set the host maximum queuing (max. 253, min. 16) and the per device
16755 * maximum queuing (max. 63, min. 4).
16757 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG)
16759 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
16760 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG)
16762 /* If the value is zero, assume it is uninitialized. */
16763 if (eep_config.max_host_qng == 0)
16765 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
16768 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
16772 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG)
16774 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
16775 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG)
16777 /* If the value is zero, assume it is uninitialized. */
16778 if (eep_config.max_dvc_qng == 0)
16780 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
16783 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
16788 * If 'max_dvc_qng' is greater than 'max_host_qng', then
16789 * set 'max_dvc_qng' to 'max_host_qng'.
16791 if (eep_config.max_dvc_qng > eep_config.max_host_qng)
16793 eep_config.max_dvc_qng = eep_config.max_host_qng;
16797 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
16798 * values based on possibly adjusted EEPROM values.
16800 asc_dvc->max_host_qng = eep_config.max_host_qng;
16801 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
16804 * If the EEPROM 'termination' field is set to automatic (0), then set
16805 * the ADV_DVC_CFG 'termination' field to automatic also.
16807 * If the termination is specified with a non-zero 'termination'
16808 * value check that a legal value is set and set the ADV_DVC_CFG
16809 * 'termination' field appropriately.
16811 if (eep_config.termination_se == 0)
16813 termination = 0; /* auto termination for SE */
16816 /* Enable manual control with low off / high off. */
16817 if (eep_config.termination_se == 1)
16821 /* Enable manual control with low off / high on. */
16822 } else if (eep_config.termination_se == 2)
16824 termination = TERM_SE_HI;
16826 /* Enable manual control with low on / high on. */
16827 } else if (eep_config.termination_se == 3)
16829 termination = TERM_SE;
16833 * The EEPROM 'termination_se' field contains a bad value.
16834 * Use automatic termination instead.
16837 warn_code |= ASC_WARN_EEPROM_TERMINATION;
16841 if (eep_config.termination_lvd == 0)
16843 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
16846 /* Enable manual control with low off / high off. */
16847 if (eep_config.termination_lvd == 1)
16849 asc_dvc->cfg->termination = termination;
16851 /* Enable manual control with low off / high on. */
16852 } else if (eep_config.termination_lvd == 2)
16854 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
16856 /* Enable manual control with low on / high on. */
16857 } else if (eep_config.termination_lvd == 3)
16859 asc_dvc->cfg->termination =
16860 termination | TERM_LVD;
16864 * The EEPROM 'termination_lvd' field contains a bad value.
16865 * Use automatic termination instead.
16867 asc_dvc->cfg->termination = termination;
16868 warn_code |= ASC_WARN_EEPROM_TERMINATION;
16876 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
16877 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
16878 * all of this is done.
16880 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
16882 * For a non-fatal error return a warning code. If there are no warnings
16883 * then 0 is returned.
16885 * Note: Chip is stopped on entry.
16888 AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
16890 AdvPortAddr iop_base;
16892 ADVEEP_38C1600_CONFIG eep_config;
16894 uchar tid, termination;
16895 ushort sdtr_speed = 0;
16897 iop_base = asc_dvc->iop_base;
16902 * Read the board's EEPROM configuration.
16904 * Set default values if a bad checksum is found.
16906 if (AdvGet38C1600EEPConfig(iop_base, &eep_config) != eep_config.check_sum)
16908 warn_code |= ASC_WARN_EEPROM_CHKSUM;
16911 * Set EEPROM default values.
16913 for (i = 0; i < sizeof(ADVEEP_38C1600_CONFIG); i++)
16915 if (i == 1 && ASC_PCI_ID2FUNC(asc_dvc->cfg->pci_slot_info) != 0)
16918 * Set Function 1 EEPROM Word 0 MSB
16920 * Clear the BIOS_ENABLE (bit 14) and INTAB (bit 11)
16923 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60 and
16924 * old Mac system booting problem. The Expansion ROM must
16925 * be disabled in Function 1 for these systems.
16928 *((uchar *) &eep_config + i) =
16929 ((*((uchar *) &Default_38C1600_EEPROM_Config + i)) &
16930 (~(((ADV_EEPROM_BIOS_ENABLE | ADV_EEPROM_INTAB) >> 8) &
16934 * Set the INTAB (bit 11) if the GPIO 0 input indicates
16935 * the Function 1 interrupt line is wired to INTA.
16937 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
16938 * 1 - Function 1 interrupt line wired to INT A.
16939 * 0 - Function 1 interrupt line wired to INT B.
16941 * Note: Adapter boards always have Function 0 wired to INTA.
16942 * Put all 5 GPIO bits in input mode and then read
16943 * their input values.
16945 AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
16946 if (AdvReadByteRegister(iop_base, IOPB_GPIO_DATA) & 0x01)
16948 /* Function 1 interrupt wired to INTA; Set EEPROM bit. */
16949 *((uchar *) &eep_config + i) |=
16950 ((ADV_EEPROM_INTAB >> 8) & 0xFF);
16955 *((uchar *) &eep_config + i) =
16956 *((uchar *) &Default_38C1600_EEPROM_Config + i);
16961 * Assume the 6 byte board serial number that was read
16962 * from EEPROM is correct even if the EEPROM checksum
16965 eep_config.serial_number_word3 =
16966 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
16968 eep_config.serial_number_word2 =
16969 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
16971 eep_config.serial_number_word1 =
16972 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
16974 AdvSet38C1600EEPConfig(iop_base, &eep_config);
16978 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
16979 * EEPROM configuration that was read.
16981 * This is the mapping of EEPROM fields to Adv Library fields.
16983 asc_dvc->wdtr_able = eep_config.wdtr_able;
16984 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
16985 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
16986 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
16987 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
16988 asc_dvc->ppr_able = 0;
16989 asc_dvc->tagqng_able = eep_config.tagqng_able;
16990 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
16991 asc_dvc->max_host_qng = eep_config.max_host_qng;
16992 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
16993 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
16994 asc_dvc->start_motor = eep_config.start_motor;
16995 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
16996 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
16997 asc_dvc->no_scam = eep_config.scam_tolerant;
17000 * For every Target ID if any of its 'sdtr_speed[1234]' bits
17001 * are set, then set an 'sdtr_able' bit for it.
17003 asc_dvc->sdtr_able = 0;
17004 for (tid = 0; tid <= ASC_MAX_TID; tid++)
17008 sdtr_speed = asc_dvc->sdtr_speed1;
17009 } else if (tid == 4)
17011 sdtr_speed = asc_dvc->sdtr_speed2;
17012 } else if (tid == 8)
17014 sdtr_speed = asc_dvc->sdtr_speed3;
17015 } else if (tid == 12)
17017 sdtr_speed = asc_dvc->sdtr_speed4;
17019 if (sdtr_speed & ASC_MAX_TID)
17021 asc_dvc->sdtr_able |= (1 << tid);
17027 * Set the host maximum queuing (max. 253, min. 16) and the per device
17028 * maximum queuing (max. 63, min. 4).
17030 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG)
17032 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
17033 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG)
17035 /* If the value is zero, assume it is uninitialized. */
17036 if (eep_config.max_host_qng == 0)
17038 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
17041 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
17045 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG)
17047 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
17048 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG)
17050 /* If the value is zero, assume it is uninitialized. */
17051 if (eep_config.max_dvc_qng == 0)
17053 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
17056 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
17061 * If 'max_dvc_qng' is greater than 'max_host_qng', then
17062 * set 'max_dvc_qng' to 'max_host_qng'.
17064 if (eep_config.max_dvc_qng > eep_config.max_host_qng)
17066 eep_config.max_dvc_qng = eep_config.max_host_qng;
17070 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
17071 * values based on possibly adjusted EEPROM values.
17073 asc_dvc->max_host_qng = eep_config.max_host_qng;
17074 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
17077 * If the EEPROM 'termination' field is set to automatic (0), then set
17078 * the ASC_DVC_CFG 'termination' field to automatic also.
17080 * If the termination is specified with a non-zero 'termination'
17081 * value check that a legal value is set and set the ASC_DVC_CFG
17082 * 'termination' field appropriately.
17084 if (eep_config.termination_se == 0)
17086 termination = 0; /* auto termination for SE */
17089 /* Enable manual control with low off / high off. */
17090 if (eep_config.termination_se == 1)
17094 /* Enable manual control with low off / high on. */
17095 } else if (eep_config.termination_se == 2)
17097 termination = TERM_SE_HI;
17099 /* Enable manual control with low on / high on. */
17100 } else if (eep_config.termination_se == 3)
17102 termination = TERM_SE;
17106 * The EEPROM 'termination_se' field contains a bad value.
17107 * Use automatic termination instead.
17110 warn_code |= ASC_WARN_EEPROM_TERMINATION;
17114 if (eep_config.termination_lvd == 0)
17116 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
17119 /* Enable manual control with low off / high off. */
17120 if (eep_config.termination_lvd == 1)
17122 asc_dvc->cfg->termination = termination;
17124 /* Enable manual control with low off / high on. */
17125 } else if (eep_config.termination_lvd == 2)
17127 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
17129 /* Enable manual control with low on / high on. */
17130 } else if (eep_config.termination_lvd == 3)
17132 asc_dvc->cfg->termination =
17133 termination | TERM_LVD;
17137 * The EEPROM 'termination_lvd' field contains a bad value.
17138 * Use automatic termination instead.
17140 asc_dvc->cfg->termination = termination;
17141 warn_code |= ASC_WARN_EEPROM_TERMINATION;
17149 * Read EEPROM configuration into the specified buffer.
17151 * Return a checksum based on the EEPROM configuration read.
17153 STATIC ushort __init
17154 AdvGet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
17156 ushort wval, chksum;
17159 ushort *charfields;
17161 charfields = (ushort *) &ADVEEP_3550_Config_Field_IsChar;
17162 wbuf = (ushort *) cfg_buf;
17165 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
17166 eep_addr < ADV_EEP_DVC_CFG_END;
17167 eep_addr++, wbuf++)
17169 wval = AdvReadEEPWord(iop_base, eep_addr);
17170 chksum += wval; /* Checksum is calculated from word values. */
17171 if (*charfields++) {
17172 *wbuf = le16_to_cpu(wval);
17177 /* Read checksum word. */
17178 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
17179 wbuf++; charfields++;
17181 /* Read rest of EEPROM not covered by the checksum. */
17182 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
17183 eep_addr < ADV_EEP_MAX_WORD_ADDR;
17184 eep_addr++, wbuf++)
17186 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
17187 if (*charfields++) {
17188 *wbuf = le16_to_cpu(*wbuf);
17195 * Read EEPROM configuration into the specified buffer.
17197 * Return a checksum based on the EEPROM configuration read.
17199 STATIC ushort __init
17200 AdvGet38C0800EEPConfig(AdvPortAddr iop_base,
17201 ADVEEP_38C0800_CONFIG *cfg_buf)
17203 ushort wval, chksum;
17206 ushort *charfields;
17208 charfields = (ushort *) &ADVEEP_38C0800_Config_Field_IsChar;
17209 wbuf = (ushort *) cfg_buf;
17212 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
17213 eep_addr < ADV_EEP_DVC_CFG_END;
17214 eep_addr++, wbuf++)
17216 wval = AdvReadEEPWord(iop_base, eep_addr);
17217 chksum += wval; /* Checksum is calculated from word values. */
17218 if (*charfields++) {
17219 *wbuf = le16_to_cpu(wval);
17224 /* Read checksum word. */
17225 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
17226 wbuf++; charfields++;
17228 /* Read rest of EEPROM not covered by the checksum. */
17229 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
17230 eep_addr < ADV_EEP_MAX_WORD_ADDR;
17231 eep_addr++, wbuf++)
17233 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
17234 if (*charfields++) {
17235 *wbuf = le16_to_cpu(*wbuf);
17242 * Read EEPROM configuration into the specified buffer.
17244 * Return a checksum based on the EEPROM configuration read.
17246 STATIC ushort __init
17247 AdvGet38C1600EEPConfig(AdvPortAddr iop_base,
17248 ADVEEP_38C1600_CONFIG *cfg_buf)
17250 ushort wval, chksum;
17253 ushort *charfields;
17255 charfields = (ushort*) &ADVEEP_38C1600_Config_Field_IsChar;
17256 wbuf = (ushort *) cfg_buf;
17259 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
17260 eep_addr < ADV_EEP_DVC_CFG_END;
17261 eep_addr++, wbuf++)
17263 wval = AdvReadEEPWord(iop_base, eep_addr);
17264 chksum += wval; /* Checksum is calculated from word values. */
17265 if (*charfields++) {
17266 *wbuf = le16_to_cpu(wval);
17271 /* Read checksum word. */
17272 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
17273 wbuf++; charfields++;
17275 /* Read rest of EEPROM not covered by the checksum. */
17276 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
17277 eep_addr < ADV_EEP_MAX_WORD_ADDR;
17278 eep_addr++, wbuf++)
17280 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
17281 if (*charfields++) {
17282 *wbuf = le16_to_cpu(*wbuf);
17289 * Read the EEPROM from specified location
17291 STATIC ushort __init
17292 AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
17294 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
17295 ASC_EEP_CMD_READ | eep_word_addr);
17296 AdvWaitEEPCmd(iop_base);
17297 return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
17301 * Wait for EEPROM command to complete
17304 AdvWaitEEPCmd(AdvPortAddr iop_base)
17308 for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++)
17310 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE)
17314 DvcSleepMilliSecond(1);
17316 if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) == 0)
17324 * Write the EEPROM from 'cfg_buf'.
17327 AdvSet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf)
17330 ushort addr, chksum;
17331 ushort *charfields;
17333 wbuf = (ushort *) cfg_buf;
17334 charfields = (ushort *) &ADVEEP_3550_Config_Field_IsChar;
17337 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
17338 AdvWaitEEPCmd(iop_base);
17341 * Write EEPROM from word 0 to word 20.
17343 for (addr = ADV_EEP_DVC_CFG_BEGIN;
17344 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++)
17348 if (*charfields++) {
17349 word = cpu_to_le16(*wbuf);
17353 chksum += *wbuf; /* Checksum is calculated from word values. */
17354 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17355 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17356 AdvWaitEEPCmd(iop_base);
17357 DvcSleepMilliSecond(ADV_EEP_DELAY_MS);
17361 * Write EEPROM checksum at word 21.
17363 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
17364 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17365 AdvWaitEEPCmd(iop_base);
17366 wbuf++; charfields++;
17369 * Write EEPROM OEM name at words 22 to 29.
17371 for (addr = ADV_EEP_DVC_CTL_BEGIN;
17372 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++)
17376 if (*charfields++) {
17377 word = cpu_to_le16(*wbuf);
17381 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17382 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17383 AdvWaitEEPCmd(iop_base);
17385 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
17386 AdvWaitEEPCmd(iop_base);
17391 * Write the EEPROM from 'cfg_buf'.
17394 AdvSet38C0800EEPConfig(AdvPortAddr iop_base,
17395 ADVEEP_38C0800_CONFIG *cfg_buf)
17398 ushort *charfields;
17399 ushort addr, chksum;
17401 wbuf = (ushort *) cfg_buf;
17402 charfields = (ushort *) &ADVEEP_38C0800_Config_Field_IsChar;
17405 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
17406 AdvWaitEEPCmd(iop_base);
17409 * Write EEPROM from word 0 to word 20.
17411 for (addr = ADV_EEP_DVC_CFG_BEGIN;
17412 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++)
17416 if (*charfields++) {
17417 word = cpu_to_le16(*wbuf);
17421 chksum += *wbuf; /* Checksum is calculated from word values. */
17422 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17423 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17424 AdvWaitEEPCmd(iop_base);
17425 DvcSleepMilliSecond(ADV_EEP_DELAY_MS);
17429 * Write EEPROM checksum at word 21.
17431 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
17432 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17433 AdvWaitEEPCmd(iop_base);
17434 wbuf++; charfields++;
17437 * Write EEPROM OEM name at words 22 to 29.
17439 for (addr = ADV_EEP_DVC_CTL_BEGIN;
17440 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++)
17444 if (*charfields++) {
17445 word = cpu_to_le16(*wbuf);
17449 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17450 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17451 AdvWaitEEPCmd(iop_base);
17453 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
17454 AdvWaitEEPCmd(iop_base);
17459 * Write the EEPROM from 'cfg_buf'.
17462 AdvSet38C1600EEPConfig(AdvPortAddr iop_base,
17463 ADVEEP_38C1600_CONFIG *cfg_buf)
17466 ushort *charfields;
17467 ushort addr, chksum;
17469 wbuf = (ushort *) cfg_buf;
17470 charfields = (ushort *) &ADVEEP_38C1600_Config_Field_IsChar;
17473 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
17474 AdvWaitEEPCmd(iop_base);
17477 * Write EEPROM from word 0 to word 20.
17479 for (addr = ADV_EEP_DVC_CFG_BEGIN;
17480 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++)
17484 if (*charfields++) {
17485 word = cpu_to_le16(*wbuf);
17489 chksum += *wbuf; /* Checksum is calculated from word values. */
17490 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17491 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17492 AdvWaitEEPCmd(iop_base);
17493 DvcSleepMilliSecond(ADV_EEP_DELAY_MS);
17497 * Write EEPROM checksum at word 21.
17499 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
17500 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17501 AdvWaitEEPCmd(iop_base);
17502 wbuf++; charfields++;
17505 * Write EEPROM OEM name at words 22 to 29.
17507 for (addr = ADV_EEP_DVC_CTL_BEGIN;
17508 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++)
17512 if (*charfields++) {
17513 word = cpu_to_le16(*wbuf);
17517 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
17518 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
17519 AdvWaitEEPCmd(iop_base);
17521 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
17522 AdvWaitEEPCmd(iop_base);
17528 * AdvExeScsiQueue() - Send a request to the RISC microcode program.
17530 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
17531 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
17532 * RISC to notify it a new command is ready to be executed.
17534 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
17535 * set to SCSI_MAX_RETRY.
17537 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode
17538 * for DMA addresses or math operations are byte swapped to little-endian
17542 * ADV_SUCCESS(1) - The request was successfully queued.
17543 * ADV_BUSY(0) - Resource unavailable; Retry again after pending
17544 * request completes.
17545 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure
17549 AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc,
17550 ADV_SCSI_REQ_Q *scsiq)
17552 ulong last_int_level;
17553 AdvPortAddr iop_base;
17555 ADV_PADDR req_paddr;
17556 ADV_CARR_T *new_carrp;
17558 ASC_ASSERT(scsiq != NULL); /* 'scsiq' should never be NULL. */
17561 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
17563 if (scsiq->target_id > ADV_MAX_TID)
17565 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
17566 scsiq->done_status = QD_WITH_ERROR;
17570 iop_base = asc_dvc->iop_base;
17572 last_int_level = DvcEnterCritical();
17575 * Allocate a carrier ensuring at least one carrier always
17576 * remains on the freelist and initialize fields.
17578 if ((new_carrp = asc_dvc->carr_freelist) == NULL)
17580 DvcLeaveCritical(last_int_level);
17583 asc_dvc->carr_freelist = (ADV_CARR_T *)
17584 ADV_U32_TO_VADDR(le32_to_cpu(new_carrp->next_vpa));
17585 asc_dvc->carr_pending_cnt++;
17588 * Set the carrier to be a stopper by setting 'next_vpa'
17589 * to the stopper value. The current stopper will be changed
17590 * below to point to the new stopper.
17592 new_carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
17595 * Clear the ADV_SCSI_REQ_Q done flag.
17597 scsiq->a_flag &= ~ADV_SCSIQ_DONE;
17599 req_size = sizeof(ADV_SCSI_REQ_Q);
17600 req_paddr = DvcGetPhyAddr(asc_dvc, scsiq, (uchar *) scsiq,
17601 (ADV_SDCNT *) &req_size, ADV_IS_SCSIQ_FLAG);
17603 ASC_ASSERT(ADV_32BALIGN(req_paddr) == req_paddr);
17604 ASC_ASSERT(req_size >= sizeof(ADV_SCSI_REQ_Q));
17606 /* Wait for assertion before making little-endian */
17607 req_paddr = cpu_to_le32(req_paddr);
17609 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
17610 scsiq->scsiq_ptr = cpu_to_le32(ADV_VADDR_TO_U32(scsiq));
17611 scsiq->scsiq_rptr = req_paddr;
17613 scsiq->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->icq_sp));
17615 * Every ADV_CARR_T.carr_pa is byte swapped to little-endian
17616 * order during initialization.
17618 scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
17621 * Use the current stopper to send the ADV_SCSI_REQ_Q command to
17622 * the microcode. The newly allocated stopper will become the new
17625 asc_dvc->icq_sp->areq_vpa = req_paddr;
17628 * Set the 'next_vpa' pointer for the old stopper to be the
17629 * physical address of the new stopper. The RISC can only
17630 * follow physical addresses.
17632 asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
17635 * Set the host adapter stopper pointer to point to the new carrier.
17637 asc_dvc->icq_sp = new_carrp;
17639 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
17640 asc_dvc->chip_type == ADV_CHIP_ASC38C0800)
17643 * Tickle the RISC to tell it to read its Command Queue Head pointer.
17645 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
17646 if (asc_dvc->chip_type == ADV_CHIP_ASC3550)
17649 * Clear the tickle value. In the ASC-3550 the RISC flag
17650 * command 'clr_tickle_a' does not work unless the host
17651 * value is cleared.
17653 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
17655 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600)
17658 * Notify the RISC a carrier is ready by writing the physical
17659 * address of the new carrier stopper to the COMMA register.
17661 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
17662 le32_to_cpu(new_carrp->carr_pa));
17665 DvcLeaveCritical(last_int_level);
17667 return ADV_SUCCESS;
17671 * Reset SCSI Bus and purge all outstanding requests.
17674 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset.
17675 * ADV_FALSE(0) - Microcode command failed.
17676 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
17677 * may be hung which requires driver recovery.
17680 AdvResetSB(ADV_DVC_VAR *asc_dvc)
17685 * Send the SCSI Bus Reset idle start idle command which asserts
17686 * the SCSI Bus Reset signal.
17688 status = AdvSendIdleCmd(asc_dvc, (ushort) IDLE_CMD_SCSI_RESET_START, 0L);
17689 if (status != ADV_TRUE)
17695 * Delay for the specified SCSI Bus Reset hold time.
17697 * The hold time delay is done on the host because the RISC has no
17698 * microsecond accurate timer.
17700 DvcDelayMicroSecond(asc_dvc, (ushort) ASC_SCSI_RESET_HOLD_TIME_US);
17703 * Send the SCSI Bus Reset end idle command which de-asserts
17704 * the SCSI Bus Reset signal and purges any pending requests.
17706 status = AdvSendIdleCmd(asc_dvc, (ushort) IDLE_CMD_SCSI_RESET_END, 0L);
17707 if (status != ADV_TRUE)
17712 DvcSleepMilliSecond((ADV_DCNT) asc_dvc->scsi_reset_wait * 1000);
17718 * Reset chip and SCSI Bus.
17721 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
17722 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
17725 AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
17728 ushort wdtr_able, sdtr_able, tagqng_able;
17729 ushort ppr_able = 0;
17730 uchar tid, max_cmd[ADV_MAX_TID + 1];
17731 AdvPortAddr iop_base;
17734 iop_base = asc_dvc->iop_base;
17737 * Save current per TID negotiated values.
17739 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
17740 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
17741 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600)
17743 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
17745 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
17746 for (tid = 0; tid <= ADV_MAX_TID; tid++)
17748 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
17753 * Force the AdvInitAsc3550/38C0800Driver() function to
17754 * perform a SCSI Bus Reset by clearing the BIOS signature word.
17755 * The initialization functions assumes a SCSI Bus Reset is not
17756 * needed if the BIOS signature word is present.
17758 AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
17759 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
17762 * Stop chip and reset it.
17764 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
17765 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
17766 DvcSleepMilliSecond(100);
17767 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_WR_IO_REG);
17770 * Reset Adv Library error code, if any, and try
17771 * re-initializing the chip.
17773 asc_dvc->err_code = 0;
17774 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600)
17776 status = AdvInitAsc38C1600Driver(asc_dvc);
17778 else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800)
17780 status = AdvInitAsc38C0800Driver(asc_dvc);
17783 status = AdvInitAsc3550Driver(asc_dvc);
17786 /* Translate initialization return value to status value. */
17792 status = ADV_FALSE;
17796 * Restore the BIOS signature word.
17798 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
17801 * Restore per TID negotiated values.
17803 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
17804 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
17805 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600)
17807 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
17809 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
17810 for (tid = 0; tid <= ADV_MAX_TID; tid++)
17812 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
17820 * Adv Library Interrupt Service Routine
17822 * This function is called by a driver's interrupt service routine.
17823 * The function disables and re-enables interrupts.
17825 * When a microcode idle command is completed, the ADV_DVC_VAR
17826 * 'idle_cmd_done' field is set to ADV_TRUE.
17828 * Note: AdvISR() can be called when interrupts are disabled or even
17829 * when there is no hardware interrupt condition present. It will
17830 * always check for completed idle commands and microcode requests.
17831 * This is an important feature that shouldn't be changed because it
17832 * allows commands to be completed from polling mode loops.
17835 * ADV_TRUE(1) - interrupt was pending
17836 * ADV_FALSE(0) - no interrupt was pending
17839 AdvISR(ADV_DVC_VAR *asc_dvc)
17841 AdvPortAddr iop_base;
17844 ADV_CARR_T *free_carrp;
17845 ADV_VADDR irq_next_vpa;
17847 ADV_SCSI_REQ_Q *scsiq;
17849 flags = DvcEnterCritical();
17851 iop_base = asc_dvc->iop_base;
17853 /* Reading the register clears the interrupt. */
17854 int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
17856 if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
17857 ADV_INTR_STATUS_INTRC)) == 0)
17859 DvcLeaveCritical(flags);
17864 * Notify the driver of an asynchronous microcode condition by
17865 * calling the ADV_DVC_VAR.async_callback function. The function
17866 * is passed the microcode ASC_MC_INTRB_CODE byte value.
17868 if (int_stat & ADV_INTR_STATUS_INTRB)
17872 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
17874 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
17875 asc_dvc->chip_type == ADV_CHIP_ASC38C0800)
17877 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
17878 asc_dvc->carr_pending_cnt != 0)
17880 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
17881 if (asc_dvc->chip_type == ADV_CHIP_ASC3550)
17883 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
17888 if (asc_dvc->async_callback != 0)
17890 (*asc_dvc->async_callback)(asc_dvc, intrb_code);
17895 * Check if the IRQ stopper carrier contains a completed request.
17897 while (((irq_next_vpa =
17898 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0)
17901 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
17902 * The RISC will have set 'areq_vpa' to a virtual address.
17904 * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr
17905 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
17906 * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr'
17907 * in AdvExeScsiQueue().
17909 scsiq = (ADV_SCSI_REQ_Q *)
17910 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->areq_vpa));
17913 * Request finished with good status and the queue was not
17914 * DMAed to host memory by the firmware. Set all status fields
17915 * to indicate good status.
17917 if ((irq_next_vpa & ASC_RQ_GOOD) != 0)
17919 scsiq->done_status = QD_NO_ERROR;
17920 scsiq->host_status = scsiq->scsi_status = 0;
17921 scsiq->data_cnt = 0L;
17925 * Advance the stopper pointer to the next carrier
17926 * ignoring the lower four bits. Free the previous
17929 free_carrp = asc_dvc->irq_sp;
17930 asc_dvc->irq_sp = (ADV_CARR_T *)
17931 ADV_U32_TO_VADDR(ASC_GET_CARRP(irq_next_vpa));
17933 free_carrp->next_vpa =
17934 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist));
17935 asc_dvc->carr_freelist = free_carrp;
17936 asc_dvc->carr_pending_cnt--;
17938 ASC_ASSERT(scsiq != NULL);
17939 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
17942 * Clear request microcode control flag.
17947 * If the command that completed was a SCSI INQUIRY and
17948 * LUN 0 was sent the command, then process the INQUIRY
17949 * command information for the device.
17951 * Note: If data returned were either VPD or CmdDt data,
17952 * don't process the INQUIRY command information for
17953 * the device, otherwise may erroneously set *_able bits.
17955 if (scsiq->done_status == QD_NO_ERROR &&
17956 scsiq->cdb[0] == INQUIRY &&
17957 scsiq->target_lun == 0 &&
17958 (scsiq->cdb[1] & ADV_INQ_RTN_VPD_AND_CMDDT)
17959 == ADV_INQ_RTN_STD_INQUIRY_DATA)
17961 AdvInquiryHandling(asc_dvc, scsiq);
17965 * Notify the driver of the completed request by passing
17966 * the ADV_SCSI_REQ_Q pointer to its callback function.
17968 scsiq->a_flag |= ADV_SCSIQ_DONE;
17969 (*asc_dvc->isr_callback)(asc_dvc, scsiq);
17971 * Note: After the driver callback function is called, 'scsiq'
17972 * can no longer be referenced.
17974 * Fall through and continue processing other completed
17979 * Disable interrupts again in case the driver inadvertently
17980 * enabled interrupts in its callback function.
17982 * The DvcEnterCritical() return value is ignored, because
17983 * the 'flags' saved when AdvISR() was first entered will be
17984 * used to restore the interrupt flag on exit.
17986 (void) DvcEnterCritical();
17988 DvcLeaveCritical(flags);
17993 * Send an idle command to the chip and wait for completion.
17995 * Command completion is polled for once per microsecond.
17997 * The function can be called from anywhere including an interrupt handler.
17998 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
17999 * functions to prevent reentrancy.
18002 * ADV_TRUE - command completed successfully
18003 * ADV_FALSE - command failed
18004 * ADV_ERROR - command timed out
18007 AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
18009 ADV_DCNT idle_cmd_parameter)
18011 ulong last_int_level;
18014 AdvPortAddr iop_base;
18016 last_int_level = DvcEnterCritical();
18018 iop_base = asc_dvc->iop_base;
18021 * Clear the idle command status which is set by the microcode
18022 * to a non-zero value to indicate when the command is completed.
18023 * The non-zero result is one of the IDLE_CMD_STATUS_* values
18024 * defined in a_advlib.h.
18026 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort) 0);
18029 * Write the idle command value after the idle command parameter
18030 * has been written to avoid a race condition. If the order is not
18031 * followed, the microcode may process the idle command before the
18032 * parameters have been written to LRAM.
18034 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
18035 cpu_to_le32(idle_cmd_parameter));
18036 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
18039 * Tickle the RISC to tell it to process the idle command.
18041 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
18042 if (asc_dvc->chip_type == ADV_CHIP_ASC3550)
18045 * Clear the tickle value. In the ASC-3550 the RISC flag
18046 * command 'clr_tickle_b' does not work unless the host
18047 * value is cleared.
18049 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
18052 /* Wait for up to 100 millisecond for the idle command to timeout. */
18053 for (i = 0; i < SCSI_WAIT_100_MSEC; i++)
18055 /* Poll once each microsecond for command completion. */
18056 for (j = 0; j < SCSI_US_PER_MSEC; j++)
18058 AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, result);
18061 DvcLeaveCritical(last_int_level);
18064 DvcDelayMicroSecond(asc_dvc, (ushort) 1);
18068 ASC_ASSERT(0); /* The idle command should never timeout. */
18069 DvcLeaveCritical(last_int_level);
18074 * Inquiry Information Byte 7 Handling
18076 * Handle SCSI Inquiry Command information for a device by setting
18077 * microcode operating variables that affect WDTR, SDTR, and Tag
18081 AdvInquiryHandling(
18082 ADV_DVC_VAR *asc_dvc,
18083 ADV_SCSI_REQ_Q *scsiq)
18085 AdvPortAddr iop_base;
18087 ADV_SCSI_INQUIRY *inq;
18092 * AdvInquiryHandling() requires up to INQUIRY information Byte 7
18095 * If less than 8 bytes of INQUIRY information were requested or less
18096 * than 8 bytes were transferred, then return. cdb[4] is the request
18097 * length and the ADV_SCSI_REQ_Q 'data_cnt' field is set by the
18098 * microcode to the transfer residual count.
18101 if (scsiq->cdb[4] < 8 ||
18102 (scsiq->cdb[4] - le32_to_cpu(scsiq->data_cnt)) < 8)
18107 iop_base = asc_dvc->iop_base;
18108 tid = scsiq->target_id;
18110 inq = (ADV_SCSI_INQUIRY *) scsiq->vdata_addr;
18113 * WDTR, SDTR, and Tag Queuing cannot be enabled for old devices.
18115 if (ADV_INQ_RESPONSE_FMT(inq) < 2 && ADV_INQ_ANSI_VER(inq) < 2)
18121 * INQUIRY Byte 7 Handling
18123 * Use a device's INQUIRY byte 7 to determine whether it
18124 * supports WDTR, SDTR, and Tag Queuing. If the feature
18125 * is enabled in the EEPROM and the device supports the
18126 * feature, then enable it in the microcode.
18129 tidmask = ADV_TID_TO_TIDMASK(tid);
18134 * If the EEPROM enabled WDTR for the device and the device
18135 * supports wide bus (16 bit) transfers, then turn on the
18136 * device's 'wdtr_able' bit and write the new value to the
18139 if ((asc_dvc->wdtr_able & tidmask) && ADV_INQ_WIDE16(inq))
18141 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
18142 if ((cfg_word & tidmask) == 0)
18144 cfg_word |= tidmask;
18145 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
18148 * Clear the microcode "SDTR negotiation" and "WDTR
18149 * negotiation" done indicators for the target to cause
18150 * it to negotiate with the new setting set above.
18151 * WDTR when accepted causes the target to enter
18152 * asynchronous mode, so SDTR must be negotiated.
18154 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
18155 cfg_word &= ~tidmask;
18156 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
18157 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
18158 cfg_word &= ~tidmask;
18159 AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
18164 * Synchronous Transfers
18166 * If the EEPROM enabled SDTR for the device and the device
18167 * supports synchronous transfers, then turn on the device's
18168 * 'sdtr_able' bit. Write the new value to the microcode.
18170 if ((asc_dvc->sdtr_able & tidmask) && ADV_INQ_SYNC(inq))
18172 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
18173 if ((cfg_word & tidmask) == 0)
18175 cfg_word |= tidmask;
18176 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
18179 * Clear the microcode "SDTR negotiation" done indicator
18180 * for the target to cause it to negotiate with the new
18181 * setting set above.
18183 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
18184 cfg_word &= ~tidmask;
18185 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
18189 * If the Inquiry data included enough space for the SPI-3
18190 * Clocking field, then check if DT mode is supported.
18192 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600 &&
18193 (scsiq->cdb[4] >= 57 ||
18194 (scsiq->cdb[4] - le32_to_cpu(scsiq->data_cnt)) >= 57))
18197 * PPR (Parallel Protocol Request) Capable
18199 * If the device supports DT mode, then it must be PPR capable.
18200 * The PPR message will be used in place of the SDTR and WDTR
18201 * messages to negotiate synchronous speed and offset, transfer
18202 * width, and protocol options.
18204 if (ADV_INQ_CLOCKING(inq) & ADV_INQ_CLOCKING_DT_ONLY)
18206 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, asc_dvc->ppr_able);
18207 asc_dvc->ppr_able |= tidmask;
18208 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, asc_dvc->ppr_able);
18213 * If the EEPROM enabled Tag Queuing for the device and the
18214 * device supports Tag Queueing, then turn on the device's
18215 * 'tagqng_enable' bit in the microcode and set the microcode
18216 * maximum command count to the ADV_DVC_VAR 'max_dvc_qng'
18219 * Tag Queuing is disabled for the BIOS which runs in polled
18220 * mode and would see no benefit from Tag Queuing. Also by
18221 * disabling Tag Queuing in the BIOS devices with Tag Queuing
18222 * bugs will at least work with the BIOS.
18224 if ((asc_dvc->tagqng_able & tidmask) && ADV_INQ_CMD_QUEUE(inq))
18226 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
18227 cfg_word |= tidmask;
18228 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
18230 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
18231 asc_dvc->max_dvc_qng);
18235 MODULE_LICENSE("Dual BSD/GPL");