2 * Blackfin On-Chip Real Time Clock Driver
3 * Supports BF53[123]/BF53[467]/BF54[2489]
5 * Copyright 2004-2007 Analog Devices Inc.
7 * Enter bugs at http://blackfin.uclinux.org/
9 * Licensed under the GPL-2 or later.
12 /* The biggest issue we deal with in this driver is that register writes are
13 * synced to the RTC frequency of 1Hz. So if you write to a register and
14 * attempt to write again before the first write has completed, the new write
15 * is simply discarded. This can easily be troublesome if userspace disables
16 * one event (say periodic) and then right after enables an event (say alarm).
17 * Since all events are maintained in the same interrupt mask register, if
18 * we wrote to it to disable the first event and then wrote to it again to
19 * enable the second event, that second event would not be enabled as the
20 * write would be discarded and things quickly fall apart.
22 * To keep this delay from significantly degrading performance (we, in theory,
23 * would have to sleep for up to 1 second everytime we wanted to write a
24 * register), we only check the write pending status before we start to issue
25 * a new write. We bank on the idea that it doesnt matter when the sync
26 * happens so long as we don't attempt another write before it does. The only
27 * time userspace would take this penalty is when they try and do multiple
28 * operations right after another ... but in this case, they need to take the
29 * sync penalty, so we should be OK.
31 * Also note that the RTC_ISTAT register does not suffer this penalty; its
32 * writes to clear status registers complete immediately.
35 #include <linux/module.h>
36 #include <linux/kernel.h>
37 #include <linux/bcd.h>
38 #include <linux/rtc.h>
39 #include <linux/init.h>
40 #include <linux/platform_device.h>
41 #include <linux/seq_file.h>
42 #include <linux/interrupt.h>
43 #include <linux/spinlock.h>
44 #include <linux/delay.h>
46 #include <asm/blackfin.h>
48 #define dev_dbg_stamp(dev) dev_dbg(dev, "%s:%i: here i am\n", __func__, __LINE__)
51 struct rtc_device *rtc_dev;
52 struct rtc_time rtc_alarm;
56 /* Bit values for the ISTAT / ICTL registers */
57 #define RTC_ISTAT_WRITE_COMPLETE 0x8000
58 #define RTC_ISTAT_WRITE_PENDING 0x4000
59 #define RTC_ISTAT_ALARM_DAY 0x0040
60 #define RTC_ISTAT_24HR 0x0020
61 #define RTC_ISTAT_HOUR 0x0010
62 #define RTC_ISTAT_MIN 0x0008
63 #define RTC_ISTAT_SEC 0x0004
64 #define RTC_ISTAT_ALARM 0x0002
65 #define RTC_ISTAT_STOPWATCH 0x0001
67 /* Shift values for RTC_STAT register */
68 #define DAY_BITS_OFF 17
69 #define HOUR_BITS_OFF 12
70 #define MIN_BITS_OFF 6
71 #define SEC_BITS_OFF 0
73 /* Some helper functions to convert between the common RTC notion of time
74 * and the internal Blackfin notion that is encoded in 32bits.
76 static inline u32 rtc_time_to_bfin(unsigned long now)
79 u32 min = (now % (60 * 60)) / 60;
80 u32 hour = (now % (60 * 60 * 24)) / (60 * 60);
81 u32 days = (now / (60 * 60 * 24));
82 return (sec << SEC_BITS_OFF) +
83 (min << MIN_BITS_OFF) +
84 (hour << HOUR_BITS_OFF) +
85 (days << DAY_BITS_OFF);
87 static inline unsigned long rtc_bfin_to_time(u32 rtc_bfin)
89 return (((rtc_bfin >> SEC_BITS_OFF) & 0x003F)) +
90 (((rtc_bfin >> MIN_BITS_OFF) & 0x003F) * 60) +
91 (((rtc_bfin >> HOUR_BITS_OFF) & 0x001F) * 60 * 60) +
92 (((rtc_bfin >> DAY_BITS_OFF) & 0x7FFF) * 60 * 60 * 24);
94 static inline void rtc_bfin_to_tm(u32 rtc_bfin, struct rtc_time *tm)
96 rtc_time_to_tm(rtc_bfin_to_time(rtc_bfin), tm);
99 /* Wait for the previous write to a RTC register to complete.
100 * Unfortunately, we can't sleep here as that introduces a race condition when
101 * turning on interrupt events. Consider this:
102 * - process sets alarm
103 * - process enables alarm
104 * - process sleeps while waiting for rtc write to sync
105 * - interrupt fires while process is sleeping
106 * - interrupt acks the event by writing to ISTAT
107 * - interrupt sets the WRITE PENDING bit
108 * - interrupt handler finishes
109 * - process wakes up, sees WRITE PENDING bit set, goes to sleep
110 * - interrupt fires while process is sleeping
111 * If anyone can point out the obvious solution here, i'm listening :). This
112 * shouldn't be an issue on an SMP or preempt system as this function should
113 * only be called with the rtc lock held.
116 * - disable PREN so the sync happens at 32.768kHZ ... but this changes the
117 * inc rate for all RTC registers from 1HZ to 32.768kHZ ...
118 * - use the write complete IRQ
120 static void rtc_bfin_sync_pending(void)
122 while (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_COMPLETE)) {
123 if (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_WRITE_PENDING))
126 bfin_write_RTC_ISTAT(RTC_ISTAT_WRITE_COMPLETE);
129 static void rtc_bfin_reset(struct device *dev)
131 struct bfin_rtc *rtc = dev_get_drvdata(dev);
132 /* Initialize the RTC. Enable pre-scaler to scale RTC clock
133 * to 1Hz and clear interrupt/status registers. */
134 spin_lock_irq(&rtc->lock);
135 rtc_bfin_sync_pending();
136 bfin_write_RTC_PREN(0x1);
137 bfin_write_RTC_ICTL(0);
138 bfin_write_RTC_SWCNT(0);
139 bfin_write_RTC_ALARM(0);
140 bfin_write_RTC_ISTAT(0xFFFF);
141 spin_unlock_irq(&rtc->lock);
144 static irqreturn_t bfin_rtc_interrupt(int irq, void *dev_id)
146 struct device *dev = dev_id;
147 struct bfin_rtc *rtc = dev_get_drvdata(dev);
148 unsigned long events = 0;
153 spin_lock_irq(&rtc->lock);
155 rtc_istat = bfin_read_RTC_ISTAT();
157 if (rtc_istat & (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY)) {
158 bfin_write_RTC_ISTAT(RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY);
159 events |= RTC_AF | RTC_IRQF;
162 if (rtc_istat & RTC_ISTAT_STOPWATCH) {
163 bfin_write_RTC_ISTAT(RTC_ISTAT_STOPWATCH);
164 events |= RTC_PF | RTC_IRQF;
165 bfin_write_RTC_SWCNT(rtc->rtc_dev->irq_freq);
168 if (rtc_istat & RTC_ISTAT_SEC) {
169 bfin_write_RTC_ISTAT(RTC_ISTAT_SEC);
170 events |= RTC_UF | RTC_IRQF;
173 rtc_update_irq(rtc->rtc_dev, 1, events);
175 spin_unlock_irq(&rtc->lock);
180 static int bfin_rtc_open(struct device *dev)
186 ret = request_irq(IRQ_RTC, bfin_rtc_interrupt, IRQF_DISABLED, "rtc-bfin", dev);
188 dev_err(dev, "request RTC IRQ failed with %d\n", ret);
197 static void bfin_rtc_release(struct device *dev)
201 free_irq(IRQ_RTC, dev);
204 static int bfin_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
206 struct bfin_rtc *rtc = dev_get_drvdata(dev);
213 spin_lock_irq(&rtc->lock);
214 rtc_bfin_sync_pending();
215 bfin_write_RTC_ISTAT(RTC_ISTAT_STOPWATCH);
216 bfin_write_RTC_SWCNT(rtc->rtc_dev->irq_freq);
217 bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() | RTC_ISTAT_STOPWATCH);
218 spin_unlock_irq(&rtc->lock);
222 spin_lock_irq(&rtc->lock);
223 rtc_bfin_sync_pending();
224 bfin_write_RTC_SWCNT(0);
225 bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() & ~RTC_ISTAT_STOPWATCH);
226 spin_unlock_irq(&rtc->lock);
231 spin_lock_irq(&rtc->lock);
232 rtc_bfin_sync_pending();
233 bfin_write_RTC_ISTAT(RTC_ISTAT_SEC);
234 bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() | RTC_ISTAT_SEC);
235 spin_unlock_irq(&rtc->lock);
239 spin_lock_irq(&rtc->lock);
240 rtc_bfin_sync_pending();
241 bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() & ~RTC_ISTAT_SEC);
242 spin_unlock_irq(&rtc->lock);
246 unsigned long rtc_alarm;
252 spin_lock_irq(&rtc->lock);
254 rtc_bfin_sync_pending();
255 if (rtc->rtc_alarm.tm_yday == -1) {
257 rtc_bfin_to_tm(bfin_read_RTC_STAT(), &now);
258 now.tm_sec = rtc->rtc_alarm.tm_sec;
259 now.tm_min = rtc->rtc_alarm.tm_min;
260 now.tm_hour = rtc->rtc_alarm.tm_hour;
261 ret = rtc_tm_to_time(&now, &rtc_alarm);
262 which_alarm = RTC_ISTAT_ALARM;
264 ret = rtc_tm_to_time(&rtc->rtc_alarm, &rtc_alarm);
265 which_alarm = RTC_ISTAT_ALARM_DAY;
268 bfin_write_RTC_ISTAT(which_alarm);
269 bfin_write_RTC_ALARM(rtc_time_to_bfin(rtc_alarm));
270 bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() | which_alarm);
273 spin_unlock_irq(&rtc->lock);
279 spin_lock_irq(&rtc->lock);
280 rtc_bfin_sync_pending();
281 bfin_write_RTC_ICTL(bfin_read_RTC_ICTL() & ~(RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY));
282 spin_unlock_irq(&rtc->lock);
289 static int bfin_rtc_read_time(struct device *dev, struct rtc_time *tm)
291 struct bfin_rtc *rtc = dev_get_drvdata(dev);
295 spin_lock_irq(&rtc->lock);
296 rtc_bfin_sync_pending();
297 rtc_bfin_to_tm(bfin_read_RTC_STAT(), tm);
298 spin_unlock_irq(&rtc->lock);
303 static int bfin_rtc_set_time(struct device *dev, struct rtc_time *tm)
305 struct bfin_rtc *rtc = dev_get_drvdata(dev);
311 spin_lock_irq(&rtc->lock);
313 ret = rtc_tm_to_time(tm, &now);
315 rtc_bfin_sync_pending();
316 bfin_write_RTC_STAT(rtc_time_to_bfin(now));
319 spin_unlock_irq(&rtc->lock);
324 static int bfin_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
326 struct bfin_rtc *rtc = dev_get_drvdata(dev);
328 alrm->time = rtc->rtc_alarm;
329 alrm->enabled = !!(bfin_read_RTC_ICTL() & (RTC_ISTAT_ALARM | RTC_ISTAT_ALARM_DAY));
333 static int bfin_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
335 struct bfin_rtc *rtc = dev_get_drvdata(dev);
337 rtc->rtc_alarm = alrm->time;
341 static int bfin_rtc_proc(struct device *dev, struct seq_file *seq)
343 #define yesno(x) ((x) ? "yes" : "no")
344 u16 ictl = bfin_read_RTC_ICTL();
348 "wkalarm_IRQ\t: %s\n"
349 "seconds_IRQ\t: %s\n"
350 "periodic_IRQ\t: %s\n",
351 yesno(ictl & RTC_ISTAT_ALARM),
352 yesno(ictl & RTC_ISTAT_ALARM_DAY),
353 yesno(ictl & RTC_ISTAT_SEC),
354 yesno(ictl & RTC_ISTAT_STOPWATCH));
360 * bfin_irq_set_freq - make sure hardware supports requested freq
361 * @dev: pointer to RTC device structure
362 * @freq: requested frequency rate
364 * The Blackfin RTC can only generate periodic events at 1 per
365 * second (1 Hz), so reject any attempt at changing it.
367 static int bfin_irq_set_freq(struct device *dev, int freq)
373 static struct rtc_class_ops bfin_rtc_ops = {
374 .open = bfin_rtc_open,
375 .release = bfin_rtc_release,
376 .ioctl = bfin_rtc_ioctl,
377 .read_time = bfin_rtc_read_time,
378 .set_time = bfin_rtc_set_time,
379 .read_alarm = bfin_rtc_read_alarm,
380 .set_alarm = bfin_rtc_set_alarm,
381 .proc = bfin_rtc_proc,
382 .irq_set_freq = bfin_irq_set_freq,
385 static int __devinit bfin_rtc_probe(struct platform_device *pdev)
387 struct bfin_rtc *rtc;
390 dev_dbg_stamp(&pdev->dev);
392 rtc = kzalloc(sizeof(*rtc), GFP_KERNEL);
396 spin_lock_init(&rtc->lock);
398 rtc->rtc_dev = rtc_device_register(pdev->name, &pdev->dev, &bfin_rtc_ops, THIS_MODULE);
399 if (unlikely(IS_ERR(rtc))) {
400 ret = PTR_ERR(rtc->rtc_dev);
403 rtc->rtc_dev->irq_freq = 1;
405 platform_set_drvdata(pdev, rtc);
414 static int __devexit bfin_rtc_remove(struct platform_device *pdev)
416 struct bfin_rtc *rtc = platform_get_drvdata(pdev);
418 rtc_device_unregister(rtc->rtc_dev);
419 platform_set_drvdata(pdev, NULL);
425 static struct platform_driver bfin_rtc_driver = {
428 .owner = THIS_MODULE,
430 .probe = bfin_rtc_probe,
431 .remove = __devexit_p(bfin_rtc_remove),
434 static int __init bfin_rtc_init(void)
436 return platform_driver_register(&bfin_rtc_driver);
439 static void __exit bfin_rtc_exit(void)
441 platform_driver_unregister(&bfin_rtc_driver);
444 module_init(bfin_rtc_init);
445 module_exit(bfin_rtc_exit);
447 MODULE_DESCRIPTION("Blackfin On-Chip Real Time Clock Driver");
448 MODULE_AUTHOR("Mike Frysinger <vapier@gentoo.org>");
449 MODULE_LICENSE("GPL");